Chapter #2 Data Storage Q. Refer to the given figures (a) and (b). A logic analyzer is used to che in figure (a) and displays the waveforms shown in figure (b). The actu display shows all four data outputs, Q0-Q3. The analyzer's cursor is position X and all four of the data output lines show a LOW level output. wrong, if anything, with the circuit? ‘ B. The circuit is in the READ mode and the outputs, Q0-Q3, should contents of the memory at that address. The chip is defective; replace C. The circuit is in the mode and should be writing the contents of address to Q0-Q3. D. The Q0-Q3 lines can be either LOW or HIGH, since the chip is i mode in which case their level is unpredictableA se Dye pe oe tia stn ’ (U/ ALG Gus gh be y 7 a Uy 2 lov wd als 5b & 5 le = /Gt ai D a is rps ws sa el Ores ae ity hb ba bl an a PX &y vy del a i I ae Jes Ev J Sa : 7 Das jl yesThe number 5 is being written to the! memory at address location 203. | The chip has not been enabled, since the. EN terminal is 0; therefore, nothing will be written to the chip and the output is trie) stated, SE D. The read/write line is Low; therefore, decimal 5 is being stored at memory location 211. | a Address Data inputs inputs HH onocore mono Q. For the given circuit, which of the following is correct?HWe es? ish = ¢ fig ) 0, 0, De rate oh oat ae i Cty a) (6 (8 t hh BABA MA eC . Moe le wp eerTe ee |e | bwfer A-Eiglain te proce and be Gn pits DRAM tele —\s1/@ oft 'Y one by f ae eorinde oH hii _ wel un bed Sent bs Ades 20h © AND J Le ane Binosy counter , bve 408 Jobe DF Lumet veer bes ff “finds by! buted 1! add tere04/46 Merls 1.How y many CMOS are required for SRAM? 22 ba. d)8, "9 ies the ‘ane aie 8 not true for SRAM? . Stores data in thelformlfcharge, b) They have low capacity but offer a €) It doesn't require periodic refreshing. 4) They are made up of six transistors. 4-An EPROM has a window to allow UV light to enter unde certain conditions. The purpose of this is to:Chapter #2 Data Storage Q. Construct a4 KB memory using 1 KB IC’sKoy Pus 1