EE001-3-2-AE Final Exam Page 1 of 5

MODULE DESCRIPTOR VERSION: VE1

No. Course Learning Outcomes Assessments
1 Interpret the design of analogue circuits. (C3, PLO2) Final Exam

2 Investigate the characteristics of analogue circuits. (C4, Group Assignment

PLO4)
3 Exemplify the ability to work effectively in a group on Group Assignment
analogue circuit design problems. (A5, PLO9)

No. Asses Question vs. Taxonomy

sment Cognitive Level Psychomotor Affective
Quest Level Level
ion
1 2 3 4 5 6 1 2 3 4 5 6 7 1 2 3 4 5
Q1 a) 8m c) 6m
b) 3m e) 5m
d) 3m

Q2 a) 2m b) 6m
c) 5m d) 6m
e) 6m

Q3 a)i) 5m b)iii)
LO1
a)ii) 4m 2m
b)i) 11m
b)ii) 3m

Q4 a)ii) 2m a)i) 8m
b)i) 10m
b)ii) 5m

POM 61% 19% 2% 18%

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EE001-3-2-AE Final Exam Page 2 of 5

This paper contains 4 questions.

Answer ALL questions.
This paper carries 100 marks.

1.

Figure Q1 shows a common-emitter amplifier. The gain of the transistor Q1 is given by β =

100, the resistances are given by RS = 500 Ω, R1 = 1 MΩ, R2 = 1 MΩ, RC = 10 kΩ, RE = 10 kΩ
and RL = 1 kΩ, and the internal capacitances are given by Cμ = 2 pF and Cπ = 20 pF.

Assume that the internal resistances rb = 10 Ω, rμ = ∞, ro = ∞ and the external capacitances CS,
CE and CL are large.

Figure Q1

a) If the supply voltage, VCC, is 12 V, compute the collector current, IC, hybrid-π parameters,
gm and rπ for the transistor Q1. [8 Marks]

b) Sketch the small-signal equivalent circuit in a form suitable for high frequency analysis.
[3 Marks]

c) By using Miller’s theorem, calculate the internal capacitances C1 and C2. [6 Marks]

d) Sketch the small-signal equivalent circuit again which includes the capacitances C1 and C2.
[3 Marks]

e) Using open-circuit time constant method, calculate the 3dB upper corner frequency, fH.
[5 Marks]

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EE001-3-2-AE Final Exam Page 3 of 5

2.

Figure Q2 shows a multi-stage common-emitter amplifier with feedback. Each transistor has a
forward current gain, β = 100. Assume that the hybrid-π resistances rb = 0, rµ = ∞ and ro = ∞.
At signal frequency, the coupling capacitances and bypass capacitances have zero reactance.

Figure Q2

a) Interpret the type of feedback topology used in the circuit shown in Figure Q2.
[2 Marks]

b) Using the appropriate two-port parameters, develop the expressions for the feedback factor
and loading impedances or admittances of the feedback network. [6 Marks]

c) Sketch the small-signal equivalent circuit of the amplifier in a form suitable for
determining the mid-band open loop gain. Include the loading effects of the feedback
network. [5 Marks]

d) Based on the circuit in (c), develop an expression for the mid-band open loop gain.
[6 Marks]

e) Given that the loop gain, βA of the amplifier is large, develop the expressions for the closed-
loop gain and closed-loop input impedance of the amplifier. [6 Marks]

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EE001-3-2-AE Final Exam Page 4 of 5

3.

a) Consider a basic inverting op-amp with closed-loop gain of ACL = -10, power supply of
±15V and the input voltage, vs(t) = 2cos(5t).

i) Sketch the expected output voltage, vo (t ) , waveform. [5 Marks]

ii) Interpret the issue faced by this type of op-amp and calculate the maximum input
voltage for the op-amp. [4 Marks]

b) Figure Q3 shows a difference amplifier where the resistor values are given by R1 = 50 kΩ,
R2 = 100 kΩ and R3 = 50 kΩ. In the non-ideal case the op-amp has the following DC
imperfections:

Input bias current : IB = 100 nA

Input offset current : Iio = ±20 nA
Input offset voltage : Vio = ±8 mV

Figure Q3

i) Produce the expressions for the output offset voltage VOS due to the input offset
currents IB+, IB- and input offset voltage Vio. [11 Marks]
ii) Compute the worst-case output offset voltage. [3 Marks]
iii) Explain the reasons for which causes the DC imperfections as mentioned above in
an op-amp. [2 Marks]

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EE001-3-2-AE Final Exam Page 5 of 5

4.

a) Figure Q4(a) shows the realisation of a Schmitt trigger. Assume that the saturation voltages
of the op-amp to be Vout = ±Vm.

Figure Q4(a)

i) With aid of equations, outline the transfer characteristics (Vout as a function of Vin).
[8 Marks]
ii) Produce the expression for hysteresis voltage, VH. [2 Marks]

b) By adding a RC feedback circuit between the inverting input and the output of the Schmitt
trigger, a square-wave generator can be formed as shown in Figure Q4(b).

i) With aid of diagrams, interpret the operation of the square-wave generator.

[10 Marks]
ii) Produce the equations for charging intervals (T1) and discharging intervals (T2),
showing the generated square waves are symmetrical. [5 Marks]

Figure Q4(b)

END OF FINAL EXAM

APU Level 2 Asia Pacific University of Technology and Innovation YYYYMMDD