WARNING: Be sure to complete the online portion of Flipped Lecture #2

before the start of lecture on Tue 26 Sep 2023 or you will lose marks.

CPEN 211: Introduction to Microcomputers

Slide Set 5: Sequential Logic

Instructor: Prof. Tor Aamodt

1
2
3
 9V LM7805 5V
1 3
2

SW3 SW4 VCC VCC

7404 7400
Battery n2 n4
U1
n1
U3
n3
U2 LED
n5

GND GND
R3 R2 R1

4
5
 Trigger
Sensor Design On / Off
This Alarm
Block
Reset

Specification:
Alarm goes on as soon as sensor pulse on “Trigger” is detected and then stays on until
“Reset” is asserted.

Trigger

Reset

Alarm

6
d q
D Q

clk
^

7
Other
than Other than L23
R31
A R31 B
locked locked

L23

Other Other
than than
R31 R5

D C
open R5 locked

8
 Sequential logic has state

Combinational Logic
Sequential Logic

9
Text: Dally §14.1
 qold
s qnew
r

10
Text: Dally §14.1
DeMorgan Graphically

11
 qold
s qnew
r

𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )

= ¬1 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )
= 0 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )

12
Text: Dally §14.1
 Axioms of Boolean Algebra
• Axioms: a set of mathematical statements
that we assert to be true.
• Identity:
– 0∧x=0
– 1∨x=1
• Idempotence:
– 1∧x=x
– 0∨x=x
• Negation:
– ¬0 = 1
– ¬1 = 0

13
Text: Dally §3.1
 qold
s qnew
r
a b AND
𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 ) 0 0 0
= ¬1 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 ) 0 1 0
1 0 0
= 0 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 ) 1 1 1

=0
14
Text: Dally §14.1
 qold
s qnew
r r s qold qnew
1 0 1 0
𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 ) 1 0 0 0

15
Text: Dally §14.1
 qold
s qnew
r r s qold qnew
1 0 1 0
𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 ) 1 0 0 0
0 0 0 0
= ¬0 ∧ (0 ∨ 0)
=1 ∧0
=0
16
Text: Dally §14.1
 qold
s qnew
r

𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )

= ¬0 ∧ (1 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )

17
Text: Dally §14.1
 Axioms of Boolean Algebra
• Axioms: a set of mathematical statements
that we assert to be true.
• Identity:
– 0∧x=0
– 1∨x=1
• Idempotence:
– 1∧x=x
– 0∨x=x
• Negation:
– ¬0 = 1
– ¬1 = 0

18
Text: Dally §3.1
 qold
s qnew
r r s qold qnew
1 0 1 0
𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 ) 1 0 0 0
0 0 0 0
= ¬0 ∧ (1 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )
0 1 0
=1 ∧1
=1
19
Text: Dally §14.1
 qold
s qnew
r

𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )

20
Text: Dally §14.1
 Reset-Set (RS) Latch

qold
s qnew
r

q=0 if r=1
q=1 if s=1 and r=0
and q holds last value if r=0 and s=0

What happens if s=1 and r=1?

Normally, we do not use an RS-latch this way.
21
Text: Dally §14.1
22
23
 Reset-Set (RS) Latch

qold
s qnew
r

q=0 if r=1
q=1 if s=1 and r=0
and q holds last value if r=0 and s=0

What happens if s=1 and r=1?

Normally, we do not use an RS-latch this way.
24
Text: Dally §14.1
 Reset-Set (RS) Latch
qold
s qnew
r

𝑞𝑞𝑛𝑛𝑛𝑛𝑛𝑛 = ¬𝑟𝑟 ∧ (𝑠𝑠 ∨ 𝑞𝑞𝑜𝑜𝑜𝑜𝑜𝑜 )

25
Text: Dally §14.1
 Reset-Set (RS) Latch

s ssss
s q
r r rrrr q

This is the more common way an RS-Latch

is drawn (does not follow bubble rule).

26
Text: Dally §14.1
 Gated RS Latch

s sg
1 1
clk 1
q
r0 0 rg 1

a b AND q=0 if rg=1

0 0 0 q=1 if sg=1 and rg=0
0 1 0
and q holds last value if rg=0 and sg=0
1 0 0
1 1 1 27
 Gated RS Latch

s sg
1 1→ 0
clk 1 → 0
q
r0 0 rg 1

a b AND q=0 if rg=1

0 0 0 q=1 if sg=1 and rg=0
0 1 0
and q holds last value if rg=0 and sg=0
1 0 0
1 1 1 28
 Gated RS Latch

s sg

clk
q
r rg

When clk is high, operates like a normal RS latch

When clk is low, maintains value, regardless of r and s
29
This is called level-sensitive, since the operation
depends on the level of the CLK signal.

30
 Gated RS Latch
s sg

clk
q
r rg

31
 Gated RS Latch
Equivalent circuit:
s sg’
q
clk

r rg’

32
 s
D sg’
0
0 Q
clk
1

1 r rg’

33
 s
D sg’
0
0
0
Q
clk
1

1 r rg’

For Gated RS-Latch:

When clk is high, operates like a normal RS latch
When clk is low, maintains value, regardless of r and s
34
 s
D sg’
1
1 Q
1
clk
0

0 r rg’

For Gated RS-Latch:

When clk is high, operates like a normal RS latch
When clk is low, maintains value, regardless of r and s
35
 s
D sg’
0
0 Q
1
clk
0

1 r rg’

For Gated RS-Latch:

When clk is high, operates like a normal RS latch
When clk is low, maintains value, regardless of r and s
36
 D Latch
s
D sg’
Q
clk

r rg’

If clk is high, Q becomes equal to D

If clk is low, Q maintains its value (regardless of D)

This is also level-sensitive

37
 Timing Diagram for a Level-Sensitive D-Latch

t1 t3 t4 t5 t6 t7 t8 t9 t10 t11
clk

Q x
U ?

time

38
39
 Lab 1 Top Level
neg_LEFT_Pushbutton LEFT_Pushbutton
neg_RIGHT_Pushbutton RIGHT_Pushbutton
A(3 downto 0)
4 ANDed_result
B(3 downto 0) AND
4 M Result(3 downto 0)
U
X 4
ADD ADDed_result

40
 Timing Diagram for a Level-Sensitive D-Latch

t1 t3 t4 t5 t6 t7 t8 t9 t10 t11
clk

Q x
U ?

time

41
Symbol for the level-sensitive D-latch:

D Q

Clk Q

42
 Hazards
a
ba
c 00 01 11 10 a
b v
c Delay d
0 0 1 1
0

0 1 3 2
1ns
Delay f
0 1 1 0 b 1ns
c

4 5 7 6 Delay e
c cN 1ns
b
Delay
a c
v
3ns

cN

d Static-1 hazard

f
Time: 0ns 1ns 2ns 3ns 4ns 5ns 6ns
43
Text: Dally §6.10
Wanted: Edge sensitive behavior

clk

D
Q

44
 Edge Triggered D Flip-Flop

Qm Qs
D D Q D Q

clock clk clk

This specific circuit implementation of D Flip-

Flop is called a “master-slave” flip-flop
45
Text: Dally §27.2 (you may ignore discussion of setup/hold time)
46
 D Flip-Flop
t1 t2 t3 t4 t5 t6 t7
clock

clock

Qm ?

x
time
 Verilog design style – for synthesizable
modules
1. Combinational modules use only
1. Assign statements
2. Case or Casex statements (with default)
3. If statements – only if all signals have a default assignment
4. Instantiations of other combinational modules
2. Sequential modules use only
1. Combinational logic
2. Explicitly declared registers (flip-flops)
3. Do not use
1. Loops
2. Always blocks except for case, casex, or if
4. Do use
1. Signal concatenation, e.g., {a, b} = {c, d}
2. Signal subranges, e.g., a[7:1] = b[6:0] ;
5. Logic is organized into small modules
1. Leaf modules not more than 40 lines
2. If it could be made two modules, it should be

(c) 2005-2012, W. J. Dally

Text: Dally §Appendix
 Verilog design style – for synthesizable
modules (page 2)
6. Use lots of comments
1. Comments themselves
2. Meaningful signal names – tempHigh, not th
3. Meaningful module names – DaysInMonth, not Mod3
7. Activation lists for case statements include ALL inputs (or use *)
8. Constants
1. All constants are `defined if used more than once
2. Width of all constants is specified 5’d31, not 31
9. Signals
1. Buses (multi-bit signals) are numbered high to low
• e.g., wire [31:0] bus
2. All signals should be high-true (except primary inputs and outputs)
10. Visualize the logic your Verilog will generate.
• If you can’t visualize it, the result will not be pretty

(c) 2005-2012, W. J. Dally

Text: Dally §Appendix
50
 Qm Qs
D

D Flip-Flop
D Q D Q

clock clk clk

t1 t2 t3 t4 t5 t6 t7
clock

clock

Qm ?

x
time
 D Flip-Flop
d q
D Q
• Input: D, Clock
• Output: Q clk
^

• Q outputs a steady value

• Edge on Clock changes Q to be D
• Flip-flop stores state
• Allows sequential circuits to iterate
52
Text: Dally §14.2
 Representing Information with Digital Signals

Binary Information Light On/Off: 1/0

Element of a set
000 White 100 Purple
001 Red 101 Orange
010 Blue 110 Green
011 Yellow 111 Black

Continuous Quantities: E.g., temperature

000 68 100 76 0000000 68 0001111 76
001 70 101 78 0000001 70 0011111 78
010 72 110 80 0000011 72 0111111 80
011 74 111 82 0000111 74 1111111 82

53
Text: Dally §1.3
 N-bit Register
N flip-flops, each storing an N-bit value:

d N N q
D Q

clk
^

54
Text: Dally §14.2
 Example: 4-bit Register
D0 D Q Q0

=
D1 D Q Q1

D Q
4 4
clock D2 D Q Q2

D3 D Q Q3

clock

55
 56
[Patt §3.6]
Other
than Other than L23
R31
A R31 B
locked locked

L23

Other Other
than than
R31 R5

D C
open R5 locked

57
[Patt §3.6]
 Synchronous Sequential Logic
next_state state
D Q

CL s s

input output
n m
clk

clk

input A B C

next_state SB=f(A,SA) SC=f(B,SB) SD=f(C,SC)

state SA SB SC SD
58
Text: Dally §14.2
 Hazards
a
ba
c 00 01 11 10 a
b v
c Delay d
0 0 1 1
0

0 1 3 2
1ns
Delay f
0 1 1 0 b 1ns
c

4 5 7 6 Delay e
c cN 1ns
b
Delay
a c
v
3ns

cN

d Static-1 hazard

f
Time: 0ns 1ns 2ns 3ns 4ns 5ns 6ns
59
Text: Dally §6.10
Voltage

Time
60
 Synchronous Sequential Logic
next_state state
D Q

CL s s

input output
n m
clk

clk

input A B C

next_state SB=f(A,SA) SC=f(B,SB) SD=f(C,SC)

state SA SB SC SD
61
Text: Dally §14.2
Example Sequential Circuit: Increment

n
n n
D Q
Adder
1 ^

clk

62
Text: Dally §14.2
Example: A Traffic-Light Controller

carew

63
Text: Dally §14.3
 Traffic Light FSM
• Finite state machine is specified by
– States, Inputs, Outputs
• Four states
– gns: Green north-south (red east-west)
– yns: Yellow north-south (red east-west)
– gew: Green east-west (red north-south)
– yew: Yellow east-west (red north-south)
• Input
– Carew: is there a car waiting on the east-west road
– Reset: return to initial state (need not go through yellow)
• Output: Two 3-bit traffic light signals (1-hot) (gyr gyr)
– 100 001: NS green, EW red; 001 010 NS red, EW yellow
64
Text: Dally §14.3
 One-hot representation
• Represent a set of N elements with N bits
• Exactly one bit is set to 1 (all other bits are 0)
• Example – encode numbers 0-7:

Binary One-hot
000 00000001
001 00000010
010 00000100
… …
110 01000000
111 10000000

65
Text: Dally §8.2
 Traffic Light FSM
• Finite state machine is specified by
– States, Inputs, Outputs
• Four states
– gns: Green north-south (red east-west)
– yns: Yellow north-south (red east-west)
– gew: Green east-west (red north-south)
– yew: Yellow east-west (red north-south)
• Input
– Carew: is there a car waiting on the east-west road
– Reset: return to initial state (need not go through yellow)
• Output: Two 3-bit traffic light signals (1-hot) (gyr gyr)
– 100 001: NS green, EW red; 001 010 NS red, EW yellow
66
Text: Dally §14.3
Complete Traffic Light State machine
¬carew | rst
carew & ¬rst ¬rst ¬rst

gns yns gew yew

100 001 010 001 001 100 001 010

rst

rst

state carew = car east-west sensor active

output = gyr gyr rst = reset
ns ew

67
Text: Dally §14.3
State Table (ignoring reset for now)
¬carew

carew

¬carew carew

68
Text: Dally §14.3
 State Assignment
• Assign values to encode each state (gns, yns,
gew, yew) on state and next_state signals

next_state state
D Q

CL s s

input output
n m
clk

69
Text: Dally §14.4
 One-Hot State Assignment

next_state state
D Q

CL s s

input output
n m
clk

70
Text: Dally §14.4
 Translating No-Reset FSM To One-Hot Controller
¬carew
carew * *

gns yns gew yew

100 001 010 001 001 100 001 010

*
ns ew

D Q D Q D Q D Q

^ ^ ^ ^
carew

clk

Input logic (one-hot states): OR of arrows into the corresponding state in state diagram.
71
Text: Dally §14.5
 Binary State Assignment (Gray Code)

next_state state
D Q

CL s s

input output
n m
clk
72
Text: Dally §14.4
Encoded state table and next-state K-maps

ns1
s1s0 s0
c 00 01 11 10
0
c 1
s1
ns1 = s0
73
Text: Dally §14.5
 Logic Equations

¬carew carew

74
Text: Dally §14.5
 Logic Equations

¬carew carew

75
Text: Dally §14.5
 Implementation of traffic-light
controller with binary state
assignment

carew

76
Text: Dally §14.5
Alternative State Table Representation
for Next State Logic

s1s0
s1s0 c ns1
ns1 ns0 output
output
00
00 0
0 0
0 0
0 100001
100001ns1 c ns0 c
c c
00
00 1
1 0
0 1
1 100001
100001 s1s0 0 1 s1s0 0 1
01
01 0
0 1
1 1
1 010001
010001 0 0 0 1

00

00
0 1 0 1
01 1 1
1 1
1 010001
010001 1 1 1 1
01

01
2 3 2 3
10
10 0 0 0 001010
s0

s0
0
1 1 0 0
11

11
10 1 0 0 001010 6 7 6 7

s1

s1
0 0 0 0
10

10
11
11 0
0 1 0 001100 4 5 4 5

11
11 1
1 1 0 001100

77
 Summary
• RS-latch remembers the past
• Gated RS-latch only changes its output when the clock
input is high
• D latch simplifies design by using a single input that
represents the value we want to store
• To simplify reasoning about delays in circuits we will
use the edge-sensitive D flip-flop in the labs
• To design a state machine we start with a state
diagram, create a state table then encode the states.
• To encode states use either a one-hot or grey code.

78