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Leakage in CMOS circuits - An introduction

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DOI: 10.1007/978-3-540-30205-6_5 · Source: DBLP

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 Leakage in CMOS Circuits – An Introduction

D. Helms1 , E. Schmidt2 , and W. Nebel1

1
OFFIS Research Institute
domenik.helms@offis.de,
http://www.lowpower.de
2
ChipVision Design Systems AG
D - 26121 Oldenburg, Germany

Abstract. In this tutorial, we give an introduction to the increasingly

important effect of leakage in recent and upcoming technologies. The
sources of leakage such as subthreshold leakage, gate leakage, pn-junction
leakage and further GIDL, hot-carrier effect and punchthrough are iden-
tified and analyzed separately and also under PTV variations.
Since leakage will dominate power consumption in future technologies,
we also review leakage optimization techniques and leakage estimation
approaches supporting optimizations especially at higher abstraction lev-
els.

1 Introduction
The three sources of power dissipation in digital CMOS circuits can be summa-
rized in the following equation:
2
Pavg = Pshort + Pswitch + Pstatic = Isc Vdd + αCL Vdd f + Ileak Vdd (1)
Between 1970 and 1980, the power consumption of a high-end processor rose
from 0.2W to 2W . Power was mainly consumed in the NMOS technology of
those days, since half of all transistors short-circuited their output to pull it
down to logic 0. In the early 1980’s, the first power-aware technology, the CMOS
technology was introduced. It was able to reduce the power requirements to levels
that much less complex systems some 10 years ago consumed. Static power Pshort
as the major contributor to the systems power consumption seemed to have been
removed for good.
A small remaining Pshort in CMOS logic is due to the direct path short
circuit current Isc , which occurs when both the NMOS and PMOS transistors
are simultaneously active, conducting current directly from supply to ground.
The second term of Equation 1, Pswitch , refers to the dynamic component of
power, where CL is the load capacitance, f the clock frequency and α the node
transition activity factor. Pswitch , which is dominating power consumption in
today’s circuits has been reduced by various techniques like voltage and threshold
voltage scaling since then.
It is exactly these techniques which lead to another change in power consump-
tion dominance. Prognoses [1] assume that in the middle of this decade static
effects will again become the most dominant source of power consumption.

E. Macii et al. (Eds.): PATMOS 2004, LNCS 3254, pp. 17–35, 2004.


c Springer-Verlag Berlin Heidelberg 2004
18 D. Helms, E. Schmidt, and W. Nebel

As analyzed in [2, 3, 4], leakage currents can be divided into 6 major contrib-
utors which will be reviewed in Section 2. In Section 3, we discuss the impact of
PTV1 variations on leakage currents. Section 4 presents existing work on high-
level leakage modeling under PTV variations and Section 5 introduces leakage
optimization techniques. Finally, Section 6 concludes this work.

Fig. 1. The 6 most prominent leakage mechanisms inside a MOS transistor

2 Leakage Sources in MOS Transistors

A MOS transistor can be represented as an electrical device with 4 different

potentials: source ϕS , drain ϕD , gate ϕG and bulk ϕB of which ϕB can be
assumed to be 0 and the others can be described as the potential difference to
bulk (e.g. VD = ϕD − ϕB = ϕD ).
In a classical view of a semi-conductor, we assume the connection between
each pair of these potentials to have a nearly infinite resistance except for the
drain-source connection for which the resistance of course can be switched by
the gate voltage between high and low impedance.

Table 1. Occurrence of the leakage mechanisms for different n-channel transistor

states. Due to low drain-source resistance for VG = 1, VD and VS can just differ
transiently

VG VD VS Sub-th Gate pn-jun. GIDL punch HCI

0 0 0 - - - - - -
√ √ √ √ √
0 0 1 -
√ √ √ √
0 1 0 - -
√ √
0 1 1 - - - -
√
1 0 0 - - - - -
√ √
1 1 1 - - - -

1
Process, thermal and voltage variations
 Leakage in CMOS Circuits – An Introduction 19

As the feature size and all related technology parameters continue to be

scaled down aggressively, the resistances become lifted to dimensions in which
they markedly influence as well the transistor’s functional behavior as the power
behavior. Leakage currents in MOS transistors can be divided into 6 different
mechanisms, occurring in different states as shown in Table 1. In the following,
we will review each of these mechanisms.

2.1 Subthreshold Current

In Figure 2 (left) the drain to source current, which is shown mainly depends
on the gate voltage. The curves can be separated at the threshold voltage into a
linear rising and a saturating, almost constant region. Even if the gate voltage
is low - far below this threshold voltage - the current through the channel is not
exactly 0. This is because a transistor is not a simple switch but in contrast to a
high-level view it is a complex analog component. A potential difference between
source and drain will thus result in a current through the channel which is called
subthreshold current. This is the best-known kind of leakage and it also has
the highest impact on the overall static power consumption at least for recent
technologies [5].

Fig. 2. Left: Drain to source current versus gate voltage for different drain voltages
taken from [4]. The drain voltage’s effect on drain-source current can be explained by
second order effects like DIBL, reducing the threshold voltage and GIDL, decreasing the
junction’s barrier. Right: Plot of Equation 3: subthreshold current versus temperature
for different threshold voltages.
20 D. Helms, E. Schmidt, and W. Nebel

In the weak inversion region, the subthreshold current’s dependence on the

most important technology parameters is given is [6, 7] as


ISU B = KVT2 (W/L) e(Vgs −Vth )/(nVT ) 1 − e−Vds /VT , (2)

where 
Cdm qsi Nch
n=1+ and K = µ0 (3)
Cox 2Φs
are technology parameters, W and L are the channel’s width and length, and Vds
is the drain-source, Vgs is the gate source voltage. VT = kB T /q is the thermal
voltage, which is a direct proportional measure to the absolute temperature, as T
is the temperature, kB is the Stefan-Boltzmann-constant and q is the elementary
charge. µ0 is the zero bias mobility, Nch is the effective channel doping, ΦS is
the potential of the surface and Cox and Cdm are the capacitances of the oxide
layer and the depletion layer. From Equation 3 we can immediately derive the
subthreshold current’s dependencies to different technological and dynamical
parameters. As can be seen in Figure 2 (right) where Equation 3 is evaluated for
different temperatures and threshold voltages, the subthreshold current varies by
several orders of magnitude as threshold voltage and temperature just differ by a
few ten percents. For upcoming technologies Figure 2 determines the following:
as the threshold voltage continues to be scaled down, the temperature’s influence
is decreased. In order to analyze this behavior in detail we evaluate the deviations
∂/∂Vth ln (Isub ) and ∂/∂T ln (Isub ), assuming independence between Vth and VT
and a high drain-source voltage Vds .
 −1
∂ ln (Isub ) nkB T
=− (4)
∂Vth q
 −1  
∂ ln (Isub ) nkB T 2 1
= (5)
∂T 2 q (Vth − Vgs ) + nkB T
Using Equations 4 and 5 and assuming Cdm = 2Cox ⇒ n = 3, the importance
of temperature and threshold voltage can be evaluated as presented in Table 2.
Since subthreshold leakage is the most important leakage mechanism in re-
cent technologies, it is worthwhile analyzing effects that influence subthreshold

Table 2. Dependence of the subthreshold current to threshold and temperature vari-

ations in Millivolt and Kelvin per decade change. As can be seen, the temperature
dependence is reduced the more the threshold voltage is scaled down: for a Vth = 1V
technology, subthreshold rose by a factor of 10 every 20.2K, for a Vth = 0.5V technol-
ogy, the temperature has to rise by 35.5K to have the same effect.

T [K] Vth [V ] ∆V [mV /dec.] ∆T [K/dec.]

300 1.0 −77.6 20.2
300 0.5 −77.6 35.5
400 1.0 −103.5 34.3
400 0.5 −103.5 58.6
 Leakage in CMOS Circuits – An Introduction 21

leakage. Besides the temperature, dynamically influencing the subthreshold cur-

rent, there are two more dynamical effects, which are the body effect and the
DIBL, increasing leakage by decreasing the threshold voltage which is given
as [8, 9]

π Nsub Xd2
Vth = Vf b + ΦS + q
2 Cox W
  
λXd
+ γ ΦS − Vs 1 −
Lef f


+ VDS e−L/2lc + 2e−L/lc .

Narrow Width Effect and Vth Roll-Off. In this simplified equation (ref.
[10] for more details), the first line describes the static component of threshold
voltage, with Nsub being the substrate doping and Xd being the width of the
depletion zone, Vf b is the flat-band voltage, the voltage at which there is no
electrical charge in the semiconductor. Xd is the thickness of the depletion layer,
γ is the body factor, ΦS is the surface potential and λ ≈ 1 is a fitting parameter.
In addition, Vth can be reduced by Vth roll-off due to an effective length reduction
of the channel. In short channel devices this simple relation is changed by a high
influence of the source and drain depletion regions to the channel’s potential
profile [6].

Body Effect. The body effect is described by the second line of the threshold
equation. Without going into detail [4], it can be linearized to a source-bulk
voltage dependent threshold voltage shift

∆Body (Vth ) = η  Vs . (6)

We can see that via the body effect, the source-bulk voltage can decrease the
subthreshold current by increasing the subthreshold voltage. As will be described
in Section 3.5, this is the main reason for data dependent leakage in CMOS
circuits, called stacking effect.

Drain Induced Barrier Lowering DIBL. The last line shows a drain-source
voltage dependent shift ∆DIBL (Vth ) where

Si Tox Xd
lc = (7)
ox η

is the characteristic length of a MOS transistor. As can be seen in Figure 2 (left),

the DIBL biases especially the transistor’s off-current.
22 D. Helms, E. Schmidt, and W. Nebel

Table 3. Prediction of the development of the subthreshold current Isub , the BTBT-
current Ipn−jun and the gate tunneling current Igate as an approximation derived
from [1, 10]

Generation Year Isub Ipn−jun Igate

90nm 2004 840pA 25pA 13pA
50nm 2010 21nA 3.0nA 52nA
25nm 2016 260nA 120nA 510nA

2.2 Gate Leakage

Subthreshold leakage is the major source of static current in recent technologies.

But today, static currents are just a small problem at all2 , since they are limited
to about 10% of the overall power consumption for high performance applications
and to below 20% for mobile applications.
For upcoming technologies the exponential rise of leakage will lead to a leak-
age domination in terms of power. The break-even point of dynamic vs. static
power for logic gates will be reached with the 65nm technology.
Gate leakage is almost negligible today, as subthreshold is approximately 60
times as high (ref. Table 3). But as subthreshold will rise by a factor of 25 from
the 90nm to the 50nm technology, gate leakage will rise by the factor of 4000 at
the same time - thus overtaking subthreshold in terms of importance. According
to [11], gate leakage alone will have a contribution of 15% to the total power
consumption in a 2004 technology generation device3 . Thus it is worthwhile to
regard other sources of leakage as well - starting with gate leakage in this section
and reviewing pn-junction leakage in the next one.
Gate leakage mainly consists of one major effect, the gate tunneling, and one
minor effect: hot carrier injection.

Gate Tunneling. Gate tunneling is the effect of carriers having a finite proba-
bility tunneling in or through the SiO2 layer, isolating the gate from the channel.
When the gate voltage is high, the carriers inside the gate will see an energy band
potential as presented in part a) of Figure 3 which is easy to handle quantum
mechanically. Due to the gate bias, the conduction band of the oxide layer is bent
to a trapezoidal shape4 as presented in b) of Figure 3. Depending on the barrier
height Φox of the oxide layer and the gate bias Vox , only one of two possible gate
tunneling mechanisms will occur:
2
Except for ultra-low power devices like hearing aids and devices with a very low
average switching activity like memories
3
The dominance of the gate leakage may be avoided due to the introduction of high-k
materials (ref. Section5.1).
4
Of course also the energy bands of the gate and the channel are bent, but this can
be ignored for the sake of simplicity
 Leakage in CMOS Circuits – An Introduction 23

Fig. 3. Gate tunneling in a MOS transistor [4]. a) Tunneling at a rectangular obstacle.

b) Introducing gate bias results in a trapezoidal reshape of the insulators energy bands.
c) Fowler-Nordheim tunneling into the insulators conduction band. d) Direct tunneling
through the insulator: conduction band to conduction band electron tunneling, con-
duction band to valence band electron tunneling and conduction band to conduction
band hole tunneling.

Fowler-Nordheim Tunneling. In the case of Vox > Φox the carriers need
not have to tunnel through the entire oxide layer as shown in part c) of Figure
3. Instead, the carriers just have to pass a triangular energy potential of the
reduced width TF N < Tox . Fowler-Nordheim tunneling carriers pass directly
from the semiconductors conduction band to the insulators conduction band.
Knowing Φox and the field across the insulator Eox , the total FN-tunneling
current Igate−f n can be calculated as [6]
√ 3/2
Lg Wg q 3 Eox
2
4 2m Φox
β
Igate−f n = αe with α = , β = − , (8)
16π 2 h̄Φox 3h̄qEox
where Lg and Wg are the effective gate’s length and width subjected to FN-
tunneling, q is the carriers charge, h̄ is Planck’s constant over 2π and m is the
effective mass of a carrier in the conduction band of silicon. But as for SiO2
Φox = 3.1eV , FN-tunneling is nearly negligible as usually Vox < Φox .

Direct Tunneling. In most cases, gate leakage current is carried by electrons

or holes, directly tunneling through the complete oxide layer - thus passing a
trapezoidal obstacle. With today’s insulator thickness of 20 − 30Å and a pro-
jected thickness of 15 − 20Å in the next five years [1], the tunneling probability
will lead to dominant static currents5 .
5
For 2006, the ITRS [1] determines gate leakage to be too high for today’s oxi-nitride
insulators
24 D. Helms, E. Schmidt, and W. Nebel

Direct tunneling occurs in 3 possible ways as shown in part d) of Figure 3:

Electrons may tunnel from the Conduction or the Valence band. Additionally,
holes can tunnel through the channel in inverse direction. As for all these effects
the energy barrier has the same shape, only the effective height of the obstacle
and the effective mass of the carrier differ, so that all 3 effects can be calculated
by

3/2
Igate−dt = α exp β − β [1 − Vox /Φox ] , (9)
using the same α and β as introduced in Equation 8.
In [12], the gate leakage Equations 8 and 9 are approximated and empirically
reduced to the parameters W , Tox and VDD as [2]
 2
VDD
Igate = K · W e−αTox /VDD (10)
Tox
where K and α can be derived experimentally or numerically.

Hot Carrier Injection HCI. In the pinch-off region of the channel, large
voltage drops result in high electric fields. Mobile carriers in high electric fields
may lead to leakage losses by a variety of mechanisms [13] as shown in Table 4.
These high-energy carriers are called hot-carriers. Carriers with energies above
the ionization threshold of 1.3eV are able to strike out electrons from their
orbit, thus producing electron hole pairs with arbitrary directions, which is called
impact ionization. The energy of some of the carriers moving towards the gate-
insulation is high enough to pass the insulator barrier. Since the barrier height
of SiO2 for electrons (≈ 3.1eV ) is lower than that for holes (≈ 4.8eV ), hot-
electron injection is more likely to occur than hot-hole injection. In addition, as
the mobility of holes inside the SiO2 barrier is lower than that of the electrons,
more holes get trapped in the insulator before reaching the gate.

Table 4. Leakage mechanisms due to high field electrons

CarrierEnergy M echanism
E > 1.12eV Light emission
1.3eV < E < 1.8eV Impact ionization
E > 3.1eV Hot-electron injection
E > 4.8eV Hot-hole injection

2.3 pn-Junction Leakage

The behavior of a pn-junction in the reverse-biased situation is well known from
the analysis of reverse biased diodes. The two classical but marginal mechanisms
causing pn-junction current are the diffusion by drift of minority carriers [14] and
electron-hole generation in the depletion region. For transistors, the gate also
introduces gated diode device action in the drain-bulk junction under the gate.
 Leakage in CMOS Circuits – An Introduction 25

Fig. 4. Left: Band-to-band tunneling in a reverse biased pn-junction. BTBT requires a

junction bias Φbi +Vapp higher than the band gap Σg , thus the n-side’s conduction band
to be lower than the p-side’s valence band. Right: Geometry of the pn-junction and
the 3 main reverse bias pn-junction leakage mechanisms: a) minority carriers drifting
through the junction b) electron-hole generation in high fields c) tunneling through the
junction.

Band-to-Band Tunneling. With a rising doping concentration, a further ef-

fect dominating pn-junction leakage appears. It is caused by a direct tunneling
of electrons from the p-side’s valence band to the n-side’s conduction band.
Due to energy conservation reasons, electrons can never tunnel upwards in an
energy-band view but just downwards, getting rid of the extra energy by emission
of a phonon. Thus, band-to-band tunneling can only occur if the voltage drop
across the junction, consisting of the reverse bias Vapp and the built-in voltage
Φbi , is higher than the silicon band gap Σg , as shown in Figure 4 (left).
The band-to band tunneling current approximately results [8] as

3/2
AEside Vapp BΣg
IBT BT −side = Wef f Yj−ef f 1/2
exp − and (11)
Σg Eside

3/2
AEbtm Vapp BΣg
IBT BT −btm = Wef f Xj−ef f 1/2
exp − where (12)
Σg Ebtm
√ √
2m q 3 4 2m
A= and B = (13)
4π 3 h̄2 3qh̄

are constants. In order to handle the complex geometry of this problem, average
effective electric fields for the junction below the source or drain Ebtm and for the
junction between source and drain Eside as effective height Yj−ef f and length
Xj−ef f of the junction was introduced (refer [8] for the details).

2.4 Gate Induced Drain Leakage GIDL

Gate induced drain leakage GIDL describes the influence of the gate-field on
the depletion layer of the drain. The higher the gate voltage, the thinner the
depletion layer becomes in the gate-drain overlap area. According to [15], GIDL
currents are carried by an increased band-to-band tunneling probability which
is given by
26 D. Helms, E. Schmidt, and W. Nebel


IGIDL = A · Es (Vgs ) exp − Es (V
B
gs )
(14)
1/2 1/2
2πq 2 mef f πmef f Σg
where A = 3/2 and B = √ , (15)
9h̄2 ΣG 8qh̄

where Es is the field of the surface, which is dependent on the gate-source voltage,
approximately given by
Vg − 1.2V
Es ≈ . (16)
3Tox

2.5 Punchthrough

A transistor’s source and drain depletion region are of course no rectangular

regions; instead, the junction lines follow a complex field-dependent profile. With
shrinking device size the effective field strength is rising because voltage is scaled
much slower than geometric properties.
Thus, for high voltages in short channel devices, the depletion regions may
be enlarged in such a way, that they electrically touch deep in the channel, which
leads to a punchthrough current flow.

3 Impacts on Leakage

In the last section, we reviewed what leakage is from a transistor level point of
view. We have seen that all these leakage sources depend on parameters - static
ones like gate length L as well as dynamic ones like temperature. From the
system level point of view, we can identify several processes having a high im-
pact on leakage currents. In this section, we will review the most prominent ones
which are process-temperature-voltage variations (PTV variations) and data de-
pendency, starting with leakage dependence on process variations. Then we will
discuss variations of the two most important dynamical parameters, temperature
and power supply. In the end we will discuss aspects of data-dependent leakage.

3.1 Inter-die Variations

Inter-die variations, also called die-to-die variations, are the collection of effects
on leakage due to variation of circuit parameters that vary from die to die. Vari-
ations in the coating, doping and etching processes will lead to slight variations
in structure sizes and doping profiles. In [16], the leakage power due to these
variations was reported to vary by a factor of 20 between the best and the worst
die on a waver.
As inter-die variations describe the variation of the total leakage power of
different dies, they cannot be used to forecast a single die’s leakage power. But
statistical approaches [17], predicting average leakage current and variation, at
least allow a prediction of the yield-loss due to too high leakage power.
 Leakage in CMOS Circuits – An Introduction 27

3.2 Intra-die Variations

Intra-die variations, also called within-die-variations, are co-generated between
design and process, depending on the details of the design [18]. They can af-
fect leakage by causing threshold voltage changes and effective length variations
spread over the die. They also must be handled in a statistical way as only
average value and variance of the process parameters are known. But in con-
trast to inter-die variations, intra-die effects affect the power distribution of the
transistors of a single system.
The intra-die variation’s influence e.g. on the subthreshold leakage (ref. Equa-
tion 3) can be modeled by a geometric approach [19] derived from the real
physical level. Considering intra-die variations of the channel length results in a
bimodal distribution as
σ2 2
Ip0 wp 2λp2 I 0 wn σn
Ileak = e p + n e 2λ2n , (17)
kp kn
where wp and wn are the total device width in the chip; kp and kn are factors to
determine the percentage of PMOS and NMOS device widths that are in OFF
state; Ip0 and In0 are the expected mean subthreshold leakage currents per unit
width of PMOS and NMOS devices; σp and σn are the standard deviations of
the channel length variation within a particular chip; λp and λn are constants
that relate channel length of PMOS and NMOS devices to their corresponding
subthreshold leakages.
The average leakage current sums up to the respective multiple of the leakage
current’s mean value. Using Equation 17, the expected overall deviation of the
summed up leakage resulting from an intra-die varying channel length of σp and
σn can then be estimated as
  
k Ileak
σ = λ 2 ln . (18)
w I0

The same approach can be used (starting with another equation) for other
sources of leakage, always leading to a prediction of the influence of parameter
variations to the power consumption distribution.

3.3 Thermal Variations

Leakage current, especially subthreshold current is very sensitive to the tem-
perature. This temperature at a specific gate and time depends on the power
behavior over time of all other surrounding gates P (− →x , t). In addition global
parameters like ambient temperature and state of the cooling device should be
regarded. Thus, for a precise thermal leakage analysis, a complete system (in-
cluding package and cooling device) must be regarded as a complex network of
heat sources and sinks. Due to the high number of inhomogenities, the tempera-
ture distribution inside the system and even the two dimensional one of the die’s
surface is a complex function, even for a simple steady state solution evaluation.
28 D. Helms, E. Schmidt, and W. Nebel

Due to the exponential leakage-temperature relation accurate thermal models

are essential: as can be seen from Table 2, for the chosen parameters T = 300K
and Vth = 1.0, a temperature difference of 1K is sufficient to increase the leakage
by 12%. Useful approaches trying to handle thermal variation are presented in
Section 4.3.

3.4 Power Supply Variations

Varying supply voltage caused by supply voltage drops (IR-drops) can signifi-
cantly affect the leakage on an IC. For VDD noise calculation, the package can
be regarded as an effective coil of inductance L. The grid can be modeled by a
capacitive and resistive system with Rg being the grid’s resistance and Cd and
Rd describing the grid’s de-cap in parallel to the load [20].
The load, i.e. the complete number of gates, can be described by a varying
resistance RL (t). With the mean supply voltage VDD given, the current deviation
µ can be calculated as
VDD
µ= (19)
dR/dt
and the VDD noise thus results as [18]

dVDD (t) /dt = µtRg + µL − µRd2 Cd (1 − et/τ ) (20)

where τ is the inverse characteristic frequency of the system.

3.5 Data Dependency

In the first place, the leakage of a transistor is just determined by its state - ON
or OFF . Of course, in CMOS designs the number of transistors being ON is
exactly known, because for every transistor in the ON state, there is a transistor
in the OFF state in the other half of the CMOS logic. But of course there are
effects that introduce a data dependency of the leakage current.

Stacking Effect. A single inverter’s leakage is low in terms of data-leakage

dependency with a difference of 2 to 3 between ON and OFF state. But as soon
as more than one transistor is used in the complementary networks, leakage
shows huge data dependency as presented in Table 5 from [21].
As can be easily seen, the gate’s overall leakage current can vary by factor
50 between different states. This can be explained as follows [22]: If a transistor
which is switched OFF is placed between the supply and a transistor of which
leakage current has to be estimated, the first transistor will cause a slight reverse
bias between the gate and the source of the second transistor. In this situation,
the body effect will increase the threshold voltage and the reduced drain-source
voltage will reduce DIBL and thus effectively further increase threshold voltage
(ref. Equation 6). Because the subthreshold current (the most dominant leakage
current in actual designs) is exponentially dependent on the threshold voltage,
a substantial leakage reduction is obtained.
 Leakage in CMOS Circuits – An Introduction 29

Table 5. Example of the data dependency of the leakage currents of the NAND and
the NOR gate.

Inputs Leakage
power [pA]
AB NAND NOR
00 10 308
01 173 540
10 304 168
11 544 112

Table 6. Example of the minimal and maximal leakage current of various circuits
dependent on the input vector.

Circuit # cells Imin [µA] Imax [µA] σ[%]

c432 187 59.7 73.9 2.4
c499 222 154 215 3.4
c880 383 95.8 132 3.4
c1355 566 128 173 3.0
c1908 996 211 313 6.1
c2670 1255 325 427 3.6
c5311 2485 670 842 2.8
c7752 3692 665 714 4.8

But as reported in [23], the data dependency of bigger systems seems to even
out this effect as presented in Table 6.
As can be seen, the relative standard deviation σ is below 6.1% for all an-
alyzed circuits. Thus, for high-level leakage analysis and optimization, data-
dependencies are not the most necessary topic. Nevertheless, there are approa-
ches that try to handle the components leakage dependency (ref. Section 4.1).

4 High-Level Leakage Estimation Techniques

In Section 2 low level analysis of leakage was presented as a set of equations
using in-detail technology information. Section 3 then explained why several of
these parameters are not accurately available at low abstraction levels. Further-
more, as the leakage power problem emerges, leakage awareness will become a
severe design constraint. Leakage optimization has to be addressed during the
complete design flow and thus leakage estimation should be available at all levels
of abstraction. As Section 2 also provided lowest level estimation equations, this
section briefly reviews proposed higher level estimation techniques.

4.1 High-Level Data-Dependent Leakage Analysis

[22] tries to accurately model the exact influence of a transistor stack. This
approach results in highly accurate predictions, but of course needs gate level
30 D. Helms, E. Schmidt, and W. Nebel

information which makes it prohibitive in terms of computational effort in the

domain of high-level modeling.
The approach of [23] is a little more abstract. Here, statistical measures
are propagated through the components. The outcome is a nth order Taylor
expansion of the leakage current depending on the single component’s inputs.
Correlation between the inputs comes with the higher correlation terms. This
approach is called leakage sensitivity. It has an estimation error of below 4%
relative standard deviation.
[24] is a highly sophisticated leakage estimation approach where a feed for-
ward neuronal network is used to distinguish between states of related leakage
behavior. Even though it is very easily evaluated, the estimation capabilities are
good for single gates, but poor for complex circuits.

4.2 A Static Power Model for Architects

Butts et al. [25] have proposed a relatively simple empirical static power model
for architects. The leakage power is calculated as

Pleak = Vdd N kdesign Ileak (21)

where N is the number of transistors of the design, kdesign is a design dependent

parameter and Ileak is a technology dependent parameter. This equation allows
to separate the contributions in a high-level and a low-level dominated factor:
Ileak depends on technology parameters like Vth , while kdesign depends on design
parameters like the fraction of transistors at logic one.
Separating the supply voltage Vdd and the number of transistors in Equation
(21) is just a first order correction which is quite straight-forward. This does not
mean that in reality the remainder, kdesign and Ileak , is independent of supply
and transistor count.
While the Ileak parameter is relatively well defined and easily tractable, the
problems obviously arise when trying to predict the kdesign parameter. The pa-
rameter can only be determined empirically and will then represent the char-
acteristics of an average device and is meant to be approximately constant for
similar designs.

4.3 A Temperature-Aware Static Power Model for Architects

(HotLeakage)
The approach of Section 4.2 is simplistic and there are further approaches trying
to increase its estimation capabilites, to cope with its flaws and to introduce
further parameters like temperature. [26,27] introduces a modified leakage model,
which has the same structure as Equation (21) but where the definition of the
parameters is refined.
Like in Section 4.2, Vdd and N are the supply voltage and the number of
transistors in the design. But in contrast to Section 4.2, the definition of kdesign
is separated for N and P transistors into kn and kp . For calculation of Ileak , the
 Leakage in CMOS Circuits – An Introduction 31

authors tried to separate every physical effect in order to make the remainder
as invariant as possible. Ileak is defined as
 −Vdd
 −|V |−V
W b(Vdd −Vdd0 ) th of f
Ileak = µ0 · COX · ·e · VT2 · 1 − e VT · e n·VT , (22)
L

which is the subthreshold leakage equation. The low level parameters can
be derived using transistor level simulations. Vdd is the current supply voltage,
Vdd0 is the nominal default supply voltage which is technology dependent. The
parameters µ0 , COX , W/L and Vdd0 are absolutely invariant with all parameters
in this approach and only depend on the technology used. In contrast, the DIBL
factor b, the subthreshold swing coefficient n and Vof f are derived from a curve
fitting on measurements based on transistor level simulations. Vdd , Vth and Vt
are calculated dynamically during the estimation [26].

5 Leakage Optimization Techniques

5.1 Transistor Engineering for Performance-Leakage Tradeoff

While scaling down devices, the parameters of a transistor have to obey the rules
of constant field scaling in order to control the performance, the reliability and
the power consumption of a device: starting at a gate length scaling factor of
k, Tox and junction thickness have to be scaled the same way in order to keep
short channel effects (SCE) under control. Down-scaling VDD is then necessary
to keep fields constant in order to prevent high field effects like hot-electron
effects. Since VDD reduction would immediately reduce performance, Vth has to
be scaled as well too to compensate.
This way, nearly every degree of freedom of choice of parameters is fixed. The
remainder of leakage optimization on transistor level is mainly due to modifying
the doping profile and the dielectricity of the oxide [4].

Well Engineering. There are two doping techniques, mainly influencing leak-
age power. Halo doping means increasing the doping level of the p-substrate
close to the inversion layer. It was introduced in order to limit the influence of
the channel length on the threshold voltage. Thus, halo doping also limits drain
induced barrier lowering by ’guarding’ the ends of the channel, lowering drain’s
and source’s influence.
Retrograde doping means changing the doping profile of the bulk in vertical
direction: Directly under the oxide layer the doping concentration is lowered and
deeper towards the bottom it is increased. Retrograde doping was introduced in
order to shift the channel away from the impurities in the oxide interface thus
reducing scattering at impurities. This technique increases threshold voltage and
thus reduces subthreshold currents, but the high-p doped layer also acts as a
punchthrough protection ’guarding’ the bottom of the channel.
32 D. Helms, E. Schmidt, and W. Nebel

Oxide Dielectricity. In most cases, modifying the channel’s doping profile

reduces drain-source leakage effects such as subthreshold, punchthrough and
DIBL. In order to minimize gate-bulk leakage, the dielectricity of the gate in-
sulator is the key parameter. By introduction of other high-k6 materials with
k > 25 factors, gate tunneling can be reduced by several orders of magnitude
thus possibly pushing away the gate leakage problem for a very long time. The
ITRS [1] projects introduction of high-k techniques for the end of this decade.

5.2 Low Leakage with Conventional Technology Using Transistor

Stacking Effect

As seen in Section 3.5, the subthreshold leakage of a gate differs markedly for
different input combinations due to the stacking effect. Without the need for a
special low leakage technology, this can be used in two different ways:
At first, idle components can be set to a low leakage state. Finding low
leakage states can be done by testing all 2n states for an n input component or
by applying heuristic approaches [21]. Using state assignment, 5-30% of leakage
power can be saved during idle time, where the overhead for generating this state
as for switching to this state is not taken into account.
Another way of using stack effect is called power gating and is done by
inserting a sleep-transistor in series to the CMOS gate [28]. By doing power
gating, 35-90% of the leakage can be saved in idle phases but at the cost of a
5-60% performance loss.

5.3 Usage of Special Low-Leakage Technologies

Assuming that all possible techniques presented in Section 5.1 are performed
resulting in transistors with the lowest possible leakage under performance con-
straints, we have to increase the level of abstraction in order to further reduce
leakage power.
There are several techniques reported which all work by identifying avail-
able slack in the gate net-list and then assigning lower performance components
with better power behavior to the gates, having sufficient slack that the timing
constraints of the circuit are not violated.
These approaches differ in the way the performance-power tradeoff are biased,
the way they performed and the way the gates are replaced.

Multiple Threshold. The multiple threshold technology (MTCMOS) contains

conventional transistors with low threshold and thus high performance and high
leakage power and contains high threshold transistors where leakage currents are
reduced for the cost of performance.
6
k is the dielectricity constant of a material
 Leakage in CMOS Circuits – An Introduction 33

The threshold can be increased by reducing the doping concentration of the

channel, by enlarging the channel length L, by modifying the body bias7 or by
enlarging the oxide thickness. All methods reduce subthreshold leakage, but the
oxide thickness enlargement has further advantages: As tunneling probability
exponentially depends of the thickness of the barrier, also gate leakage can be
reduced. In addition, the gate capacitance is reduced as the oxide thickness is en-
larged. Thus this technique also reduces dynamic power consumption. Beneath
all these advantages, the disadvantage of Tox scaling is that short channel ef-
fects are increased and consequently the channel length has to be enlarged to
compensate Vth rolloff.

Multiple Vdd . Vdd reduction was proposed quite early because it is also a very
powerful dynamical power countermeasure. Since the total leakage power results
as a product of supply voltage and leakage current Pleak = Ileak Vdd , leakage
depends at least linearly on the supply voltage. But also potential dependent
leakage effects like DIBL are reduced. [29] reports a reduction in the order of
Psubth ∝ Vdd
3
and Pgate ∝ Vdd
4
.
Multiple voltage techniques have highest impact on the power consumption,
but the overhead for supplying several voltages to the gates and the need of
introducing level shifters make it more inconvenient to use.

5.4 Thermal Control

As we have seen in Section 5.1, by using high-k insulators gate leakage can be
sufficiently reduced by a design modification that is very simple to understand,
even though it is not that easy to really perform. Gate leakage is one of the two
most important leakage sources - at least for the next 5 years. The other one, the
subthreshold current, can also be reduced by orders of magnitude by a technique
that again is simple to understand but maybe not that easy to perform:
Since small temperature differences lead to huge leakage variations, aggressive
cooling techniques up to cryogenic cooling can be applied.
Cooling techniques can strongly control subthreshold current by reducing it
by several orders of magnitude.

6 Conclusion

Leakage power will become a major issue for upcoming technologies. Leakage
analysis will become more complex as different leakage sources like gate leak-
age and band-to-band tunneling gain influence on the total power. A complete
framework for high-level leakage estimation may be available soon as this is one
major recent research concern. High-k materials and aggressive cooling may be
7
This can easily be done for silicon on insulator SOI techniques. For conventional
techniques multiple well techniques have to be applied in order to allow varying
bulk voltages
34 D. Helms, E. Schmidt, and W. Nebel

the solution to leakage problems for future technologies, but the recent and up-
coming technologies have to be controlled by more conventional, less invasive
optimizations. As on lowest levels a lot of optimization was proposed, higher
level approaches addressing leakage are missing so far.

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