Professional Documents
Culture Documents
Amit Nevase
Lecturer,
Department of Electronics & Telecommunication Engineering,
Karmaveer Bhaurao Patil Polytechnic, Satara
PO 5. The engineer and society: Assess societal, health, safety, legal and cultural
issues and the consequent responsibilities relevant to practice in field of Electronics
and Telecommunication engineering.
Total
Cred Examination Scheme
Teaching
its
Scheme
(L+T Theory Marks Practical Marks
+P)
04 -- 02 06
3 70 28 30 00 100 40 25# 10 25 10 50 20
Total 64 18 22 30 70
Drawbacks of SR FF
of IC 7474, IC 7475.
9/16/2018 Amit Nevase 15
Unit IV – Sequential Logic Circuit
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
(DAC).
Bit 2 Bit 2
Bit 3 Bit 3
…………….……..
…………….……..
To control
Physical
Transducer
n-bit Digital n-bit Variable
Variable
ADC System DAC
Actuator
Bit n-1 Bit n-1
Bit n Bit n
Digital Digital
Inputs Inputs
9/16/2018 Amit Nevase 24
Types of Data Converters
Data Converters
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Where, K is the proportionality factor and constant value for a given DAC.
9/16/2018 Amit Nevase 28
Unit V – Data Converters and PLDs
Data Converters: DAC: Types, weighted resistor circuit and R-2R
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
(MSB) R Rf
D3
2R +VCC
D2 -
4R Vo
+
D1
-VEE
8R
D0
(LSB)
Rf
R1 +VCC
Vin -
Vo
+
-VEE
Vo=-(Rf/R1).Vin
Rf
R1 If +VCC
Vin
Iin V1
Ib - Vo
+
-VEE
Vo=-Iin.Rf
V 0 IinRF
But for above circuit,
Iin ( I 1 I 2 I 3 I 4)
Therefore, output voltage for above circuit is given by,
V 0 ( I 1 I 2 I 3 I 4) RF
9/16/2018 Amit Nevase 36
Binary Weighted Resistor DAC
V 0 ( I 1 I 2 I 3 I 4 ) RF
From given circuit,
( D 3 V 1) ( D 2 V 1) ( D1 V 1) ( D 0 V 1)
I1 I2 I3 I4
R 2R 4R 8R
But according to Virtual ground concept, V1=0,
Therefore,
D3 D2 D1 D0
I1 I2 I3 I4
R 2R 4R 8R
Substitute,
D 3 D 2 D1 D 0
V 0 ( ) RF
R 2 R 4 R 8R
Taking R common
D 2 D1 D 0 RF
V 0 ( D 3 )( )
2 4 8 R
9/16/2018 Amit Nevase 37
Binary Weighted Resistor DAC
Advantages:
Simple Construction/Analysis
Fast Conversion
Disadvantages:
Requires large range of resistors (2000:1 for 12-bit
DAC) with necessary high precision for low
resistors
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
+VCC
-
R R R
+
-VEE
Vout
2R 2R 2R 2R 2R
(LSB) (MSB)
D0 D1 D2 D3
Digital Inputs
2R 2R 2R 2R 2R
Vout
(LSB) D0 D2
D1 D3 (MSB)
+E
Req=2R
Req
=2R 2R Vout 2R E
+E 2R Vout E ( )
2R 2R 2
+E
9/16/2018 Amit Nevase 42
R-2R Ladder DAC
Only one source will be active at a time (using superposition theorem)
i.e. D2 active
R R R
2R 2R 2R 2R 2R
Vout
(LSB) D0 D2
D1 D3 (MSB)
+E
R
Req=2R R
RTH
Req
=2R 2R 2R Vout
+E 2R
+E
9/16/2018 Amit Nevase 43
R-2R Ladder DAC
Thevenins equivalent
2R R 2R
RTH
E
E VTH i1 2 R
+E
VTH 2
i1 2R 2 RTH [(2 R 2 R) R] 2 R
Req=2R
E E 2R E
VTH 2R Vout ( )
2 2 2R 2R 4
2R 2R 2R 2R 2R
Vout
(LSB) D0 D2
D1 D3 (MSB)
+E
R R
Req
2R 2R 2R Vout
=2R
+E
9/16/2018 Amit Nevase 45
R-2R Ladder DAC
Loop Current method
2R R R 2R
RTH
E
E VTH i 2 2 R
+E
VTH 4
i1 2R i2 2R 4
RTH [((2 R 2 R) R) 2 R] R 2 R
Req=2R
E E 2R E
VTH 2R Vout ( )
4 4 2R 2R 8
2R 2R 2R 2R 2R
Vout
(LSB) D0 D1 D2 D3 (MSB)
+E
2R R R R
RTH
+E 2R i 2R 2R VTH
i1 2 i3
E
E VTH i 3 2 R
VTH 8
8
RTH [{(((2 R 2 R) R) 2 R) R} 2 R] R 2 R
Req=2R
E E 2R E
VTH 2R Vout ( )
8 8 2 R 2 R 16
+VCC
-
R R R
+
-VEE
2R 2R
Vout
2R 2R 2R
(LSB) (MSB)
D0 D1 D2 D3
Digital Inputs
E E E E
Using Superposition Principle, Vout
2 4 8 16
D3 D2 D1 D0
Vout
2 4 8 16
9/16/2018 Amit Nevase 49
R-2R Ladder DAC
Advantages:
Advantages:
Disadvantages:
3. One resistors per bit are 3. Two resistors per bit are
required required
Resolution:
The resolution is always equal to the weight of the LSB and is also
referred to as the step size.
step size
% Re solution 100
full scale
Accuracy:
If the values of resistance are very accurate and the other components are
also ideal, there would be perfectly liner relation between output and input
and output-input graph would be a straight line.
Because of the fact that resistances used in the circuit have some tolerances,
perfectly linear of the fact that resistance used in the circuit have some
tolerance, perfectly linear relation between input and output is not obtained.
A special case of liner error is offset error which is the output voltage when
digital input is 0000.
Linearity:
Monotonicity:
Settling Time:
Settling Time:
Temperature Sensitivity:
The reference voltage supplies and resistors of a D/A converter are all
temperature sensitive.
extent, on temperature.
The temperature sensitivity of the offset voltage and the bias current
Reference Voltages:
Types:
Offset Voltage:
Offset Voltage:
Output Voltage
Ideal Output
Digital Input
Computer Printers
Digital Thermostat
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
National Semiconductor.
MC1508/1408.
Features:
Pin Configuration:
Circuit Diagram:
Output Equation:
A1 A2 A3 A4 A5 A6 A7 A8
Vo Vref ( )
2 4 8 16 32 64 128 256
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
analog signal.
Analog
– Continuous in time
Digital
Three Stages:
Sampling
Quantizing
Encoding
The number of possible states that the converter can output is:
N=2n
Example:
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Flash ADC
Delta-Sigma ADC
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Analog
+
I/p
-
Counter Counter Counter
Ramp
Generator
RESET
Control Flip Flop Flip Flop Flip Flop
Latch Latch Latch
Circuit
Manual STROBE
Switch
Control 7-Segment 7-Segment 7-Segment
Decoder Decoder Decoder
Manual
RESET
t
VA
Ramp
Signal
t
0 t1 t2
Vc
t
Clk
t
Strobe
t
RESET
t
9/16/2018 Amit Nevase 91
1 Conversion Cycle
Manual
RESET
t
Ramp VB
Signal
t
0 t1 t2
Vc
t
Clk
t
Strobe
t
RESET
t
9/16/2018 Amit Nevase 92
Single Slope ADC
Advantages:
High accuracy
Limitations:
This A/D converter cannot take bipolar signals. This difficulty can
Any noise of zero means, riding the input analog signal is not
rejected by system.
R Comparator
-
+
+
- Counter Counter Counter
Integrator
Vin
tFIX tmeas
t
Then the ADC discharges the capacitor at a fixed rate with the
counter counts the ADC’s output bits. A longer discharge time
results in a higher count
Advantages:
High accuracy
Low cost
Disadvantages:
accuracy
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Binary
….. O/P
DAC
MSB is set to 1.
9/16/2018 Amit Nevase 101
Conversion Process In Successive Approximation ADC
Advantages:
The conversion time is equal to the “n” clock cycle period for an
n-bit ADC.
of analog signal
Disadvantages:
Circuit is complex.
Sr. Successive
Parameter Dual Slope
No. Approximation
Accuracy of
3 Less Accurate More Accurate
conversion
Resolution:
Accuracy:
1
The accuracy of A/D conversion is limited by the
2 LSB
Speed:
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Pin Configuration:
Circuit Diagram:
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
00000001 1011111100100100
big array (list) of data
00000002 1001110011110111
FFFFFFFE 1100101000110001
array at any given index
FFFFFFFF 0110101111010000
ROM RAM
PROM Static
EPROM
EEPROM
Dynamic
FLASH
NOR
NAND
Processor Registers
Very Fast, Very
Small Size Expensive
Small
Capacity Processor Cache
Very Fast, Expensive
Power ON
Medium Size Immediate Term
Medium
Capacity Random Access Memory
Power ON Fast, affordable
Very Short Term
Small Size
Power OFF Flash/USB
Large
Slower, Cheap
Capacity Short Term
Power OFF
Large Size Long Term
Very Large
Capacity CDs, DVD’s and Tape
Backup
Very Slow, Affordable
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
word line
Two lines are connected to each dynamic RAM cell - the Word
Line (W/L) and the Bit Line (B/L) connect as shown so that the
required cell within a matrix can have data read or written to it.
and bit lines and this reduces the time to access the
Once the selected row is read into the row latch, WE_L
forces the input bit on DIN to be merged into the row
latch in the bit position selected by the column address
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
ROM stands for Read Only Memory. The data and instructions in
ROM are stored by the manufacturer at the time of its
manufacturing.
This data and programs cannot be changed or deleted after
wards. The data or instructions stored in ROM can only be read
but new data or instructions cannot be written into it.
This is the reason why it is called Read Only Memory.
ROM stores data and instructions permanently. When the power
is turned off, the instructions stored in ROM are not lost. That is
the reason ROM is called non-volatile memory.
Diode means a
“1” is stored at
this location
data output
active low
Masked ROM
RAM ROM
EPROM EEPROM
EPROM EEPROM
Data can be erased only byte Data can be erased only block
by byte by giving electrical by block.
pulses.
0808/0809 specification
Memory: RAM and ROM basic building blocks, Read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Next, the CS and OE signals are activated, after a delay of tGQ , the output
enable access time measured with respect to the High to Low transition of
the OE signal, valid data appears on the data lines.
The tAQ , address access time is measured from the beginning of the valid
address that appears on the address lines to the appearance of valid data on
the data lines.
The tEQ measures the chip enable access time which is the time for the valid
data to appear after the High to Low transition of the chip select signal CS.
Next, the CS and WE signals are activated. The write enable signal WE is
activated after a minimum time of tS(A) the address setup time which is
measured from the beginning of the valid address.
The time for which the WE signal remains active is known as the write pulse
width. After the WE signal becomes active the data that is to be written in
the memory at the addressed location is applied at the data lines.
The WE signal must remain valid after data is applied at the data input lines
and must remain valid for a minimum time duration tWD. The data must
remain valid for a time th(D), hold time after WE signal is deactivated.
9/16/2018 Amit Nevase 179
Memory Write Operation
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Here, the inputs of AND gates are not of programmable type. So, we have to
generate 2n product terms by using 2n AND gates having n inputs each. We
can implement these product terms by using nx2n decoder. So, this decoder
generates ‘n’ min terms.
Here, the inputs of OR gates are programmable. That means, we can program
any number of required product terms, since all the outputs of AND gates are
applied as inputs to each OR gate. Therefore, the outputs of PROM will be in
the form of sum of min terms.
9/16/2018 Amit Nevase 187
Programmable Read Only Memory (PROM)
Example: Let us implement the following Boolean functions using PROM.
A( X , Y , Z ) m(5, 6, 7)
B( X , Y , Z ) m(3,5, 6, 7)
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
Here, the inputs of AND gates are programmable. That means each AND gate
has both normal and complemented inputs of variables. So, based on the
requirement, we can program any of those inputs. So, we can generate only
the required product terms by using these AND gates.
Here, the inputs of OR gates are also programmable. So, we can program any
number of required product terms, since all the outputs of AND gates are
applied as inputs to each OR gate. Therefore, the outputs of PAL will be in the
form of sum of products form.
each function.
functions.
9/16/2018 Amit Nevase 194
Programmable Logic Array (PLA)
The programmable AND gates have the access of both
normal and complemented inputs of variables. In the above
figure, the inputs X , X ,Y ,Y , Z & Z , are available at the inputs
of each AND gate. So, program only the required literals in
order to generate one product term by each AND gate.
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
AND gates.
Here, the inputs of AND gates are programmable. That means each AND gate
has both normal and complemented inputs of variables. So, based on the
requirement, we can program any of those inputs. So, we can generate only
the required product terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number
of inputs to each OR gate will be of fixed type. Hence, apply those required
product terms to each OR gate as inputs. Therefore, the outputs of PAL will
be in the form of sum of products form.
functions.
Here, the inputs of OR gates are of fixed type. So, the necessary
product terms are connected to inputs of each OR gate. So that
the OR gates produce the respective Boolean functions. The
symbol ‘.’ is used for fixed connections.
9/16/2018 Amit Nevase 202
Advantages of PAL
Highly efficient
Highly secure
High Reliability
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
PAL devices.
used to sum off all min terms from the AND output.
9/16/2018 Amit Nevase 205
Block Diagram of Generic Array Logic (GAL)
0808/0809 specification
Memory: RAM and ROM basic building blocks, read and write
PLD: Basic building blocks and types of PLDs, PLA, PAL, GAL.
https://www.mepits.com/tutorial/80/vl
si/programmable-logic-device-pld
https://www.tutorialspoint.com/digital
_circuits/digital_circuits_programmable
_logic_devices.htm
http://ecetutorials.com/digital-
electronics/successive-approximation-
adc-analog-to-digital-converter/