Ade Manual 2021-22 - Merged

Rashtreeya Sikshana Samithi Trust
RV Inst
Institute of Technology and Managem
ment®
(Affiliated to VTU, Belagavi)
JP Nagar, Bengaluru – 560076
Department of Computer Science & Engineering
Department of Information Science & Engineering
Course Name: Analog and Digital Electronics Laboratory

Course Code: 18CSL37
III SEMESTER
2018 Scheme
Prepared By:
Dr. Jyothi A P
Assistant Professor, Department of Computer Science and Engineering,
RVITM, Bengaluru – 560076
Dr. Niharika PK
Associate Professor, Department of Information Science and Engineering,
RVITM, Bengaluru – 560076
Faculty in Charge:
Dr. Jyothi A P
Dr. Niharika PK
Email: jyothiap.rvitm@rvei.edu.in
jyothiap.rvitm@rvei.edu.in, niharikapk.rvitm@rvei.edu.in
RV Institute of Technology & Management®
ANALOG AND DIGITAL ELECTRONICS LABORATORY

(Effective from the academic year 2018 -2019) SEMESTER – III
Course Code 18CSL37 CIE Marks 40

Number of Contact Hours/Week 0:2:2 SEE Marks 60
Total Number of Lab Contact Hours 36 Exam Hours 03
Credits – 2
Course Learning Objectives: This course (18CSL37) will enable students to:
This laboratory course enable students to get practical experience in design, assembly
and evaluation/testing of
 Analog components and circuits including Operational Amplifier, Timer, etc.
 Combinational logic circuits.
 Flip - Flops and their operations
 Counters and registers using flip-flops.
 Synchronous and Asynchronous sequential circuits.
 A/D and D/A converters
Descriptions (if any):
 Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant.
 For Part A (Analog Electronic Circuits) students must trace the wave form on Tracing sheet /
Graph sheet and label trace.
 Continuous evaluation by the faculty must be carried by including performance of a student in
both hardware implementation and simulation (if any) for the given circuit.
 A batch not exceeding 4 must be formed for conducting the experiment. For simulation individual
student must execute the program.
Laboratory Programs:
PART A (Analog Electronic Circuits)
1. Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50% and >50%)
using NE 555 timer IC. Simulate the same for any one duty cycle.
2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle. And
simulate the same.
3. Using ua 741 opamap, design a window comparate for any given UTP and LTP. And
simulate the same.
PART B (Digital Electronic Circuits)
4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic
gates. And implement the same in HDL.
5. Given a 4-variable logic expression, simplify it using appropriate technique and realize the
simplified logic expression using 8:1 multiplexer IC. And implement the same in HDL.
6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table. And
implement the same in HDL.
7. Design and implement code converter I)Binary to Gray (II) Gray to Binary Code using basic
gates.
8. Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and
demonstrate its working.
9. Design and implement an asynchronous counter using decade counter IC to count up from 0
to n (n<=9) and demonstrate on 7-segment display (using IC-7447)
Laboratory Outcomes: The student should be able to:
 Use appropriate design equations / methods to design the given circuit.
 Examine and verify the design of both analog and digital circuits using simulators.
 Make us of electronic components, ICs, instruments and tools for design and testing of circuits
III-Semester, ADE Lab Manual (18CSL37) Page 1

for the given the appropriate inputs.

 Compile a laboratory journal which includes; aim, tool/instruments/software/components used,
design equations used and designs, schematics, program listing, procedure followed, relevant theory,
results as graphs and tables, interpreting and concluding the findings.
Conduct of Practical Examination:
 Experiment distribution
o For laboratories having only one part: Students are allowed to pick one experiment from the lot
with equal opportunity.
o For laboratories having PART A and PART B: Students are allowed to pick one experiment
from PART A and one experiment from PART B, with equal opportunity.
 Change of experiment is allowed only once and marks allotted for procedure to be made zero of
the changed part only.
 Marks Distribution (Courseed to change in accoradance with university regulations)
a) For laboratories having only one part – Procedure + Execution + Viva-Voce: 15+70+15 =
100 Marks
b) For laboratories having PART A and PART B
i. Part A – Procedure + Execution + Viva = 6 + 28 + 6 = 40 Marks
ii. Part B – Procedure + Execution + Viva = 9 + 42 + 9 = 60 Marks

General Instructions to Students:

1. Understand the theoretical concept for the respective experiment.
2. Draw the circuit diagram in the given space in the observation book.
3. Tabulate the readings in the observation book and plot the graphs if necessary.
4. Every Student must at least construct one circuit.
5. After the completion of the experiment, get signature in the observation book.
6. Before coming to next lab, make sure that records will be updated and signed from
theconcerned faculty.
Guide Lines for Writing Manual:

Blank Page (USE PENCIL)
Practical No:
Aim:
Circuit Diagram:
Theory:
Procedure:
Calculation:
Result:
Ruled Page (USE PEN)
Practical No:
Aim:
Apparatus Required:
Characteristics/Wave form/ Observation Table:
Result:

INTRODUCTION TO ADE LAB
Electronics Components can be mainly classified into Active and Passive Components.
Active components rely on a source of energy and usually can inject power into a circuit.
Example: Active components include amplifying components such as transistors, opamps,
and tunnel diodes.
Passive components can't introduce net energy into the circuit. They also can't rely on a source
of power, except for what is available from the (AC) circuit they are connected to. As a
consequence they can't amplify.
Example: Passive components include resistors, capacitors and inductors.
Bread-Board is used in a laboratory for constructing the different circuits and testing them.
The breadboard contains a number of metal clips aligned beneath the array of holes so that when
we insert the lead of a component (say, resistor) inside a hole, the clip grips the lead tightly. It
has a T arrangement. All the five holes correspond to one node since all of them are connected
together electrically by the metal clip. That means up to 5 wires can be connected to this single
node.
For grounding purpose, we can use any horizontal line out of four power/rail lines. Each
horizontal power line contains 10 groups, where each group contains 5 holes. The first five group
is interconnected, The next five is interconnected. Out of eight available options any one group
can be used to create a common ground.

PASSIVE COMPONENTS
Resistors: opposes the flow of electrons (current). The symbols are shown below
Resistance is measured in units called “Ohm”. Resistors can be broadly of two types. Fixed
Resistors and Variable Resistors.
Fixed Resistors: A fixed resistor is one for which the value of its resistance is specified and
cannot be varied in general.
Resistance Value: The resistance value is displayed using the color code ( the colored bars/the
colored stripes ), because the average resistor is too small to have the value printed on it
with numbers. The resistance value is a discrete value.
COLOR CODING
Example 1: (Brown=1),(Black=0),(Orange=3)
10 x 103= 10k ohm ; Tolerance(Gold) = ±5%
Colour code Table to Find the Value of Carbon Resistors

First-and / Fourth-Band /
Colour code Second- Band Third-Band / Multiplier
Digit Tolerance
/Digit Band
Band
Black 0 0 100 = 1
Brown 1 1 101 = 10 1%
Red 2 2 102 =100 2%
Orange 3 3 103 =1000 / 1-K 3%
Yellow 4 4 104 =10000 / 10-K 4%
Green 5 5 105 =100000 / 100-K
Blue 6 6 106 =1000000 / 1-M
Violet 7 7 107 =10000000 / 10-M

Gray 8 8 108 =100000000 / 100-M

White 9 9 109 =1000000000/ 1-G
Gold 5%
Silver 10%
No Colour 20%
Resistor Color Codes

Mnemonic for color coding of resistors“BB ROY Goes to Bombay Via GateWay with Gold and Silver”
OR
“BB ROY of Great Britain has a Very Good Wife with no interest in Gold and Silver”.
Tolerance of the resistor is also an important property to consider. A 100 Ω resistor with 10%
tolerance, means that its value can be any fixed value between 90 to 110 ohms. A 120 Ω resistor
with 10% tolerance, means that its value can be any fixed value between 108 to 132 ohms.
Capacitor: The function of the capacitor is to store electric charge or in effect electrical energy.
It is very useful as a filter, and for passing AC and blocking DC. The symbol is
Microfarad (uF) Code

0.1 104
0.01 103
Power Supply
A power supply is a separate unit or part of a circuit that supplies power to the rest of the circuit
or to a system. The power supply takes the current from your wall electrical socket and
converts it into the various voltages your circuit needs.
Two types of power supplies used in our lab are
1. Variable DC Power Supply
2. Fixed Power supply
Multimeter
A meter is a measuring instrument. An ammeter measures current, a voltmeter measures the
potential difference (voltage) between two points, and an ohmmeter measures resistance. A
multimeter combines these functions and possibly some additional functions like ohmmeter etc
into a single instrument.
Signal/Function Generator
A function generator is a device that can produce various patterns of voltage at a variety of
frequencies and amplitudes. It is used to test the response of circuits to common input signals.
The electrical leads from the device are attached to the ground and signal input terminals of the
device under test.
Most function generators allow the user to choose the shape of the output from a small number
of options.
• Square wave - The signal goes
• Sine wave - The signal curves like a sinusoid from high to low voltage.
• Triangle wave - The signal goes from high to low voltage at a fixed rate.
The amplitude control on a function generator varies the voltage diff and low voltage of the
output signal. The frequency control of a function generator controls the rate at which output
signal oscillates.

Cathode Ray Oscilloscope

An oscilloscope is easily the most useful instrument available for testing circuits because it
allows you to see the signals at different points in the circuit. The best way of investigating an
electronic system is to monitor signals at the input and output of each system block, checking
that each block is operating as expected and is correctly linked to the next.

Electronics Circuits with PSPICE

Introduction to PSPICE
SPICE (Simulation Program for Integrated Circuits Emphasis) is a general purpose analog
circuit simulator that is used to verify circuit designs and to predict the circuit behavior.
PSpice is a PC version of SPICE and HSpice is a version that runs on workstations and larger
computers.
PSpice has analog and digital libraries of standard components (such as NAND, NOR, flip-flops,
and other digital gates, op amps, etc) which makes it a useful tool for a wide range of analog and
digital applications.
Getting Started
To get started, double click on the PSpice Schematic icon.
This screen is the schematic layout that is used by Pspice. The toolbar on the right-hand side of
the screen is the one associated with building the circuits.
1.Goto drawget new part(you can use ctrl+g)select the component used in the circuit (like
for resistor r,capacitor c,DC Regulated power supply VDC, Diode 1N4002,VSIN for sin wave
generation, uA741 for opAMP,555D for triple five timer) place in the schematic area.
2. For ground use GND_EARTH from get new part.

3. Give the values to the components according to the design.
4. Draw wire using this icon.
5. Use voltage level marker for the output .
6. Go to setup analysis ,tick and double click on transient set final time and step size.
7. Click on the save button .
8. Click on the simulate button .

9. Output waveform will be displayed.

DIGITAL ELECTRONICS LABORATORY
LOGIC DESIGN
Study of All Basic Gates and its pin out diagram
 IC-7404, NOT Gate

 IC-7408, AND Gate
 IC-7432, OR Gate

Study of Universal Gates and its pin out diagram
 IC-7400, NAND Gate (2-Inputs Gate)

 IC-7410, NAND Gate (3-Inputs Gate)
 IC-7402, NOR Gate

 IC-7486, Exclusive-OR Gate

 Exclusive-NOR Gate

EX-OR GATE IMPLEMENTATION USING BASIC GATES

Logic Design with XLINX Software (VHDL)

Steps to run vhdl code in XILINX ISE Design Suite 14.7 software
Step-1:Double click on the ISE Design Suite 14.7 icon
Step-2:Goto File menu and select new project. Then the following window will appear
Now we have to give a valid file name in the path “C:\Xilinx\14.7”.

For example:halfadder

Select hdl and click on the next button.
Step-3: After step 2 the following window will open

In this window you have to select Sparten3E Family and XC3S100E device.The preferred Language should be
VHDL. Now click on the next button.
Step-4:Once you click on the Next button The following window will open. It includes all the details of your
project’
click on the Finish button.
step-5:Later the following window will open.
In the above window you will see your project name in the left corner of the window. Right click on that as follows

and click on theNew Source option. Now the window will open

Select VHDL Module. Give any suitable file name and click on Next button.
Step-6:The following window will open
Here you set your behavioral model according to your project. and click on the next button.
Now the following window will open
Check the details and click on finish button

Step 7:Now you have to tpye the VHDL code of your project in the following window
click on save button.

Double click on the check syntax option.
f there is no errors it will display the following message
“Process "Check Syntax" completed successfully”
Step 8:Now we have simulate by choosing the simulate option as follows;
Now you have to choose your behavioral model and double click on simulate behavioural model as follows

Now the following window will open
Here you have to check your output by enforcing the values as follows:

Now you have to enter the values and check the output as follows: enter the value click on apply and press ok
button.
Now check the output


1. Design an astable multivibrator ciruit for three cases of duty cycle (50%, <50%
and >50%) using NE 555 timer IC. Simulate the same for any one duty cycle
AIM : To design and implement an astable multivibrator using 555 Timer for a given
frequency and duty cycle.
COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitorsof
0.1 μF, 0.01 μF, Regulated power supply, CRO, Diode (1N4148/ )
THEORY:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. The multivibrators are classified as: Astable or free
running multivibrator: It alternates automatically between two states (low and
high for a rectangular output) and remains in each state for a time dependent upon
the circuit constants. It is just an oscillator as it requires no external pulse for its
operation. Monostable or one shot multivibrator: It has one stable state and one
quasi stable. The application of an input pulse triggers the circuit time constants.
After a period of time determined by the time constant, the circuit returns to its
initial stable state. The process is repeated upon the application of each trigger
pulse.
Bistable Multivibrators: It has both stable states. It requires the application of an

external triggering pulse to change the output from one state to other. After the
output has changed its state, it remains in that state until the application of next
trigger pulse. Flip flop is an example.
DESIGN:
For Astable multivibratorTON=

0.693 (RA+RB) C
TOFF=0.693 RB C
With the diode connected in parallel with RB the effect of RB is shunted during chargingof the
capacitor, therefore the equations for TON and TOFF is given by
TON= 0.693 RA C
TOFF=0.693 RB C

Case 1: 50% duty cycle

Let Frequency =1kHz, T=1ms, C=0.1 μFTON =
TOFF=0.5ms
For RA, 0.5ms= 0.693 * RA *0.1 *10-6RA =7.2
kΩ= RB
Case 2: >50% duty cycle, let Duty cycle be 75%

0.75ms
TOFF= 0.25ms
For RA, 0.75ms= 0.693 * RA *0.1 *10-6RA =10

kΩ
For RB, 0.25ms= 0.693 * RA *0.1 *10-6RB =3.6
kΩ
Case 3: <50% duty cycle, let Duty cycle be 25%
0.25ms
TOFF= 0.75ms
For RA, 0.25ms= 0.693 * RA *0.1 *10-6RA

=3.6 kΩ
For RB, 0.75ms= 0.693 * RA *0.1 *10-6RB =10
kΩ
Given frequency (f) = 1KHz and duty cycle >50% ,
The time period T =1/f = 1ms = tH+ tL
Where this the time the output is high and tL is the time the output is low.
From the theory of astable multivibrator using 555 Timer(refer Malvino), we have
tL = 0.693 RB C ------(1)
tH = 0.693 (RA + RB)C ------(2)
T = tH+ tL = 0.693 (RA +2RB) C

Fig 1: Circuit Diagram and actual connections
Fig.2: Circuit Diagram for 50% and < 50% Duty cycle and output waveform for
(50%)
Fig 3 Output waveform duty cycle >50%

Fig 4 Output waveform duty cycle < 50%
PROCEDURE :
1. Before making the connections, check the components using multimeter.

2. Make the connections as shown in figure and switch on the power supply.
3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty cycle.
RESULT: The frequency of the oscillations = ___ Hz.
Note:
Each division in oscilloscope is 0.2
Time=no of div in x-axis x time base
Amplitude= no of div in y-axis x volt/div
Duty cycle= (Ton/Ton +Toff) *100

Simulation
Circuit diagram: Astable multivibrator for duty cycle >50%
Output waveform:
Type of analysis: TIME DOMAIN

(TRANSIENT)Run to time: 10m
Step size: 0.01m

Sample Viva Questions & Answers

a. Define 555 IC?
The 555 timer is an integrated circuit specifically designed to perform signal

generation and timing functions.
b. List the basic blocks of IC 555 timers?
A relaxation oscillator
RS flip flop Two comparator Discharge transistor
c. List the features of 555 Timer?

It is available in three packages. 8 pin metals can, 8 pin dip, 14 pin dip.It has
very high temperature stability.
d. List the applications of 555 timers in monostable mode of operation:

*Linear ramp generator
*Frequency divider
*Pulse width modulation.
e. What is the applications of 555 Timer?

 Astable multivibrator
 Monostable multivibrator
 Missing pulse detector
 Linear ramp generator
 Frequency divider
 Pulse width modulation
 FSK generator

2. Using ua 741 Opamp, design a 1 kHz Relaxation Oscillator with 50% duty cycle.
AndSimulate the same.
AIM : To design and implement a rectangular waveform generator (op-amp
relaxationoscillator) for a given frequency.
COMPONENTS REQUIRED:
Op-amp μA 741, Resistor of 1KΩ, 10KΩ, 20 kΩ Potentiometer, Capacitor of 0.1
μF,Regulated DC power supply, CRO
THEORY:
Op-Amp Relaxation Oscillator is a simple Square wave Generator which is also called as a Free running
oscillator or Astablemultivibrator or Relaxation oscillator.In this figure theop-amp operates in the
saturation region. Here, a fraction R2/(R1+R2)) of output is fed back to the noninverting input
terminal. Thus reference voltage is (R2/(R1+R2)) Vo. And may take values as +(R2/(R1+R2))
Vsator - (R2/(R1+R2)) Vsat. The output is also fed back to the inverting input terminal after
integrating by means of a low-pass RC combination. Thus whenever the voltage at inverting input
terminal just exceeds reference voltage, switching takes place resulting in a square wave output.
DESIGN :
�+�
The period of the output rectangular wave is given as T= 2RCln�−�-----------(1)
��
Where, β=� is the feedback fraction
� +��
If R1 = R2, (duty cycle=50%) then from equation (1) we have T = 2RC ln(3)
Another example, if R2=1.16 R1, then T = 2RC ----------(2)

1 1
Example: Design for a frequency of 1KHz (implies T= � = 103 = 10−3 =1ms
Use R2=1.16 R1, for equation (2) to be applied.
Let R1 = 10KΩ, then R2 = 11.6KΩ (use 20kΩ potentiometer as shown in circuit figure) Choose next a value of C and
then calculate value of R from equation (2).
� 10−3
Let C=0.1µF (i.e., 10-7),then R= =
2� 2 � 10−7
= 5KΩ
�1
The voltage across the capacitor has a peak voltage of Vc =� Vsat
1 +�2
PROCEDURE:
1. Before making the connections check all the components using multimeter.

2. Make the connections as shown in figure and switch on the power supply.
3. Observe the voltage waveform across the capacitor on CRO.
4. Also observe the output waveform on CRO. Measure its amplitude and frequency.
WAVEFORM:
RESULT:

The frequency of the oscillations = …………Hz. (Note: f=1/T; T=Ton+Toff. To calculate T use the following: No. of
divisions occupied horizontally in CRO by one cycle of output wave X times/division knob reading along
with units [sec/micro/milli])
Simulation:
RELAXATION OSCILLATOR
TYPE OF ANALYSIS : TIME DOMAIN
RUN TO TIME : 4ms
MAXIMUM STEP SIZE : 0.01ms

1. What are oscillators?

Oscillators produce a waveform (mostly sine or square waves) of desired amplitude
and frequency. They can take input from the output itself. For a complete oscillator
circuit we require a feedback device, amplifier and feedback factor. Oscillators
designed to producea high-power AC output from a DC supply are usually called
inverters.
2. Application of electronic oscillator?
An electronic oscillator is an electronic circuit that produces a repetitive electronic
signal, often a sine wave or a square wave. They are widely used in innumerable
electronic devices. Common examples of signals generated by oscillators include
signals broadcast by radio and television transmitters, clock signals that regulate
computers and quartz clocks, and the sounds produced by electronic beepers and
video games.
3. What do you mean by voltage follower?
The lowest gain that can be obtained from a non-inverting amplifier
with feedback Is 1. When the non-inverting amplifier is configured for
unity, it is called a voltage Follower.
4. Types of electronic oscillator?`
There are two main types of electronic oscillator: the harmonic oscillator and
the relaxation oscillator.

3. Using ua 741Opamp, design a window comparator for any given UTP and LTP.
Andsimulate the same
AIM : To design and implement a window comparator for a given UTP and LTP values
COMPONENTS REQUIRED:
Two Op amp IC μA 741, Two diode 1N4007, Resistor of 1KΩ, DC regulated power Supply,
trainer kit (+12v & -12v is given to Op amp from this), Signal generator, CRO.
THEORY
A Window Comparator is basically the inverting and the non-inverting comparators combined
into a single comparator stage. The window comparator detects input voltage levels that
are within a specific band or window of voltages, instead of indicating whether a
voltage is greateror less than some preset or fixed voltage reference point.
This time, instead of having just one reference voltage value, a window comparator will have
two reference voltages implemented by a pair of voltage comparators. One which triggers
an opamp comparator on detection of some upper voltage threshold, VREF(UPPER) and
one which triggers an op-amp comparator on detection of a lower voltage threshold level,
VREF(LOWER). Then the voltage levels between these two upper and lower reference
voltages is called the “window”, hence its name.
DESIGN

CIRCUIT:
Circuit Diagram of Window Comparator
RESULTS:
The output is shown in the form of a waveform as depicted below. And correlate it with the
practical values on the CRO

Output Waveforms

Simulation:
Components to be placed in the schematic:
Two Op amp IC μA 741, Two diode 1N4007, Resistor of 1KΩ, DC regulated power Supply,
trainer kit (+12v & -12v is given to Op amp from this).
UTP =3V, LTP = -3V
Output waveform:
Type of analysis: TIME DOMAIN (TRANSIENT)

Run to time: 100m
Step size: 0.01m

1. What is a comparator?
In electronics, a comparator is a device that compares two voltages or currents and
outputs a digital signal indicating which is larger. It has two analog input terminals and
and one binary digital output
2. What is meant by UTP and LTP?
3. What is a window comparator?

A window detector circuit, also called window comparator circuit or dual edge limit
detector circuits is used to determine whether an unknown input is between two precise
reference threshold voltages. It employs two comparators to detect over-voltage or under-
voltage.
4. What are the applications of window comparator?
The humidity monitoring system of soil based on wireless sensor networks using Arduino
project is designed for developing an automatic irrigation system that can control the
switching operation (on/off) pump motor depending upon the moisture content in the soil.
In smoke alarm circuit

PART-B
4.Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using
basic gates. And implement the same in HDL
Components Used:
Sl.No Name of The Component IC Number Quantity

1 AND gate 7408 2
2 OR gate 7432 1
3 Not gate 7404 1
4 EXOR gate 7486 1
5 Patch chords - 2 sets
6 Trainer Kit - -
Theory:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B,
is called a half-adder. Addition will result in two output bits; one of which is the sum bit,
S, and the other is the carry bit, C. The Boolean functions describing the half adder are:
Sum = � ⊕ � Cout = A B
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:
Sum = � ⊕ �⊕ �� Cout = AB + Cin (� ⊕ �)
Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a
difference bit D and a borrow out bit B-out. This operation is called half subtraction and
the circuit to realize it is called a half subtractor. The Boolean functions describing the
half- Subtractor are:
D=�⊕� Bout = A' B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtracter are:
D = � ⊕ �⊕ �� Br= A'B + A' (Cin) + B (Cin)
i) To realize Half Adder

Truth Table
Inputs Outputs
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Boolean ExpressionS =A⊕B and C=AB

Circuit Diagram

Circuit Diagram
Half adder circuit using basic gates
ii) Full Adder

Truth Table Boolean Expressions
Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Circuit Diagram
Full adder circuit using basic gates
iii) Half Subtractor

Truth Table
Boolean expression :
D=A⊕B
Inputs Outputs Br=A'B
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Circuit Diagram
Half Subtractor using basic gates

iv) Full Subtractor

Truth Table Boolean Expressions
Inputs Outputs
A B C(Bin) D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Circuit Diagram
Using basic gates

Procedure:
1. Verify all components & patch chords whether they are in good condition or not.
2. Make connections as shown in the circuit diagram.
3. Give supply to the trainer kit.
4. Provide input data to circuit via switches
5. Verify truth table sequence & observe outputs.
Result:
The truth table of above circuits are verified.
VHDL Programs:
1. Half Adder and Half Subtractor
library ieee;
use ieee.std_logic_1164.all;
entity addsub is
port (a:in std_logic;
b:in std_logic;
sum: out std_logic;
carry: out std_logic;
difference: out std_logic;
borrow: out std_logic;
end addsub;
architectural Behavioral of addsub is
begin
sum <= ((a and not (b)) or (not (a) and b);
carry <= (a and b);
difference <=( a and not (b)) or (not (a) and b);
borrow <= (not (a) and b);
end behavioral
output:

2. Full Adder and Full Subtractor

library ieee;
entity fulladdsub is
port (a, b, c:in std_logic;
sum: out std_logic;
carry: out std_logic;
difference: out std_logic;
borrow: out std_logic;
end addsub;
architectural Behavioral of fulladdsub is
begin
sum <= (not(a) and not (b) and c) or (not (a) and b and not (c) ) or (a and not (b) and not (c))or (a and b
and c);
carry <= (a and c) or (b and c) or (a and b);
difference <= (not(a) and not (b) and c) or (not (a) and b and not (c) ) or (a and not (b) and not (c))or (a
and b and c);
borrow <= (not(a) and c) or (b and c) or (not(a) and b);
end behavioral
output:

Sample Viva Question & Answers
1. What is the use of half adder? It is used for adding 2 bit data
2. What is difference between half adder and half subs tractor? The only difference is in
carry & borrows expression.
3. What is use of Full Sub tractor? Full sub tractor is used for differentiate three bit data.
4. How many half adders required to make a full adder? 2 Half Adder
5. If input of half Subtractor is 11 then output is? Difference= 0, borrow=0

5. a) Given a 4-variable logic expression, simplify it using appropriate technique and

realize the simplified logic expression using 8:1 multiplexer IC. And implement the
same inHDL.
a) E.g.,
Simplify the function using MEV technique
f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)
Decimal LSB f MEV map entry
0}0 0000 0 0----- Do
1 0001 0
1}2 0010 1 1----- D1
9 0011 1
0100 1 1---- D2
2}4 0101 1
5
0110 0 0---- D3
3}6 0111 0
7
1000 X X---- D4
4}8 1001
9
1010 X----
X D5
5}10 1011
11
1100 d---
X D6
6}12 1101
13
1110 d---
X D7
7}14 1111
15 0
1
0
1
Components Used:

1 8:1 Mux 74151 1
2 NOT gate 7404 1
3 Patch chords - 1 set
4 Trainer Kit - -
Pin Diagram of ICs Used:

Theory:
Multiplex means many into one. A multiplexer is a circuit with many inputs but only one output.
The inputs of the multiplexer are divided into two categories namely, data inputs and select inputs.
A multiplexer having ‘n’ data inputs have ‘m’ control signals such that n≤ 2m. Depending on the
value of the select inputs, data on one of the ‘n’ inputs is steered to the output. The figure shows
the block diagram of a multiplexer.
Multiplexer can be used to implement any logic expression. Commercial multiplexer ICs come in
integer power of 2, e.g. 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexers. Hence to implement a logic
expression with ‘n’ variables, a multiplexer with ‘n’ select inputs is needed i.e. 2n – to-1
multiplexer. Hence it is called as universal logic circuit.

Procedure:
1. Verify all components and patch cards whether they are in good condition or not.
2. Make connection as shown in the circuit diagram
3. Switch on the trainer kit
4. Provide input data to circuit via toggle switches
5. Verify truth table sequence and observe outputs on the trainer kit
Truth Table for the solved expression f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)(to

verify)

HDL Program
I MULTIPLEXER
Zout
8 8:1
3
TruthTable SEL
INPUTS OUTPUTS
SEL (2) SEL (1) SEL (0) Zout
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
1 1 0 I(6)
1 1 1 I(7)
-- VHDL code for 8 to 1 mux (Behavioral modeling).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux1 is
Port ( I : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
zout : out std_logic);
end mux1;
architecture behavioral of mux1 is
begin
zout <= I(0) when sel="000" else
I(1) when sel="001" else
I(7);
end behavioral;

Output:
3) What is a de-multiplexer
De-Multiplexer is the device which has 1 input and many outputs. Based on select input it
will choose one of the output line to transmit the input.
4) How many data select input for
8:1 Mux? 3
5) If the F value is 1 then what is the entry in

MEV map? 1

6. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
Andimplement the same in HDL
Components used:

1 3 input NAND gate 7410 2 (5 gates)
2 2 input NAND gate 7400 1 (4 gates)
4 Trainer Kit - -
Theory:
The circuit below shows the solution. To the RS flip-flop we have added two new
connections from the Q and Q' outputs back to the original input gates. Remember that a
NAND gate may have any number of inputs, so this causes no trouble. To show that we
have done this, we change the designations of the logic inputs and of the flip-flop itself.
The inputs are now designated J (instead of S) and K (instead of R). The entire circuit is
known as a JK flip-flop.
In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q'
outputs will only change state on the falling edge of the CLK signal, and the J and K
inputs will control the future output state pretty much as before. However, there are
some important differences.
Since one of the two logic inputs is always disabled according to the output state of
the overall flip-flop, the master latch cannot change state back and forth while the
CLK input is at logic 1. Instead, the enabled input can change the state of the master
latch once, after which this latch will not change again. This was not true of the RS
flip-flop.
If both the J and K inputs are held at logic 1 and the CLK signal continues to change,
the Q and Q' outputs will simply change state with each falling edge of the CLK
signal. (The master latch circuit will change state with each rising edge of CLK.) We
can use this characteristic to advantage in a number of ways. A flip-flop built
specifically to operate this way is typically designated as a T (for Toggle) flip-flop.
The lone T input is in fact the CLK input for other types of flip-flops.
The JK flip-flop must be edge triggered in this manner. Any level-triggered JK latch
circuit will oscillate rapidly if all three inputs are held at logic 1. This is not very
useful. For the same reason, the T flip-flop must also be edge triggered. For both
types, this is the only wayto ensure that the flip-flop will change state only once on
any given clock pulse.
Because the behavior of the JK flip-flop is completely predictable under all

conditions, this is the preferred type of flip-flop for most logic circuit designs. The
RS flip-flop is only used in applications where it can be guaranteed that both R and S
cannot be logic 1 at the same time.
At the same time, there are some additional useful configurations of both latches and
flip- flops. In the next pages, we will look first at the major configurations and note
their properties. Then we will see how multiple flip-flops or latches can be combined
to perform useful functions and operations.
Master Slave Flip Flop:

The control inputs to a clocked flip flop will be making a transition at approximately the
same times as triggering edge of the clock input occurs. This can lead to unpredictable
triggering.
A JK master flip flop is positive edge triggered, where as slave is negative edge triggered.
Therefore master first responds to J and K inputs and then slave. If J=0 and K=1,
master resets on arrival of positive clock edge. High output of the master drives the K
input of the slave. For the trailing edge of the clock pulse the slave is forced to reset. If
both the inputs are high, it changes the state or toggles on the arrival of the positive clock
edge and the slave toggles on the negative clock edge. The slave does exactly what the
master does.
Function Table:
INPUTs OUPUTS
Clk ---Q comments
J K Q
0 0 Q0 Q0 No change
Reset
0 1 0 1
Set
1 0 1 0
toggle
1 1 Q0 Q0

Circuit Diagram:
Note:
Connect PRE and CLR to “HIGH/VCC” Connect
CLK[] to “1 Hz- Auto pulse”
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JK_FF is
port( J, K, clk, rst : in std_logic;
Q, Qbar : out std_logic);
end JK_FF;
architecture behavioral of JK_FF is

begin
process(clk, rst)
variable qn : std_logic;
begin
if(rst = '1')then
qn := '0';
elsif(clk'event and clk = '1')then
if(J='0' and K='0')then
qn := qn;

elsif(J='0' and K='1')then

qn := '0';
qn := '1';
qn := not qn;
else
null;
end if;
else
null;
end if;
Q <= qn;
Qbar <= not qn;
end process;
end behavioral;
Test bench:
library ieee;
entity JK_FF_tb is
end JK_FF_tb;
architecture testbench of JK_FF_tb is
component JK_FF is
port(J, K, clk, rst : in std_logic;
Q, Qbar : out std_logic
);
end component;
signal J, K, clk, rst : std_logic;

signal Q, Qbar : std_logic;
begin
uut: JK_FF port map(
J => J,
K => K,
clk => clk,
rst => rst,
Q => Q,
Qbar => Qbar);
clock: process
begin
clk <= '1';
wait for 10 ns;

clk <= '0';
wait for 10 ns;
end process;
Force: process
begin
J <= '0';
K <= '0';
rst <= '0';
wait for 20 ns;
J <= '0';
K <= '1';
rst <= '0';
wait for 20 ns;
J <= '1';
K <= '0';
rst <= '0';
wait for 20 ns;
J <= '1';
K <= '1';
rst <= '0';
wait for 20 ns;
J <= '1';
K <= '1';
rst <= '0';
wait for 20 ns;
J <= '0';
K <= '0';
rst <= '0';
wait for 20 ns;
J <= '0';
K <= '0';
rst <= '1';
wait for 20 ns;
end process;
end testbench;
Waveform:

1. What is flip-flop?
Flip-flop is a 1 bit storing element.
2. What is disadvantage of JK flip-

flop?Race around condition.
3. What is race around condition?
When pulse width is more than signal width, then for single change of pulse
widthmany no. of times signal changes its state which is known as race around
condition.
4. To remove race around condition what we

use?Master slave Flip-flop.
5. D flip-flop is used
for?Providing delay.
6. What is full form of T flip-

flop?Toggle flip-flop

7. Design and implement code converter I)Binary to Gray II) Gray to Binary Code using
basic gates.
Description:
Gray Code is one of the most important codes. It is a non-weighted code which belongs to a
class of codes called minimum change codes. In this codes while traversing from one step
to another step only one bit in the code group changes. In case of Gray Code two
adjacent code numbers differs from each other by only one bit.
Binary to gray code conversion is a very simple process. There are several steps to do this
types of conversions.
(1) The M.S.B. of the gray code will be exactly equal to the first bit of the given binary number.
(2) Now the second bit of the code will be exclusive-or of the first and second bit of the given
binary number, i.e if both the bits are same the result will be 0 and if they are different the
result will be 1.
(3) The third bit of gray code will be equal to the exclusive-or of the second and third bit
of thegiven binary number. Thus the Binary to gray code conversion goes on.
Example:
Gray code to binary conversion is again very simple and easy process. Following steps has to
be followed.
(1) The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
(2) Now if the second gray bit is 0 the second binary bit will be same as the previous or the
first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it
was 0 it willbe 1.
(3) This step is continued for all the bits to do Gray code to binary
conversion.Example:

Components required:
IC 7486, Patch Cords and digital trainer Kit.
1) BINARY TO GRAY
CONVERSION

1. To remove race around condition what we use?

Master slave Flip-flop.
2. D flip-flop is used for?

Providing delay.
3. What is full form of T flip-flop?

Toggle flip-flop
4. What is race around condition?

When pulse width is more than signal width, then for single change of pulse width
many no. of times signal changes its state which is known as race around condition.

Circuit Diagram: BINARY TO GRAY CODE
TRUTH TABLE:

II) GRAY TO BINARY CONVERSION

Circuit Diagram: Gray to Binary
Procedure:
1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.
Result: Binary to gray code conversion and vice versa is realized using EX-OR gates
1. What is flip-flop?
Flip-flop is a 1 bit storing element.
2. What is disadvantage of JK
flip-flop?
Race around condition.

8) Design and implement a mod n (n<8) synchronous up counter using JK FF IC’s

anddemonstrate its working.
Components used:

1 JK FF 7476 2 (3 FF)
2 AND Gate 7408 1
4 Trainer Kit - -
Pin diagram of
Function Table:

Function Table:
Theory:
The ripple counter requires a finite amount of time for each flip flop to change state. This problem can be
solved by using a synchronous parallel counter where every flip flop is triggered in synchronism with the
clock and all the output which are scheduled to change do so simultaneously.
The counter progresses counting upwards in a natural binary sequence from count 000 to count 100
advancing count with every negative clock transition and get back to 000 after this cycle.

Transition Table:
Present State Next State Jc Kc Jb Kb Ja Ka

Qc Qb Qa Qc+1 Qb+1 Qa+1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 X X X X X X X X X
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X
Circuit diagram of Mod-5 synchronous Up-Counter using JK- FF [7476] IC’s

Circuit diagram of Mod-8 synchronous Up-Counter using JK- FF [7476] IC’s
Procedure:
(1) Verify all the components and patch chords whether they are good condition or not.
(2) Make connection as shown in the circuit diagram.
(3) Give supply to the trainer kit.
(4) Provide input data to circuit via switches.
(5) Verify the truth table sequence and observe outputs
Truth Table for Mod-8 Up counter.

Sample Viva Questions & Answers:
1) What is counter?
A counter is a device which stores (and sometimes displays) the number of timesa
particular event or process has occurred, often in relationship to a clock signal.
2) What are synchronous counters?

In synchronous counters, the clock inputs of all the flip-flops are connected together and
are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in
parallel).
3) What is Asynchronous counters?
In this type, the output of one flip flop will be given as clock input to the next FF. Only
one (first) FF will be connected to clock input.
4) What is the difference between combinational logic and sequential logic?

Combinational circuits are not triggered by timing pulses, sequential circuits are triggered
by timing pulses.
5) How many FFs are required to construct a decade

counter?
4 FFs

9. Design and implement asynchronous counter using decade counter IC to count up

from0 to n (n≤9) and demonstrate on 7-segment display (using IC-7447).
Components used: IC 74LS90, IC 7447(BCD to seven segment decoder), Patch chords, Power
chords and Trainer kit.
Pin Diagram of 7490
Pin Diagram of 7447
Theory:
Asynchronous counter is a counter in which the clock signal is connected to the clock input of
only first stage flip flop. The clock input of the second stage flip flop is triggered by the output of
the first stage flip flop and so on. This introduces an inherent propagation delay time through a
flip flop. A transition of input clock pulse and a transition of the output of a flip flop can never
occur exactly at the same time. Therefore, the two flip flops are never simultaneously triggered,
which results in asynchronous counter operation.

Circuit Diagram
For mod 9
connect Q0 and Q3 to reset(clear) through an AND gate. Reset should not be connected to the
switch
For mod8
Connect Q3 to reset
For mod7
Connect Q2, Q1,Q0 to reset through an And Gate
For Mod 6
Connect Q2 and Q1 to reset through an AND gate
For mod 5
For Mod 4
Connect Q2 to reset
For mod 3
For mod 2
Connect Q1 to reset

Function Table for mod 7:
Clock Qc Qb Qa
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sample Viva Question & Answers:
1) What is decade counter?

A decade counter is a binary counter that is designed to count to 10
2) What is the shift resistor?
Shift resistor is a device which is used for storing and processing the bit in series or
parallel.
3) Types of shift resistor?
 Serial-in/serial-out shift register
 Serial-in/parallel-out shift register
 Parallel-in/parallel-out shift register
 Parallel-in/serial-out shift register
4) What do you mean by clock enable?

When the Clock Enable input is High, the enabled load and shift actions take place on
the next active Clock transition. When Clock Enable is Low, the register contents are
unaffected by the Clock.

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Rashtreeya Sikshana Samithi Trust

(Affiliated to VTU, Belagavi)

JP Nagar, Bengaluru – 560076

Department of Computer Science & Engineering

Department of Information Science & Engineering

Course Name: Analog and Digital Electronics Laboratory

ANALOG AND DIGITAL ELECTRONICS LABORATORY

Course Code 18CSL37 CIE Marks 40

III-Semester, ADE Lab Manual (18CSL37) Page 1

for the given the appropriate inputs.

III-Semester, ADE Lab Manual (18CSL37) Page 2

General Instructions to Students:

Guide Lines for Writing Manual:

III-Semester, ADE Lab Manual (18CSL37) Page 3

INTRODUCTION TO ADE LAB

III-Semester, ADE Lab Manual (18CSL37) Page 4

Resistors and Variable Resistors.

Colour code Table to Find the Value of Carbon Resistors

III-Semester, ADE Lab Manual (18CSL37) Page 5

Gray 8 8 108 =100000000 / 100-M

Resistor Color Codes

Microfarad (uF) Code

III-Semester, ADE Lab Manual (18CSL37) Page 7

Cathode Ray Oscilloscope

III-Semester, ADE Lab Manual (18CSL37) Page 8

Electronics Circuits with PSPICE

III-Semester, ADE Lab Manual (18CSL37) Page 9

3. Give the values to the components according to the design.

4. Draw wire using this icon.

5. Use voltage level marker for the output .

7. Click on the save button .

8. Click on the simulate button .

III-Semester, ADE Lab Manual (18CSL37) Page 10

DIGITAL ELECTRONICS LABORATORY

Study of All Basic Gates and its pin out diagram

 IC-7404, NOT Gate

III-Semester, ADE Lab Manual (18CSL37) Page 11

Study of Universal Gates and its pin out diagram

 IC-7400, NAND Gate (2-Inputs Gate)

III-Semester, ADE Lab Manual (18CSL37) Page 12

 IC-7486, Exclusive-OR Gate

III-Semester, ADE Lab Manual (18CSL37) Page 13

EX-OR GATE IMPLEMENTATION USING BASIC GATES

III-Semester, ADE Lab Manual (18CSL37) Page 14

Logic Design with XLINX Software (VHDL)

Step-1:Double click on the ISE Design Suite 14.7 icon

Now we have to give a valid file name in the path “C:\Xilinx\14.7”.

III-Semester, ADE Lab Manual (18CSL37) Page 15

Select hdl and click on the next button.

Step-3: After step 2 the following window will open

III-Semester, ADE Lab Manual (18CSL37) Page 16

click on the Finish button.

step-5:Later the following window will open.

III-Semester, ADE Lab Manual (18CSL37) Page 17

III-Semester, ADE Lab Manual (18CSL37) Page 18

Step-6:The following window will open

Now the following window will open

Check the details and click on finish button

III-Semester, ADE Lab Manual (18CSL37) Page 19

click on save button.

III-Semester, ADE Lab Manual (18CSL37) Page 20

Double click on the check syntax option.

f there is no errors it will display the following message

For RA, 0.75ms= 0.693 * RA 0.1 10-6RA =10

For RA, 0.25ms= 0.693 * RA 0.1 10-6RA