New Active Capacitance Multiplier For Low

Cutoff Frequency Filter Design

Hala Y. Darweesh Fathi A. Farag Yaser A. Khalaf
Hala.darwish@zu.edu.eg ffarag@zu.edu.eg ykhalaf@zu.edu.eg
Teaching Assistant, Elec. and Comm. Dept., Associate Professor, Elec. and Comm. Dept., Assistant Professor, Elec. and Comm. Dept.,
Zagazig University, Zagazig. Zagazig University, Zagazig. Zagazig University, Zagazig.

 In this paper, capacitance multiplication is done using

Abstract— This paper presents a new topology for an only CMOS current multiplier cell (CMC). The
active capacitance multiplier. This circuit affords a proposed current conveyor cell [3-4] is employed in this
technique to implement a high capacitance value work. The current mode signal processing is preferred
using a small on-chip capacitor. The proposed for low supply voltage, due to the square law relation
capacitance multiplier is build up by cascading between the current and voltage of the MOSFET device
current multiplier cells (CMC). The circuit is or logarithmic relation in BJT devices. Moreover, the
preferred for low power low voltage applications current mode signal processing has the advantage of
since it is based on CMOS inverters and op-amps wide bandwidth, greater linearity, and simple circuitry
only. The capacitance multiplier is employed in the over voltage-mode signal processing.
design of a second-order LPF with a programmable In section II, the CMC principle of operation is
cutoff frequency. The cutoff frequency can be as low discussed. The implementation of the capacitance
as 65 Hz using an on-chip capacitor of 1pF only. The multiplier is explained in section III. The design of the
static power dissipation is equal to 3 mW. Some second-order low pass filter is demonstrated in section
practical considerations are discussed. The circuit is IV. Error analysis and performance improvement are
simulated using CMOS 0.13µm process. Simulation provided in section V. Finally, conclusion is presented in
results show good agreement with the analytical section VI.
calculations.
II. OPERATION OF OUR PROPOSED CMC
I. INTRODUCTION
The schematic diagram and the symbol of our proposed
Many applications, such as sensors, MEMS and CMC are shown in Fig.1-a and b respectively.
biomedical devices require filters with very low cutoff
FBINV
frequencies. To implement such filters one can use large
2 1
resistance while the other can use large capacitance.
Large capacitance can not be implemented on an
11
integrated circuit because it consumes large silicon area, Iin INV1
2
and also is prone to coupling noise. In large resistance 1
+
3
Vo
1 2 io1
-
design, additionally to area consumption, the power loss Vb
INV2
becomes significant. 7
Io
1 2 io2 Vx
Many techniques are developed to solve this problem.
Active capacitance multiplier [1] is one of these .
.
techniques. The capacitance amplification done by .
INVn
Cataldo et. al.[1] used resistors which lead to raise many 1 2 ion
sources of errors. Cataldo also proposed an alternative
circuit topology; in which the power consumption is
highly dependent on the multiplication factor. In [2] they
use a programmable trancsconducatnce value of the
(a)
OTA to control the pole of the filter.

978-1-4244-1847-3/07/$25.00 ©2007 IEEE IEEE ICM - December 2007

Authorized licensed use limited to: NXP Semiconductors. Downloaded on August 18,2023 at 03:34:50 UTC from IEEE Xplore. Restrictions apply.
 Iin
T1
X
CMC Io
(n) Z
Vb Y C=KC1

0
(b)
(a)
Fig.1 (a) CMC schematic diagram. (b) CMC symbol.
Iin
C1 nIin
The basic principle of this circuit is that when Iin is 0 X
CMC1
X
CMC2 n2Iin
X
CMCm
(n) Z (n) Z ... (n) Z
applied to the input of the circuit, it will flow into the Y Y Y

feedback inverter (FBINV). The FBINV is matched to Io

each output inverter (INV1 through INVn). So, if Vx is K*C1

set to be equal to Vb then, the same current (Iin) will flow
into the output of each inverter connected to the output.
Consequently, the total output current (Io) is equal to n× (b)
Iin, where n is the number of the output inverters. In this
case, n is considered to be the multiplication factor of Fig.3 Grounded-capacitor realization (a) Actual
this block. By cascading this block to m stages, the total connectivity (b) Active grounded-capacitor multiplier.
multiplication factor (K) will be nm, as shown in Fig.2.

(B) Floating Capacitor Realization

Iin
nIin
X X X
CMC1
(n) Z
CMC2
(n) Z
n2Iin
...
CMCm
(n) Z
Generally, the floating-capacitor is the capacitor in
Y Y Y
which neither of its terminals is connected to ground, as
Io shown in Fig.4-a. The equivalent active floating-
capacitor implementation is shown in Fig. 4-b.
Fig.2 Cascaded CMC. T1

C=n2 C1

III. CAPACITANCE AMPLIFIER T2

As an application of the CMC is the impedance (a)

amplification. Here, we will focus on capacitance
amplification to use it in a very low cutoff frequency
filters desing. There are two strategies to implement the Y Y
capacitor, based on its connectivity in the circuit. if one CMC CMC Io=n2I
(n) Z (n) Z T1
of the capacitor terminals is connected to ground, it will X X
be implemented using grounded capacitor technique. But I
if both terminals are not connected to ground, it will be
implemented by the floating capacitor technique. The C1
two techniques are examined as follows:

(A) Grounded Capacitor Realization Y

CMC
Y
CMC Io=n2I
I (n) Z (n) Z
X X T2
One of the simplest connection of the capacitor is
grounded capacitor, shown in Fig. 3-a. The active
capacitor implementation is designed, as shown in Fig.
3-b. In this circuit, the real integrated capacitor C1 is (b)
equal to C/K, i.e. the on-chip capacitor area will be Fig.4 Floating capacitor realization. (a) Equivalent
reduced by factor K. The lower value of C1 is limited by circuit. (b) Using capacitance multiplier.
the thermal noise.

IEEE ICM - December 2007

Authorized licensed use limited to: NXP Semiconductors. Downloaded on August 18,2023 at 03:34:50 UTC from IEEE Xplore. Restrictions apply.
IV. SECOND ORDER LPF CIRCUIT DESIGN

To illustrate the realization of both grounded and

floating capacitor, a second order LPF shown in Fig.5-a
can be implemented using our proposed circuits. The
new topology of the second order LPF is shown in Fig.
5-b. In this circuit, the value of C2, which is grounded-
capacitor, is equal to n2 × C4 and the value of C1, which
is floating-capacitor, is equal to n2 × C3. In our proposed
circuit, there is no need to use the unity gain op-amp,
since the main function of the op-amp is to maintain the
output voltage to be equal to the voltage across C2
regardless the output current value. This can be done (a)
using the dummy CMC block.

(a)

(b)

Fig.6(a) Op-amp circuit. (b) Frequency response

The circuit shown in Fig.5-b is designed for different

cutoff frequencies (65.59, 1.268K and 5.3K Hz,
respectively) with supply voltage of 1.5V. The
programmability is done only by changing the
multiplication factor, K, to be equal to 214, 104 and 74,
respectively. The resistance values are 8 KΩ each. The
capacitor values are 1pF each. The frequency response
of the proposed circuit is shown in Fig. 7, which
demonstrates good agreement with the designed
parameters. The circuit reports low static-power
consumption of 3 mW.

(b)
Fig.5 (a) Ordinary second order LPF. (b) Second order
LPF with capacitance multiplier.

The circuit shown in Fig. 5-b is designed using 0.13µm

CMOS technology. The op-amp circuit which is used in
CMC is shown in Fig. 6-a. The op-amp is designed for
48 dB open loop gain with GBW of 26 MHz while it is
loaded with 10 inverters) as shown in Fig. 6-b.

IEEE ICM - December 2007

Authorized licensed use limited to: NXP Semiconductors. Downloaded on August 18,2023 at 03:34:50 UTC from IEEE Xplore. Restrictions apply.
 The aforementioned equation shows the importance of
having a large gain op-amp for highly accurate
multiplication factor. Also, the required accuracy of the
CMC is limited by the maximum number of the CMOS
inverters connected in parallel at the output section of
CMC. Moreover, the maximum current driven by the
CMC limits the maximum number of the CMC cascaded
stages. This maximum current is limited by the ability of
the FBINV of the last stage to source/sink current. The
FBINV current limits depend on the inverter design and
maximum swing of the op-amp.

VI. CONCLUSION

Fig.7 Frequency response of the second order LPF with
capacitance multiplier
V. PRACTICAL CONSIDERATIONS
In practical design, some considerations should be
highlighted due to its significant effect on the systematic
error. One of the major sources of errors is the finite
open loop gain of the op-amp which impacts the
multiplication factor n.
The current error ∆I of the CMC circuit, shown in Fig. 8,
can be expressed as follow:
In this paper, a new technique for an active capacitance
implementation has been introduced. The designed
circuit is based only on the conventional CMOS inverter
as a transconductance cell. Therefore, the proposed
circuit is suitable for low voltage and low power
operation. The proposed active capacitance has been
tested for two capacitor topologies (grounded and
floating capacitor). These capacitors have been
incorporated into a second-order lowpass filter. The
filter has been designed and simulated by using 0.13µm
technology available from IBM. Some practical
considerations are studied. The circuit is designed for 1.5
supply voltage with programmability cutoff frequency
and the static power dissipation is equal to 3 mW.

ACKNOWLEDGMENT

Where; The authors would like to thank the MOSIS Company

A:is the open loop gain of the op-amp. and IBM foundry for providing us with the models used
gmp: is the inverter PMOS transconductance. in this work.
gmn: is the inverter NMOS transconductance.
C: is the load capacitance. REFERENCES
ω: is the radian frequency. [1] G. Di Cataldo, G. Ferri, S. Pennisi, "Active
and capacitance multipliers using current conveyors",
International Symposium on Circuits and Systems
(ISCAS), vol. 1, pp., 1998.
Where; [2] A. Arnaud and C. Galup-Montoro, "A fully
rop: is the output impedance of PMOS. integrated 0.5 - 7 Hz CMOS bandpass amplifier",
ron: is the output impedance of NMOS. International Symposium on Circuits and Systems
(ISCAS), Vancouver, Canada, vol. 1, pp.445-448,
May 2004.
[3] A. S. Sdedra and K. C. Smith,"A second generation
current conveyor and its applications" IEEE
Transactions on circuits and systems, Vol. CT-
17.pp.132-14,Feb.1970.
[4] F. A. Farag and H. F. A. Hamed "Low Voltage Low
Power CMOS Current Conveyor Cells" International
Computer Engineering Conference (ICENCO2004)
Fig.8 CMC block p.p 642-645, Dec.2004.

IEEE ICM - December 2007

Authorized licensed use limited to: NXP Semiconductors. Downloaded on August 18,2023 at 03:34:50 UTC from IEEE Xplore. Restrictions apply.