Final DDCOLab Manual

Maharaja Education Trust(R), Mysuru
Maharaja Institute of Technology Mysore

Belawadi, SrirangaPattana Taluk, Mandya –571477
Approved by AICTE, New Delhi,

Affiliated to VTU, Belagavi & Recognized by Government of Karnataka
LabManual
Digital Design & Computer Organization (BCS302)

Prepared by:
Ms. MALASHREE M S
Assistant Professor
Department of Computer Science Engineering
MIT Mysore
Department of Computer Science and Engineering
Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 1

MAHARAJA INSTITUTE OF TECHNOLOGY MYSORE
Behind Belawadi, KRMills, Srirangapatna(T), Mandya-571477
SYLLABUS AND INDEX
Subject: Digital Design and Computer Organization Subject Code: BCS302
SL. Contents
No.
Given a 4-variable logic expression, simplify it using appropriate

1 technique and simulate the same using basic gates.
Design a 4 bit full adder and subtractor and simulate the same using
2 basic gates.
Design Verilog HDL to implement simple circuits using structural, Data

3 flow and Behavioural model.
Design Verilog HDL to implement Binary Adder-Subtractor – Half and

4 Full Adder, Half and Full Subtractor.
Design Verilog HDL to implement Decimal adder.

5
Design Verilog program to implement Different types of multiplexer like

6 2:1, 4:1 and 8:1.
Design Verilog program to implement types of De-Multiplexer.

7
Design Verilog program for implementing various types of Flip-Flops such

8 as SR, JK and D.

Simulation Package P-Spice:
Simulation is designed to provide a realistic imitation of the operation of a real-world process or

system over time. Example: The control and operation of a vehicle, aircraft or other complex
system used for training.
SPICE (Simulation Program for Integrated Circuits Emphasis) is a general purpose analog
circuit simulator, that allows the user simulate a circuit and verify circuit designs and to predict
the circuit behavior and also extract key voltage & current.
P-Spice is a PC version of SPICE and H-Spice is a version that runs on workstations and larger
computers. P-Spice has analog and digital libraries of standard components (such as NAND,
NOR, flip-flops, and other digital gates, op-amps, etc) which makes it a useful tool for a wide
range of analog and digital applications.
XilinxISE:
Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile") their
designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to
different stimuli, and configure the target device with the programmer.
In electronics ,a hardware description language (HDL) is a specialized computer language used
to describe the structure and behavior of electronic circuits ,and most commonly ,digital logic
circuits.
Register-transfer-level abstraction is used in hardware description languages (HDLs) like
Verilog and VHDL to create high-level representations of a circuit, from which lower-level
representations and ultimately actual wiring can be derived.Design at the RTL level is typical
practice in modern digital design.
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model
electronic systems. It is most commonly used in the design and verification of digital circuits at
the register-transfer level of abstraction. It is also used in the verification of on a log circuits and
mixed-signal circuits, as well as in the design of genetic circuits
AND GATE:
The AND gate performs logical multiplication known as AND function .if any one of the
input is low then output will be low. When the output is high means two inputs are high.
Fig: Truth table Fig: Pin layout Fig: Timing diagram

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high,
when any one of the input is high .The output is low when both the inputs are low.
Fig: Symbol & truth table Fig: Pin diagram Fig: Timing diagram
NOTGATE:
The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and
any one of the input is low .The output is low level when both inputs are high. The Nand-gate is
an and-gate with an inverter on the output .So instead of drawing several gates like this:
We draw a single and-gate with a little ring on the output like this:

The Nand-gate, like the and-gate can take an arbitrary number of inputs. The truth table for the
Nand-gate is like the one for the and-gate, except that all output values have been inverted:
NORGATE:
The nor-gate is an or-gate with an inverter on the output. So instead of drawing several gates we
can write like this:
We draw a single or-gate with a little ring on the output like this:
The nor-gate, like the or-gate can take an arbitrary number of inputs. The truth table for the nor-
gate is like the one for the or-gate, except that all output values have been inverted:

Exclusive-ORGATE:
The “Exclusive OR Gate” is another type of digital logic gate commonly used in arithmetic
operations since it can be used to give the sum of two binary numbers as well as error-detection and
correction circuits.
Logic Design Software Experiments:

It is one of most popular of software tool used to synthesize VHDL code .This tool Includes
many steps. To make user feel comfortable with the tool the steps are given below:-
1. Double click on Project navigator.(Assumed icon is present on desktop).
 Select NEW PROJECT in FILEMENU.
 Enter following details as per your convenience
 Project name: sample
 Project location: C:\example
 Top level module: HDL
2. In NEWPROJECT dropdown Dialog box, Choose your appropriate device specification.

Example is given below:
 Device family: Spartn2
 Device: xc2s200
 Package: PQ208
 TOP Level Module: HDL
 Synthesis Tool: XST
 Simulation: Model sim /others
 Generate sim lang: VHDL

3.In source window right click on specification, select new

source Enter the following details
Entity: sample
Architecture: Behavioral
Enter the input and output port and modes.
This will create sample.VHD source file. Click Next and finish the initial Project
preparation.
4. Double click on synthesis. If error occurs edit and correct VHDL code
5. Double click on Lunch model sim (or any equivalent simulator if you are using) for
functional simulation of your design.
6.Right click on sample.VHD in source window, select new
source
Select source: Implementation constraints file.
Filename: sample
This will create sample. UCF constraints file.
7. Double click on Edit constraint (Text) in process
window. Edit and enter pin constraints with syntax:
NET“NETNAME”LOC=“PINNAME”
8. Double click on Implement, which will carry out translate, mapping, place and route of your
design. Also generate program file by double clicking on it, intern which will create .bit file.
9. Connect JTAG cable between your kit and parallel pot of your computer.
10. Double click on configure device and select mode in which you want to configure your device.
For ex: select slave serial mode in configuration window and finish your configuration
11. Right click on device and select ‘program ’. Verify your design giving appropriate inputs and
check for the output.
12. Also verify the actual working of the circuit using pattern generator &logic analyzer.

1. Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same using basic gates.
Aim: To simulate the 4 variable expressions realized using basic gates.
Theory: Boolean algebra is a branch of mathematics that deals with operations on logical values
with binary variables. The Boolean variables are represented as binary numbers to represent truths:
1 = true and 0 = false. Elementary algebra deals with numerical operations whereas Boolean algebra
deals with logical operations.
Boolean algebra is the category of algebra in which the variable’s values are the truth values, true
and false, ordinarily denoted 1 and 0 respectively. It is used to analyze and simplify digital circuits
or digital gates. It is also called Binary Algebra or logical Algebra. It has been fundamental in the
development of digital electronics and is provided for in all modern programming languages. It is
also used in set theory and statistics.
The important operations performed in Boolean algebra are – conjunction (∧), disjunction (∨) and
negation (¬). Hence, this algebra is far way different from elementary algebra where the values of
variables are numerical and arithmetic operations like addition, subtraction is been performed on
them.
Assume that the 4-variable Boolean function Y = F(A,B,C,D) = ∑ (2, 4, 5, 7, 10, 14)
INPUT OUTPUT
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

Result: Boolean expression is verified
2. Design a 4 bit full adder and Subtractor and simulate the same using basic gates.
Aim: To simulate 4bit adder and subtractor
Theory: In digital circuits, an adder–subtractor is a circuit that is capable

of adding or subtracting numbers (in particular, binary). Below is a circuit that adds or subtracts
depending on a control signal. It is also possible to construct a circuit that performs both addition
and subtraction at the same time.
Having an n-bit adder for A and B, then S = A + B. Then, assume the numbers are in two's
complement. Then to perform B − A, two's complement theory says to invert each bit of A with
a NOT gate then add one. This yields S = B + A + 1, which is easy to do with a slightly modified
adder.
By preceding each A input bit on the adder with a 2-to-1 multiplexer where:
 Input 0 (I0) is A
 Input 1 (I1) is A
that has control input D that is also connected to the initial carry, then the modified adder performs
 addition when D = 0, or
 subtraction when D = 1.
This works because when D = 1 the A input to the adder is really A and the carry in is 1.
Adding B to A and 1 yields the desired subtraction of B − A.
A way you can mark number A as positive or negative without using a multiplexer on each bit is to
use an XOR gate to precede each bit instead.
 The first input to the XOR gate is the actual input bit
 The second input for each XOR gate is the control input D
This produces the same truth table for the bit arriving at the adder as the multiplexer solution does
since the XOR gate output will be what the input bit is when D = 0 and the inverted input bit
when D = 1.

Fig: 4 bit Adder/Subtractor
TRUTH TABLE FOR 4BIT FULL ADDER
cin A3 A2 A1 A0 B3 B2 B1 B0 Out3 out2 out1 out0 CO

0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 1 0 0 0
0 0 0 1 1 0 0 1 1 0 1 1 0 0
0 0 1 0 0 0 1 0 0 1 0 0 0 0
0 0 1 0 1 0 1 0 1 1 0 1 0 0
0 0 1 1 0 0 1 1 0 1 1 0 0 0
0 0 1 1 1 0 1 1 1 1 1 1 0 0
0 1 0 0 0 1 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 0 1 0 0 1 0 1
0 1 0 1 0 1 0 1 0 0 1 0 0 1
0 1 0 1 1 1 0 1 1 0 1 1 0 1
0 1 1 0 0 1 1 0 0 1 0 0 0 1
0 1 1 0 1 1 1 0 1 1 0 1 0 1
0 1 1 1 0 1 1 1 0 1 1 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
Fig: 4bit full adder/subtractor

TRUTH TABLE FOR 4 BIT FULL SUBSTRACTOR
cin A3 A2 A1 A0 B3 B2 B1 B0 D3 D2 D1 D0 BO
1 0 0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 0 1 1
1 0 0 1 1 0 0 0 1 0 0 1 0 1
1 0 1 0 0 0 0 1 1 0 0 0 1 1
1 1 0 0 0 0 0 1 0 0 1 1 0 1
1 1 0 1 0 0 1 1 0 0 1 0 0 1
1 0 1 1 1 0 1 1 1 0 0 0 0 1
1 0 0 1 0 0 1 0 0 1 1 1 0 0
1 1 0 0 1 1 0 1 1 1 1 0 1 0
1 1 0 1 0 1 0 1 1 1 1 1 1 0
1 0 1 1 1 1 0 1 1 1 1 0 0 0
1 0 1 1 0 1 1 0 0 1 0 1 0 0
1 1 0 0 1 1 1 1 1 1 0 1 0 0
1 1 0 1 0 1 1 1 0 1 1 0 0 0
1 1 1 1 0 1 1 1 1 1 1 1 1 0
RESULTS & CONCLUSIONS:
1) The truth table of 4-bit adder/subtractor is verified.
3. Design Verilog HDL to implement simple circuit using structural, Data flow and behavioural
model.
Aim: To implement simple circuit using Structural, Data flow and Behavioural model.
Theory: Verilog HDL composed of a text using keywords. Keywords are identifiers that defines
the language constrains like module, endmodule, input, output, wire, not,or etc.
Verilg HDL describes the digital circuits as a set of modules, a module is basic building block of a
Verilog HDL. It is declared by the keyword module and always terminated by the keyword
endmodule. Each of this module has an interface to other module to describe how they are
interconnected.
Modeling techniques used to describe the circuits are:

i) Dataflow modeling: concurrent statements are used to describe the flow of signal
ii) Behavioural modeling: Describes the behavior of functionality of the circuit
iii) Gate level or structural modeling: Components or gates are used to model the circuit

Fig: simple Circuit

Dataflow:
module simple_circuit(A,B,C,D);
input A,B,C;
output D;
wire w1,w2,w3,w4;
assign w1=(!B);
assign w2=(!C);
assign w3=(A && w1);
assign w4=(A && w2);
assign w3=(w3 && w4);
endmodule
Behavioural:
input A,B,C;
output D;
reg D;
wire w1,w2,w3,w4;
always@(A,B,C)
begin
w1=(!B);
w2=(!C);
w3=(A && w1);
w4=(A && w2);
w3=(w3 && w4);
endmodule
Structural:
input A,B,C;
output D;
wire w1,w2,w3,w4;
not (w1,B);
not (w2,C);
and (w3,A,w1);
and (w4,A,w2);
or (D,w3,w4);
endmodule

1. Structural, Data flow and Behavioural model using Verilog HDL is implemented and verified

4. Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half
and Full Subtractor.
Aim: To simulate half adder, full adder, half subtractor and full subtractor in VHDL
Theory: Adder circuit is a combinational digital circuit that is used for adding numbers. A
typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as
the output. Adders are used in the arithmetic logic units, in other parts of the processor, where
they are used to calculate addresses, table indices, increment and decrement operators.
 Half-Adder: A combinational logic circuit that adds two single binary digits A and B. It has
two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next
digit of a multi-digit addition.
 Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit (Cin). A combinational logic
circuit that adds two data bits A, B, and a carry-in bit Cin, is called a full-adder. It has
two outputs, sum (S) and carry (C).
 Subtractor circuit is a combinational digital circuit that is used for subtracting numbers.
A typical subtractor circuit produces a diffrence bit (denoted by D) and a brrow bit
(denoted by B) as the output.
 Half Subtractor: The half-subtractor is a combinational circuit which is used to perform

subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two
outputs D (difference) and B (borrow).
 Full Subtractor: A combinational circuit of full-subtractor performs the operation of

subtraction of three bits—the minuend, subtrahend, and borrow generated from the
subtraction operation of previous significant digits and produces the outputs difference and
borrow.
PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.

4. Give supply to the trainer kit.
5. Provide input data to the circuit via switches.
6. Observe the outputs and verify the Truth Table

Half Adder Circuit Half Subtractor Circuit
Full Adder Circuit Full Subtractor Circuit
OBSERVATION TABLE:
Truth Table for Half Adder: Truth Table for Half Subtractor:
Input Output Input Output

A B sum carry A B Diff Borrow
0 0 0 0 0 0 0 0
0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 1
SUM = A̅∙ B + A ∙ B̅ Difference = A̅∙ B+A ∙ B̅

CARRY = A ∙ B Borrow = A̅∙ B

Truth Table for Full Adder: Truth Table for Full Subtractor:
Input Output Input Output

A B Cin Sum carry A B Cin Diff Borrow
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 0 1 0 1 1
0 1 1 0 1 0 1 1 0 1
1 0 0 1 0 1 0 0 1 0
1 0 1 0 1 1 0 1 0 0
1 1 0 0 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1
Carry =∑(3, 5, 6) Borrow =∑(1, 2, 3, 7)

(after simplifying using K map) (after simplifying using K map)
Carry = A. B + B. C + C. A Borrow= A̅. C + A̅. B +
B. C
SIMULATION:
Half Adder VHDL Code:

library IEEE;
useIEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.All;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HalfAdder is
Port ( A, B : in STD_LOGIC;
Sum, Carry : out STD_LOGIC);
end HalfAdder;
architecture equation of HalfAdder is
begin
sum <= ((not A)and B)or(A and(notB));
carry <= A and B;
end equation;

Output Waveform for Half Adder:
Half Subtractor VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity HalfSub is
Port ( A,B : in STD_LOGIC;
Diff,Borrow : out STD_LOGIC);
end HalfSub;
architecture equation of HalfSub is
begin
Diff<=((not A)and B)or(A and(not B));
Borrow<=((not A)and B);
end equation;
Output Waveform for Half Subtractor:
Full Adder VHDL Code:

library IEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
entity FullAdder is
Port ( A,B,C : in STD_LOGIC;
Sum,Carry : outSTD_LOGIC); end FullAdder;
architecture equation of
FullAdder is begin
sum<=(((not A)and(not b)and c)or((not A)and B and(not C))or(a and(not B)and(not C))or(A
and B and C));
carry<=(A and B)or(B and C)or(A and C);
end equation;

Output Waveform for Full Adder:
Full Subtractor VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
entity FullSubtractor is
Port ( A,B,C : in STD_LOGIC;
Diff,Borrow : out STD_LOGIC);
end FullSubtractor;
architecture equation of FullSubtractor is begin
Diff <= (((not A)and(not b)and c)or((not A)and B and(not C))or(a and(not B)and(not
C))or(A and B and C));
Borrow <= (A and B)or(B and C)or(A and C);
end equation;
Output Waveform for Full Subtractor:
1. The truth table of half adder, half subtractor, full adder and full subtractor is verified.
2. The output waveform of half adder, half subtractor, full adder and full subtractor is
simulated and verified
5. Design Verilog HDL to implement Decimal adder.

Aim: To simulate Decimal adder in VHDL
Theory: BCD stands for binary coded decimal. It is used to perform the addition of BCD
numbers. A BCD digit can have any of ten possible four-bit representations. Suppose, we have
two 4-bit numbers A and B. The value of A and B can vary from 0(0000 in binary) to 9(1001 in
binary) because we are considering decimal numbers.

Fig: symbol and circuit of of 4-bit adder
Truth table
Verilog code for BCD addition:
//module declaration with inputs and outputs

module bcd_adder(a,b,carry_in,sum,carry);
//declare the inputs and outputs of the module with their sizes.
input [3:0] a,b;
input carry_in;
output [3:0] sum;
output carry;
//Internal variables
reg [4:0] sum_temp;
reg [3:0] sum;
reg carry;
//always block for doing the addition

always @(a,b,carry_in)
begin
sum_temp = a+b+carry_in; //add all the inputs
if(sum_temp > 9)

begin
sum_temp = sum_temp+6; //add 6, if result is more than 9.
carry = 1; //set the carry output
sum = sum_temp[3:0];
end
else begin
carry = 0;
sum = sum_temp[3:0];
end
end
endmodule
Output waveform
1) The truth table of Decimal adder is verified.

2) The output waveform of Decimal adder is simulated and verified
6. Design Verilog program to implement different types of multiplexer like 2:1, 4:1 and 8:1.
Aim: To simulate 2:1, 4:1 and 8:1 multiplexer in VHDL
Theory: A multiplexer (or mux; spelled sometimes as multiplexor), also known as a data selector,
is a device that selects between several analog or digital input signals and forwards the selected
input to a single output line.[1] The selection is directed by a separate set of digital inputs known as
select lines. A multiplexer of inputs has select lines, which are used to select which input line to
send to the output.
A multiplexer makes it possible for several input signals to share one device or resource, for
example, one analog-to-digital converter or one communications transmission medium, instead of
having one device per input signal. Multiplexers can also be used to implement Boolean
functions of multiple variables.

Fig: symbol and truthtable of 2:1 mux
// Behavioral description of 2-to-1 line multiplexer

module mux2x1_bh (A,B,select,Y); i
nput A,B,select;
output Y;
reg Y;
always @(select or A or B)
if (select==1)
Y=A;
else
Y=B;
Endmodule
Output Waveform for 2:1 multiplexer:
4:1 MULTIPLEXER

Fig: symbol and truth table of 4:1 mux

module mux4x1_bh (i0,i1,i2,i3,select,y);
input i0,i1,i2,i3;
input [1:0]select;
output y;
reg y;
always @( i0 or i1 or i2 or i3 or select)
case (select)
2’b00: y=i0;
2’b01: y=i1;
2’b10: y=i2;
2’b11: y=i3;
Endcase
Endmodule
8:1 MULTIPLEXER
Fig: symbol and truth table of 8:1 mux


module Mux(in,sel,y);
input [7:0]D;
input [2:0]sel;
output reg out;
always @(*)
case(sel)
3'd0:y=D[0];
3'd1:y=D[1];
3'd2:y=D[2];
3'd3:y=D[3];
3'd4:y=D[4];
3'd5:y=D[5];
3'd6:y=D[6];
3'd7:y=D[7];
endcase
endmodule
 The truth table of 2:1, 4:1 and 8:1 multiplexer is verified.

 The output waveform of 2:1, 4:1 and 8:1 multiplexer simulated and verified.
7. Design Verilog program to implement types of De-multiplexer.
Aim: To simulate 1:2, 1:4 and 1:8 Demultiplexer in VHDL

Theory: A demultiplexer is a digital circuit that takes a single input signal and chooses one of
several output lines based on a set of control signals (also known as a demux or data selector). It
essentially serves the opposite purpose from a multiplexer, which selects one output from a multiple
of inputs.
//1:8 Demultiplexer

Fig: Symbol and truth table of 1:8 Demux

module Demultiplexer1_8(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2 & ~s1 &~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule
Waveform of 1:8 Demux
//1:4 Demultiplexer
Fig: Symbol and truth table of 1:4 Demux
module Demultiplexer1_4(in,s0,s1,d0,d1,d2,d3);
input in,s0,s1;
output d0,d1,d2,d3;
assign d0=(in & ~s1 & ~s0 ),
d1=(in & ~s1 &s0),
d2=(in & s1 &~s0),
d3=(in & s1 &s0),
endmodule
OR
module demux1_4(a_in,sel,y_out)
input[1:0]sel;
output[3:0]y_out;
reg[3:0]y_out;
always@(a_in,sel)
begin
case(sel)
2’b00:beginy_out[0]=a_in;y_out[1]=1’b0;
y_out[2]=1’b0;y_out[3]=1’b0;
end
2’b01:beginy_out[0]=1’b0;y_out[1]=a_in;
y_out[2]=1’b0;y_out[3]=1’b0;
end
2’b10:begin y_out[0]=1’b0;y_out[1]=1’b0;
y_out[2]=a_in;y_out[3]=1’b0;
end
2;b11:begin y_out[0]=1’b0;y_out=1’b0;
y_out[2]=1’b0;y_out[3]=a_in;
end
default:y_out=3’b000;
endcase
end
endmodule
Output waveform of 1:4 Demux

1:2 Demultiplexer
Fig: Symbol and truth table of 1:2 demux

Simulation
module Demux_1_2(
input s,
input d,
output y0,
output y1);
not(sn,s);
and(y0,sn,d);
and(y1,s,d);
endmodule
 The truth table of 2:1, 4:1 and 8:1 multiplexer is verified.

 The output waveform of 2:1, 4:1 and 8:1 multiplexer simulated and verified
8. Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
Aim: To simulate SR, JK and D Flipflop in VHDL
Theory: In electronics, flip-flops and latches are circuits that have two stable states that can store
state information – a bistable multivibrator. The circuit can be made to change state
by signals applied to one or more control inputs and will output its state (often along with its logical
complement too). It is the basic storage element in sequential logic. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers, communications, and
many other types of systems.
Flip-flops and latches are used as data storage elements to store a single bit (binary digit) of data;
one of its two states represents a "one" and the other represents a "zero". Such data storage can be
used for storage of state, and such a circuit is described as sequential logic in electronics. When
used in a finite-state machine, the output and next state depend not only on its current input, but
also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and
for synchronizing variably-timed input signals to some reference timing signal.
SR Flip-flop:
The SR Flip-Flop is also known as the gated or clocked SR latch. The clocked SR latch or SR flip-
flop temporarily stores or holds the information until it is needed in digital circuits. ‘S’ and ‘R’ are
the two inputs to the SR flip-flop. It has two outputs, the main output ‘Q’ and the complements of
the main output ‘ Q’ ‘. The SR Flip-Flop is a storage element with only one bit.

The SR flip-flop is a gated SR flip-flop with a clock input circuitry that does not prevent the illegal
or invalid output state that can arise when both inputs S and R are equal to logic level “1”. The SR
latch is constructed using two cross-coupled NAND gates. Let us discuss in detail about these in the
upcoming sections.
Fig: symbol and truth table of SR flip-flop
Circuit Diagram:
Simulation:
module srff(clk,s,r,q,qb);
input clk,s,r;
output reg q,qb;
always @ (posedge clk)begin

case({s,r})
2'b00:
q <= q;
qb<=~q;
2'b01:
q <= 0;
qb<=~q;
2'b10:
q <= 1;
qb<=~q;
2'b11:
q <= 1'bx;
qb<=~q;
default:

q <= q;
endcase
end
Output waveform of SR Flip-flop
JK Flip-flop:
JK Flip Flop is one of the most used flip-flops in digital circuits. The universal flip flop has two
inputs, ‘J’ and ‘K.’ The JK Flip Flop is a gated SR Flip-Flop with a clock input circuitry that
prevents the illegal or invalid output when both inputs S and R are equal to logic level “1.”
In the SR Flip-Flop, the ‘S’ and ‘R’ are the shortened abbreviated letters for the Set and Reset, but J
and K are not. Instead, the J and K are autonomous letters chosen to distinguish the flip flop design
from other types. Let us discuss in detail JK Flip-Flop in the upcoming sections.
Fig: Symbol and truth table of JK Flip-flop
Circuit Diagram:

Simulation:
module jkff(clk,j,k,q,qb);
input clk,j,k;
output reg q,qb;
always @ (posedge clk)begin

case({j,k})
2'b00:
q <= q;
qb<=~q;
2'b01:
q <= 0;
qb<=~q;
2'b10:
q <= 1;
qb<=~q;
2'b11:
q <= ~q;
qb<=~q;
default:
q <= q;
endcase
end
endmodule
Output waveform of SR Flip-flop
D Flip-flop:
D flip-flop is a two-input flip-flop. The inputs are the data (D) input and a clock (CLK) input. The
clock is a timing pulse generated by the equipment to control operations. The D flip-flop is used to
store data at a predetermined time and hold it until it is needed. This circuit is sometimes called a

delay flip-flop. In other words, the data input is delayed up to one clock pulse before it is seen in the
output.
The simplest form of a D flip-flop is shown in the figure below, view A. Now, follow the
explanation of the circuit using the truth table and the timing diagram shown in the figure,
Fig: Symbol and truth table of D flip-flop
Circuit diagram:
Simulation:
module RisingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q);
input D;
input clk;
input sync_reset;
output reg Q;
always @(posedge clk)
begin
if(sync_reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule

Output waveform:
 The truth table of half adder, half subtractor, full adder and full subtractor is verified
 The output waveform of half adder, half subtractor, full adder and full subtractor is
simulated and verified

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Maharaja Education Trust(R), Mysuru

Maharaja Institute of Technology Mysore

Approved by AICTE, New Delhi,

Digital Design & Computer Organization (BCS302)

Department of Computer Science and Engineering

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 1

SYLLABUS AND INDEX

Subject: Digital Design and Computer Organization Subject Code: BCS302

Given a 4-variable logic expression, simplify it using appropriate

Design Verilog HDL to implement simple circuits using structural, Data

Design Verilog HDL to implement Binary Adder-Subtractor – Half and

Design Verilog HDL to implement Decimal adder.

Design Verilog program to implement Different types of multiplexer like

Design Verilog program to implement types of De-Multiplexer.

Design Verilog program for implementing various types of Flip-Flops such

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 2

Simulation Package P-Spice:

Simulation is designed to provide a realistic imitation of the operation of a real-world process or

Fig: Truth table Fig: Pin layout Fig: Timing diagram

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 3

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 4

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 5

Logic Design Software Experiments:

2. In NEWPROJECT dropdown Dialog box, Choose your appropriate device specification.

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 6

3.In source window right click on specification, select new

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 7

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 8

Result: Boolean expression is verified

Aim: To simulate 4bit adder and subtractor

Theory: In digital circuits, an adder–subtractor is a circuit that is capable

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 9

Fig: 4 bit Adder/Subtractor

TRUTH TABLE FOR 4BIT FULL ADDER

cin A3 A2 A1 A0 B3 B2 B1 B0 Out3 out2 out1 out0 CO

Fig: 4bit full adder/subtractor

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 10

TRUTH TABLE FOR 4 BIT FULL SUBSTRACTOR

RESULTS & CONCLUSIONS:

1) The truth table of 4-bit adder/subtractor is verified.

Modeling techniques used to describe the circuits are:

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 11

Fig: simple Circuit

RESULTS & CONCLUSIONS:

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 12

 Half Subtractor: The half-subtractor is a combinational circuit which is used to perform

 Full Subtractor: A combinational circuit of full-subtractor performs the operation of

3. Make connections as shown in the circuit diagram.

6. Observe the outputs and verify the Truth Table

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 13

Half Adder Circuit Half Subtractor Circuit

Full Adder Circuit Full Subtractor Circuit

Input Output Input Output

SUM = A̅∙ B + A ∙ B̅ Difference = A̅∙ B+A ∙ B̅

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 14

Input Output Input Output

Carry =∑(3, 5, 6) Borrow =∑(1, 2, 3, 7)

Half Adder VHDL Code:

Prof. Malashree M S, Dept of CSE, MIT, Mysore Page 15

Output Waveform for Half Adder:

Half Subtractor VHDL Code:

Output Waveform for Half Subtractor:

Full Adder VHDL Code: