Digital IC technology Advanced rapidly = Small-scale integration (SSI), with fewer than 12 gates per chip = Medium-scale integration (MSI), with 12 to 99 equivalent gates per chip = Large-Scale and Very Large Scale integration (LSI and VLSI), tens of thousands of gates per chip = Ultra-large-scale integration (ULSI), with over 100,000 gates per chip = Giga-scale integration (GSI), with 1 million or more gates.Digital IC technology Complexity Number of Gates Small-scale integration(SSl) Fewer than 12 Medium-scale integration(MSI) 12 to 99(10? - 10°) Latge-scale integration(LSl) 100 to 9,999(10° ~ 10°) Very large-scale integration(VLSI) 10,000 to 99,999(10° - 10”) Ulira large-scale integration(ULS)) 100,000 to 999,999(10' - 10°) Giga-scale integration(GS)) 1,000,000 or more( 10° - 10"') Tera-scale integration(TSl) (10"? or more)O Most of the reasons that modern digital systems use integrated circuits (adv.) = Integrated circuits pack a lot more circuitry in a small package «The overall size of any digital system is reduced «The cost is dramatically reduced because of the economies of mass-producing large volumes of similar devices = Integrated circuits have made digital systems more reliable by reducing the number of external interconnections + Discrete components(transistor, diode, resistor, etc.) are protected from poor soldering, breaks or shorts in connecting paths on a circuit board. = Integrated circuits reduced the amount of electrical power.There are some things that Integrated Circuits cannot do (Dis.) e Integrated circuits can not handle very large currents or voltages (because the heat generated in such small spaces would cause temperatures to rise beyond acceptable limits) e Integrated circuits can not easily implement certain electrical devices such as inductors, transformers, and large capacitors For these reason e Integrated circuits are principally used to perform low-power circuit operations that are commonly called information processing Various Logic Families e Bipolar transistors : TTL and ECL e Unipolar MOSFET transistors : NMOS, PMOS, and CMOS@\n this chapter “We will present the important characteristics of each of IC families @ Current and Voltage Parameters : *Viy (min) : high- level input voltage “Vi, (max) : low- level input voltage “Voy (min) : high- level output voltage “Vo, (max) : low- level output voltage “liq: high- level input current “el. : low- level input current “logy : high- level output current “lg. : low- level output current ' Fan-Out( = Loading Factor ) “maximum number of standard logic inputs that an output can drive reliably -Fan-Out = 10 : one logic gate can drive 10 standard logic inputsPropagation Delays : (INVERTER) ® te,,- delay going from LOW to HIGH © te, “delay going from HIGH to LOW = Itis measured between the 50 percent points on the input and output transitions. In some logic circuits, ta, and tp_4 are not the same value, and both will vary depending on capacitive loading conditions. The values of propagation times are used as a measure of the relative speed of logic circuits. A logic circuit with values of 10 ns is a faster logic circuit than one with values of 20 ns under specified load conditions. Input 1 ° Output 1Power Requirements Every IC requires a certain amount of electrical power to operate. e Power supply terminal on a chip : Veo (TTL), Von (Or OS) Current loc on the Voc supply : » Iocu | Current when all of the gate outputs are HIGH »lec. : Current when all of the gate outputs are LOW WY, V, Voc Tf loon fheIn some logic circuits, Iccy and lec, will be different values. OFor these vices, the average current is computed based on the assumption that gate outputs are LOW half the time and HIGH half the time. eAverage Current » Iec(avg) = (lech + leer ) 12 eAverage Power » Pp(avg) = Iec(avg) X VeeNoise Imm @Noise Immunity eStray electric and magnetic fields can induce voltages on the connecting wires between logic circuits » These unwanted, spurious signals are called noise Noise Immunity » Circuit's ability to tolerate noise without causing spurious changes in the output voltage« Noise Margin : » Quantitative measure of noise immunity = High-state noise margin : Van = Vou (min) - Vix (min) = Low-state noise margin : Ve = Vit (max) - Vo. (max) Logic Logic 1 1 Vou (rnin) vy 2 FL Vin tenin) | 2 | | disatiowed range $s Vou (max) Logic Logic 0 0 Output voltage Input voltage ranges requirements (o coy VoltageXample 1 The input/output voltage specifications for the standard TTL family are listed in Table 8-1. Use these values to determine the following. (a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input. (b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input. TABLE 8-1 | Parameter Min (V) Typical (V) Max (V) Vou 24 34 Vou 02 04 Vee 20° Mie os “Normally only the minimum Vjy and maximum Viz, values are given. (a)The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input : Viau = Vou (min) - Vie (min) =2.4V-2.0V=0.4V (b) The maximum-amplitude noise spike that can be tolerated when a LOW output is driving an input : Vi = Vir (max) - Vor (max) = 0.8V-04V=04VCurrent-Sourcing and Current-Sinking Action e Current Sourcing Action : »When the output of gate 1 is in the HIGH state Low e— athe output of gate 1 is acting asa source of current for the gate 2 input Voc Load gate Driving gate supplies Low e— (sources) current to load gate in HIGH state, Driving gateCurrent-Sourcing and Current-Sinking Action e Current Sinking Action : »When the output of gate 1 is in the LOW state o athe output of gate 1 is acting asa sink of current for the gate 2 input Driving gate Voc Driving gate receives (sinks) current from load gate in LOW state. Load gateLecture 5 FINISHED