This article has been accepted for publication in IEEE Transactions on Circuits and Systems--II: Express Briefs.
This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2023.3324584
3.6-pJ /spike, 30-Hz Silicon Neuron Circuit in
0.5-V, 65 nm CMOS for Spiking Neural Networks
Srikanth Vuppunuthala, Student Member, IEEE, Vijay Shankar Pasupureddi, Senior Member, IEEE,
Abstract—In large-scale neuromorphic systems, a spiking neu-
ral network (SNN) provides a promising solution for energy-
efficient computing. Optimizing SNN building blocks like neurons
and synapses can further enhance computing efficiency. Due to
their simplicity and computational efficiency, integrate-and-fire
neuron (I&F) models are widely used in SNNs. In the past
proposals of I&F neuron models, the main issue is the short-
circuit currents in CMOS inverters, which significantly inhibit
the circuit’s optimal performance and energy efficiency. This
paper presents an energy-efficient differential-pair integrator
(DPI) based I&F silicon neuron (SiN) circuit by utilizing the
subthreshold source-coupled logic (STSCL) circuit topology as a
replacement for CMOS inverters and incorporating a low supply
voltage to mitigate leakage currents effectively. The proposed SiN
is implemented in 65 nm CMOS technology with a supply voltage
of 0.5-V and has an energy consumption of 3.6 pJ/spike with a
spiking frequency (rate) of 30 Hz.
Index Terms—After-hyperpolarization (AHP), differential-pair
integrator (DPI), integrate-and-fire neuron, silicon neuron, spik-
ing neural network, subthreshold source-coupled logic.
I. I NTRODUCTION
T HE human brain’s exceptional energy efficiency and
massive parallelism in complex cognitive tasks encourage
building systems that mimic the biological brain [1]. The third-
generation artificial neural network (ANN) is a brain-inspired
spiking neural network (SNN) [2] that emulates biological
brain functions with better bio-plausibility than other neural
networks under tight power constraints. This can paves a new
path for the implementation of forthcoming intelligent devices
for ultra-low power real-time computing applications such as
health monitoring, IoT, and mobile devices. Many SiNs are
needed in SNNs to imitate complex brain-like functionality.
So, individual SiN hardware must be energy-efficient, com-
pact, and robust.
Numerous VLSI models of neuromorphic SiNs have been
implemented in the past ranging from simple integrate-and-
fire models to sophisticated conductance-based models [3]-[6]
depending on the intricacy and degree of emulation. In [7],
a leaky integrate-and-fire (I&F) neuron circuit is presented,
integrating spike-frequency adaptation, a tunable refractory
period, and voltage threshold modulation. However, significant
power dissipation occurs due to the short-circuit currents
flowing through the inverters during the switching time and
the DC current flowing through the source-follower circuit. In
[8], a DPI-based I&F neuron is introduced for implementing
tunable dynamic conductances, which offers an advantage over
Srikanth Vuppunuthala and Vijay Shankar Pasupureddi are with the
School of Electrical Sciences, Indian Institute of Technology Bhubaneswar,
Bhubaneswar, Odisha, India (email: sv35@iitbbs.ac.in; vijay@iitbbs.ac.in).
Authorized licensed use limited to: Indian Institute of Technology - BHUBANESWAR. Downloaded on February 06,2024 at 10:23:56 UTC from IEEE Xplore. Restrictions apply.
© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
the standard current-mode log-domain circuit [9] by enabling
control of circuit gain through an additional independent
bias voltage. However, high supply voltage and short-circuit
currents flowing through the inverters during the switching
time cause significant power consumption. Several neuron
circuits [10][11] have recently been implemented using the
FDSOI process. This choice is driven by the ultra-low leakage
currents offered by the FDSOI process, despite it not being
cost-effective to produce biologically plausible dynamics with
time constants in the order of seconds. In recent years, research
on emerging stochastic artificial neurons (SANs) [12]-[16] has
surged due to their simpler circuits, inherent randomness, and
smaller size compared to CMOS neurons. While SANs can
replicate basic functions like firing, refractory periods, tunable
output frequencies, and frequency adaptation, they cannot
mimic advanced features of biological neurons, such as lateral
inhibition, variable spiking modes, and chaos [17]. CMOS
neurons are cost-effective and mimic the advanced features of
biological neurons, however, the deployment of subthreshold
CMOS inverters as reported in [7][8], causes a brief period
during the transition between logic levels when both the pull-
up and pull-down transistors simultaneously conduct, leading
to significant short-circuit power consumption.
To address this issue, this paper presents a DPI-based I&F
neuron circuit based on the STSCL topology with drain-
substrate shorted pMOS load devices [18]. STSCL circuits,
with their differential structure, can minimize the overlap of
conducting paths, thus reducing short-circuit power. Moreover,
STSCL circuits operate at lower supply voltages, effectively
reducing subthreshold leakage current and dynamic power
consumption. The STSCL topology used offers additional
advantages. Firstly, the delay of the gate can be controlled
by the tail bias current. Secondly, the load resistance of the
STSCL gate can be controlled by the pMOS load device
source-gate voltage, providing control over the gate’s delay.
These benefits result in two extra degrees of control over the
neuron spiking frequency modulation. The proposed STSCL-
based I&F neuron is implemented in 65 nm CMOS with
a supply voltage of 0.5-V and energy consumption of 3.6
pJ/spike with a biologically plausible spiking rate of 30 Hz.
This paper is organized in the following manner. The
neuron circuit topology is presented in section II, followed by
simulation results and discussions in section III, and finally,
conclusions are presented in section IV.
II. T HE S ILICON N EURON C IRCUIT T OPOLOGY
This section presents the proposed design of the neuron
circuit. To design the neuron circuit HVT (High threshold
 This article has been accepted for publication in IEEE Transactions on Circuits and Systems--II: Express Briefs. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2023.3324584

voltage) FETs have been preferred due to their low subthresh- From the EKV model [19], the subthreshold pMOS device
old leakage currents for the applied gate-to-source voltage, as I–V characteristics are given by
illustrated in Fig. 1 to get the required low currents.  V 
 
VBG −VT 0 SB VDB
ISD = I0 · e np UT
e UT − e UT (1)

Where ISD is the source to drain current, np is the subthresh-

old slope factor, UT is the thermal voltage, and VT 0 is the
threshold voltage of the pMOS. VSB , VDB , VBG are the source
to the body, drain to the body, and body to gate voltages of
pMOS, respectively. For drain-substrate shorted pMOS device
(MN 1,N 2 ) VDB = 0, hence
  
VDG −VT 0 VSD
ISD = I0 · e n p UT
e UT
−1 (2)
(a) (b)
Fig. 1. Leakage current analysis of (a) nMOS and (b) pMOS with different Differentiating the ISD with respect to the VSD results in
threshold voltages in subthreshold region.
inverse of the load resistance, RSD of the STSCL gate, and it
is given by
 −1
∂ISD
RSD = (3)
∂VSD
 −1
np UT V
(np −1) npSD
−VSD
RSD = (np − 1) e UT
+e np UT
(4)
Ib
where  
VSG −VT 0
Ib = I0 e n p UT
(5)
Fig. 2. Block diagram of DPI-based silicon neuron circuit.
From (4) and (5), it can be demonstrated that when VSD =
0, the load resistance, RSD of pMOS load (MN 1,N 2 ) is finite
A. Neuron circuit design and equal to
The block diagram of the DPI-based silicon neuron circuit
UT −
 
VSG −VT 0
is shown in Fig. 2 and its corresponding circuit level imple- RSD |VSD =0 = ·e n p UT
(6)
mentation is shown in Fig. 3. The proposed neuron circuit I0
comprises an input DPI circuit (ML1 -ML5 ) that represents This implies that the load devices (MN 1,N 2 ) possess the
the leak conductance behaviour of the real neurons, a spike capability to elevate the output node VN or VP to VDD (Fig.
generating STSCL-based positive feedback mechanism (MN 1 - 3). This property of the STSCL circuit helps to make Iadp and
MN 10 ) that models the Sodium (Na+) channels of neurons. If b to zero when Vmem is less than the Vth , which eventually
A spike reset circuit (MK1 -MK6 ), which models the Potas- reduces the static power dissipation of the neuron circuit.
sium (K+) channels of a biological neuron, and an AHP The typical delay (td ) of the STSCL gate is given by Eq.
circuit (MA1 -MA6 ) implements a spike-frequency adaptation 7, where VSW = RSD · Iss .
mechanism that models the neuron’s Calcium conductance.
Cmem is an integrating capacitor that models the membrane ln(2) · VSW · CL
td = (7)
capacitance of a neuron. All the capacitors used in the design Iss
are MIM (Metal-Insulator-Metal) caps. The values and sizes
Therefore, from Eq. 7, it is evident that the delay of the STSCL
of capacitors are shown in Table I.
is dependent on RSD and Iss . Hence, by tuning the Iss through
Vbn N a and RSD through Vbp N a as shown in Fig. 3, the
TABLE I
C APACITANCE VALUES AND DIMENSIONS EMPLOYED IN THE DESIGN delay of the neuron is adjusted which in turn tunes the spiking
frequency of the proposed neuron circuit.
Cmem Cahp Cr
Value 135 fF 665 fF 135 fF
Length 8 µm 18 µm 8 µm III. R ESULTS AND D ISCUSSION
Width 8 µm 18 µm 8 µm
The proposed DPI-based silicon neuron is implemented in
65 nm CMOS with a supply voltage of 0.5 V. The simulation
In the STSCL circuit shown in Fig. 4a, the pMOS devices
results of the proposed neuron circuit, such as spike frequency
with their drain-body contacts intentionally shorted, are em-
adaptation, energy consumption per spike, Monte Carlo, and
ployed as gate-controlled load devices with high resistivity.
PVT analyses are presented in this section.
Authorized licensed use limited to: Indian Institute of Technology - BHUBANESWAR. Downloaded on February 06,2024 at 10:23:56 UTC from IEEE Xplore. Restrictions apply.
© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
 This article has been accepted for publication in IEEE Transactions on Circuits and Systems--II: Express Briefs. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2023.3324584

Fig. 3. Proposed STSCL-based integrate-and-fire(I&F) neuron schematic.

(a) (b) (a) (b)

Fig. 4. (a) Subthreshold SCL gate and (b) Membrane voltage (Vmem ) over Fig. 5. (a) Spiking rate variation of Vmem with Vth and (b) Spike-frequency
time. adaptation: Vmem and Vahp over time.

A. Neuron circuit simulation results
Isyn from Fig. 3 represents the presynaptic currents re-
ceived by the neuron’s dendrites. The input DPI integrates
the received currents and the current provided by the AHP
mechanism leading to an increase in the membrane voltage
(Vmem ).
Z Vth Z t
Cmem dVmem = (Isyn − Iahp ) dt (8)
0 0
As Vmem approaches the switching threshold Vth of the
STSCL circuit, the voltage of the output node VN decreases,
leading to an increase in the current If b through MN 6 and
MN 8 . This, in turn, causes a sharp rise in Vmem , contributing
to the spike generation mechanism. During the spike genera-
tion time the Cmem charges with a current of Isyn −Iahp +If b .
Immediately after the spike is generated, the decrease in node
VN voltage starts to increase the current Ic flowing through
the MK2 , consequently charging the capacitor Cr . As the
capacitor attains a sufficiently high voltage, Ireset initiates an
increase and pulls Vmem down to zero, thereby establishing
the reset mechanism. During the spike reset mechanism the
Cmem discharges with a current of Isyn − Iahp + If b − Ireset .
The transistor sizes are adjusted in order to ensure that Ireset
has the capability to pull Vmem to zero. The Vmem generated
by the proposed neuron circuit for a Vth of 230 mV is shown
in Fig. 4b along with the spiking period of Vmem variation
with Vth is shown in Fig. 5a. The spike-frequency adaptation
behaviour obtained by appropriately adjusting the parameters
of the AHP block of Fig. 3 and the neuron’s response to
the constant injected current are demonstrated in Fig. 5b.
The after-hyperpolarization voltage (Vahp ) increases with each
spike, reducing the overall current that charges Cmem . Once
the Vahp attains a stable state, the spiking frequency of the
neuron stays constant to a lower value than its initial value.
The neuron’s response to a step input for various settings
of the parameters such as Vbn na , Vbp na , Vack and Vgain
illustrated in Fig. 6. The increase in Vbn na increases Iss ,
reducing both the delay in the STSCL gate and the node
voltage VN . This reduction in VN leads to increased currents
If b and Ireset , ultimately resulting in higher charging and
discharging rates of the Cmem . As a result, the spiking rate
of the neuron increases, as illustrated in Fig. 6a. As the
Vbp na increases, it induces a decrease in the voltage VN .
Consequently, the neuron’s maximum spiking rate increases,
shown in Fig. 6b. Increasing the parameter Vack decreases
the current responsible for charging Cr , leading to a slow-
down reset mechanism. As a result, the neuron’s spiking rate
decreases, shown in Fig. 6c. As expected, increasing Vgain

Authorized licensed use limited to: Indian Institute of Technology - BHUBANESWAR. Downloaded on February 06,2024 at 10:23:56 UTC from IEEE Xplore. Restrictions apply.
© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
 This article has been accepted for publication in IEEE Transactions on Circuits and Systems--II: Express Briefs. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2023.3324584

Fig. 7. Energy per spike versus spiking rate

(a) (b)
currents through STSCL topology and mitigating leakage
currents with low supply voltage.

(c)
Fig. 6. Spiking rate versus input current for different values of (a) Vbn
(b) Vbp na , (c) Vack , and (d) Vgain .
reduces the Igain so the most of Iin flow into the Cmem
which eventually reduces the integration time and increases
the neuron’s spiking rate shown in Fig. 6d.
B. Energy per spike
The energy consumed per spike (Es ) is an essential figure
of merit (FoM) for neuron circuits to implement massively
parallel large-scale neuromorphic processors. It is given by
Pavg
Es =
fspike
where Pavg is the average power consumption of the neuron
and fspike is the spiking frequency. The proposed neuron
circuit’s simulated Es corresponds to the spiking rate shown
in Fig. 7.
The proposed neuron’s Es compared with the previous
works in Table II. The proposed neuron circuit achieved better
Es compared to previous works by eliminating short circuit
C. Impact of non-idealities
In order to evaluate the impact of the non-idealities on
the proposed design, Monte Carlo simulations have been
performed to evaluate the device mismatches and PVT anal-
yses have been performed to evaluate the effect of process,
temperature, and supply variations on the spiking rate of the
neuron. Monte Carlo analysis has been performed for the
neuron circuit with a sample count of 500, injecting DC
(d)
current (Isyn ) into the LEAK block through ML1 , as shown
na , in Fig. 3. Moreover, the bias currents were adjusted to attain a
spiking rate of 120 Hz while activating the AHP circuit. The
Monte Corlo results with mean is around the desired value
(≈120 Hz) with a standard deviation of 39.36 Hz as shown
in Fig. 8a. The deviation in the spiking rate is due to the
subthreshold operation of the transistors.
The process corner simulations have been performed to
observe the influence of process corner variation on the spiking
rate of the proposed neuron. The proposed neuron can produce
the spiking in all the process corners for the corresponding
input stimulus current (Isyn ) with some variation in the spiking
rate. The variation in spiking rate with corresponding input
(9) stimulus current at different corners is shown in Fig. 8b.
The effect of temperature and supply voltage variation
on the spiking rate of the proposed neuron is observed by
adjusting bias currents to attain a stable spiking rate of 120
Hz at 25◦ C and at a supply voltage of 0.5 V. Then the change
in spiking rate is observed by varying the temperature from
-10◦ C to 70◦ C and the simulated results is shown in Fig. 9a.
The change in spiking rate with supply variation from 450
mV to 550 mV is shown in Fig. 9b. The variation in the

TABLE II
P ERFORMANCE COMPARISON OF PROPOSED NEURON WITH PREVIOUS WORKS

Silicon Neurons (SiNs) Emerging Stochastic Artificial neurons (SANs)

Reference This Work [7] [8] [5] [6] [10] [12] [13] [14] [15] [16]
HfO2 Antiferro- V O2
Pt/HfAlOx GST
Material Silicon Silicon Silicon Silicon Silicon Silicon (Hafnium magnetic (Vanadium
TiN/Ag/Pt (Ge2 Sb2 T e5 )
Oxide) SOT 1 Dioxide)
MTJ PCM MIT
65 nm 350 nm 350 nm 180 nm 28 nm 22 nm Ferro- (Magnetic (Phase- (Metal-
Technology Filament
CMOS CMOS CMOS CMOS CMOS FDSOI electric Tunneling Change Insulator
Junction) Memory) Transition)
Type Mixed Mixed Mixed Mixed Mixed Mixed - - Digital Digital -
Vdd 0.5 V 3.3 V 3.3 V 1.8 V 0.7-1 V 0.8 V - - - - -
Frequency 30 Hz 100 Hz - 30 Hz - 30 Hz - 50 kHz Tens of kHz 35-40 kHz 3 GHz
Energy/spike 3.6 pJ 900 pJ 267 pJ 883 pJ 2.3-30 nJ 14 pJ 16 f J 1-10 pJ - 5 pJ 5.6 f J

Authorized licensed use limited to: Indian Institute of Technology - BHUBANESWAR. Downloaded on February 06,2024 at 10:23:56 UTC from IEEE Xplore. Restrictions apply.
© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
 This article has been accepted for publication in IEEE Transactions on Circuits and Systems--II: Express Briefs. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2023.3324584
(a) (b)
Fig. 8. (a) Monte Carlo results for the distribution of the spiking rate of
proposed neuron circuit and (b) Spiking rate versus input current at different
process corners.
spiking rate of the proposed neuron is because the leakage
currents of subthreshold transistors depend exponentially on
both temperature and supply voltage [20] [21].
(a) (b)
Fig. 9. Spiking rate with (a) temperature variation and (b) supply variation.
D. Layout
The layout of the proposed neuron circuit is shown in Fig.
10. The layout of the neuron circuit, including the bias circuit,
occupies an active area of 55 × 37 µm2 .
Fig. 10. Layout of the proposed neuron circuit, including the bias circuit.
IV. C ONCLUSIONS
This work presented an energy-efficient STSCL-based in-
tegrate and fire neuron circuit topology implemented in 0.5-
V, 65 nm CMOS with a refractory period, spike frequency
adaptation, spiking frequency modulation mechanisms. The
proposed neuron produces biologically feasible neural dynam-
ics by matching the time constants to those observed in natural
signals like speech. Therefore, the proposed neuron topology is
a good candidate for deployment in large-scale neuromorphic
systems for energy-efficient computing.
Authorized licensed use limited to: Indian Institute of Technology - BHUBANESWAR. Downloaded on February 06,2024 at 10:23:56 UTC from IEEE Xplore. Restrictions apply.
© 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
R EFERENCES
[1] M. Davies et al., “Loihi: A Neuromorphic Manycore Processor with
On-Chip Learning,” in IEEE Micro, vol. 38, no. 1, pp. 82-99, Jan-
uary/February 2018.
[2] W. Maass, “Networks of spiking neurons: The third generation of neural
network models,” Neural Netw., vol. 10, no. 9, pp. 1659–1671, 1997.
[3] M. Mahowald and R. Douglas, “A silicon neuron,” Nature, vol. 354, pp.
515–518, 1991.
[4] M. F. Simoni, G. S. Cymbalyuk, M. E. Sorensen, R. L. Calabrese and
S. P. DeWeerth, “A multiconductance silicon neuron with biologically
matched dynamics,” in IEEE Transactions on Biomedical Engineering,
vol. 51, no. 2, pp. 342-354, Feb. 2004.
[5] S. Moradi, N. Qiao, F. Stefanini and G. Indiveri, “A Scalable Multicore
Architecture With Heterogeneous Memory Structures for Dynamic Neu-
romorphic Asynchronous Processors (DYNAPs),” in IEEE Transactions
on Biomedical Circuits and Systems, vol. 12, no. 1, pp. 106-122, Feb.
2018.
[6] C. Mayr et al., “A Biological-Realtime Neuromorphic System in 28
nm CMOS Using Low-Leakage Switched Capacitor Circuits,” in IEEE
Transactions on Biomedical Circuits and Systems, vol. 10, no. 1, pp.
243-254, Feb. 2016.
[7] G. Indiveri, E. Chicca and R. Douglas, “A VLSI array of low-power spik-
ing neurons and bistable synapses with spike-timing dependent plasticity,”
in IEEE Transactions on Neural Networks, vol. 17, no. 1, pp. 211-221,
Jan. 2006.
[8] P. Livi and G. Indiveri, “A current-mode conductance-based silicon
neuron for address-event neuromorphic systems,” 2009 IEEE International
Symposium on Circuits and Systems, Taipei, Taiwan, 2009, pp. 2898-
2901.
[9] D. R. Frey, “Log-domain filtering: An approach to current-mode filtering,”
IEE Proceedings G: Circuits, Devices and Systems, vol. 140, no. 6, pp.
406–416, December 1993.
[10] A. Rubino, C. Livanelioglu, N. Qiao, M. Payvand and G. Indiveri,
“Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromor-
phic Intelligence,” in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 68, no. 1, pp. 45-56, Jan. 2021.
[11] H. Eslahi, T. J. Hamilton and S. Khandelwal, “Compact and Energy
Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI,” in
IEEE Transactions on Nanotechnology, vol. 21, pp. 189-195, 2022.
[12] Lu, Yi-Fan and Li, Yi and Li, Haoyang and Wan, Tian-Qing and Huang,
Xiaodi and He, Yu-Hui and Miao, Xiangshui, “Low-Power Artificial
Neurons Based on Ag/TiN/HfAlOx/Pt Threshold Switching Memristor
for Neuromorphic Computing,” in IEEE Electron Device Letters, vol. 41,
no. 8, pp. 1245-1248, Aug. 2020.
[13] Dutta Sourav, Schafer Clemens, Gomez Jorge, Ni Kai, Joshi Siddharth,
Datta Suman, “Supervised Learning in All FeFET-Based Spiking Neural
Network: Opportunities and Challenges,” Frontiers in Neuroscience, vol.
41, 2020.
[14] Kurenkov, Aleksandr and DuttaGupta, Samik and Zhang, Chaoliang and
Fukami, Shunsuke and Horio, Yoshihiko and Ohno, Hideo, “Artificial
Neuron and Synapse Realized in an Antiferromagnet/Ferromagnet Het-
erostructure Using Dynamics of Spin–Orbit Torque Switching,” Advanced
Materials, vol. 31, April 2019.
[15] Tuma, Tomas and Pantazi, Angeliki and Gallo, Manuel and Sebastian,
Abu and Eleftheriou, Evangelos, “Stochastic phase-change neurons,”
Nature Nanotechnology, vol. 11, May 2016.
[16] Yi, Wei and Tsang, Kenneth and Lam, Stephen and Bai, Xiwei and
Crowell, Jack and Flores, Elias, “Biological plausibility and stochasticity
in scalable VO2 active memristor neurons,” Nature Communications, vol.
9, November 2018.
[17] Li, Zong-xiao and Geng, Xiao-ying and Wang, Jingrui and Zhuge,
Fei, “Emerging Artificial Neuron Devices for Probabilistic Computing,”
Frontiers in Neuroscience, vol. 15, 2021.
[18] A. Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz, “Subthreshold Source-
Coupled Logic Circuits for Ultra-Low-Power Applications,” in IEEE
Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1699-1710, July 2008.
[19] C. Enz and E. Vittoz, Charge-Based MOS Transistor Modeling: The
EKV Model for Low-Power and RF IC Design. New York: Wiley, 2006.
[20] Sourikopoulos, Ilias and Hedayat, Sara and Loyez, Christophe and
Danneville, François and Hoel, Virginie and Mercier, Eric and Cappy,
Alain, “A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology,”
Frontiers in Neuroscience, vol. 11, 2017.
[21] L. Zhang, J. Zhang, Y. Wang, X. Zhang and R. Huang, “A Multi-Mode
Silicon Neuron Circuit With High Robustness Against PVT Variation,”
2018 IEEE International Symposium on Circuits and Systems (ISCAS),
pp. 1-4, 2018.