5.

Registers and Counter

Chapter Outline
•

G. Kassahun B.
Introduction to counters and Registers
• Basic Shift Register Functions
• Types of Shift Registers

ECENG 3101 Lecture 5

• Shift Register Counters and there Applications
• Operation Counters - Up/Down Counters
• Counter Decoding

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5. Registers and Counter
INTRODUCTION

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• A clocked sequential circuit consists of a group of flip-flops
and combinational gates connected to form a feedback path.
• A circuit with flip-flops is considered a sequential circuit even

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in the absence of combinational gates.
• Circuits that include flip-flops are classified by the function
they perform.
• Two such circuits are registers and counters.

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5. Registers and Counter
REGISTERS

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• A register is a group of flip-flops, each one of which is capable
of storing one bit of information.
• An n-bit register consists of a group of n flip-flops.

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• A register consists of a group of flip-flops together with gates
that affect their operation. (they determine how the
information is transferred into register).
• The simplest register is one with parallel inputs and without
any gates.

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5. Registers and Counter
REGISTER
Four bit Register TTL 74171 • Simplest registers without

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any gates
• When CLEAR is 0 the flip
flop is resetting.

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• When CLEAR is 1 the flip
flop is in normal clock
operation.

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5. Registers and Counter
Register with parallel load

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• The transfer of new information into a register is referred to as
loading or updating the register.
• If all the bits of the register are loaded simultaneously with a

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common clock pulse, we say that the loading is done in
parallel.

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5. Registers and Counter
Register with Parallel Load
• Four-bit register with parallel load

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5. Registers and Counter
Register with Parallel Load
• Additional gates implement 2-channel mux

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• Data is always transfer at positive clock pulse
• When “Load-input” is “1” ,the data from inputs transfer to registers
• When “Load-input” is “0” ,the flip-flop output (present state)

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transfer to register and implement “no change” condition

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5. Registers and Counter
Basic Shift Register Functions
• Shift registers consist of arrangements of flip-f1ops and are

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important in applications involving the storage and transfer of
data in a digital system.
• In General, A Register is used solely for storing and shifting

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data.
• The Total storage capacity is total number of flip – flops since a
single flip flop can store single bit of data.

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5. Registers and Counter
Basic Shift Register Functions
• A register capable of shifting the binary information held in

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each cell to its neighboring cell in a selected direction is called
a shift register.
• It consists of a chain of flip-flops in cascade, with the output of

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one flip-flop connected to the input of the next flip-flop.
• All flip-flops receive common clock pulses, which activate the
shift of data from one stage to the next.
• We can control the shift operation by connecting (shift
control) with the clock through an AND gate

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5. Registers and Counter
Types of Shift Registers
• Serial In - Serial Out Shift Registers

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• Traditional Logic symbol

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5. Registers and Counter
Types of Shift Registers
• Serial In - Parallel Out Shift Registers

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• Logic Symbol

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5. Registers and Counter
Types of Shift Registers
• Parallel In – Serial Out Shift Registers

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• Traditional Logic symbol

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5. Registers and Counter
Types of Shift Registers
• Parallel In – Parallel Out Shift Registers

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5. Registers and Counter

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Application of Shift Register
Serial Transfer
• A digital system is said to operate in serial mode when information is
transferred and manipulated one bit at a time.
• Information is transferred one bit at a time by shifting the bits out of

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the source register into the destination register.
• The serial transfer of information from register A to register B is
done with shift registers where the SO of register A is connected to
the SI of register B.

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5. Registers and Counter
Application of Shift Register
Serial Transfer

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• Serial transfer from register A to register B

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5. Registers and Counter
Serial Transfer
• EXAMPLE:

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• Suppose the 4 – bit shift register and control signal that
supervises the transfer is designed in such a way that a clock
generator will produce four pulses T1 T2 T3 and T4. assuming

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the register are trigged at positive edge of clock determine the
state of registers in each steps if the binary content of register A
before shift is 1011 and B is 0010?

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5. Registers and Counter
Serial Transfer
• Answer Serial transfer from register A to register B

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5. Registers and Counter
Serial Transfer
• In the parallel mode, information is available from all bits of a
register and all bits can be transferred simultaneously during one

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clock pulse.

• In the serial mode, the registers have a single serial input and a single

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serial output. The information is transferred one bit at a time while
the registers are shifted in the same direction.

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5. Registers and Counter
Application of Shift Register
Design of Serial Adder

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• Two binary numbers to be added are stored in two shift registers.
• Bits are added one pair at time through full – adder
• One register is used to store the final sum result

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5. Registers and Counter
Design of Serial Adder

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5. Registers and Counter
Serial Addition

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5. Registers and Counter
Serial Addition with JK flip – flop

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5. Registers and Counter
Universal shift register
• A register capable of shifting in one direction only is a unidirectional

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shift register.

• A register capable of shifting in both direction is a bidirectional shift

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register.

• If the register has both shifts and parallel-load capabilities, it is

referred to as a universal shift register.

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5. Registers and Counter
Universal shift register
The most general shift register has the following capabilities:

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 A clear control to clear the register to 0.
A clock input to synchronize the operation.
A shift-right control and the serial input & output lines associated

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with it.
A shift-left control and the serial input & output lines associated
with it.
A parallel-load control and the n input lines associated with the
parallel transfer.
n parallel output lines.
A control state that leaves the information in the register unchanged 25
in response to the clock.
5. Registers and Counter
Universal shift register

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5. Registers and Counter
Universal shift register

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5. Registers and Counter
Shift Register Counters

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Ring Counter

• A ring counter is a
circular shift register with

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only one flip-flop being
set at any particular time;
all others are cleared
• The single bit is shifted
from one flip-flop to the
next to produce the
sequence of timing
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signals
5. Registers and Counter
Shift Register Counters

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Johnson counter
• Johnson counters are a variation of standard ring counters,
with the inverted output of the last stage feedback to the

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input of the first stage.
• They are also known as twisted ring counters.
• An n-stage Johnson counter yields a count sequence of length
2n, so it may be considered to be a mod-2n counter

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5. Registers and Counter
Johnson counter

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5. Registers and Counter
COUNTERS
• A special type of register that goes through a prescribed sequence

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of states upon the application of the clock pulses.

• A counter that follows the binary number sequence is called a

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binary counter.

• An n-bit binary counter consists of n flip-flops and can count in

binary from 0 to 2n-1.

• Counters are available in two categories:

• Ripple counters (Asynchronous)
• Synchronous counters 31
5. Registers and Counter
Binary ripple counter
• It consists of a series connection of complementing flip-flops (T or D

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or JK), with the output of each flip-flop connected to the C input of
the next higher order flip-flop.
• The flip-flop holding the LSB receives the incoming count pulses.

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• The T inputs of all the flip-flops are connected to logic 1, making
each f-f complement if the clock input goes through a negative
transition.
• For D f-f, the complemented output connected to the D input.

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5. Registers and Counter
Binary ripple counter

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5. Registers and Counter
Binary ripple counter

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5. Registers and Counter
BCD Ripple counter (Decade Counter)
• A decimal counter follows a sequence of 10 states and returns to 0

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after the count of 9.
• The BCD counter is a decade counter, since it counts from 0 to 9.

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5. Registers and Counter
BCD Ripple counter (Decade Counter)

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5. Registers and Counter
BCD Ripple counter (Decade Counter)

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5. Registers and Counter
BCD Ripple counter (Decade Counter)
• To count in decimal from 0 to 99, we need a two-decade counter.

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• To count in decimal from 0 to 999, we need a three-decade counter.

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5. Registers and Counter
Synchronous counters
• They are different from ripple counters in that clock pulses are

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applied to the input of all flip-flops.
• The decision whether a flip-flop is to be complemented is
determined from the values of the data inputs.

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• If T = 0 or J = K = 0, the flip-flop does not change state.
• If T = 1 or J = K = 1, the flip-flop complements.

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5. Registers and Counter
Synchronous Binary Counter
• The flip – flop at list significant position is complemented by every

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clock pulse but a flip – flop on other position is complemented if all
flip – flops in lower significant position are set to 1.
• If the enable input is 0,aII J and K inputs are equal to “0” and clock

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does not change the state of the Counter
• J and K inputs are equal to 1 if all previous least significant stages
are equal to 1 and the count is enabled
• A synchronous countdown binary counter goes through the binary
states in reverse order, 1 11 1 down to 0000 and back to 11 1 1 to
repeat the count

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5. Registers and Counter
Synchronous Binary Counter

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5. Registers and Counter
Synchronous up – down counter

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• When the up input is 1, the circuit counts up,

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since the T inputs receive their signals from
the values of the previous normal outputs of
the flip-flop
• When the down input is 1 and the up input
is 0, the circuit counts down, since the
complemented outputs of the previous flip-
flops are applied to the T input
• When the up and down inputs are both 0,
the circuit does not change state and remains
in the same count 42
• When the up and down inputs are both I,
the circuit counts up
5. Registers and Counter
BCD Counter

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• Counts in a BCD code through 0000 to 1001
• The state table becomes

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5. Registers and Counter
BCD Counter

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• The flip – flops input equations can be simplified by means of
K – maps and unused states from 10 to 15 are taken as don`t
cares. The simplified function becomes
• TQ1 = 1

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• TQ2 = Q’8Q1 The circuit diagram can be
• TQ4 = Q2Q1 constructed from
• TQ8 = Q8Q1 + Q4Q2Q1 • Four flip – flops
• Y = Q8Q1 • Five and gate and
• One or gate
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5. Registers and Counter
Binary counter with parallel load

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• Counters in digital systems require a parallel-load capability
for transferring an initial binary number into the counter prior
to the count operation.

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Binary counter with parallel load

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5. Registers and Counter
BCD counter using counter with parallel load

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• In each case a count control is set to 1 to enable the count
through the clock input. Also remember that the load control
inhibits the count and that the clear independent of any
control input.

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5. Registers and Counter
Counter with unused state

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• A circuit with n flip –flops has 2n states
• There are occasions when a sequential logic circuit uses less
number this maximum possible number of states.

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• When simplifying the input equations the unused states are
treated as don`t care condition
• Consider the following mod 6 counter

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Counter with unused state

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