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8 7 6 5 4 3 2 1

320S-13 for Lenovo


LPC for dubug

page43
NGFF(KEY E) PCIE X1 for WIFI CH0
D WIFI/BT MODULE DDR4 2133MT/S
USB2.0 for Bluetooth
4GB/8GB DDR4 page19~21 D

page26 NGFF(KEY M) PCIE X4


CH1
SSD 128GB / 256GB / 512GB DDR4 2133MT/S

kabylake U SPI SPI NOR FLASH


nVidia PCIE X4 W25Q64FVZPIQ page24
page74~80 N17S 10W (KBY-U_2+2U/4+2U)
UART3 Debug connector page56
USB2.0

Type C EDP signal


LCM Connector
C (USB3.0 only) USB Switch USB3.0 EDP_BKLT_EN 13.3" 16:9 C
1920x1080 pixels FHD/EDP
page54~55 Realtek/RTS5448‐GR EDP_BKLT_PWM page36
USB2.0
Camera
USB Charger DMIC
Digital array, D‐Mic ,x2
TPS2546RTER
TDP : 15W
HDA Speaker 2*1W page46~48
page42 USB 3.0 USB3.0/USB2.0 AUDIO CODEC
Conexant/CX11802
Audio JACK

HDMI
B page35 HDMI B
PCIEX1 Card Reader 4 IN1 card
BGA 1356 balls 4 in 1(SD, SDHC, SDXC, MMC) page27
BayHub/OZ711LV1LN‐B‐0‐TR
42 x 24 mm
Touchpad I2C USB2.0
page50 USB 2.0 page37
page3~15

LPC
DC Jack
GPIO SMBUS
Charger With DC-in LED
Hall sensor*1 OZ8690LN O2MICRO page58
page38
FEELING/FD2H002BY‐LF BATTERY
EC Controller
A ENE/ KB9028 SMBUS A
NOVO button with LED GPIO page50 THERMAL SENSOR
page51 SOC page29
Rescue key G788P81U page29

page30 Speed//PWM
FAN
Matrix
keyboard page50 Project: 320S-13
Engineer: Jason
Size Title: Rev
COVER PAGE V01
Custom
Date: Monday, April 10, 2017 Sheet 1 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

TABLE OF CONTENTS
D
01 -- COVER PAGE 31 -- NA 61--PWR-DDR
D
02 -- TABLE OF CONTENTS 32 -- NA 62--PWR-+V2P5U_VPP
03--SKL-U(1/12)DDI,MISC,XDP,EDP 33 -- NA 63--PWR-+1.0V_PRIM
04--SKL-U(2/12)DDR4 34 -- NC_HDMI LEVEL SHIFTERS 64--PWR-NA
05--SKL-U(3/12)SPI,ESPI,SMB,LPC 35 -- NC_HDMI CONNECTOR 65--PWR-+1.8V_PRIM
06--SKL-U(4/12)HDA,EMMC,SD 36 -- DISPLAY 66--PWR-CPU VR IC
07--SKL-U(5/12)CLK,GPIO 37 -- TOUCH PANEL AND DOCK 67--PWR-VCC_CORE/GT/SA
08--SKL-U(6/12)GPIO 38 -- SENSORS & LID 68--PWR-Block Diagram
09--SKL-U(7/12)PCIE,USB,SATA 39 -- FRONT AND REAR CAMERA CON 69--PWR_Change list
C 10--SKL-U(8/12)Power 40 -- CAMERA DISCRETE CONTROLL C

11--SKL-U(9/12)Power 41 -- TPM
12--SKL-U(10/12)Power,SVID 42 -- USB3.0 CONN
13--SKL-U(11/12)GND 43 -- WLAN WIFI BT MODULE
14--SKL-U(12/12)RSVD 44 -- WWAN MODULE
15--SOC (DECOUPLING) 45 -- MICRO SIM
16--NA 46 -- AUDIO CODEC
17--NA 47 -- AUDIO-MIC AND SPKRS
B
18--NA 48 -- IO board CONN B
19--DDR4_CHA 49 -- DC JACK
20--DDR4_CHB 50 -- EMBEDDED CONTROLLER
21--DDR4 Decoupling 51 -- BUTTON & LED
22--NA 52 -- TYPE-C MULTIPLEXER
23--RF / EMC Solution 53 -- TYPE-C PD CONTROLLER
24 -- SYSTEM FLASH 54 -- NC_TYPE-C BOOST VR
25 -- NC_EMMC 55 -- TYPE-C CONNECTOR
26 -- PCIE SSD MODULE 56 -- UART CONN & HOLE & CLIP
A
27 -- NC_MICRO-SD CARD 57 -- HW Change list A
28 -- NC_SD CARD POWER 58--PWR_DCIN/BATT CONN
29 -- CPU THERMAL SENSOR 59--PWR_CHARGER(OZ8690)
30 -- FAN conn 60--PWR-+V5P0A / +V3P3A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title: Rev
sky_y_mrd._ TABLE OF CONTENTS V01
Wed Jun 03 11:22:42 2015 Custom
Date: Monday, April 10, 2017 Sheet 2 of 81
8 7 6 5 4 3 2 1
A B C D E

UC1A SKL-U
Rev_0.53
E55 C47
35 DDI1_TX0_DN DDI1_TXN[0] EDP_TXN[0] EDP_TX0_SOC_DN 36
F55 C46
35 DDI1_TX0_DP DDI1_TXP[0] EDP_TXP[0] EDP_TX0_SOC_DP 36
35 DDI1_TX1_DN E58
F58
DDI1_TXN[1] EDP_TXN[1]
D46
C45
EDP_TX1_SOC_DN 36 <eDP>
35 DDI1_TX1_DP DDI1_TXP[1] EDP_TXP[1] EDP_TX1_SOC_DP 36
F53 A45
HDMI 35 DDI1_TX2_DN DDI1_TXN[2] EDP_TXN[2]
G53 B45
35 DDI1_TX2_DP DDI1_TXP[2] EDP_TXP[2]
F56 A47
35 DDI1_TX3_DN DDI1_TXN[3] EDP_TXN[3]
G56 B47
35 DDI1_TX3_DP DDI1_TXP[3] EDP_TXP[3]

C50 E45
DDI2_TXN[0] DDI EDP EDP_AUXN EDP_AUX_SOC_DN 36
D50 F45
DDI2_TXP[0] EDP_AUXP EDP_AUX_SOC_DP 36
C52
DDI2_TXN[1]
D52 B52
DDI2_TXP[1] EDP_DISP_UTIL
1 A50 1
<Type-c>--->Remove B50
DDI2_TXN[2]
DDI2_TXP[2] DDI1_AUXN
G50
D51 F50
DDI2_TXN[3] DDI1_AUXP
C51 E48
+V3P3A DDI2_TXP[3] DDI2_AUXN
F48
DDI2_AUXP
G46
DISPLAY SIDEBANDS DDI3_AUXN
F46
DDI3_AUXP
R1092 L13
35 DDI1_DDC_SCK GPP_E18/DDPB_CTRLCLK DDI1_HPD
2.2K L12 L9
DDI1_HPD 35
3/17 change to NI 5% 35 DDI1_DDC_SDA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0
L7
GPP_E14/DDPC_HPD1 TP_SMC_EXTSMI_N
R0402_N TP1063 TP_DDI2_DDC_SCL N7 L6 TP1049
NI DDI2_DDC_SDA
GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 SMC_RUNTIME_SCI_N
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 EDP_HPD SMC_RUNTIME_SCI_N 50
L10
+1.0VS_VCCIO GPP_E17/EDP_HPD EDP_HPD 36
N11
GPP_E22/DDPD_CTRLCLK
N12 R12
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN EDP_BKLT_EN 36
R11
24.9R EDP_COMP EDP_BKLTCTL EDP_BKLT_PWM 36
R1009 E52 1 OF 20 U13 From eDP
R0402 1% I EDP_RCOMP EDP_VDDEN EDP_VDD_EN 36

SKL-U_BGA1356
<BOM Structure>

+1.0VS_VCCSTG

R1024
1K UC1D SKL-U
R0402 Rev_0.53
5% TP1019 CATERR_SOC_N D63
+1.0V_VCCST PECI_SOC CATERR#
I R1022 43R R0402_N1% I A54
50 PECI_EC H_PROCHOT#_R PECI
50,59,66 PROCHOT_N R1023 499R R0402 1% I C65 JTAG
THERMTRIP_SOC_N PROCHOT#
C63
THERMTRIP# XDP_TCK0
CRB install 499R,ARMOUR install 0R A65 B61
THERMTRIP_SOC_N SKTOCC# PROC_TCK XDP_TDI
R1021 1K CPU MISC D60
R0402_N 1% I PROC_TDI XDP_TDO
C55 A61
BPM#[0] PROC_TDO XDP_TMS
2 D55 C60 2
BPM#[1] PROC_TMS XDP_TRST_N
B54 B59
BPM#[2] PROC_TRST#
C56
BPM#[3] XDP_TCK1_PCH
B56
TP_GPP_E_3_CPU_GP_0 A6 PCH_JTAG_TCK XDP_TDI
TP1020 D59
GPP_E3/CPU_GP0 PCH_JTAG_TDI XDP_TDO
TP100 A7 A56
GPP_E7/CPU_GP1 PCH_JTAG_TDO XDP_TMS
BA5 C59
GPP_B3/CPU_GP2 PCH_JTAG_TMS XDP_TRST_N
AY5 C61
43 BT_RF_KILL_N GPP_B4/CPU_GP3 PCH_TRST#
A59 XDP_TCK0
CPU_POPIRCOMP JTAGX
R1025 49.9R R0402 1% I AT16
PCH_OPIRCOMP PROC_POPIRCOMP
R1026 49.9R R0402 1% I AU16
EDRAM_OPIO_RCOMP PCH_OPIRCOMP
RC7 49.9R R0402 1% I H66
EOPIO_RCOMP OPCE_RCOMP
RC8 49.9R R0402 1% I H65
OPC_RCOMP
4 OF 20

SKL-U_BGA1356
<BOM Structure>

+V3P3A +V3P3A 4,5,6,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70


+1.0VS_VCCIO +1.0VS_VCCIO 10,14
+1.0VS_VCCSTG +1.0VS_VCCSTG 10,12
+1.0V_VCCST +1.0V_VCCST 7,10,12,14,66

+1.0VS_VCCSTG
3 3
R1028 51R R0402 5% I XDP_TDO

R1029 51R R0402 5% NI XDP_TMS

R1027 51R R0402 5% NI XDP_TDI

R1031 51R R0402 5% NI XDP_TCK0

R1034 51R R0402 5% NI XDP_TCK1_PCH

R1032 51R R0402 5% I XDP_TCK0

R1033 51R R0402 5% NI XDP_TRST_N

4 4

Project: 320S-13
Engineer: Jason
Size Title:KBL-U(1/12)DDI,MISC,XDP,EDP Re v
Custom V01
Date: Monday, April 10, 2017 Sheet 3 of 81
A B C D E
5 4 3 2 1

Non‐Interleaved Non‐Interleaved SKL-U


UC1B SKL-U UC1C
Rev_0.53 Rev_0.53
AU53
DDR0_CKN[0] M_A_DIM0_CK_DDR0_DN 19
AL71 AT53 AF65 AN45
D 19 M_A_DQ<0> DDR0_DQ[0] DDR0_CKP[0] M_A_DIM0_CK_DDR0_DP 19 19 M_A_DQ<16> DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] M_B_DIM0_CK_DDR0_DN 20 D
AL68 AU55 AF64 AN46
19 M_A_DQ<1> DDR0_DQ[1] DDR0_CKN[1] 19 M_A_DQ<17> DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1]
AN68 AT55 AK65 AP45
19 M_A_DQ<2> DDR0_DQ[2] DDR0_CKP[1] 19 M_A_DQ<18> DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] M_B_DIM0_CK_DDR0_DP 20
AN69 AK64 AP46
19 M_A_DQ<3> DDR0_DQ[3] 19 M_A_DQ<19> DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
AL70 BA56 AF66
19 M_A_DQ<4> DDR0_DQ[4] DDR0_CKE[0] M_A_DIM0_CKE0 19 19 M_A_DQ<20> DDR1_DQ[4]/DDR0_DQ[20]
AL69 BB56 AF67 AN56
19 M_A_DQ<5> DDR0_DQ[5] DDR0_CKE[1] 19 M_A_DQ<21> DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] M_B_DIM0_CKE0 20
AN70 AW56 AK67 AP55
19 M_A_DQ<6> DDR0_DQ[6] DDR0_CKE[2] 19 M_A_DQ<22> DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1]
AN71 AY56 AK66 AN55
19 M_A_DQ<7> DDR0_DQ[7] DDR0_CKE[3] 19 M_A_DQ<23> DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2]
AR70 AF70 AP53
19 M_A_DQ<8> DDR0_DQ[8] 19 M_A_DQ<24> DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
AR68 AU45 AF68
19 M_A_DQ<9> DDR0_DQ[9] DDR0_CS#[0] M_A_DIM0_CS0_N 19 19 M_A_DQ<25> DDR1_DQ[9]/DDR0_DQ[25]
AU71 AU43 AH71 BB42
19 M_A_DQ<10> DDR0_DQ[10] DDR0_CS#[1] 19 M_A_DQ<26> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] M_B_DIM0_CS0_N 20
AU68 AT45 AH68 AY42
19 M_A_DQ<11> DDR0_DQ[11] DDR0_ODT[0] M_A_DIM0_ODT0 19 19 M_A_DQ<27> DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1]
AR71 AT43 AF71 BA42
19 M_A_DQ<12> DDR0_DQ[12] DDR0_ODT[1] 19 M_A_DQ<28> DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] M_B_DIM0_ODT0 20
AR69 AF69 AW42
19 M_A_DQ<13> DDR0_DQ[13] 19 M_A_DQ<29> DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
AU70 BA51 AH70
19 M_A_DQ<14> DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A5 19 19 M_A_DQ<30> DDR1_DQ[14]/DDR0_DQ[30]
AU69 BB54 AH69 AY48
19 M_A_DQ<15> DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] M_A_A9 19 19 M_A_DQ<31> DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A5 20
BB65 BA52 AT66 AP50
19 M_A_DQ<32> DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M_A_A6 19 19 M_A_DQ<48> DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A9 20
AW65 AY52 AU66 BA48
19 M_A_DQ<33> DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A8 19 19 M_A_DQ<49> DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A6 20
AW63 AW52 AP65 BB48
19 M_A_DQ<34> DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] M_A_A7 19 19 M_A_DQ<50> DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A8 20
AY63 AY55 AN65 AP48
19 M_A_DQ<35> DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG0 19 19 M_A_DQ<51> DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] M_B_A7 20
BA65 AW54 AN66 AP52
19 M_A_DQ<36> DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A12 19 19 M_A_DQ<52> DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] M_B_BG0 20
AY65 BA54 AP66 AN50
19 M_A_DQ<37> DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_A11 19 19 M_A_DQ<53> DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] M_B_A12 20
BA63 BA55 AT65 AN48
19 M_A_DQ<38> DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_A_ACT_N 19 19 M_A_DQ<54> DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_A11 20
BB63 AY54 AU65 AN53
19 M_A_DQ<39> DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] R0402_N 0R
M_A_BG1 19 19 M_A_DQ<55> DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# M_B_ACT_N 20
19 M_A_DQ<40> BA61 RM97 19 M_A_DQ<56> AT61 AN52
M_B_BG1 20
DDR0_DQ[24]/DDR0_DQ[40] 5% NI DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] R0402_N 0R
19 M_A_DQ<41> AW61 AU46
M_A_A13 19 19 M_A_DQ<57> AU61 RM98
DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR1_DQ[25]/DDR0_DQ[57] 5% NI
BB59 AU48 AP60 BA43
19 M_A_DQ<42> DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] M_A_A15_CAS_N 19 19 M_A_DQ<58> DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M_B_A13 20
AW59 AT46 AN60 AY43
19 M_A_DQ<43> DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_A14_WE_N 19 19 M_A_DQ<59> DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M_B_A15_CAS_N 20
BB61 AU50 AN61 AY44
19 M_A_DQ<44> DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_A_A16_RAS_N 19 19 M_A_DQ<60> DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] M_B_A14_WE_N 20
AY61 AU52 AP61 AW44
19 M_A_DQ<45> DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_BA0 19 19 M_A_DQ<61> DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M_B_A16_RAS_N 20
BA59 AY51 AT60 BB44
19 M_A_DQ<46> DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_A_A2 19 19 M_A_DQ<62> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_BA0 20
AY59 AT48 AU60 AY47
19 M_A_DQ<47> DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_BA1 19 19 M_A_DQ<63> DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] M_B_A2 20
AY39 AT50 AU40 BA44
20 M_B_DQ<0> DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A10_AP 19 20 M_B_DQ<16> DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_BA1 20
AW39 BB50 AT40 AW46
20 M_B_DQ<1> DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] M_A_A1 19 20 M_B_DQ<17> DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A10_AP 20
AY37 AY50 AT37 AY46
20 M_B_DQ<2> DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_A_A0 19 20 M_B_DQ<18> DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A1 20
AW37 BA50 AU37 BA46
C 20 M_B_DQ<3> DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] M_A_A3 19 20 M_B_DQ<19> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] M_B_A0 20 C
BB39 BB52 AR40 BB46
20 M_B_DQ<4> DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] M_A_A4 19 20 M_B_DQ<20> DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] M_B_A3 20
BA39 AP40 BA47
20 M_B_DQ<5> DDR0_DQ[37]/DDR1_DQ[5] 20 M_B_DQ<21> DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] M_B_A4 20
BA37 AM70 AP37
20 M_B_DQ<6> DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] M_A_DQS_DN<0> 19 20 M_B_DQ<22> DDR1_DQ[38]/DDR1_DQ[22]
BB37 AM69 AR37 AH66
20 M_B_DQ<7> DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] M_A_DQS_DP<0> 19 20 M_B_DQ<23> DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] M_A_DQS_DN<2> 19
AY35 AT69 AT33 AH65
20 M_B_DQ<8> DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] M_A_DQS_DN<1> 19 20 M_B_DQ<24> DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] M_A_DQS_DP<2> 19
AW35 AT70 AU33 AG69
20 M_B_DQ<9> DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] M_A_DQS_DP<1> 19 20 M_B_DQ<25> DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] M_A_DQS_DN<3> 19
AY33 BA64 AU30 AG70
20 M_B_DQ<10> DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] M_A_DQS_DN<4> 19 20 M_B_DQ<26> DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] M_A_DQS_DP<3> 19
AW33 AY64 AT30 AR66
20 M_B_DQ<11> DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] M_A_DQS_DP<4> 19 20 M_B_DQ<27> DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] M_A_DQS_DN<6> 19
BB35 AY60 AR33 AR65
20 M_B_DQ<12> DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] M_A_DQS_DN<5> 19 20 M_B_DQ<28> DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] M_A_DQS_DP<6> 19
BA35 BA60 AP33 AR61
20 M_B_DQ<13> DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] M_A_DQS_DP<5> 19 20 M_B_DQ<29> DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] M_A_DQS_DN<7> 19
BA33 BA38 AR30 AR60
20 M_B_DQ<14> DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] M_B_DQS_DN<0> 20 20 M_B_DQ<30> DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] M_A_DQS_DP<7> 19
BB33 AY38 AP30 AT38
20 M_B_DQ<15> DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] M_B_DQS_DP<0> 20 20 M_B_DQ<31> DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] M_B_DQS_DN<2> 20
AY31 AY34 AU27 AR38
20 M_B_DQ<32> DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] M_B_DQS_DN<1> 20 20 M_B_DQ<48> DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] M_B_DQS_DP<2> 20
AW31 BA34 AT27 AT32
20 M_B_DQ<33> DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] M_B_DQS_DP<1> 20 20 M_B_DQ<49> DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] M_B_DQS_DN<3> 20
AY29 BA30 AT25 AR32
20 M_B_DQ<34> DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] M_B_DQS_DN<4> 20 20 M_B_DQ<50> DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] M_B_DQS_DP<3> 20
AW29 AY30 AU25 AR25
20 M_B_DQ<35> DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] M_B_DQS_DP<4> 20 20 M_B_DQ<51> DDR1_DQ[51] DDR1_DQSN[6] M_B_DQS_DN<6> 20
BB31 AY26 AP27 AR27
20 M_B_DQ<36> DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] M_B_DQS_DN<5> 20 20 M_B_DQ<52> DDR1_DQ[52] DDR1_DQSP[6] M_B_DQS_DP<6> 20
BA31 BA26 AN27 AR22
20 M_B_DQ<37> DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQS_DP<5> 20 20 M_B_DQ<53> DDR1_DQ[53] DDR1_DQSN[7] M_B_DQS_DN<7> 20
BA29 AN25 AR21
20 M_B_DQ<38> DDR0_DQ[54]/DDR1_DQ[38] 20 M_B_DQ<54> DDR1_DQ[54] DDR1_DQSP[7] M_B_DQS_DP<7> 20
BB29 AW50 AP25
20 M_B_DQ<39> DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR0_A_ALERT_N 19 20 M_B_DQ<55> DDR1_DQ[55]
AY27 AT52 AT22 AN43
20 M_B_DQ<40> DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR0_A_PARITY 19 20 M_B_DQ<56> DDR1_DQ[56] DDR1_ALERT# DDR1_B_ALERT_N 20
AW27 AU22 AP43
20 M_B_DQ<41> DDR0_DQ[57]/DDR1_DQ[41] 20 M_B_DQ<57> DDR1_DQ[57] DDR1_PAR DDR4_DRAMRST_N DDR1_B_PARITY 20
AY25 AY67 AU21 AT13
20 M_B_DQ<42> DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +V_DDR_CA_VREF 19 20 M_B_DQ<58> DDR1_DQ[58] DRAM_RESET# DDR4_DRAMRST_N 19
AW25 AY68 AT21 AR18 SM_RCOMP0
20 M_B_DQ<43> DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ 20 M_B_DQ<59> DDR1_DQ[59] DDR_RCOMP[0] SM_RCOMP1
BB27 DDR CH - A BA67 AN22 AT18
20 M_B_DQ<44> DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +V_DDR_VREFDQ02_CHB 20 20 M_B_DQ<60> DDR1_DQ[60] DDR_RCOMP[1]
BA27 AP22 DDR CH - B AU18 SM_RCOMP2
20 M_B_DQ<45> DDR0_DQ[61]/DDR1_DQ[45] DDR_VTT_CTRL 20 M_B_DQ<61> DDR1_DQ[61] DDR_RCOMP[2]
BA25 AW67 AP21
20 M_B_DQ<46> DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL 20 M_B_DQ<62> DDR1_DQ[62]
BB25 AN21
20 M_B_DQ<47> DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20
20 M_B_DQ<63> DDR1_DQ[63] 3 OF 20
RM1 RM2 RM3
100R 80.6R 1% 200R
SKL-U_BGA1356 SKL-U_BGA1356 1% R0402_N 1%
<BOM Structure> <BOM Structure> R0402_N I R0402_N
I I

B B

+V1P2U_VDDQ +V3P3A

Default
CM1 RM4
0.1uF 10V 10% 100K
C0402 5%
Memory size 4Gb or 8Gb 16Gb X5R R0402
UM10 I I
1 5
RM95,RM96,RM97,RM98 RM95,RM96,RM97,RM98 NC VCC
need uninstall need install page4,19,20 DDR_VTT_CTRL
DRAM M9 pin 2
A
4
RM99,RM100 RM99,RM100 Y SM_PG_CTRL 61
3
need install need uninstall GND

74AUP1G07GW
RM79,RM81,RM83,RM85, RM79,RM81,RM83,RM85, sot_353
DRAM E9 pin RM87,RM89,RM91,RM93 RM87,RM89,RM91,RM93 page19,20 I
need install 0 ohm need install 240 ohm

RM3 200 ohm RM3 121 ohm


need install need install page4
SOC RCOMP0

2/2 Add (4Gb 8Gb) & (16Gb) BOM option table


A A

Project: 320S-13
+V3P3A
Engineer: Jason
+V3P3A 3,5,6,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70
+V1P2U_VDDQ +V1P2U_VDDQ 10,19,20,21,61 Size Title: Rev
Custom KBL-U(2/12)DDR4 V01
Date: Tuesday, May 23, 2017 Sheet 4 of 81

5 4 3 2 1
5 4 3 2 1

+V3P3A +V3P3A +V3P3A +V3P3A


SKL-U
UC1E
Rev_0.53
SPI - FLASH
SMBUS, SMLINK R1055 R1053
AV2 1K 100K R9872 R9873
24,50 FLASH_SPI_CLK SPI0_CLK
TP_SMB_CLK
24,50 FLASH_SPI_MISO AW3 R7 TP1053 R0402 R0402 10K 10K
SPI0_MISO GPP_C0/SMBCLK
AV3 R8 TP_SMB_DATA TP1054 5% 5% 5% 5%
24,50 FLASH_SPI_MOSI SPI0_MOSI GPP_C1/SMBDATA
STRAP_GPP_C2 NI NI R0402_N R0402_N
AW2 R10
SPI Flash 24 FLASH_SPI_IO2 SPI0_IO2 GPP_C2/SMBALERT# I I
AU4
24 FLASH_SPI_IO3 SPI0_IO3
AU3 R9 SML0_CLK TP9998
24,50 FLASH_SPI_CS0_N SPI0_CS0# GPP_C3/SML0CLK
SML0_DATA
AU2 W2 TP9999
SPI0_CS1# GPP_C4/SML0DATA
D AU1 W1 STRAP_GPP_C5 D
SPI0_CS2# GPP_C5/SML0ALERT#

W3 SML1_CLK_R R9861 0R R0402_N 5% I


SPI - TOUCH GPP_C6/SML1CLK
V3 SML1_DATA_R R9862 0R R0402_N 5% I
GPP_C7/SML1DATA
M2 AM7 THERMAL_ALERT#_R R9863 0R R0402_N 5% NI
GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# THERMAL_ALERT# 29
M3
GPP_D2/SPI1_MISO
J4 3/2 R9863 change to NI,THERMAL HW shutdown
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
+V3P3SX GPP_D22/SPI1_IO3
M1 LPC
GPP_D0/SPI1_CS#
AY13
GPP_A1/LAD0/ESPI_IO0 LPC_AD0 43,50
BA13 WLAN/EC
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_AD1 43,50
BB13
GPP_A3/LAD2/ESPI_IO2 LPC_AD2 43,50
R1066 G3 AY12
CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_AD3 43,50
5/9 EC_KBRST# Add PU R1066 10Kohm +V3P3SX 10K G2 BA12
5% CL_DATA GPP_A5/LFRAME#/ESPI_CS#
TP_PM_SUS_STAT_N LPC_FRAME_N 43,50
G1 BA11
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET#
R0402_N TP1052
I
AW13 AW9 LPC_CLK_EC_R R1064 I 22R R0402 5%
50 EC_KBRST# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK
LPC_CLK_PRT80_R R1065 I LPC_CLK_EC 50
AY9 22R R0402 5%
GPP_A10/CLKOUT_LPC1 LPC_CLK_PRT80 43
To EC AY11 AW11
50 LPC_SERIRQ GPP_A6/SERIRQ 5 OF 20 GPP_A8/CLKRUN# PM_CLKRUN_N 50
LPC Mode
SKL-U_BGA1356 +V3P3A
<BOM Structure>
+V3P3A
R1061
8.2K
C R1059 10K R0402 5% I LPC_SERIRQ R0402 C
5%
5
/
9
P
a
g
e
5
0
E
C
p
i
n
2
4
B
A
T
_
C
H
G
O
K
_
L
E
D
_
N
c
h
a
n
g
e
t
o
E
C
_
K
B
R
S
T
#
,
c
o
n
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t
t
o
S
O
C
p
i
n
A
W
1
3
(
R
C
I
N
)
PM_CLKRUN_N I

R1073
1K
R0402
5%
NI

+V3P3A +V3P3A 3,4,6,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70

+V3P3SX +V3P3SX 6,7,8,9,10,26,27,30,35,36,43,46,50,75

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:KBL-U(3/12)SPI,ESPI,SMB,LPC Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 5 of 81
5 4 3 2 1
5 4 3 2 1

To Enable ME Override
R9848 0R STRAP_HDA_SDO_SOC
50 ME_Flash_EN R0402_N 5% I

D Difference with armour 5/23 R9848 install,BIOS request D


Add EC to enable ME override

RC393 33R R0402 5% I HDA_SYNC_SOC


46 HDA_SYNC
R1086 33R R0402 5% I HDA_BCLK
46 HDA_BCLK_R
RC395 33R R0402 5% I STRAP_HDA_SDO_SOC +V3P3A
46 STRAP_HDA_SDO
RC394 33R R0402 5% I HDA_RST_N_SOC
46 HDA_RST_N
R1054
1K
R0402
5%
NI
UC1G SKL-U
Rev_0.53
AUDIO

HDA_SYNC_SOC BA22
HDA_SYNC/I2S0_SFRM
HDA_BCLK AY22
HDA_BLK/I2S0_SCLK
STRAP_HDA_SDO_SOC BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
HDA_SDI0
HDA for AUDIO 46 HDA_SDI0 BA21
AY21
HDA_SDI0/I2S0_RXD
AB11
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD
HDA_RST_N_SOC AW22 AB13
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 AB12
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
AY20 W12
I2S1_SFRM GPP_G3/SD_DATA2
AW20 W11
I2S1_TXD GPP_G4/SD_DATA3
W10
GPP_G5/SD_CD#
C AK7 W8 Difference with armour C
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
AK6 W7 TP_SD_WP R9864 0R R0402_N 5% NI Add 0ohm NI
GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK9
GPP_F2/I2S2_TXD
AK10 BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
BB9
GPP_A16/SD_1P8_SEL

H5 AB7 SDMMC_RCOMP R1015 200R R0402 1% I


GPP_D19/DMIC_CLK0 SD_RCOMP
D7
43 WIFI_DISABLE_N GPP_D20/DMIC_DATA0

D8 AF13
GPP_D17/DMIC_CLK1 GPP_F23
C8
+V3P3SX GPP_D18/DMIC_DATA1

R1052 100K AW5


R0402 5% NI GPP_B14/SPKR
7 OF 20

46 HDA_SPKR
SKL-U_BGA1356
1/4 Connect codec <BOM Structure>

+V3P3A +V3P3A 3,4,5,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70


+V3P3SX +V3P3SX 5,7,8,9,10,26,27,30,35,36,43,46,50,75

B B
SKL_ULT
UC1I
Rev_0.53
CSI-2

A36 C37
CSI2_DN0 CSI2_CLKN0
B36 D37
CSI2_DP0 CSI2_CLKP0
C38 C32
CSI2_DN1 CSI2_CLKN1
D38 D32
CSI2_DP1 CSI2_CLKP1
C36 C29
CSI2_DN2 CSI2_CLKN2
D36 D29
CSI2_DP2 CSI2_CLKP2
A38 B26
CSI2_DN3 CSI2_CLKN3
B38 A26
CSI2_DP3 CSI2_CLKP3

C31 E13 CSI2_COMP R1013 100R R0402 1% I


CSI2_DN4 CSI2_COMP
D31 B7 CSI2_FLASH_STROBE TP1061
CSI2_DP4 GPP_D4/FLASHTRIG
C33
CSI2_DN5
D33 3/18 Add TP1061
CSI2_DP5 EMMC
A31
CSI2_DN6
B31 AP2
CSI2_DP6 GPP_F13/EMMC_DATA0
5/10 Del TP1055,TP1056,TP1057,TP1058,TP1059,TP1060,TP1016,TP1017, A33 AP1
CSI2_DN7 GPP_F14/EMMC_DATA1
MIPI defferential don't test point B33 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2
AN3
GPP_F16/EMMC_DATA3
A29 AN1
CSI2_DN8 GPP_F17/EMMC_DATA4
B29 AN2
CSI2_DP8 GPP_F18/EMMC_DATA5
C28 AM4
CSI2_DN9 GPP_F19/EMMC_DATA6
D28 AM1
CSI2_DP9 GPP_F20/EMMC_DATA7
A27
CSI2_DN10
B27 AM2
A CSI2_DP10 GPP_F21/EMMC_RCLK A
C27 AM3
CSI2_DN11 GPP_F22/EMMC_CLK
D27 AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 EMMC_RCOMP R1014 200R R0402 1% I
EMMC_RCOMP

SKL-U_BGA1356 Project: 320S-13


<BOM Structure>
Engineer: Jason
Size Title:KBL-U(4/12)HDA,EMMC,SD Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 6 of 81
5 4 3 2 1
5 4 3 2 1

XTAL_24M_SOC_IN

XTAL_24M_SOC_OUT R1057 1M
R0402 5% U22,U22F

SKL_ULT Y1001
UC1J
Rev_0.53 2 GN D
1
Y2 Y1

CLOCK SIGNALS 3 4
+3V_PRIM Y3 Y4
PCIE_REFCLK_SSD_DN_R
GN D
R9887 0R R0402_N5%I D42
26 PCIE_REFCLK_SSD_DN R0402_N5%I PCIE_REFCLK_SSD_DP_R CLKOUT_PCIE_N0 24MHZ 10PPM
R9888 0R C42 X4S32X25
26 PCIE_REFCLK_SSD_DP CLKOUT_PCIE_P0 C1250 C1249
AR10
26 SSD_CLK_REQ_N GPP_B5/SRCCLKREQ0# 8.2pF 50V 0.1pF U22,U22F 8.2pF 50V 0.1pF
R9865 R9866 NPO NPO
D D
10K 10K SSD Close to SOC B42 C0402_N C0402_N
5% 5% CLKOUT_PCIE_N1
A42 F43
R0402_N R0402_N HW_ID0 AT7
CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
E43 U22,U22F U22,U22F
I I GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P

D41 BA17
HW_ID0 CLKOUT_PCIE_N2 GPD8/SUSCLK SUS_CLK 43,50
C41
HW_ID1 HW_ID1 CLKOUT_PCIE_P2 XTAL_24M_SOC_IN
AT8 E37 3/10 Change C1249,C1250 from 22pF to 8.2pF
GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL_24M_SOC_OUT +V1P0A_VCCPRIM
E35
XTAL24_OUT
D40
74 CLK_PCIE_GPU# CLKOUT_PCIE_N3 XCLK_BIASREF
C40 E42 R1019 2.7K R0402 1% I
74 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P3 XCLK_BIASREF XTAL_32K_SOC_OUT
AT10
74 GPU_CLKREQ# GPP_B8/SRCCLKREQ3# XTAL_32K_SOC_IN
R1088 R1089 AM18
RTCX1 XTAL_32K_SOC_OUT
10K 10K B40 AM20
5% 5% SD 27 PCIE_REFCLK_SD_DN_R CLKOUT_PCIE_N4 RTCX2 XTAL_32K_SOC_IN R1056
A40 10M
R0402_N R0402_N 27 PCIE_REFCLK_SD_DP_R CLKOUT_PCIE_P4 SRTC_RST_N R0402 5% I
AU8 AN18
27 SD_CLK_REQ_N GPP_B9/SRCCLKREQ4# SRTCRST#
NI NI AM16 RTC_RST_N
PCIE_REFCLK_WLAN_DN_R E40 RTCRST#
43 PCIE_REFCLK_WLAN_DN_R PCIE_REFCLK_WLAN_DP_R E38 CLKOUT_PCIE_N5

Difference with armour


WLAN 43 PCIE_REFCLK_WLAN_DP_R
AU7
CLKOUT_PCIE_P5
Y1000
43 WLAN_CLK_REQ_N GPP_B10/SRCCLKREQ5#
Modify HW_ID 1 2

10 OF 20 32.768KHz +/-20ppm
CRY2_3215
C1251 I C1252
SKL-U_BGA1356
15pF 50V 5% 15pF 50V 5%
<BOM Structure> NPO NPO
C0402_N C0402_N
SRTC_RST_N 5/22 change CAPs
1/13 Add RTC reset circuit. R9885 0R I I
R0402_N 5% NI
+V3P3SX
R9884 0R RTC_RST_N
R0402_N 5% I
D
Q8209 3/10 Change Y1000 from seiko to HOSONIC
R10050
50 SRTCRST_EC 2N7002 250mA 60V
10K sot_323_dgs
5%
G S 3/10 Change C1251,C1252 from 18pF to 12pF
C R9883 I C
R0402_N
I 10K 3/21 Change C1251,C1252 from 12pF to 15pF,
GPU_CLKREQ#
5% hosonic & seiko share
R0402_N
I

+V1P0A_VCCPRIM +V1P0A_VCCPRIM 14
+V3P3A +V3P3A 3,4,5,6,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70
+V3P3SX +V3P3SX 5,6,8,9,10,26,27,30,35,36,43,46,50,75

+RTCVCC +RTCVCC 11
+3V_PRIM +3V_PRIM 8,11
+1.0V_VCCST +1.0V_VCCST 3,10,12,14,66 +RTCVCC
+V3P3A

R1072 R1058 R1060 R1062


10K 20K 20K 1M
5% 5% 5% 5%
R0402_N R0402_N R0402_N R0402_N
I I I I
PM_BATLOW_N
RTC_RST_N SRTC_RST_N SM_INTRUDER_N
UC1K SKL-U
Rev_0.53
+V3P3A +V3P3SX SYSTEM POWER MANAGEMENT C1254 C1253
SLP_S0_N 1uF 6.3V 10% 1uF 6.3V 10%
AT11 TP9996 X5R X5R
GPP_B12/SLP_S0#
AP15 C0402_N C0402_N
GPD4/SLP_S3# SLP_S3_SOC 50
R1093 R1071 AN10 BA16 I I
26,27,43,50,74 PLT_RST_N PM_SYSRST_N GPP_B13/PLTRST# GPD5/SLP_S4# SLP_S4_SOC 50
2.2K 2.2K B5 AY16
5% 5% SYS_RESET# GPD10/SLP_S5# SLP_S5_SOC 50
AY17
50 RSMRST_N RSMRST#
R0402_N R0402_N AN15 SLP_SUS_N
I NI TP_CPUPWRGD SLP_SUS# SLP_SUS_N 11
TP1021 A68 AW15
H_VCCST_PWRGD B65 PROCPWRGD SLP_LAN# +3V_PRIM
B BB17 B
VCCST_PWRGD GPD9/SLP_WLAN# SLP_A_N
AN16 TP9997
PM_SYSRST_N GPD6/SLP_A#
B6
50 SYS_PWROK SYS_PWROK
BA20 BA15
RSMRST_N 50 IMVP_PCH_PWRGD RSMRST_N PCH_PWROK GPD3/PWRBTN# AC_PRESENT_R PM_PWRBTN_R_N 50 +1.0V_VCCST
BB20 AY15 R1020
DSW_PWROK GPD1/ACPRESENT
AU13 10K
TP_SUS_PWR_DN_ACK AR13 GPD0/BATLOW# PM_BATLOW_N 50 5%
R1079 TP1081
TP_SUSACK_N GPP_A13/SUSWARN#/SUSPWRDNACK R0402_N H_VCCST_PWRGD R1044 1K
100K TP1048 AP11
5% GPP_A15/SUSACK# PME_N I
AU11 R0402_N I 5%
R0402_N GPP_A11/PME# SM_INTRUDER_N
BB15 AP16
26,27,43 PCIE_WAKE_PCH_N WAKE# INTRUDER#
I AM15 IMVP_PCH_PWRGD C A
GPD2/LAN_WAKE# EXT_PWR_GATEB
AW17 AM10 TP1025
+V3P3A GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# R200_PWR_EN
AT15 AM11 TP1022
GPD7/RSVD GPP_B2/VRALERT# CR1003
11 OF 20 R9886
RB521C30 100mA 30v
R1041 10K 100K SOD-923
R0402_N 5% I 5%
SKL-U_BGA1356 I
R0402_N
<BOM Structure> NI

+V3P3A

IMVP_PCH_PWRGD R1048
29,66 VR_PWRGD R1042 0R
R0402_N 5% I 100K
5%
R0402_N
I
2/24 Add R1042,VR_PWRGD connect to SOC and EC
R1046 0R
50 AC_PRESENT R0402_N I 5%

R1047 0R AC_PRESENT_R
50,59 AC_PRES R0402_N NI 5%

A A
CHG_ACOK change to ACPRES
from Charger IC

Project: 320S-13
Engineer: Jason
Size Title:KBL-U(5/12)CLK,GPIO Rev
Custom V01
Date: Monday, May 22, 2017 Sheet 7 of 81
5 4 3 2 1
5 4 3 2 1

UC1F SKL-U
Rev_0.53
LPSS ISH

AN8
GPP_B15/GSPI0_CS#
AP7 P2
+V3P3SX GPP_B16/GSPI0_CLK GPP_D9
AP8 P3 TP9995
D 50,75 GC6_FB_EN_3.3 TP_STRAP_GPP_B18 GPP_B17/GSPI0_MISO GPP_D10 D
TP1009 AR7 P4
GPP_B18/GSPI0_MOSI GPP_D11
P1
+V3P3A GPP_D12
AM5
R10046 GPP_B19/GSPI1_CS#
AN7 M4
5% 10K GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA
AP5 N3
R0402_N STRAP_GPP_B22 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL
R1051 100K AN5
DIS R0402_N 5% NI GPP_B22/GSPI1_MOSI
N1
GPP_D7/ISH_I2C1_SDA
50,75 DGPU_PWR_EN RI91 I AB1 N2
5%R0402_N I GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
0R 0402 5% 50,74 DGPU_HOLD_RST# R10095 0R AB2
GPP_C9/UART0_TXD
W4 AD11
43 WLAN_RST GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPU_EVENT#_SOC AB3 AD12
R10075 GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
5% 10K
R0402_N AD1
56 UART2_RXD GPP_C20/UART2_RXD
NI UART for debug 56 UART2_TXD AD2 U1
GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
AD3 U2
GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
AD4 U3
Add the GPIO for Hall sensor GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS#
5/23 confirm BIOS, not used LID U4
GPP_D16/ISH_UART0_CTS#/SML0BALERT#

U7 AC1 MEM_DEC0
50 TOUCH_PAD_DAT0 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD MEM_DEC1
U6 AC2
50 TOUCH_PAD_CLK0 GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD MEM_DEC2
AC3
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
U8 AB4
GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U9
GPP_C19/I2C1_SCL ALS_INT_N
AY8 TP9994
GPP_A18/ISH_GP0
AH9 BA8
GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 GYROSCOPE_INT
AH10 BB7 TP8210
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2
BA7 TP8211
GPP_A21/ISH_GP3
AH11 AY7
GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 TOUCH_PAD_INT 50
AH12 AW7
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5
AP13
GPP_A12/BM_BUSY#/ISH_GP6
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL 6 OF 20

+3V_PRIM +3V_PRIM +3V_PRIM


C SKL-U_BGA1356 C
<BOM Structure> Memory Dectection
R9801 R9806
+3V_PRIM +3V_PRIM 7,11 R9803 10K 10K
10K 1% 1%
+V3P3SX +V3P3SX 5,6,7,9,10,26,27,30,35,36,43,46,50,75 1% R0402_N R0402_N
R0402_N NI I
+V3P3A +V3P3A 3,4,5,6,7,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70 NI MEM_DEC0 MEM_DEC1 MEM_DEC2

R9802 R9807
R9804
10K 10K
10K 1% 1%
1%
R0402_N R0402_N
R0402_N
I NI
I

75 GPU_EVENT#
DIS SOD_323 BAT54WS D6607 GPU_EVENT#_SOC

Samsung_4GB Micron_4GB Hynix_4GB Samsung_8GB Micron_8GB Hynix_8GB Samsung_16GB Micron_16GB

MEM_DEC0 0 1 0 1 0 1 0 1

MEM_DEC1 0 0 1 1 0 0 1 1

MEM_DEC2 0 0 0 0 1 1 1 1
Default

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:KBL-U(6/12)GPIO Rev
Custom V01
Date: Tuesday, May 23, 2017 Sheet 8 of 81
5 4 3 2 1
5 4 3 2 1

UC1H SKL-U
Rev_0.53

SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN USB3_P1_RX_DN 42
G8
USB3_1_RXP USB3_P1_RX_DP 42
74 PCIE_CRX_GTX_N0
H13
G13
PCIE1_RXN/USB3_5_RXN USB3_1_TXN
C13
D13
USB3_P1_TX_DN 42 USB3.0 CONN
74 PCIE_CRX_GTX_P0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_P1_TX_DP 42
C9978 0.22uF 10V 10% C0402_N X5R I PCIE_CTX_GRX_N0_C B17
74 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P0_C A17 PCIE1_TXN/USB3_5_TXN
C9979 0.22uF 10V 10% C0402_N X5R I J6
74 PCIE_CTX_GRX_P0 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3_P2_WP2_RX_DN 54
H6
USB3_2_RXP/SSIC_1_RXP USB3_P2_WP2_RX_DP 54
74 PCIE_CRX_GTX_N1
G11
F11
PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN
B13
A13
USB3_P2_WP2_TX_DN 54 Type-c
D 74 PCIE_CRX_GTX_P1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_P2_WP2_TX_DP 54 D
C9588 0.22uF 10V 10% C0402_N X5R I PCIE_CTX_GRX_N1_C D16
74 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1_C C16 PCIE2_TXN/USB3_6_TXN
C9589 0.22uF 10V 10% C0402_N X5R I J10
74 PCIE_CTX_GRX_P1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
H10
USB3_3_RXP/SSIC_2_RXP
GPU x4 H16 B15
74 PCIE_CRX_GTX_N2 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN
G16 A15
74 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2_C D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C9590 0.22uF 10V 10% C0402_N X5R I
74 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2_C C17 PCIE3_TXN
C9591 0.22uF 10V 10% C0402_N X5R I E10
74 PCIE_CTX_GRX_P2 PCIE3_TXP USB3_4_RXN
F10
USB3_4_RXP
G15 C15
74 PCIE_CRX_GTX_N3 PCIE4_RXN USB3_4_TXN
F15 D15
74 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3_C B19 PCIE4_RXP USB3_4_TXP
C9592 0.22uF 10V 10% C0402_N X5R I
74 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3_C A19 PCIE4_TXN
C9980 0.22uF 10V 10% C0402_N X5R I AB9
74 PCIE_CTX_GRX_P3 PCIE4_TXP USB2N_1 USB2_P1_WP1_DN 42
AB10 USB3.0 connector
USB2P_1 USB2_P1_WP1_DP 42
F16
27 PCIE_SD_LN0_RX_SOC_DN PCIE5_RXN
E16 AD6
27 PCIE_SD_LN0_RX_SOC_DP CPU_SD_TX_DN PCIE5_RXP USB2N_2 USB2_P2_WP2_DN 55
SD Card C9586 0.1uF 10V 10%X5R C0402_N I C19 AD7 Type-c
27 PCIE_SD_LN0_TX_SOC_DN CPU_SD_TX_DP PCIE5_TXN USB2P_2 USB2_P2_WP2_DP 55
C9587 0.1uF 10V 10%X5R C0402_N I D19
27 PCIE_SD_LN0_TX_SOC_DP PCIE5_TXP
AH3
USB2N_3
G18 AJ3
43 PCIE_WLAN_LN0_RX_SOC_DN PCIE6_RXN USB2P_3
F18
43 PCIE_WLAN_LN0_RX_SOC_DP PCIE6_RXP
NGFF WIFI Module 43 PCIE_WLAN_LN0_TX_SOC_DN D20 AD9
PCIE6_TXN USB2N_4 USB2_P4_BT_DN 43
C20 AD10 BT
43 PCIE_WLAN_LN0_TX_SOC_DP PCIE6_TXP USB2P_4 USB2_P4_BT_DP 43
F20 AJ1
PCIE7_RXN/SATA0_RXN USB2N_5
E20 AJ2
PCIE7_RXP/SATA0_RXP USB2P_5
B21 USB2
PCIE7_TXN/SATA0_TXN
A21 AF6
PCIE7_TXP/SATA0_TXP USB2N_6 USB2_P6_WP3_DN 37
AF7 USB 2.0
USB2P_6 USB2_P6_WP3_DP 37
C G21 C
PCIE8_RXN/SATA1A_RXN
F21 AH1
PCIE8_RXP/SATA1A_RXP USB2N_7 USB2_P7_CAM_DN 36
D21 AH2 Camera
PCIE8_TXN/SATA1A_TXN USB2P_7 USB2_P7_CAM_DP 36
C21
PCIE8_TXP/SATA1A_TXP
AF8
USB2N_8
E22 AF9
26 PCIE9_SSD_RX_DN PCIE9_RXN USB2P_8
E23
26 PCIE9_SSD_RX_DP PCIE9_SSD_TX_DN PCIE9_RXP
26 PCIE9_SSD_TX_DN_C C0600 0.22uF 10V 10% C0402_N X5R I B23 AG1
PCIE9_TXN USB2N_9
C0601 0.22uF 10V 10% C0402_N X5R I PCIE9_SSD_TX_DP A23 AG2
26 PCIE9_SSD_TX_DP_C PCIE9_TXP USB2P_9

F25 AH7
26 PCIE10_SSD_RX_DN PCIE10_RXN USB2N_10
E25 AH8
26 PCIE10_SSD_RX_DP PCIE10_SSD_TX_DND23 PCIE10_RXP USB2P_10
26 PCIE10_SSD_TX_DN_C C0602 0.22uF 10V 10% C0402_N X5R I
PCIE10_TXN
C0603 0.22uF 10V 10% C0402_N X5R I PCIE10_SSD_TX_DPC23 AB6 USB2_COMP R1012 113R R0402 1% I
26 PCIE10_SSD_TX_DP_C PCIE10_TXP USB2_COMP
AG3 USB2_P1_WP1_OTG_ID R1084 1K R0402_N 5% I
USB2_ID
R1063 100R PCIE_RCOMP_N F5 AG4 USB2_VBUSSENSE R1085 1K R0402_N 5% I
PCIE_RCOMPN USB2_VBUSSENSE
NGFF SSD R0402 1% I PCIE_RCOMP_P E5
PCIE_RCOMPP
A9
XDP_PRDY_N GPP_E9/USB2_OC0# USB2_P1_WP0_OC_N 42
TP1051 D56 C9
XDP_PREQ_N PROC_PRDY# GPP_E10/USB2_OC1# USB2_P2_WP1_OC_N 54,55
TP1062 D61 D9 Difference with armour
TP_EC_CS_WAKE PROC_PREQ# GPP_E11/USB2_OC2#
USB2_P2_WP3_OC_N USB2_P3_WP2_OC_N 37 B9 modify to WWAN_PWR_ON
TP1050 BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3#

E28 J1 TP_SATA0_DEVSLP TP1079


26 PCIE11_SSD_RX_DN PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
SATA1_DEVSLP
E27 J2 TP8201
26 PCIE11_SSD_RX_DP PCIE11_SSD_TX_DND24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1
26 PCIE11_SSD_TX_DN_C C0604 0.22uF 10V 10% C0402_N X5R I J3 Difference with armour
PCIE11_SSD_TX_DPC24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SATA2_DEVSLP 26 modify SATA2_DEVSLP
26 PCIE11_SSD_TX_DP_C C0605 0.22uF 10V 10% C0402_N X5R I
PCIE11_TXP/SATA1B_TXP
E30 H2 TP_SSD_SATA0_PCIE_DET_N TP1080
26 PCIE12_SSD_RX_DN PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
F30 H3 TP1082
26 PCIE12_SSD_RX_DP PCIE12_SSD_TX_DNA25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
SSD_SATA_PCIE_DET_N
26 PCIE12_SSD_TX_DN_C C0606 0.22uF 10V 10% C0402_N X5R I G4 Difference with armour
PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
B C0607 0.22uF 10V 10% C0402_N X5R I PCIE12_SSD_TX_DP B25 SSD_SATA_PCIE_DET_N connect to G4 pin B
26 PCIE12_SSD_TX_DP_C PCIE12_TXP/SATA2_TXP
H1 TP_EDP2DSI_CORE_PWR_EN TP8213
GPP_E8/SATALED#
Difference with armour
SSD interface SATA change to PCIE 8 OF 20
+V3P3A
SATA1A change to PCIE port 9,10,11,12 Checklist:
Gen1 and Gen2=100nF SKL-U_BGA1356
Gen3=220nF <BOM Structure>
GPIO DEVICE CONTROL R9882
10K
5%
USB_OC0# Type C R0402_N
I
USB_OC1# USB2 Port 2 USB2_P2_WP3_OC_N

USB_OC2# NA 1/7 Add PU +V3P3A


+V3P3SX
USB_OC3# WWAN_PWR_ON
DEVSLP0 NA R1087
Difference with armour 100K
DEVSLP1 NA R1050 install,R1087 uninstall 5%
R0402_N
NI
DEVSLP2 NGFF SSD KEY M
SSD_SATA_PCIE_DET_N
SATA_GP0 NA
NOTE: R1050
SATA_GP1 NA USE FITC TO ALLOW SELECTION OF 10K
A PCIE VS SATA BASED ON STRAPPING: 5% A
R0402_N
SATA_GP2 SSD_SATA_PCIE_DET_N GPP_E_2 FOR SATA2/PCIE: I
1 - SATA2, 0 - PCIE P9,P10,P11,P12

Project: 320S-13
+V3P3A +V3P3A 3,4,5,6,7,8,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70 Engineer: Jason
+V3P3SX +V3P3SX 5,6,7,8,10,26,27,30,35,36,43,46,50,75
Size Title:KBL-U(7/12)PCIE,USB,SATA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 9 of 81

5 4 3 2 1
5 4 3 2 1

+V1P2U_VDDQ +1.0VS_VCCIO
+VCC_SA
UC1N SKL-U
+V5P0A +V5P0A +V5P0S Rev_0.53
CPU POWER 3 OF 4
RC421
+V5P0A to +V5P0S AU23
VDDQ_AU23 VCCIO1
AK28 100R 1%
R0402
1/13 新增 +V5P0S AU28
VDDQ_AU28 VCCIO2
AK30
AU35 AL30 I
VDDQ_AU35 VCCIO3 VCCSA_SENSE
CC98 CC97 CC96 AU42 AL42
VDDQ_AU42 VCCIO4 VSSSA_SENSE
1uF 6.3V 10% 1uF 6.3V 10% 0.1uF 10V 10% BB23 AM28
X5R X5R X5R VDDQ_BB23 VCCIO5
BB32 AM30
C0402 C0402 C0402 VDDQ_BB32 VCCIO6
BB41 AM42 RC422
I I I VDDQ_BB41 VCCIO7
BB47 100R 1%
VDDQ_BB47 R0402
BB51 AK23
VDDQ_BB51 VCCSA1 +VCC_SA I
UC5 11/17_Follow 543977_SKL_PDDG_Rev0_91 AK25
VCCSA2
1 14 CC95 10PF ->22us(Spec:<= 65us) G23
VIN1 VOUT1 VCCSA3
2 13 AM40 G25
D VIN1-1 VOUT1-1 +1.2V_VDDQC VDDQC VCCSA4 D
G27
VCCSA5
3 12 CC95 10pF 50V 0.5pF +1.0V_VCCST A18 G28 12/2 Close to CPU
ON1 CT1 C0402 NPO I VCCST VCCSA6
J22
VCCSA7
4 11 A22 J23
VBIAS GND +1.0VS_VCCSTG VCCSTG_A22 VCCSA8
J27
R0402 5% I VCCSA9
RC420 0R 5 10 CC94 1000pF 50V 10% +1.2V_VCCSFR_OC AL23 K23
50,60 SLP_S3_N ON2 CT2 C0402 X7R I +V3P3SX VCCPLL_OC VCCSA10
K25
+V3P3A VCCSA11
6 9 K20 K27
VIN2 VOUT2-1 +1.0V_VCCSFR VCCPLL_K20 VCCSA12
7 8 K21 K28
VIN2-1 VOUT2 VCCPLL_K21 VCCSA13
K30
VCCSA14
1/4 modify OK 15
GPAD VCCIO_SENSE
CC164 CC165 AM23 T124
VCCIO_SENSE VSSIO_SENSE
1uF 6.3V 10% EM5209VF 0.1uF 10V 10% AM22 T125
X5R dfn14p_ph0p4_3x2_h0p8 X5R VSSIO_SENSE
C0402 I C0402 H21 VSSSA_SENSE
I I VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE 66
H20
14 OF 20 VCCSA_SENSE VCCSA_SENSE 66

SKL-U_BGA1356
+V3P3A to +V3P3SX <BOM Structure>
12/22 新 增+V3P3S
X

+V5P0A +1.0V_PRIM +1.0VS_VCCSTG +1.0V_VCCSTU +1.0V_VCCST +V1P2U_VDDQ +1.2V_VCCSFR_OC

2/24 pin9 connect GND,need change to +1.0V_PRIM RC188 0R CC89 0.1uF 10V 10%
R0402 5% I C0402 X5R I RC140 0R RC141 0R BSC Side
5/31 add CAP, change to 330uF R0402 5% I PSC Side R0402 5% I
CC88 C10038 CC117 +1.0VS_VCCIO
+

0.1uF 10V 10% 100uF 6.3V +/-20% 1uF 6.3V 10% UC6
X5R SMD3.5X2.8mm X5R 1 8 +1.0VS_VCCSTG_IO RC189 0R CC90 0.1uF 10V 10% CC48 CC49
C0402 NI C0402 VIN1 VOUT3 R0805_N 5% I C0402 X5R I
2 1uF 6.3V 10% 1uF 6.3V 10%
I I VIN2 X5R X5R
7
VOUT2 C0402 C0402
C 9 Imax : 2.73 A C
VIN thermal I I
6 CC99 10uF 6.3V 20%
VOUT1 C0402_N X5R NI
3
VBIAS
CC100 10uF 6.3V 20%
SLP_S3_N RC187 0R R0402 5% I 4 5 C0402_N X5R NI
ON GND
5/31 uninstall CAPs
1/27 Intel Add 10uF x2 RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0
AOZ1334DI-02
tps22961_8P_h0p8
I +1.0V_VCCSFR +1.0VS_VCCSTG

+1.0V_PRIM to +1.0VS_VCCSTG / +1.0VS_VCCIO RC143


R0402
0R
5% I PSC Side BSC Side

CC55 CC142
1uF 6.3V 10% 1uF 6.3V 10%
X5R X5R
+V5P0A +1.0V_PRIM C0402 C0402
I I
2/24 pin9 connect GND,need change to +1.0V_PRIM

CC376
CC380 1uF 6.3V 10% +1.0V_VCCSTU
0.1uF 10V 10% X5R UC7
+1.0V_VCCSTU_IO
X5R
C0402
C0402
I
1
2
VIN1 VOUT3
8 RC430
R0402
0R
5% I +1.8V_PRIM to +V1P8S
I VIN2 +V5CP
VOUT2
7 11/24 新 增+V1P8 S +V1P8S
9 CC379 +1.8V_PRIM for Finger print,Audio codec
VIN thermal
6 0.1uF 10V 10%
VOUT1 X5R
3
VBIAS C0402 CC449
EN_1.0V_VCCSTU I CC451
RC142 0R 4 5 CC450 0.1uF 10V 10%
50,60 SLP_S4_N R0402 5% I ON GND 1uF 6.3V 10% X5R
X7R 1uF 6.3V 10%
X7R C0402
C0402
TPS22961DNYR C0402 I
I UC8
tps22961_8P_h0p8 I
B I 1 14 B
VIN1 VOUT1
2 13
VIN1-1 VOUT1-1
SLP_S3_N RC442
+1.0V_PRIM to +1.0V_VCCSTU R0402
0R
I
5% 3
ON1 CT1
12 CC448
C0402
1000pF 50V 10%
X7R I
4 11
VBIAS GND

RC453 0R 5% 5 10 CC453 1000pF 50V 10%


50,60 EC_ALW_EN R0402 I ON2 CT2 C0402 X7R I
6 9 +V5P0A
+V5CP VIN2 VOUT2-1
7 8
VIN2-1 VOUT2

15
GPAD
CC454
CC455 EM5209VF
dfn14p_ph0p4_3x2_h0p8 0.1uF 10V 10%
1uF 6.3V 10% X5R
X7R I
C0402
C0402
I
I
+1.0VS_VCCIO
BSC Side PSC Side +V5CP to +V5P0A
11/28 新 增
10uF 6.3V 20%

10uF 6.3V 20%

1uF 6.3V 10%

1uF 6.3V 10%

1uF 6.3V 10%

1uF 6.3V 10%

1uF 6.3V 10%

1uF 6.3V 10%

1uF 6.3V 10%

1uF 6.3V 10%

CC27 CC28 CC29 CC30 CC31 CC32 CC33 CC34 CC35 CC36 RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
C0603 C0603 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
NI NI I I I I I I I I +V1P2U_VDDQ +1.2V_VDDQC +V1P2U_VDDQ
BSC Side
RC208 0R
R0603 5% I
5/31 uninstall CAPs
10uF 6.3V 20%

10uF 6.3V 20%

10uF 6.3V 20%

10uF 6.3V 20%

10uF 6.3V 20%


CC41 CC42 CC43
CC47
X5R
CC37
X5R
CC38
X5R
CC39
X5R
CC40
X5R
22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
C0603 C0603 C0603 C0603 C0603
X5R X5R X5R
A I I I I I
C0603_N C0603_N C0603_N A
I I I

+VCC_SA +VCC_SA 15,67


+V1P8S +V1P8S 75
+V5CP +V5CP 42,60
+1.8V_PRIM +1.8V_PRIM 11,56,65 +V1P2U_VDDQ: 10UF/6.3V/0603 *4
+V3P3A +V3P3A 3,4,5,6,7,8,9,11,24,29,35,37,42,50,55,56,60,62,65,66,70 CC47 Follow 543016_SKL_U_Y_PDG_0_9 22UF/6.3V/0402 *3
+V5P0S +V5P0S 30,35,46
+V5P0A +V5P0A 11,37,50,54,61,62,63,65,66,67,69,70,75 Project: 320S-13
+1.0V_PRIM +1.0V_PRIM 11,14,63,75
+V3P3SX +V3P3SX 5,6,7,8,9,26,27,30,35,36,43,46,50,75 Engineer: Jason
+V1P2U_VDDQ +V1P2U_VDDQ 4,19,20,21,61
Size Title:KBL-U(8/12)Power Rev
+1.0VS_VCCSTG +1.0VS_VCCSTG 3,12 V01
+1.0VS_VCCIO C
+1.0VS_VCCIO 3,14
Date: Monday, July 03, 2017 Sheet 10 of 81

5 4 3 2 1
5 4 3 2 1

+1.0V_PRIM
+1.0V_PRIM
+1.0V_PRIM +1.0V_APLL +3V_PRIM +3V_HDA

CC91 UC1O SKL-U


1uF 6.3V 10% Rev_0.53
X7R CPU POWER 4 OF 4
RC148 0R RC150 0R CC61
R0603 5% I R0402 5% I 1uF 6.3V 10% C0402 AB19
X7R I VCCPRIM_1P0_1
AB20 AK15
CC123 CC134
near pin K15, L15 C0402 P18
VCCPRIM_1P0_2 VCCPGPPA
AG15
+3V_PGPPA
I VCCPRIM_1P0_3 VCCPGPPB +3V_PGPPB
22uF 6.3V 20% 22uF 6.3V 20% CC72 CC163 Y16
+3V_PGPPC
X5R X5R VCCPGPPC
1uF 6.3V 10% 1uF 6.3V 10% +1.0V_PRIM AF18 Y15
+3V_PRIM
C0603_N C0603_N X7R X7R VCCPRIM_CORE_1 VCCPGPPD
AF19 T16
NI NI C0402 C0402 +1.0VO_DSW VCCPRIM_CORE_2 VCCPGPPE +3V_PGPPE
V20 AF16
I I VCCPRIM_CORE_3 VCCPGPPF +3V_1.8V_PGPPF
V21 AD15
VCCPRIM_CORE_4 VCCPGPPG +3V_PRIM
D D
+1.0V_PRIM AL1 V19
+3V_PRIM
DCPDSW_1P0 VCCPRIM_3P3_V19

Follow 543016_SKL_U_Y_PDG_1_0 K17 T1


+1.0V_MPHYAON VCCMPHYAON_1P0_1 VCCPRIM_1P0_T1 +1.0V_DTS
CC85 L1
VCCMPHYAON_1P0_2
+1.0V_CLK5_F24NS 1uF 6.3V 10% AA1
+1.8V_PRIM
+3V_PGPPA X7R VCCATS_1P8
+3V_PRIM +1.0V_PRIM N15
C0402 VCCMPHYGT_1P0_N15
CC68 N16 AK17
+3V_PRIM_RTC
I VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
RC152 0R 1uF 6.3V 10% N17
R0603 5% I X7R VCCMPHYGT_1P0_N17
P15 AK19
near pin N18 C0402 P16
VCCMPHYGT_1P0_P15 VCCRTC_AK19
BB14
+RTCVCC
I VCCMPHYGT_1P0_P16 VCCRTC_BB14

CC135 CC130 +1.0V_PRIM K15 BB10 CC71 0.1uF 10V 10%


VCCAMPHYPLL_1P0_1 DCPRTC C0402 X5R I
22uF 6.3V 20% 22uF 6.3V 20% RC197 0R L15
X5R X5R R0402 5% I VCCAMPHYPLL_1P0_2
A14
C0603_N C0603_N VCCCLK1 +1.0V_CLK6_24TBT
+3V_SPI +1.0V_APLL V15
NI NI VCCAPLL_1P0
K19
VCCCLK2
CC67 +1.0V_PRIM AB17
VCCPRIM_1P0_AB17
1uF 6.3V 10% Y18 L21
+1.0V_APLL
X7R VCCPRIM_1P0_Y18 VCCCLK3
RC154 0R
C0402 R0402 5% I +1.0V_PRIM AD17 N20
NI
+3VALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
AD18
VCCDSW_3P3_AD18
AJ17 L19
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS
+1.0V_CLK4_F100OC +3V_PGPPB
AJ19 A10
+3V_HDA VCCHDA VCCCLK6 +1.0V_CLK6_24TBT
CC122
RC190 0R 1uF 6.3V 10% AJ16 AN11 PRIMCORE_VID0 T130
R0603 5% I RC161 0R
near pin AF20, X7R
+3V_SPI VCCSPI GPP_B0/CORE_VID0
AN13 PRIMCORE_VID1 T131
GPP_B1/CORE_VID1
R0402 5% I AF21, T19, T20 C0402
I
+1.0V_PRIM AF20
VCCSRAM_1P0_1
CC102 AF21
VCCSRAM_1P0_2
CC136 CC137 1uF 6.3V 10% T19
X7R VCCSRAM_1P0_3
22uF 6.3V 20% 22uF 6.3V 20% T20
X5R X5R C0402 VCCSRAM_1P0_4
C0603_N C0603_N I AJ21
NI NI
+3V_PRIM VCCPRIM_3P3_AJ21

+1.0V_PRIM +1.0V_PRIM AK20


C VCCPRIM_1P0_AK20 C
N18
+1.0V_PRIM VCCAPLLEBB 15 OF 20
+3V_PGPPC

+1.0V_PRIM
SKL-U_BGA1356
RC163 0R <BOM Structure>
R0402 5% I CC80 CC81 CC82
CC73 1uF 6.3V 10% 22uF 6.3V 20% 22uF 6.3V 20% 1/11 reserve to BATT conn
Imax : 2.57A 1uF 6.3V 10%
near pin N15, N16 X7R X5R X5R
CC76 X7R N17, P15, P16 C0402 C0603_N C0603_N 3/9 Del RC429,don't connect to BATT_RTC
near pin AF18, 1uF 6.3V 10%
X7R
C0402
I
I I NI RTC Battery
AF19, V20, V21 C0402
I Per 543016_SKL_U_Y_PDG_0_9
VCCRTC does not exceed 3.2 V From PDG
CC7 Close UC1.AK19.
+3V_1.8V_PGPPF +1.8V_PRIM
Power Rail Voltage +RTCBATT_R RC19 +RTCBATT
+1.0V_MPHYAON +RTCVCC 1K
+1.8V_PRIM R0402
RC172 0R RC206 0R +CHGRTC 3.383V(MAX) 5% JRTC1
R0402 5% I R0402 5% NI DC1 I
RC175 0R 2
15mils 15mils 1
R0402 5% I 1
CC103 CC389 BAT54C(VF) 240 mV 15mils 2
2
1uF 6.3V 10% Intel review: need close to pin AA1 1uF 6.3V 10% 3
X7R X7R G1
C0402 C0402 PAD1
CC87 +3VL_RTC 3.143V CC7 1
+V3.3AL G2
NI I PAD2
1uF 6.3V 10% 1uF 6.3V 10%
X7R X7R BAT54C 200mA 30V
C0402 Result : Pass C0402 SOT_23 @RTC1 11255W90-2P-S-5A-HF-R
I I I wtb_2p_1p25_90_BAT
+3V_PGPPE I
SHUNWO
LITHIUM BATT

CIS ok
CR2032

B CR2025 B
+1.0V_CLK6_24TBT RC167 0R CR2025
R0402 5% I I
CC74
RC169 0R 1uF 6.3V 10%
R0603 5% I X7R
C0402
I
CC86 CC75 CC138 CC139
1uF 6.3V 10% 1uF 6.3V 10% 22uF 6.3V 20% 22uF 6.3V 20%
X7R X7R X5R X5R
C0402
NI
C0402
NI
C0603_N
NI
C0603_N
NI +3V_PRIM_RTC
+V3P3A to +3V_PRIM
+3V_PRIM
+V3P3A
+V5P0A +V3P3A
RC171 0R R153 0R
+1.0V_DTS R0402 5% I R0805_N 5% NI

CC140 CC141 CC52 CC50 For NON-DS3


1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
RC162 0R X7R X7R For DS3 X7R X7R +3V_PRIMJP R159 0R
R0402 5% I C0402 C0402 C0402 C0402 R0805_N 5% I
I I I I CC51
0.1uF 10V 10%
UC4 For DS3 X5R
C0402
1 7 I
VIN1 VOUT1
RC428 0R 2 8
50,60 +V3.3A_PWRGD R0402 5% I VIN2 VOUT2

RC191 0R EN_3V_PRIM 3 6 CC53 1000pF 50V 10%


Follow 543016_SKL_U_Y_PDG_0_9 7 SLP_SUS_N R0402 5% NI ON CT C0402 X7R I

+1.0V_PRIM +3V_PRIM +1.8V_PRIM 4


VBIAS
1/4 Modify OK 5
GND
A 9 A
EPAD

CC111 CC112 CC113 CC114 CC115 CC116 AOZ1336DI


22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% WDFN8p_PH0p5_2X2_H0p8
X5R X5R X5R X5R X5R X5R I
C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N
NI NI NI NI NI NI +V3P3A +3VALW_DSW For DS3
+RTCVCC +RTCVCC 7
+1.0V_PRIM
+3V_PRIM
+1.0V_PRIM 10,14,63,75
+3V_PRIM 7,8
Project: 320S-13
RC173 0R +1.8V_PRIM +1.8V_PRIM 10,56,65
R0603 5% I +V3P3A +V3P3A 3,4,5,6,7,8,9,10,24,29,35,37,42,50,55,56,60,62,65,66,70 Engineer: Jason
+V5P0A +V5P0A 10,37,50,54,61,62,63,65,66,67,69,70,75 Size Title:KBL-U(9/12)Power Rev
Follow 543016_SKL_U_Y_PDG_0_9
Custom V01
Date: Monday, April 10, 2017 Sheet 11 of 81

5 4 3 2 1
5 4 3 2 1

+VCC_GT +VCC_GTX

+VCC_GT +VCC_GT RC452 0R


+VCC_CORE +VCC_CORE
UC1M SKL-U R0805_N 5%
+VCC_GT VCC_VCCGT Rev_0.53 U22F
UC1L SKL-U VCC_VCCGT CPU POWER 2 OF 4
Rev_0.53
CPU POWER 1 OF 4 N70
RC448 0.2mR 5% VCCGT56
A48 N71
A30
VCC_A30 VCC_G32
G32 R0805_N U22,U22F A53
VCCGT1 VCCGT57
R63
A34 G33 VCCGT2 VCCGT58
VCC_A34 VCC_G33 A58 R64
D A39 G35 +VCC_CORE VCCGT3 VCCGT59 +VCC_GTX VCC_VCCGTX D
VCC_A39 VCC_G35 A62 R65
A44 G37 VCCGT4 VCCGT60
VCC_A44 VCC_G37 A66 R66
AK33 G38 RC449 0.2mR 5% VCCGT5 VCCGT61
VCC_AK33 VCC_G38 AA63 R67 RC446 0.2mR
AK35
VCC_AK35 VCC_G40
G40 R0805_N U42 AA64
VCCGT6 VCCGT62
R68 R0805_N 5%
AK37 G42 VCCGT7 VCCGT63
AK38
VCC_AK37 VCC_G42
J30
AA66
VCCGT8 VCCGT64
R69 U22F
VCC_AK38 VCC_J30 AA67 R70 +VCC_CORE
AK40 J33 VCCGT9 VCCGT65
VCC_AK40 VCC_J33 AA69 R71
AL33 J37 VCCGT10 VCCGT66
VCC_AL33 VCC_J37 AA70 T62 RC447 0.2mR
AL37 J40 VCCGT11 VCCGT67
AL40
VCC_AL37 VCC_J40
K33
AA71
VCCGT12 VCCGT68
U65 R0805_N 5%
U42
VCC_AL40 VCC_K33 AC64 U68
AM32 K35 VCCGT13 VCCGT69
VCC_AM32 VCC_K35 AC65 U71
AM33 K37 VCCGT14 VCCGT70
VCC_AM33 VCC_K37 AC66 W63
AM35 K38 VCCGT15 VCCGT71
VCC_AM35 VCC_K38 AC67 W64
AM37 K40 VCCGT16 VCCGT72
VCC_AM37 VCC_K40 AC68 W65
AM38 K42 VCCGT17 VCCGT73
VCC_AM38 VCC_K42 AC69 W66
G30 K43 Trace Length < 25 mils VCCGT18 VCCGT74
VCC_G30 VCC_K43 AC70 W67
VCCGT19 VCCGT75
AC71 W68
K32 E32 VCCGT20 VCCGT76
RSVD_K32 VCC_SENSE VCCSENSE 66 J43 W69
E33 VCCGT21 VCCGT77
VSS_SENSE VSSSENSE 66 J45 W70
AK32 VCCGT22 VCCGT78
RSVD_AK32 J46 W71
B63 SOC_SVID_ALERT# VCCGT23 VCCGT79 +VCC_GTX
VIDALERT# J48 Y62
AB62 A63 SOC_SVID_CLK VCCGT24 VCCGT80
VCCOPC_AB62 VIDSCK
SOC_SVID_DAT SOC_SVID_CLK 66 J50
P62 D64 VCCGT25 VCC_VCCGTX
VCCOPC_P62 VIDSOUT J52
V62 VCCGT26
VCCOPC_V62 J53 AK42
For CPU2+3e SKU G20 +1.0VS_VCCSTG VCCGT27 VCCGTX_AK42
VCCSTG_G20 J55 AK43
H63 VCCGT28 VCCGTX_AK43
VCC_OPC_1P8_H63 J56 AK45
VCCGT29 VCCGTX_AK45
J58 AK46
G61 VCCGT30 VCCGTX_AK46
VCC_OPC_1P8_G61 J60 AK48
K48
VCCGT31 VCCGTX_AK48
AK50 U22F
C AC63
VCCOPC_SENSE U22,U22F K50
VCCGT32 VCCGTX_AK50
AK52 RC450 0R
C
AE63 VCCGT33 VCCGTX_AK52
VSSOPC_SENSE RC451 0R K52 AK53 R0402 5%
R0402 5% VCCGT34 VCCGTX_AK53
K53 AK55
AE62 VCCGT35 VCCGTX_AK55
VCCEOPIO_1 K55 AK56
AG62 VCCGT36 VCCGTX_AK56
VCCEOPIO_2 K56 AK58
VCCGT37 VCCGTX_AK58
K58 AK60
AL63 VCCGT38 VCCGTX_AK60
VCCEOPIO_SENSE K60 AK70
AJ62 VCCGT39 VCCGTX_AK70
VSSEOPIO_SENSE L62 AL43
12 OF 20 VCCGT40 VCCGTX_AL43
L63 AL46 6.0A
VCCGT41 VCCGTX_AL46
L64 AL50
VCCGT42 VCCGTX_AL50
SKL-U_BGA1356 L65 AL53
VCCGT43 VCCGTX_AL53
<BOM Structure> L66 AL56 For CPU2+3e SKU
VCCGT44 VCCGTX_AL56
L67 AL60
VCCGT45 VCCGTX_AL60
L68 AM48
VCCGT46 VCCGTX_AM48
L69 AM50
VCCGT47 VCCGTX_AM50
L70 AM52
VCCGT48 VCCGTX_AM52
L71 AM53
VCCGT49 VCCGTX_AM53
M62 AM56
VCCGT50 VCCGTX_AM56
+1.0V_VCCST N63 AM58
Place the PU VCCGT51 VCCGTX_AM58
N64 AU58
VCCGT52 VCCGTX_AU58
SVID ALERT resistors close to CPU N66
N67
VCCGT53 VCCGTX_AU63
AU63
BB57
VCCGT54 VCCGTX_BB57
N69 BB66
RC179 VCCGT55 VCCGTX_BB66
56R VCCGT_SENSE J70 AK62
1% 66 VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE1 VCCGTX_SENSE2
J69 AL61
R0402 66 VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE
I
13 OF 20
SOC_SVID_ALERT# RC180 220R
B SOC_SVID_ALERT#_R 66 Trace Length < 25 mils B
R0402 1% I SKL-U_BGA1356
(To VR) <BOM Structure>

+1.0V_VCCST
Place the PU
resistors close to CPU
SVID DATA RC181
100R 1%
R0402
I
+VCC_CORE +VCC_GT
SOC_SVID_DAT
SOC_SVID_DAT 66
RC423 RC425
(To VR) 100R 1% 100R 1%
R0402 R0402
I I
VCCSENSE VCCGT_SENSE
VSSSENSE VSSGT_SENSE

+VCC_CORE RC424 RC426


+VCC_CORE 15,23,67
+1.0VS_VCCSTG 100R 1% 100R 1%
+1.0VS_VCCSTG 3,10 R0402 R0402
+VCC_GT +VCC_GT 15,67 I I
+1.0V_VCCST +1.0V_VCCST 3,7,10,14,66

A A

12/2 Close to CPU

Project: 320S-13
Engineer: Jason
Size Title:KBL-U(10/12)Power,SVID Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 12 of 81
5 4 3 2 1
5 4 3 2 1

D D
UC1P SKL-U UC1Q SKL-U
Rev_0.53 Rev_0.53 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3 Rev_0.53
A5 AL65 AT63 BA49 F8 L18
VSS1 VSS71 VSS141 VSS209 VSS278 VSS319
A67 AL66 AT68 BA53 G10 L2
VSS2 VSS72 VSS142 VSS210 VSS279 VSS320
A70 AM13 AT71 BA57 G22 L20
VSS3 VSS73 VSS143 VSS211 VSS280 VSS321
AA2 AM21 AU10 BA6 G43 L4
VSS4 VSS74 VSS144 VSS212 VSS281 VSS322
AA4 AM25 AU15 BA62 G45 L8
VSS5 VSS75 VSS145 VSS213 VSS282 VSS323
AA65 AM27 AU20 BA66 G48 N10
VSS6 VSS76 VSS146 VSS214 VSS283 VSS324
AA68 AM43 AU32 BA71 G5 N13
VSS7 VSS77 VSS147 VSS215 VSS284 VSS325
AB15 AM45 AU38 BB18 G52 N19
VSS8 VSS78 VSS148 VSS216 VSS285 VSS326
AB16 AM46 AV1 BB26 G55 N21
VSS9 VSS79 VSS149 VSS217 VSS286 VSS327
AB18 AM55 AV68 BB30 G58 N6
VSS10 VSS80 VSS150 VSS218 VSS287 VSS328
AB21 AM60 AV69 BB34 G6 N65
VSS11 VSS81 VSS151 VSS219 VSS288 VSS329
AB8 AM61 AV70 BB38 G60 N68
VSS12 VSS82 VSS152 VSS220 VSS289 VSS330
AD13 AM68 AV71 BB43 G63 P17
VSS13 VSS83 VSS153 VSS221 VSS290 VSS331
AD16 AM71 AW10 BB55 G66 P19
VSS14 VSS84 VSS154 VSS222 VSS291 VSS332
AD19 AM8 AW12 BB6 H15 P20
VSS15 VSS85 VSS155 VSS223 VSS292 VSS333
AD20 AN20 AW14 BB60 H18 P21
VSS16 VSS86 VSS156 VSS224 VSS293 VSS334
AD21 AN23 AW16 BB64 H71 R13
VSS17 VSS87 VSS157 VSS225 VSS294 VSS335
AD62 AN28 AW18 BB67 J11 R6
VSS18 VSS88 VSS158 VSS226 VSS295 VSS336
AD8 AN30 AW21 BB70 J13 T15
VSS19 VSS89 VSS159 VSS227 VSS296 VSS337
AE64 AN32 AW23 C1 J25 T17
VSS20 VSS90 VSS160 VSS228 VSS297 VSS338
AE65 AN33 AW26 C25 J28 T18
VSS21 VSS91 VSS161 VSS229 VSS298 VSS339
AE66 AN35 AW28 C5 J32 T2
VSS22 VSS92 VSS162 VSS230 VSS299 VSS340
AE67 AN37 AW30 D10 J35 T21
VSS23 VSS93 VSS163 VSS231 VSS300 VSS341
AE68 AN38 AW32 D11 J38 T4
VSS24 VSS94 VSS164 VSS232 VSS301 VSS342
C AE69 AN40 AW34 D14 J42 U10 C
VSS25 VSS95 VSS165 VSS233 VSS302 VSS343
AF1 AN42 AW36 D18 J8 U63
VSS26 VSS96 VSS166 VSS234 VSS303 VSS344
AF10 AN58 AW38 D22 K16 U64
VSS27 VSS97 VSS167 VSS235 VSS304 VSS345
AF15 AN63 AW41 D25 K18 U66
VSS28 VSS98 VSS168 VSS236 VSS305 VSS346
AF17 AP10 AW43 D26 K22 U67
VSS29 VSS99 VSS169 VSS237 VSS306 VSS347
AF2 AP18 AW45 D30 K61 U69
VSS30 VSS100 VSS170 VSS238 VSS307 VSS348
AF4 AP20 AW47 D34 K63 U70
VSS31 VSS101 VSS171 VSS239 VSS308 VSS349
AF63 AP23 AW49 D39 K64 V16
VSS32 VSS102 VSS172 VSS240 VSS309 VSS350
AG16 AP28 AW51 D44 K65 V17
VSS33 VSS103 VSS173 VSS241 VSS310 VSS351
AG17 AP32 AW53 D45 K66 V18
VSS34 VSS104 VSS174 VSS242 VSS311 VSS352
AG18 AP35 AW55 D47 K67 W13
VSS35 VSS105 VSS175 VSS243 VSS312 VSS353
AG19 AP38 AW57 D48 K68 W6
VSS36 VSS106 VSS176 VSS244 VSS313 VSS354
AG20 AP42 AW6 D53 K70 W9
VSS37 VSS107 VSS177 VSS245 VSS314 VSS355
AG21 AP58 AW60 D58 K71 Y17
VSS38 VSS108 VSS178 VSS246 VSS315 VSS356
AG71 AP63 AW62 D6 L11 Y19
VSS39 VSS109 VSS179 VSS247 VSS316 VSS357
AH13 AP68 AW64 D62 L16 Y20
VSS40 VSS110 VSS180 VSS248 VSS317 VSS358
AH6 AP70 AW66 D66 L17 Y21
VSS41 VSS111 VSS181 VSS249 VSS318 VSS359
AH63 AR11 AW8 D69
VSS42 VSS112 VSS182 VSS250
AH64 AR15 AY66 E11
VSS43 VSS113 VSS183 VSS251 18 OF 20
AH67 AR16 B10 E15
VSS44 VSS114 VSS184 VSS252
AJ15 AR20 B14 E18
VSS45 VSS115 VSS185 VSS253
AJ18 AR23 B18 E21
VSS46 VSS116 VSS186 VSS254 SKL-U_BGA1356
AJ20 AR28 B22 E46
VSS47 VSS117 VSS187 VSS255 <BOM Structure>
AJ4 AR35 B30 E50
VSS48 VSS118 VSS188 VSS256
AK11 AR42 B34 E53
VSS49 VSS119 VSS189 VSS257
AK16 AR43 B39 E56
VSS50 VSS120 VSS190 VSS258
AK18 AR45 B44 E6
VSS51 VSS121 VSS191 VSS259
AK21 AR46 B48 E65
VSS52 VSS122 VSS192 VSS260
AK22 AR48 B53 E71
B VSS53 VSS123 VSS193 VSS261 B
AK27 AR5 B58 F1
VSS54 VSS124 VSS194 VSS262
AK63 AR50 B62 F13
VSS55 VSS125 VSS195 VSS263
AK68 AR52 B66 F2
VSS56 VSS126 VSS196 VSS264
AK69 AR53 B71 F22
VSS57 VSS127 VSS197 VSS265
AK8 AR55 BA1 F23
VSS58 VSS128 VSS198 VSS266
AL2 AR58 BA10 F27
VSS59 VSS129 VSS199 VSS267
AL28 AR63 BA14 F28
VSS60 VSS130 VSS200 VSS268
AL32 AR8 BA18 F32
VSS61 VSS131 VSS201 VSS269
AL35 AT2 BA2 F33
VSS62 VSS132 VSS202 VSS270
AL38 AT20 BA23 F35
VSS63 VSS133 VSS203 VSS271
AL4 AT23 BA28 F37
VSS64 VSS134 VSS204 VSS272
AL45 AT28 BA32 F38
VSS65 VSS135 VSS205 VSS273
AL48 AT35 BA36 F4
VSS66 VSS136 VSS206 VSS274
AL52 AT4 F68 F40
VSS67 VSS137 VSS207 VSS275
AL55 AT42 BA45 F42
VSS68 VSS138 VSS208 VSS276
AL58 AT56 BA41
VSS69 VSS139 VSS277
AL64 AT58
VSS70 VSS140
16 OF 20 17 OF 20

SKL-U_BGA1356 SKL-U_BGA1356
<BOM Structure> <BOM Structure>

A A

Project: 320S-13
Engineer: Jason
Size Title:KBL-U(11/12)GND Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 13 of 81

5 4 3 2 1
5 4 3 2 1

+1.0VS_VCCIO
D D

R9760
1K UC1S SKL-U
5%
R0402_N
Rev_0.53
RESERVED SIGNALS-1
I
CFG_0 E68 BB68
CFG[0] RSVD_TP_BB68
B67 BB69
CFG[1] RSVD_TP_BB69
D65
CFG[2]
D67 AK13
CFG[3] RSVD_TP_AK13
R1049 1K CFG_4 E70 AK12
R0402_N 5% I CFG[4] RSVD_TP_AK12
C68
CFG[5]
D68 BB2
CFG[6] RSVD_BB2
C67 BA3
CFG[7] RSVD_BA3
F71
CFG[8]
G69
CFG[9]
F70 AU5
CFG[10] TP5
G68 AT5
CFG[11] TP6
H70
CFG[12]
G71
CFG[13]
H69 D5
CFG[14] RSVD_D5
G70 D4
CFG[15] RSVD_D4
B2 UC1T SKL-U
RSVD_B2
E63 C2
CFG[16] RSVD_C2 Rev_0.53
F63 SPARE
CFG[17]
B3
RSVD_B3
E66 A3 AW69 F6
CFG[18] RSVD_A3 RSVD_AW69 RSVD_F6
F66 AW68 E3XTAL_24M_SOC_IN_U42
CFG[19] RSVD_AW68 RSVD_E3
C AW1 AU56 C11 C
RSVD_AW1 RSVD_AU56 RSVD_C11
R1068 49.9R NOA_RCOMP E60 AW48 B11
CFG_RCOMP RSVD_AW48 RSVD_B11
R0402 1% I E1 XTAL_24M_SOC_OUT_U42 C7 A11
RSVD_E1 RSVD_C7 RSVD_A11
ITP_PMODE E8 E2 U12 D12
ITP_PMODE RSVD_E2 RSVD_U12 RSVD_D12
U11 C12
RSVD_U11 RSVD_C12
AY2 BA4 H11 F52
+V1P0A_VCCPRIM RSVD_AY2 RSVD_BA4 RSVD_H11 RSVD_F52
AY1 BB4
RSVD_AY1 RSVD_BB4 20 OF 20
R1067 1K
D1 A4
RSVD_D1 RSVD_A4
D3 C4
R0402_N 5% I RSVD_D3 RSVD_C4 SKL-U_BGA1356
K46 BB5 <BOM Structure>
RSVD_K46 TP4
K45
RSVD_K45
A69
RSVD_A69
AL25 B69
RSVD_AL25 RSVD_B69
AL27
RSVD_AL27
AY3 RC182 0R XTAL_24M_SOC_IN_U42
+1.0V_PRIM +V1P0A_VCCPRIM RSVD_AY3 R0402 5% I
C71
RSVD_C71
B70 D71
RSVD_B70 RSVD_D71 XTAL_24M_SOC_OUT_U42 R10002 1M
C70
RC427 0R F60
RSVD_C70 R0402 5% U42
R0402 5% I RSVD_F60
C54
RSVD_C54
A52 D54
RSVD_A52 RSVD_D54 Y1002
2 GND
1
BA70 AY4 Y2 Y1
RSVD_TP_BA70 TP1
BA68 BB3
RSVD_TP_BA68 TP2 3 4
Y3 GND Y4

J71 AY71 RC183 0R


RSVD_J71 VSS_AY71 R0402 5% I 24MHZ 10PPM
J68 AR56
B RSVD_J68 ZVM# C9977 X4S32X25 C9976 B
8.2pF 50V 0.1pF U42 8.2pF 50V 0.1pF
F65 AW71
VSS_F65 RSVD_TP_AW71 NPO NPO
G65 AW70
VSS_G65 RSVD_TP_AW70 C0402_N C0402_N
+1.0V_VCCST
F61 AP56 U42 U42
RSVD_F61 MSM#
E61 C64 SKL_CNL# RC184 100K
RSVD_E61 PROC_SELECT# R0402 5% I
19 OF 20

SKL-U_BGA1356 Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0


<BOM Structure>
For 2+3e Solution
PM_ZVM#
+1.0VS_VCCIO +1.0VS_VCCIO 3,10
PM_MSM#
+V1P0A_VCCPRIM +V1P0A_VCCPRIM 7
+1.0V_PRIM +1.0V_PRIM 10,11,63,75
+1.0V_VCCST +1.0V_VCCST 3,7,10,12,66

A A

Display Port Presence Strap

1 : Disabled; No Physical Display Port


CFG4 attached to Embedded Display Port Project: 320S-13
0 : Enabled; An external Display Port device is Engineer: Jason
connected to the Embedded Display Port Size Title:KBL-U(12/12)RSVD Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 14 of 81

5 4 3 2 1
5 4 3 2 1

+VCC_CORE

12/30 check PDG


CC173 CC174 CC175 CC176 & 220uF pull power side
47uF 4V 20% 47uF 4V 20% 47uF 4V 20% 47uF 4V 20%
C0805_N C0805_N C0805_N C0805_N
X5R X5R X5R X5R
I I I I

+VCC_CORE
47uF x8 change 47uF x4
D
CC182
X5R
CC183
X5R
CC184
22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
X5R
CC186 CC187 CC188 CC189 CC190 CC362 CC363 CC364 CC365 CC366 CC367 CC368 CC369
22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
22uF x9 cgange 22uF x17 D
C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N
I I I I I I I I I I I I I I I I
10uF x15
1uF x35
CC193 CC194 CC195 CC196 CC197 CC198 CC199 CC200 CC201 CC202 CC203 CC204 CC205 CC206 CC207
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
I I I I I I I I I I I I I I I

CC306 CC307 CC308 CC309 CC310 CC311 CC312 CC313 CC314 CC315 CC316 CC317 CC318 CC319 CC320 CC321 CC322 CC323
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
I I I I I I I I I I I I I I I I I I

CC333 CC334 CC335 CC336 CC337 CC338 CC339 CC340 CC324 CC325 CC326 CC327 CC328 CC329 CC330 CC331 CC332
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
I I I I I I I I I I I I I I I I I

C C

12/30 check PDG


& 220uF pull power side

+VCC_GT
+VCC_GT +VCC_GT 47uF x3 change 47uF x0
CC243 CC244 CC245 CC246 CC247 CC248 CC249 CC370 CC371 CC372 CC373 CC374 CC375 CC381 CC382 CC383 CC384
22uF x7 cgange 22uF x13
22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
X5R
C0603_N
10uF x12
I I I I I I I I I I I I I I I I I

1uF x14
1/27 Intel Add

CC257 CC258 CC259 CC260 CC261 CC262 CC263 CC264 CC265 CC266 CC304 CC305
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
I I I I I I I I I I I I

B B
+VCC_GT

CC341 CC342 CC343 CC344 CC345 CC346 CC347 CC348 CC349 CC350 CC351 CC352 CC353 CC354 CC390 CC391
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 22uF 6.3V 20% 22uF 6.3V 20%
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0603_N C0603_N
I I I I I I I I I I I I I I NI NI

3/14 Power:add CC390,CC391 reserved

+VCC_SA
+VCC_SA 12/30 check PDG

CC295 CC296
47uF x2
47uF 4V 20%
C0805_N
X5R
47uF 4V 20%
C0805_N
X5R
10uF x13
1uF x7
I I

CC282 CC283 CC284 CC285 CC286 CC287 CC288 CC289 CC290 CC291 CC292 CC293 CC294
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
I I I I I I I I I I I I I
A A

+VCC_CORE +VCC_CORE 12,23,67


+VCC_GT +VCC_GT 12,67
+VCC_SA +VCC_SA 10,67
CC355 CC356 CC357 CC358 CC359 CC360 CC361
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X5R X5R X5R X5R X5R X5R X5R
C0201 C0201 C0201 C0201 C0201 C0201 C0201
I I I I I I I
Project: 320S-13
Engineer: Jason
Size Title:SOC (DECOUPLING) Rev
C V01
Date: Monday, May 22, 2017 Sheet 15 of 81

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
B V01
Date: Monday, April 10, 2017 Sheet 16 of 81

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
B V01
Date: Monday, April 10, 2017 Sheet 17 of 81
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 18 of 81

5 4 3 2 1
5 4 3 2 1

UM2A +V1P2U_VDDQ
VDD B3
+V1P2U_VDDQ VDD B9
UM1A VDD D1 +V1P2U_VDDQ
VDD B3 VDD J1
VDD B9 VDD J9 UM2B
VDD D1 UM1B M_A_A0 P3 A0 VDD L1 G2 DQ0
M_A_A1 4 M_A_DQ<23>
VDD J1
4 M_A_DQ<14> G2 DQ0 P7 A1 VDD L9
4 M_A_DQ<17> F7 DQ1 RM10
VDD J9 F7 DQ1 M_A_A2 R3 A2 VDD R1 H3 DQ2 1.8K
4 M_A_DQ<13> M_A_A3 4 M_A_DQ<22> 1%
P3 A0 VDD L1 H3 DQ2 N7 A3 VDD T9 H7 DQ3
4 M_A_A0 4 M_A_DQ<11> M_A_A4 4 M_A_DQ<20> R0402_N
P7 A1 VDD L9 H7 DQ3 N3 A4 VDD G7 H2 DQ4
4 M_A_A1 4 M_A_DQ<8> M_A_A5 4 M_A_DQ<18> I
R3 A2 VDD R1 H2 DQ4 P8 A5 H8 DQ5
4 M_A_A2 4 M_A_DQ<10> M_A_A6 4 M_A_DQ<16> 1% VREFCA_CHA
N7 A3 VDD T9
4 M_A_DQ<12> H8 DQ5 P2 A6 4 M_A_DQ<19> J3 DQ6 L RM9 2R7
4 M_A_A3 M_A_A7 4 +V_DDR_CA_VREF I R0402_N
N3 G7 J3 R8 A1 J7
4 M_A_A4
P8
A4
A5
VDD 4 M_A_DQ<15>
J7
DQ6
DQ7
L M_A_A8 R2
A7
A8
VDDQ
VDDQ A9
4 M_A_DQ<21> DQ7
4 M_A_A5 4 M_A_DQ<9> M_A_A9
P2 A6 R7 A9 VDDQ C1
+V1P2U_VDDQ E7 DQM CM6 RM11
4 M_A_A6 M_A_A10_AP
R8 A7 VDDQ A1
+V1P2U_VDDQ
E7 DQM M3 A10/AP VDDQ D9 G3 0.022uF 16V 10% 1.8K
4 M_A_A7 M_A_A11 4 M_A_DQS_DP<2> DQS X7R 1%
R2 A8 VDDQ A9 G3 T2 A11 VDDQ F2 F3
D 4 M_A_A8 4 M_A_DQS_DP<1> DQS
M_A_A12 4 M_A_DQS_DN<2> DQS# C0402_N R0402_N D
R7 A9 VDDQ C1 F3 M7 A12/BC VDDQ F8
4 M_A_A9 4 M_A_DQS_DN<1> DQS#
M_A_A13 I I
M3 A10/AP VDDQ D9 T8 A13 VDDQ G1 MT40A512M16HA-083E:A
4 M_A_A10_AP M_A_A14_WE_N bga96_p8mm_9p1x14p1
T2 A11 VDDQ F2 MT40A512M16HA-083E:A L2 A14/WE VDDQ G9
4 M_A_A11 bga96_p8mm_9p1x14p1 M_A_A15_CAS_N
M7 A12/BC VDDQ F8 M8 A15/CAS VDDQ J2 I RM12
4 M_A_A12 M_A_A16_RAS_N
T8 A13 VDDQ G1 I L8 A16/RAS VDDQ J8 24.9R
4 M_A_A13 +V2P5U_VPP R0402
L2 A14/WE VDDQ G9
4 M_A_A14_WE_N 1%
M8 A15/CAS VDDQ J2
4 M_A_A15_CAS_N I
L8 A16/RAS VDDQ J8 VPP B1
4 M_A_A16_RAS_N +V2P5U_VPP
VPP R9
UM2C
B1 M_A_BA0 N2 BA0 A3 DQ0
VPP
M_A_BA1 4 M_A_DQ<26>
R9 N8 BA1 B8 DQ1
VPP 4 M_A_DQ<29>
UM1C 4 M_A_DQ<31> C3 DQ2
N2 BA0 A3 DQ0 VSSQ A2 C7 DQ3
4 M_A_BA0 4 M_A_DQ<6> M_A_DIM0_CKE0 4 M_A_DQ<24>
N8 BA1 B8 DQ1 K2 CKE/CKE0 VSSQ A8 C2 DQ4
4 M_A_BA1 4 M_A_DQ<0> M_A_DIM0_CK_DDR0_DP K7 4 M_A_DQ<30>
C3 DQ2 VSSQ C9 C8 DQ5
4 M_A_DQ<3> M_A_DIM0_CK_DDR0_DN K8 CLK 4 M_A_DQ<28>
A2 C7 D2 D3
K2 CKE/CKE0
VSSQ
VSSQ A8
4 M_A_DQ<5>
C2
DQ3
DQ4
CLK#
VSSQ
VSSQ D8
4 M_A_DQ<27>
D7
DQ6
DQ7
U
4 M_A_DIM0_CKE0 4 M_A_DQ<2> 4 M_A_DQ<25>
K7 VSSQ C9 C8 DQ5 VSSQ E3
4 M_A_DIM0_CK_DDR0_DP CLK 4 M_A_DQ<4>
K8 D2 D3 E8 E2
4 M_A_DIM0_CK_DDR0_DN CLK#
VSSQ
VSSQ D8
4 M_A_DQ<7>
D7
DQ6
DQ7
U M_A_DIM0_ODT0 K3 ODT
VSSQ
VSSQ H1
+V1P2U_VDDQ
B7
DQM
4 M_A_DQ<1> 4 M_A_DQS_DP<3> DQS
VSSQ E3 VSSQ H9 A7
4 M_A_DQS_DN<3> DQS#
+V0.6S_VTT
VSSQ E8 E2 DQM VSSQ F1
+V1P2U_VDDQ
K3 ODT VSSQ H1 B7 RM6 240R F9 ZQ MT40A512M16HA-083E:A
4 M_A_DIM0_ODT0 4 M_A_DQS_DP<0> DQS R0402_N 1% I bga96_p8mm_9p1x14p1
VSSQ H9 A7
4 M_A_DQS_DN<0> DQS#
M_A_BG0 I M_A_DIM0_CK_DDR0_DP RM13 R0402_N 1% I
VSSQ F1 M2 BG0 VSS B2 36R
RM5 240R F9 ZQ MT40A512M16HA-083E:A VSS E1
R0402_N 1% I bga96_p8mm_9p1x14p1 N9 E9 RM81 0R
TEN VSS C10036
M2 B2 G8 R0402_N 5% I
4 M_A_BG0 BG0 VSS I VSS 3300pf 25V 10%
VSS E1 M_A_ACT_N L3 VSS K1 3/20 U22 add Cap
ACT# X7R
N9 E9 RM79 0R K9
TEN VSS VSS C0402_N U22
VSS G8 R0402_N 5% I
VSS M9 M_A_BG1
L3 VSS K1 DDR4_DRAMRST_R P1 RESET# VSS N1 M_A_DIM0_CK_DDR0_DN RM14 36R R0402_N 1% I
4 M_A_ACT_N ACT#
VSS K9 VSS T1
VSS M9 M_A_BG1 DDR0_A_PARITY T3 PAR 3/16 Change to 36 ohm
DDR4_DRAMRST_R P1 RESET# VSS N1 M_A_A0 RM15 36R R0402_N 1% I
VSS T1 M_A_A1 RM16 36R R0402_N 1% I
C T3 PAR 1/19 Inte:check samsung DDP package,reserved. M_A_A2 RM17 36R R0402_N 1% I C
4 DDR0_A_PARITY M_A_DIM0_CS0_N M_A_A3 R0402_N 1% I
L7 CS# RM18 36R
M_A_A4 RM19 36R R0402_N 1% I
DDR0_A_ALERT_N P9 M_A_A5 RM20 36R R0402_N 1% I
ALERT#
L7 CS# NC T7 M_A_A6 RM21 36R R0402_N 1% I
4 M_A_DIM0_CS0_N M_A_A7 R0402_N 1% I
RM22 36R
P9 M_A_A8 RM23 36R R0402_N 1% I
4 DDR0_A_ALERT_N ALERT#
M_A_A9 R0402_N 1% I
NC T7 RM24 36R
VREFCA M1 VREFCA_CHA M_A_A10_AP RM25 36R R0402_N 1% I
M_A_A11 RM26 36R R0402_N 1% I
MT40A512M16HA-083E:A CM3 M_A_A12 RM27 36R R0402_N 1% I
VREFCA M1 VREFCA_CHA bga96_p8mm_9p1x14p1 47nF 16V 10% M_A_A13 RM28 36R R0402_N 1% I
I
X7R M_A_A14_WE_N RM29 36R R0402_N 1% I
MT40A512M16HA-083E:A CM2 C0402_N M_A_A15_CAS_N RM30 36R R0402_N 1% I
bga96_p8mm_9p1x14p1 47nF 16V 10% I M_A_A16_RAS_N RM31 36R R0402_N 1% I
X7R
I
C0402_N
I M_A_BA0 RM32 36R R0402_N 1% I
M_A_BA1 RM33 36R R0402_N 1% I
M_A_DIM0_CKE0 RM34 36R R0402_N 1% I
+V1P2U_VDDQ +V1P2U_VDDQ M_A_DIM0_ODT0 RM35 36R R0402_N 1% I
UM3A UM4A M_A_BG0 RM36 36R R0402_N 1% I
VDD B3 VDD B3 M_A_ACT_N RM37 36R R0402_N 1% I

VDD B9 VDD B9 DDR0_A_PARITY RM38 36R R0402_N 1% I


VDD D1 UM3B VDD D1 M_A_DIM0_CS0_N RM39 36R R0402_N 1% I
VDD J1 G2 DQ0 VDD J1 UM4B M_A_BG1 RM95 36R R0402_N 1% NI
4 M_A_DQ<58> 4 M_A_BG1 0R R0402_N 5% I
VDD J9
4 M_A_DQ<56> F7 DQ1 VDD J9
4 M_A_DQ<50> G2 DQ0 RM99
M_A_A0 P3 A0 VDD L1 H3 DQ2 M_A_A0 P3 A0 VDD L1 F7 DQ1
M_A_A1 4 M_A_DQ<63> M_A_A1 4 M_A_DQ<48>
P7 A1 VDD L9 H7 DQ3 P7 A1 VDD L9 H3 DQ2
M_A_A2 4 M_A_DQ<57> M_A_A2 4 M_A_DQ<55>
R3 A2 VDD R1 H2 DQ4 R3 A2 VDD R1 H7 DQ3
M_A_A3 4 M_A_DQ<62> M_A_A3 4 M_A_DQ<49>
N7 A3 VDD T9 H8 DQ5 N7 A3 VDD T9 H2 DQ4
M_A_A4 4 M_A_DQ<60> M_A_A4 4 M_A_DQ<54>
N3 G7 J3 N3 G7 H8
M_A_A5 P8
A4 VDD 4 M_A_DQ<59>
J7
DQ6 L M_A_A5 P8
A4 VDD 4 M_A_DQ<52>
J3
DQ5
+V1P2U_VDDQ
M_A_A6 P2
A5
A6
4 M_A_DQ<61> DQ7
M_A_A6 P2
A5
A6
4 M_A_DQ<51>
J7
DQ6
DQ7
L
M_A_A7 M_A_A7 4 M_A_DQ<53>
R8 A7 VDDQ A1 E7 DQM R8 A7 VDDQ A1
M_A_A8 +V1P2U_VDDQ M_A_A8 DDR0_A_ALERT_N 1% R0402_N I
R2 A8 VDDQ A9 G3 R2 A8 VDDQ A9
+V1P2U_VDDQ E7 DQM RM40 49.9R
M_A_A9 4 M_A_DQS_DP<7> DQS
M_A_A9
R7 A9 VDDQ C1 F3 R7 A9 VDDQ C1 G3
M_A_A10_AP 4 M_A_DQS_DN<7> DQS#
M_A_A10_AP 4 M_A_DQS_DP<6> DQS
M3 A10/AP VDDQ D9 M3 A10/AP VDDQ D9 F3
B M_A_A11 M_A_A11 4 M_A_DQS_DN<6> DQS# B
T2 A11 VDDQ F2 MT40A512M16HA-083E:A T2 A11 VDDQ F2
M_A_A12 M7 A12/BC VDDQ F8 bga96_p8mm_9p1x14p1 M_A_A12 M7 A12/BC VDDQ F8 MT40A512M16HA-083E:A
M_A_A13 T8 A13 VDDQ G1 I M_A_A13 T8 A13 VDDQ G1 bga96_p8mm_9p1x14p1
M_A_A14_WE_N L2 A14/WE VDDQ G9 M_A_A14_WE_N L2 A14/WE VDDQ G9 I +V1P2U_VDDQ
M_A_A15_CAS_N M8 A15/CAS VDDQ J2 M_A_A15_CAS_N M8 A15/CAS VDDQ J2
M_A_A16_RAS_N L8 A16/RAS VDDQ J8 M_A_A16_RAS_N L8 A16/RAS VDDQ J8
+V2P5U_VPP +V2P5U_VPP RM41
470R
B1 B1 5%
VPP VPP
R9 UM3C R9 UM4C R0402_N
VPP VPP
A3 A3 I
4 M_A_DQ<46> DQ0 4 M_A_DQ<38> DQ0 RM42
M_A_BA0 N2 BA0 B8 DQ1 M_A_BA0 N2 BA0 B8 DQ1
M_A_BA1 4 M_A_DQ<40> M_A_BA1 4 M_A_DQ<36> DDR4_DRAMRST_R
N8 BA1 C3 DQ2 N8 BA1 C3 DQ2
4 M_A_DQ<47> 4 M_A_DQ<39> 4 DDR4_DRAMRST_N DDR4_DRAMRST_R 20
C7 DQ3 C7 DQ3
4 M_A_DQ<45> 4 M_A_DQ<32>
VSSQ A2 C2 DQ4 VSSQ A2 C2 DQ4
M_A_DIM0_CKE0 4 M_A_DQ<42> M_A_DIM0_CKE0 4 M_A_DQ<34> 0R
K2 CKE/CKE0 VSSQ A8
4 M_A_DQ<41> C8 DQ5 K2 CKE/CKE0 VSSQ A8
4 M_A_DQ<37> C8 DQ5 CM7
M_A_DIM0_CK_DDR0_DP K7 C9 D3 M_A_DIM0_CK_DDR0_DP K7 C9 D3 I 0.1uF 10V 10%
M_A_DIM0_CK_DDR0_DN K8 CLK VSSQ
VSSQ D2
4 M_A_DQ<43>
D7
DQ6
DQ7
U M_A_DIM0_CK_DDR0_DN K8 CLK VSSQ
VSSQ D2
4 M_A_DQ<35>
D7
DQ6
DQ7
U R0402 C0402
CLK# 4 M_A_DQ<44> CLK# 4 M_A_DQ<33> X5R
VSSQ D8 VSSQ D8 5%
E3 E2 E3 E2 NI
VSSQ +V1P2U_VDDQ DQM VSSQ +V1P2U_VDDQ DQM
VSSQ E8 B7 VSSQ E8 B7
M_A_DIM0_ODT0 ODT
4 M_A_DQS_DP<5> DQS
M_A_DIM0_ODT0 ODT
4 M_A_DQS_DP<4> DQS
K3 VSSQ H1 A7 K3 VSSQ H1 A7
4 M_A_DQS_DN<5> DQS# 4 M_A_DQS_DN<4> DQS#
VSSQ H9 VSSQ H9
VSSQ F1 MT40A512M16HA-083E:A VSSQ F1 MT40A512M16HA-083E:A
RM7 240R F9 ZQ bga96_p8mm_9p1x14p1 RM8 240R F9 ZQ bga96_p8mm_9p1x14p1
R0402_N 1% I R0402_N 1% I
I I
M_A_BG0 M2 BG0 VSS B2 M_A_BG0 M2 BG0 VSS B2
VSS E1 VSS E1
N9 E9 RM83 0R N9 E9 RM85 0R
TEN VSS TEN VSS
G8 R0402_N 5% I G8 R0402_N 5% I
VSS VSS
M_A_ACT_N L3 VSS K1 M_A_ACT_N L3 VSS K1
ACT# ACT#
VSS K9 VSS K9
VSS M9 M_A_BG1 VSS M9 M_A_BG1
DDR4_DRAMRST_R P1 RESET# VSS N1 DDR4_DRAMRST_R P1 RESET# VSS N1
VSS T1 VSS T1
DDR0_A_PARITY T3 PAR DDR0_A_PARITY T3 PAR

A A

M_A_DIM0_CS0_N L7 CS# M_A_DIM0_CS0_N L7 CS#

DDR0_A_ALERT_N DDR0_A_ALERT_N +V1P2U_VDDQ +V1P2U_VDDQ 4,10,20,21,61


P9 P9
ALERT# ALERT# +V2P5U_VPP +V2P5U_VPP 20,21,62
NC T7 NC T7
+V0.6S_VTT +V0.6S_VTT 20,21,61

VREFCA M1 VREFCA_CHA VREFCA M1 VREFCA_CHA

MT40A512M16HA-083E:A CM4 MT40A512M16HA-083E:A CM5 Project: 320S-13


bga96_p8mm_9p1x14p1 47nF 16V 10% bga96_p8mm_9p1x14p1 47nF 16V 10%
I
X7R
C0402_N
I
X7R
C0402_N
Engineer: Jason
I I Size Title:DDR4_CHA Rev
C V01
Date: Monday, April 10, 2017 Sheet 19 of 81
5 4 3 2 1
5 4 3 2 1

UM5A +V1P2U_VDDQ
UM6A
VDD B3 +V1P2U_VDDQ
VDD B9 VDD B3
VDD D1 VDD B9
VDD J1 UM5B VDD D1 UM6B
VDD J9 VDD J1
P3 A0 VDD L1 G2 DQ0 VDD J9 G2 DQ0
4 M_B_A0 4 M_B_DQ<14> M_B_A0 4 M_B_DQ<23>
P7 A1 VDD L9 F7 DQ1 P3 A0 VDD L1 F7 DQ1
4 M_B_A1 4 M_B_DQ<9> M_B_A1 4 M_B_DQ<16>
R3 A2 VDD R1 H3 DQ2 P7 A1 VDD L9 H3 DQ2
4 M_B_A2 4 M_B_DQ<11> M_B_A2 4 M_B_DQ<18>
N7 A3 VDD T9 H7 DQ3 R3 A2 VDD R1 H7 DQ3
4 M_B_A3 4 M_B_DQ<12> M_B_A3 4 M_B_DQ<17>
N3 A4 VDD G7 H2 DQ4 N7 A3 VDD T9 H2 DQ4
4 M_B_A4 4 M_B_DQ<15> M_B_A4 4 M_B_DQ<19> +V1P2U_VDDQ
P8 A5 H8 DQ5 N3 A4 VDD G7 H8 DQ5
4 M_B_A5 4 M_B_DQ<8> M_B_A5 4 M_B_DQ<20>
P2 J3 P8 J3
4 M_B_A6
R8
A6
A7 VDDQ A1
4 M_B_DQ<10>
J7
DQ6
DQ7
L M_B_A6 P2
A5
A6
4 M_B_DQ<22>
J7
DQ6
DQ7
L
4 M_B_A7 4 M_B_DQ<13> M_B_A7 4 M_B_DQ<21>
R2 A8 VDDQ A9 R8 A7 VDDQ A1
4 M_B_A8 M_B_A8
R7 A9 VDDQ C1
+V1P2U_VDDQ
E7 DQM R2 A8 VDDQ A9
+V1P2U_VDDQ
E7 DQM RM48
4 M_B_A9 M_B_A9
M3 A10/AP VDDQ D9 G3 R7 A9 VDDQ C1 G3 1.8K
D 4 M_B_A10_AP 4 M_B_DQS_DP<1> DQS
M_B_A10_AP 4 M_B_DQS_DP<2> DQS 1% D
T2 A11 VDDQ F2 F3 M3 A10/AP VDDQ D9 F3
4 M_B_A11 4 M_B_DQS_DN<1> DQS#
M_B_A11 4 M_B_DQS_DN<2> DQS# R0402_N
M7 A12/BC VDDQ F8 T2 A11 VDDQ F2
4 M_B_A12 M_B_A12 I
T8 A13 VDDQ G1 MT40A512M16HA-083E:A M7 A12/BC VDDQ F8
4 M_B_A13 M_B_A13 MT40A512M16HA-083E:A VREFCA_CHB
L2 A14/WE VDDQ G9 bga96_p8mm_9p1x14p1 T8 A13 VDDQ G1 RM47 2R7 1%
4 M_B_A14_WE_N M_B_A14_WE_N bga96_p8mm_9p1x14p1 4 +V_DDR_VREFDQ02_CHB I R0402_N
M8 A15/CAS VDDQ J2 I L2 A14/WE VDDQ G9
4 M_B_A15_CAS_N M_B_A15_CAS_N
L8 A16/RAS VDDQ J8 M8 A15/CAS VDDQ J2 I
4 M_B_A16_RAS_N +V2P5U_VPP M_B_A16_RAS_N L8 A16/RAS VDDQ J8 CM12 RM49
+V2P5U_VPP 0.022uF 16V 10% 1.8K
B1 UM5C X7R 1%
VPP
R9 B1 UM6C C0402_N R0402_N
VPP VPP
A3 R9 I I
4 M_B_DQ<7> DQ0 VPP
N2 BA0 B8 DQ1 A3 DQ0
4 M_B_BA0 4 M_B_DQ<4> M_B_BA0 4 M_B_DQ<38>
N8 BA1 4 M_B_DQ<3> C3 DQ2 N2 BA0 4 M_B_DQ<37> B8 DQ1 RM50
4 M_B_BA1 M_B_BA1
4 M_B_DQ<1>
C7 DQ3 N8 BA1 4 M_B_DQ<35>
C3 DQ2 24.9R
A2 C2 C7 R0402
VSSQ 4 M_B_DQ<6> DQ4 4 M_B_DQ<32> DQ3
K2 A8 C8 A2 C2 1%
4 M_B_DIM0_CKE0
K7
CKE/CKE0 VSSQ
C9
4 M_B_DQ<5>
D3
DQ5 U M_B_DIM0_CKE0 K2
VSSQ
A8
4 M_B_DQ<39>
C8
DQ4
I
4 M_B_DIM0_CK_DDR0_DP
K8
CLK VSSQ
VSSQ D2
4 M_B_DQ<2>
D7
DQ6
DQ7 M_B_DIM0_CK_DDR0_DP K7
CKE/CKE0 VSSQ
VSSQ C9
4 M_B_DQ<36>
D3
DQ5
DQ6
U
4 M_B_DIM0_CK_DDR0_DN CLK# 4 M_B_DQ<0> M_B_DIM0_CK_DDR0_DN K8 CLK 4 M_B_DQ<33>
VSSQ D8 VSSQ D2 D7 DQ7
CLK# 4 M_B_DQ<34>
VSSQ E3 E2 DQM VSSQ D8
+V1P2U_VDDQ
VSSQ E8 B7 VSSQ E3 E2 DQM
4 M_B_DQS_DP<0> DQS +V1P2U_VDDQ
K3 ODT VSSQ H1 A7 VSSQ E8 B7
4 M_B_DIM0_ODT0 4 M_B_DQS_DN<0> DQS#
M_B_DIM0_ODT0 ODT
4 M_B_DQS_DP<4> DQS
VSSQ H9 K3 VSSQ H1 A7
4 M_B_DQS_DN<4> DQS#
VSSQ F1 MT40A512M16HA-083E:A VSSQ H9
RM43 240R F9 ZQ bga96_p8mm_9p1x14p1 VSSQ F1 MT40A512M16HA-083E:A
R0402_N 1% I RM44 240R F9 ZQ bga96_p8mm_9p1x14p1
I
M2 B2 R0402_N 1% I
4 M_B_BG0 BG0 VSS I
VSS E1 M_B_BG0 M2 BG0 VSS B2
N9 E9 RM87 0R E1
TEN VSS VSS
G8 R0402_N 5% I N9 E9 RM89 0R
VSS TEN VSS
L3 K1 G8 R0402_N 5% I
4 M_B_ACT_N ACT# VSS VSS
VSS K9 M_B_ACT_N L3 VSS K1
ACT#
VSS M9 M_B_BG1 VSS K9
P1 RESET# VSS N1 VSS M9 M_B_BG1
19 DDR4_DRAMRST_R DDR4_DRAMRST_R
VSS T1 P1 RESET# VSS N1
T3 PAR 1/19 Inte:check samsung DDP package,reserved. VSS T1
4 DDR1_B_PARITY DDR1_B_PARITY T3 PAR
C C

L7 CS#
4 M_B_DIM0_CS0_N M_B_DIM0_CS0_N L7 CS#
P9
4 DDR1_B_ALERT_N ALERT#
DDR1_B_ALERT_N
NC T7 P9 ALERT#
NC T7

VREFCA M1 VREFCA_CHB
VREFCA M1 VREFCA_CHB
CM8
MT40A512M16HA-083E:A 47nF 16V 10% CM9 +V0.6S_VTT
bga96_p8mm_9p1x14p1 X7R MT40A512M16HA-083E:A 47nF 16V 10%
I C0402_N bga96_p8mm_9p1x14p1 X7R
I I C0402_N
I

M_B_DIM0_CK_DDR0_DP RM51 36R R0402_N 1% I

UM7A +V1P2U_VDDQ
+V1P2U_VDDQ C10037
UM8A
3300pf 25V 10%
VDD B3 3/20 U22 add Cap X7R
VDD B9 UM7B VDD B3 C0402_N U22
VDD D1 VDD B9
VDD J1 G2 DQ0 VDD D1 UM8B M_B_DIM0_CK_DDR0_DN RM52 36R R0402_N 1% I
4 M_B_DQ<46>
VDD J9 F7 DQ1 VDD J1
M_B_A0 4 M_B_DQ<45>
P3 A0 VDD L1
4 M_B_DQ<43> H3 DQ2 VDD J9
4 M_B_DQ<55> G2 DQ0 3/16 Change to 36 ohm
M_B_A1 P7 A1 VDD L9 H7 DQ3 M_B_A0 P3 A0 VDD L1 F7 DQ1 M_B_A0 RM53 36R R0402_N 1% I
M_B_A2 4 M_B_DQ<44> M_B_A1 4 M_B_DQ<48> M_B_A1 R0402_N 1% I
R3 A2 VDD R1
4 M_B_DQ<47> H2 DQ4 P7 A1 VDD L9
4 M_B_DQ<51> H3 DQ2 RM54 36R
M_B_A3 N7 A3 VDD T9 H8 DQ5 M_B_A2 R3 A2 VDD R1 H7 DQ3 M_B_A2 RM55 36R R0402_N 1% I
M_B_A4 4 M_B_DQ<40> M_B_A3 4 M_B_DQ<49> M_B_A3 R0402_N 1% I
N3 A4 VDD G7
4 M_B_DQ<42> J3 DQ6 L N7 A3 VDD T9
4 M_B_DQ<50> H2 DQ4 RM56 36R
M_B_A5 P8 A5 J7 DQ7 M_B_A4 N3 A4 VDD G7 H8 DQ5 M_B_A4 RM57 36R R0402_N 1% I
M_B_A6 4 M_B_DQ<41> M_B_A5 4 M_B_DQ<52> M_B_A5 R0402_N 1% I
P2 A6 P8 A5 4 M_B_DQ<54> J3 DQ6 L RM58 36R
M_B_A7 R8 A7 VDDQ A1 E7 DQM M_B_A6 P2 A6 J7 DQ7 M_B_A6 RM59 36R R0402_N 1% I
M_B_A8 +V1P2U_VDDQ M_B_A7 4 M_B_DQ<53> M_B_A7 R0402_N 1% I
R2 A8 VDDQ A9 G3 R8 A7 VDDQ A1 RM60 36R
M_B_A9 4 M_B_DQS_DP<5> DQS
M_B_A8 M_B_A8 R0402_N 1% I
R7 A9 VDDQ C1 F3 R2 A8 VDDQ A9
+V1P2U_VDDQ
E7 DQM RM61 36R
M_B_A10_AP 4 M_B_DQS_DN<5> DQS#
M_B_A9 M_B_A9 R0402_N 1% I
M3 A10/AP VDDQ D9 R7 A9 VDDQ C1 G3 RM62 36R
B M_B_A11 M_B_A10_AP 4 M_B_DQS_DP<6> DQS
M_B_A10_AP R0402_N 1% I B
T2 A11 VDDQ F2 MT40A512M16HA-083E:A M3 A10/AP VDDQ D9 F3 RM63 36R
M_B_A12 M_B_A11 4 M_B_DQS_DN<6> DQS#
M_B_A11 R0402_N 1% I
M7 A12/BC VDDQ F8 bga96_p8mm_9p1x14p1 T2 A11 VDDQ F2 RM64 36R
M_B_A13 T8 A13 VDDQ G1 I
M_B_A12 M7 A12/BC VDDQ F8 MT40A512M16HA-083E:A M_B_A12 RM65 36R R0402_N 1% I
M_B_A14_WE_N L2 A14/WE VDDQ G9 M_B_A13 T8 A13 VDDQ G1 bga96_p8mm_9p1x14p1 M_B_A13 RM66 36R R0402_N 1% I
M_B_A15_CAS_N M8 A15/CAS VDDQ J2 M_B_A14_WE_N L2 A14/WE VDDQ G9 I
M_B_A14_WE_N RM67 36R R0402_N 1% I
M_B_A16_RAS_N L8 A16/RAS VDDQ J8 M_B_A15_CAS_N M8 A15/CAS VDDQ J2 M_B_A15_CAS_N RM68 36R R0402_N 1% I
+V2P5U_VPP M_B_A16_RAS_N L8 A16/RAS VDDQ J8 M_B_A16_RAS_N RM69 36R R0402_N 1% I
+V2P5U_VPP
VPP B1 UM7C
R9 B1 UM8C M_B_BA0 RM70 36R R0402_N 1% I
VPP VPP
A3 DQ0 R9 M_B_BA1 RM71 36R R0402_N 1% I
M_B_BA0 4 M_B_DQ<27> VPP
M_B_DIM0_CKE0 R0402_N 1% I
N2 BA0 4 M_B_DQ<24> B8 DQ1 4 M_B_DQ<62> A3 DQ0 RM72 36R
M_B_BA1 N8 BA1 C3 DQ2 M_B_BA0 N2 BA0 B8 DQ1 M_B_DIM0_ODT0 RM73 36R R0402_N 1% I
4 M_B_DQ<30> M_B_BA1 4 M_B_DQ<61> M_B_BG0 R0402_N 1% I
4 M_B_DQ<25>
C7 DQ3 N8 BA1 4 M_B_DQ<59>
C3 DQ2 RM74 36R
VSSQ A2 C2 DQ4 C7 DQ3 M_B_ACT_N RM75 36R R0402_N 1% I
M_B_DIM0_CKE0 4 M_B_DQ<26> 4 M_B_DQ<57> DDR1_B_PARITY R0402_N 1% I
K2 CKE/CKE0 VSSQ A8
4 M_B_DQ<28> C8 DQ5 VSSQ A2
4 M_B_DQ<63> C2 DQ4 RM76 36R
M_B_DIM0_CK_DDR0_DP K7 C9 D3 M_B_DIM0_CKE0 K2 A8 C8 M_B_DIM0_CS0_N RM77 36R R0402_N 1% I
M_B_DIM0_CK_DDR0_DN K8 CLK VSSQ
D2
4 M_B_DQ<31>
D7
DQ6 U M_B_DIM0_CK_DDR0_DP K7
CKE/CKE0 VSSQ
C9
4 M_B_DQ<60>
D3
DQ5
M_B_BG1 RM96 36R R0402_N 1% NI
CLK#
VSSQ
VSSQ D8
4 M_B_DQ<29> DQ7
M_B_DIM0_CK_DDR0_DN K8 CLK VSSQ
VSSQ D2
4 M_B_DQ<58>
D7
DQ6
DQ7
U 4 M_B_BG1
RM100 0R R0402_N 5% I
CLK# 4 M_B_DQ<56>
VSSQ E3 E2 DQM VSSQ D8
+V1P2U_VDDQ
VSSQ E8 B7 VSSQ E3 E2 DQM
M_B_DIM0_ODT0 4 M_B_DQS_DP<3> DQS +V1P2U_VDDQ
K3 ODT VSSQ H1 A7 VSSQ E8 B7
4 M_B_DQS_DN<3> DQS#
M_B_DIM0_ODT0 ODT
4 M_B_DQS_DP<7> DQS
VSSQ H9 K3 VSSQ H1 A7
4 M_B_DQS_DN<7> DQS#
VSSQ F1 MT40A512M16HA-083E:A VSSQ H9
RM45 240R F9 ZQ bga96_p8mm_9p1x14p1 VSSQ F1 MT40A512M16HA-083E:A
R0402_N 1% I RM46 240R F9 ZQ bga96_p8mm_9p1x14p1
I
M_B_BG0 M2 BG0 VSS B2 R0402_N 1% I
I
+V1P2U_VDDQ
VSS E1 M_B_BG0 M2 BG0 VSS B2
N9 E9 RM91 0R E1
TEN VSS VSS
VSS G8 R0402_N 5% I N9 VSS E9 RM93 0R DDR1_B_ALERT_N RM78 49.9R 1% R0402_N I
TEN
M_B_ACT_N L3 VSS K1 VSS G8 R0402_N 5% I
ACT#
VSS K9 M_B_ACT_N L3 VSS K1
ACT#
VSS M9 M_B_BG1 VSS K9
DDR4_DRAMRST_R P1 RESET# VSS N1 VSS M9 M_B_BG1
VSS T1 DDR4_DRAMRST_R P1 RESET# VSS N1
DDR1_B_PARITY T3 PAR VSS T1
DDR1_B_PARITY T3 PAR
A A

M_B_DIM0_CS0_N L7 CS#
M_B_DIM0_CS0_N +V1P2U_VDDQ +V1P2U_VDDQ 4,10,19,21,61
L7 CS#
DDR1_B_ALERT_N +V2P5U_VPP +V2P5U_VPP 19,21,62
P9 ALERT#
DDR1_B_ALERT_N +V0.6S_VTT +V0.6S_VTT 19,21,61
NC T7 P9 ALERT#
NC T7

VREFCA M1 VREFCA_CHB

CM10
VREFCA M1 VREFCA_CHB
Project: 320S-13
MT40A512M16HA-083E:A 47nF 16V 10% CM11
bga96_p8mm_9p1x14p1 X7R MT40A512M16HA-083E:A 47nF 16V 10% Engineer: Jason
I C0402_N bga96_p8mm_9p1x14p1 X7R
I I C0402_N
Size Title:DDR4_CHB Rev
I C V01
Date: Monday, April 10, 2017 Sheet 20 of 81

5 4 3 2 1
5 4 3 2 1

+V1P2U_VDDQ
+V1P2U_VDDQ +V1P2U_VDDQ

CM13 CM14 CM15 CM16 CM17 CM18 CM19 CM20 CM21 CM22 CM63 CM64 CM65 CM66 CM67 CM68 CM69 CM70 CM71 CM72 CM73 CM74
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
I I I I I I I I I I I I I I I I I I I I I I

D D

+V1P2U_VDDQ

CM36
1uF 6.3V 10%
CM37
1uF 6.3V 10%
CM38
1uF 6.3V 10%
CM39
1uF 6.3V 10%
CM40
1uF 6.3V 10%
CM41
1uF 6.3V 10%
CM42
1uF 6.3V 10%
CM43
1uF 6.3V 10%
CM44
1uF 6.3V 10%
CM25
1uF 6.3V 10%
1uF:4 as near each x16
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
C0402
I
C0402
I
C0402
I
C0402
I
C0402
I
C0402
I
C0402
I
C0402
I
C0402
I
C0402
I
DRAM device as
possible

+V1P2U_VDDQ

CM45 CM46 CM47 CM48 CM49 CM50 CM51 CM52 CM53 CM54
10uF:Distributed around
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
X5R
C0603
the DRAM devices
I I I I I I I I I I

1uF:2 as near each x20


C
DRAM device as C

+V0.6S_VTT +V0.6S_VTT
possible

CM104 CM105 CM106 CM107 CM92 CM93 CM94 CM95 CM96 CM97
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
I I I I I I I I I I

+V0.6S_VTT

+V2P5U_VPP +V2P5U_VPP
CM102 CM103 CM98 CM99 CM100 CM101 CM108 CM109 CM110 CM111
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
CM26 CM27 CM28 CM29 CM84 CM85 CM86 CM87 CM88 CM89 I I I I I I I I I I
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
I I I I I I I I I I
+V0.6S_VTT
B B

4/6 install CAPs


CM112 CM113 CM114 CM115 CM116 CM117 CM118 CM119 CM120 CM121
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
+V2P5U_VPP X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
I I I I I I I I I I

CM90 CM91 CM59 CM60 CM61 CM62


1uF:2 as near each x16
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
X7R
C0402
DRAM device as
I I I I I I
possible +V0.6S_VTT

CM55 CM56 CM57 CM58

+V2P5U_VPP
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
X5R X5R X5R X5R
10uF:Distributed around
C0603 C0603 C0603 C0603
I I I I the DRAM devices
CM30 CM31 CM32 CM33 CM34
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
X5R X5R X5R X5R X5R
10uF:Distributed around
C0603 C0603 C0603 C0603 C0603
I I I I I the DRAM devices +V0.6S_VTT

CM124 CM122 CM127 CM123 CM125 CM126


1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10%
A X7R X7R X7R X7R X7R X7R A
C0402 C0402 C0402 C0402 C0402 C0402
I I I I I I

3/31 add CAPs

+V1P2U_VDDQ +V1P2U_VDDQ 4,10,19,20,61


+V2P5U_VPP +V2P5U_VPP 19,20,62 Project: 320S-13
+V0.6S_VTT +V0.6S_VTT 19,20,61
Engineer: Jason
Size Title:DDR4 Decoupling Rev
C V01
Date: Monday, April 10, 2017 Sheet 21 of 81

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 22 of 81

5 4 3 2 1
5 4 3 2 1

RF Solution
Cross Moat Cap.

+VCC_CORE
C2313
D D

0.01uF 16V 10%


I
X7R
C0402

C2314

0.01uF 16V 10%


I
X7R
C0402

C C

EMC Solution

B B

+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,35,36,43,46,50,75


+VCC_SA +VCC_SA 10,15,67
+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70

A A

Project: 320S-13
Engineer: Jason
Size Title:RF / EMC Solution Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 23 of 81
5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

+V3P3A +V3P3A_SPI_FLASH

A C
D
CR3000 RB521C30 100mA 30v D
SOD-923
I
40mA
SH9512
+V3P3A_SPI_FLASH
NI
R0402_N
0R
5%

C3058
0.1uF 10V 10%
R9761 R3001 R3002 X5R
10K 10K 10K C0402_N
5% 5% 5% I
R0402_N R0402_N R0402_N
SPI ROM
I I I
U3002
R9871 0R R0402_N 5% I FLASH_SPI_CS0_N_R 1 8
5,50 FLASH_SPI_CS0_N FLASH_SPI_MISO_R /CS VCC FLASH_SPI_IO3_R
5,50 FLASH_SPI_MISO R9742 33R R0402_N 1% I 2 7
FLASH_SPI_IO2_R DO(IO1) /HOLD(IO3) FLASH_SPI_CLK_R
R3021 33R R0402_N 1% I 3 6
5 FLASH_SPI_IO2 /WP(IO2) CLK FLASH_SPI_MOSI_R
4 5
GND DI(IO0)
C C
W25Q64FVSSIQ
I
R9869 33R R0402_N 1% I
5,50 FLASH_SPI_MOSI
R9870 33R R0402_N 1% I
5,50 FLASH_SPI_CLK
R3022 33R R0402_N 1% I
5 FLASH_SPI_IO3

Difference with ARMOUR


Series-resistor 0R change to 33R 4/5 Remove BIOS Socket

ROM Socket

B B

2/24 SIV:Delet ROM Socket @U3002

+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,29,35,37,42,50,55,56,60,62,65,66,70

A A

Project: 320S-13
Engineer: Jason
BPAGE DRAWING
INTERNAL ONLY Size Title:SYSTEM FLASH Rev
sky_y_mrd.GND
Custom V01
Wed Jun 03 11:22:52 2015
Date: Monday, April 10, 2017 Sheet 24 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
Engineer: Jason
BPAGE DRAWING
INTERNAL ONLY
Size Title:NA Rev
sky_y_mrd.GND
Custom V01
Wed Jun 03 11:22:52 2015
Date: Monday, April 10, 2017 Sheet 25 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

M.2 SSD Module 1.4A @ADATA 128GB SSD


2.6A @ADATA 256GB SSD
+V3P3SX +V3P3A_SSD
SH4200

D 0R I
R0805_N D
5%

Change SH4200 0805 shunt to resistor

+V3P3A_SSD

C4209 C4204 C4205 C4206 C4207 C4208


22uF 6.3V 20% 22uF 6.3V 20% 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10%
X5R X5R X5R X5R X5R X5R
C0603_N C0603_N C0402_N C0402_N C0402_N C0402_N
I I I I I I
CIS ok
2/16 change CONN +V3P3A_SSD
JSSD1
C C

1 2
GND_1 3.3V_2
3 4
GND_3 3.3V_4
5 6
9 PCIE9_SSD_RX_DN PERn3 Reserved_6
7 8
9 PCIE9_SSD_RX_DP PERp3 Reserved_8
9 10
GND_9 DAS/DSS# (O)(OD)
11 12
9 PCIE9_SSD_TX_DN_C PETn3 3.3V_12
13 14
9 PCIE9_SSD_TX_DP_C PETp3 3.3V_14
15 16
GND_15 3.3V_16
17 18
9 PCIE10_SSD_RX_DN PERn2 3.3V_18
19 20
9 PCIE10_SSD_RX_DP PERp2 Reserved_20
21 22
GND_21 Reserved_22
23 24
9 PCIE10_SSD_TX_DN_C PETn2 Reserved_24
25 26
9 PCIE10_SSD_TX_DP_C PETp2 Reserved_26
27 28
GND_27 Reserved_28
29 30
9 PCIE11_SSD_RX_DN PERn1 Reserved_30
PCIE12 RX follow 9 PCIE11_SSD_RX_DP 31
33
PERp1
GND_33
Reserved_32
Reserved_34
32
34 +V3P3A_SSD
35 36
intel CRB 9
9
PCIE11_SSD_TX_DN_C
PCIE11_SSD_TX_DP_C
37
39
PETn1
PETp1
Reserved_36
DEVSLP (I)(0/3.3V)
38
40
SATA2_DEVSLP 9
R4207
1/4 Add R4206 PU
GND_39 Reserved_40
B R4200 0R R0402_N5% I PCIE12_SSD_RX_DP_R 41 42 10K B
9 PCIE12_SSD_RX_DP PERn0/SATA-B+ Reserved_42
R4201 0R R0402_N5% I PCIE12_SSD_RX_DN_R 43 44 5%
9 PCIE12_SSD_RX_DN PERp0/SATA-B- Reserved_44 R0402_N
45 46
GND_45 Reserved_46
Difference with armour 47 48 I
SSD interface SATA change to PCIE 9 PCIE12_SSD_TX_DN_C PETn0/SATA-A- Reserved_48
49 50
If install SATA CARD,R4200,R4201 need install 0.01uF 9 PCIE12_SSD_TX_DP_C PETp0/SATA-A+ PERST# (I)(0/3.3V)
SSD_CLK_REQ_N_R PLT_RST_N 7,27,43,50,74
51 52 R4206 0RR0402_N5% I
SSD_CLK_REQ_N 7
C0606,C0607 need install 0.01uF GND_51 CLKREQ# (IO)(0/3.3V)
53 54 M.2_SSD_PE_WAKE_N R4205 0R
7 PCIE_REFCLK_SSD_DN REFCLKN PEWake# (IO)(0/3.3V) R0402_N 5% NI
PCIE_WAKE_PCH_N 7
55 56
7 PCIE_REFCLK_SSD_DP REFCLKP Reserved_56
57 58 Pin54
GND_57 Reserved_58
PICE module spec is N/C
SATA module spec is N/C
Key M
NGFF 67 68 PM_SUSCLK_SSD TP9980
NC32 SUSCLK(32kHz) (I)(0/3.3V)
SSD module PCIE SATA Pin69 69 70
interface PEDET (OC-PCIe) 3.3V_70
PICE module spec is N/C 71 72 Pin68
SATA module spec is GND GND_71 3.3V_72
R4200,R4201 install 0ohm R4200,R4201 install 0.01uF 73 74 PICE module spec is N/C
GND_73 3.3V_74 SATA module spec is N/C
Reference C0606,C0607 install 0.22uF C0606,C0607 install 0.01uF

GND12

GND13
75
GND_75

R1050 install 10Kohm R1050 uninstall 10Kohm


Detect pin R1087 uninstall 100Kohm R1087 install 100Kohm APCI0079-P002A

76

77
I

A
Default A
3/16 Add SSD(PCIE or SATA) BOM option table
C
o
le
-
a
ye
P
C
I
Es
1
2
R
X
,
rR
e4
s
e0
r
v
e
d4
R
4
2
0
2
,
R
4
2
0
3

+V3P3SX +V3P3SX 5,6,7,8,9,10,27,30,35,36,43,46,50,75


p
l
a
s
c
l
o
e
t
o

2
0
,
R
2
0
1

Project: 320S-13
Engineer: Jason
BPAGE DRAWING
INTERNAL ONLY
Size Title:PCIE SSD MODULE Rev
sky_y_mrd.+V3P3.26
Custom V01
Wed Jun 03 11:22:52 2015
Date: Monday, April 10, 2017 Sheet 26 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

SD_VDD1

+V3P3SX +3.3V_AUX NOTE4:


ALL OF CAPCITORS ARE CERAMIC CAPCITORS;
REFER THE DESIGN GUIDE FOR THE BYPASS CAPACITOR PLACEMENT.

1
SH4300 0R IF RTD3-COLD IS NOT NEEDED TO BE SUPPORTED, C2 CAN BE DR2
R0402 5% I CR14 CR13
REMOVED, PIN1, PIN10, PIN12 AND PIN18 SHARE SAME CAPACITOR 0.1uF 10V 10% 4.7uF 6.3V 20%
D
SH9519 0R
+3.3V_MAIN C4. PIN12 CONNECTED TO +3.3V_MAIN.
IF RTD3-COLD IS NEEDED TO BE SUPPORTED, +3.3V_MAIN NEED TO
0402 0402 Micro SD AZ5725-01F.R7GR 1uA 5V
I I D
R0402 5% I BE SWITCHED ON/OFF BY EXTERNAL POWER SWITCH.
SD_D2 Connector DFN1006p2x

2
EMC_I

SD_D3 2/16 change CONN

SD_CMD JR1

SD_CLK_R L9514 SD_CLK


1 2 4
VDD
60ohm 200mA +-25% L0402 I 9 SD_CD#
CD#
Close to IC SD_D0 G2
G2
SEE NOTE 4 SD_D0 7 G1
DAT0 G1
SD_D1 8
+3.3V_MAIN 6/26 EMC solution SD_D2 DAT1

1
1 DR1
DAT2
SD_D3 2
CR6 CD/DAT3
UR1

33

32

31

30

29

28

27

26

25
0.1uF 10V 10% SD_CLK 5 6
CLK VSS
X5RC0402_N SD_CMD 3 AZ5725-01F.R7GR 1uA 5V

GND

PE_12VCCAIN

PLL_DLL_12VCCVIN

SD_D2

SD_D3

SD_CMD

SD_D0
SD_CLK
I

CORE_12VCCO
CMD DFN1006p2x

2
EMC_I
CR9051
CR3 ST-TF1-008B1 I
6.8pF 50V 0.5pF
0.1uF 10V 10% NPO
1 24 SD_D1 Close to CONN
X5RC0402_N PE_33VCCAIN SD_D1 C0402_N
I
C
I 6/26 EMC solution C
2 23 SD_CLK_REQ_N
7 PCIE_REFCLK_SD_DN_R PE_REFCLKM CLKREQ# SD_CLK_REQ_N 7
SEE NOTE 6
3 22
7 PCIE_REFCLK_SD_DP_R PE_REFCLKP LED#_IO1

RR1 191 1%
R0402_N I 4 21
PE_REXT SD_WPI

5
9 PCIE_SD_LN0_TX_SOC_DN PE_RXM
SD_CD#
20
SD_CD#

6
9 PCIE_SD_LN0_TX_SOC_DP PE_RXP
2/15 Jerry suggest 19
SD_IO_LDO_CAP

C10032 0.1uF 10V 10%X5R C0402_N I PCIE_SD_LN0_RX_SOC_DP_C


7
9 PCIE_SD_LN0_RX_SOC_DP PE_TXP
18
SD_IO_SKT_33VIN +3.3V_MAIN
SEE NOTE 4
C10033 0.1uF 10V 10%X5R C0402_N I PCIE_SD_LN0_RX_SOC_DN_C
8
9 PCIE_SD_LN0_RX_SOC_DN PE_TXM

MAIN_LDO_12VOUT

IO0_MAIN_LDOSEL
17
SD_VDD1

PE_RET#_GATE#
SD_SXT_33VOUT

ALIX_LDO_CAP
MAIN_LDO_VIN

MAIN_LDO_EN
CR10

DEV_WAKE#
ALIX_33VIN
B
CR4 1uF 6.3V 10% B
0.1uF 10V 10% CR8 X7R

X5RC0402_N 4.7uF 10V 10% CR9 C0402


I R10051 X5R
0.1uF 10V 10% I
OZ711LV1LN-B-0-TR 10K C0603_N
C0402_N X5R

10

11

12

13

14

15

16
I 5% I I
R0402_N
I

CR7
CR5 SEE NOTE 4 1uF 6.3V 10% SEE NOTE 4
+3.3V_AUX
4.7uF 10V 10% X7R
X5R C0402
C0603_N CR2 +3.3V_MAIN I
4.7uF 10V 10% SEE NOTE 5
I
X5R
SEE NOTE 4 PCIE_WAKE_PCH_N 7
C0603_N
I PLT_RST_N 7,26,43,50,74
+3.3V_AUX
NOTE5: +3.3V_MAIN
1.IF RTD3-COLD IS NEEDED TO BE SUPPORTED, WAKE# MUST
BE PULLED-UP TO +3.3V_AUX ON THE MB. DURING D3 COLD, SEE NOTE 4
+3.3V_AUX R10042
WAKE# WILL BE ASSERTED AT THE EVENT OF SD CARD
CR1 10K
INSERTION OR REMOVAL. 4.7uF 10V 10% 5%
2.IF RTD3-COLD IS NOT NEEDED TO BE SUPPORTED, THERE IS X5R R0402_N
A NO REQUIREMENT CONNECTION FOR WAKE#. A
C0603_N I
SD_CLK_REQ_N
I

NOTE6: +V3P3SX +V3P3SX 5,6,7,8,9,10,26,30,35,36,43,46,50,75


1.PE_CLKREQ# MUST BE PULLED-UP TO +3.3V_AUX
ON THE MB. NOTE3:
2.THE TX/RX/REFCLK/PE_CLKREQ# ARE GROUP TERMINAL 33 (GND) IS THE EXPOSED PAD
SIGNALS, AND EACH PCIE PORT HAS EACH ON THE BOTTOM OF PACKAGE AND MUST BE
SIGNALS COMBINATION.
PLEASE CONFIRM CHIPSET VENDOR WHICH SIGNALS
SOLDERED TO GND OF PCB. Project: 320S-13
ARE SAME GROUP, AND CONNECT THOSE GROUP
SIGNALS TO OZ711LV1LN. Engineer: Jason
BPAGE DRAWING
INTERNAL ONLY Size Title:<SD CARD> Rev
apl_ff.s
Custom V01
Fri May 27 06:47:20 2016
Date: Monday, June 26, 2017 Sheet 27 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title:NA Rev
sky_y_mrd.GND
Wed Jun 03 11:22:53 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 28 of 81
8 7 6 5 4 3 2 1
1 2 3 4 5

+V3P3A

QX12A
2N7002KDW 115mA 60V
SOT363V
I

G1
SML0_CLK
A SMB2_THM_CLK 50 A

S1

D1
EC

G2
SML0_DATA
SMB2_THM_DATA 50

S2

D2
QX12B
2N7002KDW 115mA 60V
SOT363V
I

1/4 Add connect to SOC


& EC

B
+V3P3A
CPU THERMAL SENSOR SHUTDOWN# 60 B

RI70 0R
EC_WRST# 50
1/5 Power modify +V3P3A R0402_N 5% NI

C2829
0.1uF 16V 10% QT1B D2
X7R 2N7002KDW 115mA 60V
C0402 SOT363V RT1 330K VR_PWRGD 7,66
I U2800 I S2 G2 R0402_N 5% I
1 8 SML0_CLK
VCC SCLK
H_THERMDA 2 7 SML0_DATA
+V3P3A DXP SDATA
I
C2830 2200pF 50V 10% H_THERMDC 3 6 THERMAL_ALERT# R2808 7.5K
C0402 X7R DXN ALERT# R0402_N 1% I
+V3P3A
CPU_THERM# 4 5
THERM# GND
D1 QT1A
R2807 2N7002KDW 115mA 60V
10.5K 1% G788P81U SOT363V
R0402 MSOP8_PH0P65_3X3_H1P1 G1 S1 I
I I
C C

THERMAL_ALERT# 5
3/2 If HW shutdown,
H_THERMDA QT1,RT1,R6011 need install,R9863 change to NI
3

Q2800
MMBT3904 200mA 40V 1
sot_23
I
2

H_THERMDC

D D
+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,35,37,42,50,55,56,60,62,65,66,70

Project: 320S-13
Engineer: Jason
Size Title:CPU THERMAL SENSOR Rev
B V01
Date: Monday, May 22, 2017 Sheet 29 of 81
1 2 3 4 5
1 2 3 4 5

+V5P0S

40mil 3/7 R9847 connect to +V5P0S,change to +V3P3SX

C3000 C3001
A 10uF 10V 20% 0.1uF 10V 10% A
X5R X7R
C0603 C0402 +V3P3SX +V5P0S
I I +V3P3SX
40mil 1/11 Update FAN pin define

R3000 R9847 JFAN1

G2
10K 10K
5% 5% SH9521

SH2
R0402 R0402 1
I NI I 1
0R
R0603_N 2
50 FAN_SPEED1 5% 2

3
3 5/10 change FAN CONN
C3002
0.01uF 16V 10% EC_FAN_PWM1 4
X7R 50 EC_FAN_PWM1 4

SH1
C0402
I 50208-00401-001

G1
con_fpc4p_ph0p8_h1p7
I

6/21 JFAN1 footprint CON_FPC4P_PH0P6_H1P55


FAN conn change to con_wtb_4p_ph0p6_h1p55_50376

CIS ok
B B

+V5P0S +V5P0S 10,35,46


+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,35,36,43,46,50,75

+V5P0S

40mil 3/7 R9847 connect to +V5P0S,change to +V3P3SX

C10024 C10023
10uF 10V 20% 0.1uF 10V 10%
X5R X7R
C0603 C0402 +V3P3SX +V5P0S
I I +V3P3SX
40mil
R10038 R10039 JFAN2

G2
10K 10K
5% 5% SH9522

SH2
R0402 R0402 1
I NI I 1
0R
R0603_N 2
50 FAN_SPEED2 5% 2 5/10 change FAN CONN
3
3
C10025
C 0.01uF 16V 10% EC_FAN_PWM2 4 C
X7R 50 EC_FAN_PWM2 4
C0402 SH1
I 50208-00401-001
G1

con_fpc4p_ph0p8_h1p7
I

D D

Project: 320S-13
Engineer: Jason
Size Title:FAN conn Rev
Custom V01
Date: Wednesday, May 10, 2017 Sheet 30 of 81

1 2 3 4 5
Project: 320S-13
Engineer: Jason
Size Title:NA Rev
E V01
Date: Monday, April 10, 2017 Sheet 31 of 81
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title:NA Rev
sky_y_mrd.+V3P3.32
Wed Jun 03 11:22:55 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 32 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title:NA Rev
sky_y_mrd.+V1P0.33
Wed Jun 03 11:22:55 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 33 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Wed Jun 03 11:22:56 2015
Date: Monday, April 10, 2017 Sheet 34 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

for EMI Co-lay HDMI_TX2_CMC_DP

HDMI Connector NI R3201 0ohm 0402 5% C HDMI_TX2_CMC_DN

HDMI_TX1_CMC_DP
L3201
C3201 0.1UF C 0402 10V HDMI_TX2_CMC_DP A1 A2 HDMI_TX2_DP HDMI_TX1_CMC_DN
D
3 DDI1_TX0_DP
C3202 0.1UF C 0402 10V HDMI_TX2_CMC_DN B1 B2 HDMI_TX2_DN HDMI_TX0_CMC_DP D
3 DDI1_TX0_DN
SDCW2012C-2-900TF R3211
HDMI_TX0_CMC_DN 470R 0402 5%
R3202 0ohm 0402 5% I
HDMI_CLK_CMC_DP R3212
NI C R3204 R3207
HDMI_CLK_CMC_DN 470R 0402 5%
R3203 470R 0402 5% 470R 0402 5%
NI 0ohm 0402 5% I
I
I
L3202 R3205
C3203 0.1UF C 0402 10V HDMI_TX1_CMC_DP B1 C B2 HDMI_TX1_DP R3208 470R 0402 5%
3 DDI1_TX1_DP
470R 0402 5% I
HDMI_TX1_CMC_DN HDMI_TX1_DN R3206
C3204 0.1UF C 0402 10V A1 A2 I
3 DDI1_TX1_DN 470R 0402 5%
SDCW2012C-2-900TF R3209 I
R3210 470R 0402 5%
NI 0ohm 0402 5% I
HDMI_PLS_FET
C +V3P3SX
R3213
NI 0ohm 0402 5%

R10043
L3203
C D
HDMI_TX0_CMC_DP HDMI_TX0_DP 10K
C3205 0.1UF C 0402 10V A1 A2
3 DDI1_TX2_DP 5% Q3201
C R0402_N C
C3206 0.1UF C 0402 10V HDMI_TX0_CMC_DN B1 B2 HDMI_TX0_DN BSS138 300mA 50V
3 DDI1_TX2_DN I G
SDCW2012C-2-900TF sot23_gsd
R3214 I
NI 0ohm 0402 5%
S

C
R3216
NI 0ohm 0402 5%
+V5P0S +VHDMI
JHDMI1
L3204
C
20
C3207 0.1UF C 0402 10V HDMI_CLK_CMC_DP B1 B2 HDMI_CLK_DP SHELL1
3 DDI1_TX3_DP 21
SHELL2
HDMI_TX2_DP 1
C3208 0.1UF C 0402 10V HDMI_CLK_CMC_DN A1 A2 HDMI_CLK_DN D2+
3 DDI1_TX3_DN FH2 2
SDCW2012C-2-900TF HDMI_TX2_DN D2 Shield
350mA 16V SMD1206 3
R3217 HDMI_TX1_DP D2-
NI 0ohm 0402 5% 1206 4
I D1+
5
D1 Shield
HDMI_TX1_DN 6
HDMI_TX1_DN
C HDMI_TX0_DP D1-
7
HDMI_TX0_DN D0+
HDMI_TX1_DP 8
HDMI_TX0_DP D0 Shield
HDMI_CLK_DP HDMI_TX0_DN 9
HDMI_TX2_DP D0-
HDMI_CLK_DN ESD3202 HDMI_CLK_DP 10
HDMI_TX2_DN ESD3201 CK+
11
B B

10
CK Shield
HDMI_CLK_DN

9
7

6
10

12
9
7

+VHDMI CK-
HDMI_CEC_1

NC
NC

NC
NC
13
NC
NC

NC
NC

CE Remote
14
NC
HDMI_DDC_SCL 15
DDC CLK
HDMI_DDC_SDA 16
1 I/O1 I/O3 4 DDC DATA
1 I/O1 I/O3 4 17
2 I/O2 I/O4 5 GND
2 I/O2 I/O4 5 18
+5V
HDMI_HPD 19
HP DET
+VHDMI C3209 C3210 22
SHELL3
22pF 50V 5% 23

1uF 10V 0402


GND

GND
SHELL4
GND

GND

NPO
AZ1045-04F.R7G C0402_N 91HDA-0061-40000H
A

AZ1045-04F.R7G

3
+V3P3A I
8

lcc10_ns_2p5x1p0_p65h CON_HDMI_19P_1001050-03111
lcc10_ns_2p5x1p0_p65h D3201
EMC_NI I
EMC_NI +V3P3A BAT42W-7-F DIODES
C

Q3202 +V3P3SX
RN_+VHDMI
BSS138 300mA 50V C3211
1uF 10V 0402

R3218 R3219
R3221 R3222
D
S
10K 0402 1%

10K 0402 1%

10K 0402 1%

10K 0402 1%

5/3 change to 1M
R3220 PLACE CLOSE TO J_HDMI
1M 5%
G R0402 G

A sot23_gsd I A
DDI1_DDC_SCK I HDMI_DDC_SCL
3 DDI1_DDC_SCK HDMI_HPD

D
S
3 DDI1_HPD

1
C3212 R3223 CR9052
Q3203

1uF 10V 0402

100K 0402 1%
Q3204 2N7002KW 115mA 60V
BSS138 300mA 50V +V5P0S +V5P0S 10,30,46 sot_323_dgs
I AZ5725-01F.R7GR 1uA 5V
DDI1_DDC_SDA HDMI_DDC_SDA +V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,36,43,46,50,75 DFN1006p2x
3 DDI1_DDC_SDA

2
I
D
S

+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,37,42,50,55,56,60,62,65,66,70

G
Project: 320S-13
sot23_gsd
I
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title:HDMI CONNECTOR Rev
sky_y_mrd.GND
Wed Jun 03 11:22:56 2015 Custom V01
Date: Monday, May 22, 2017 Sheet 35 of 81
8 7 6 5 4 3 2 1
+V3P3SX
EDP DISPLAY 1920X1200 (12.2INCH) +V3P3_DISPLAY
+V3P3_DISPLAY_CONN +VBATA_BKLT_CONN

SH8201
JEDP1 2/22 change CONN
C8207 I 0R +V3P3_DISPLAY_CONN
22uF 6.3V 20% R0603_N
5% 1
X5R
C8201 C8200 EDP_HPD 2
C0603_N C9541
10uF 6.3V 20% 1uF 6.3V 10% 3 41
I U8201 X5R X5R 0.1uF 10V 10%
4
3/22 FB8200 0603 Bead change to JP8200 JUMP_43X79 5 1
C0603_N C0402_N
X5R R8211
VIN VOUT 5
R9584 I I
C0402_N 100K
6 42
75R I 5%
7
EDP_VDD_EN 3 1% R0402_N
3 EDP_VDD_EN EN R0402_N I 3 EDP_HPD
EDP_HPD 8
9 43
2 4 NI
GND SS EDP_AUX_CONN_DP 10
EDP_AUX_CONN_DN 11
APL3512ABI-TRG C9583
12 44
SOT23_5 0.01uF 16V 10% EDP_TX0_CONN_DN
+VBATA_BKLT_CONN 13
I C0402_N
Change the SH8200 SH8201 0402 EDP_TX0_CONN_DP 14
X7R
shunt to resistor 5/11 change CAPs 15 45
Difference with armour I
EDP_TX1_CONN_DN 16
U8201 WS4601E-5/TR
EDP_TX1_CONN_DP 17
change to APL3512ABI-TRG
18
C8202 C9540 EDP_BKLT_PWM 19
10uF 25V 20% 10uF 25V 20% 3 EDP_BKLT_PWM EDP_BKLT_EN 20
X5R X5R 3 EDP_BKLT_EN
C0603_N C0603_N +V3P3SX 21
22
I I
R9917 0R 23
R0402_N 5% I 24
25
EDP_BKLT_EN
46 DMIC_DATA
26
46 DMIC_CLK
27
R8221 USB2_P7_CAM_DN_R 28
100K USB2_P7_CAM_DP_R 29
Difference with armour 5% 30
R9771 0R Add R8221 change to install USB 2.0 Camera
R0402_N
R0402_N I 5% I
67ohm 320mA +-25%
L9505
RBD3 0R 0402 5% I
EDP_TX1_SOC_DP C8213 0.1uF 10V 10% EDP_TX1_C_DP A1 A2 EDP_TX1_CONN_DP
3 EDP_TX1_SOC_DP C0402_N I
X5R 50406-03041-001
EDP_TX1_SOC_DN C8214 0.1uF 10V 10% EDP_TX1_C_DN B1 B2 EDP_TX1_CONN_DN CON_FPC30P_PH0P5_H1P2_40553W90
3 EDP_TX1_SOC_DN C0402_N X5R I LBD2 I
USB2_P7_CAM_DN_R
CO-CH_L4_PH0P8_H1_AB 9 USB2_P7_CAM_DN
1 2
NI 4 3 USB2_P7_CAM_DP_R
R9772 0R 9 USB2_P7_CAM_DP
R0402_N I 5% 90 Ohm@100MHz 20V +/-25% EMC_NI CIS ok
R9773 0R
R0402_N I 5%
67ohm 320mA +-25% RBD4 0R 0402 5% I
L9506
EDP_TX0_SOC_DP C8215 0.1uF 10V 10% EDP_TX0_C_DP A1 A2 EDP_TX0_CONN_DP
3 EDP_TX0_SOC_DP C0402_N X5R I
EDP_TX0_SOC_DN C8216 0.1uF 10V 10% EDP_TX0_C_DN B1 B2 EDP_TX0_CONN_DN 6.5V x [80.6/(220+80.6)] = 1.743V VGS= -4.5V
3 EDP_TX0_SOC_DN C0402_N X5R I 1.743V - 6.5V = -4.757V
CO-CH_L4_PH0P8_H1_AB
JP8200
JUMP
NI 3/23 Add
JUMP_43X79
R9774 0R NOBOM
1 2
R0402_N I 5%
R9775 0R +VSYS +VBATA_BKLT_CONN
Q8200
R0402_N I NI5% DMP3160L-7 -2.7A -30V
S D

D
CO-CH_L4_PH0P8_H1_AB
sot23_gsd
EDP_AUX_SOC_DP C8217 0.1uF 10V 10% EDP_AUX_C_DP B1 B2 EDP_AUX_CONN_DP C8219 C8220 C8221 R8200 C8222 C8223
3 EDP_AUX_SOC_DP

G
I
C0402_N X5R I 1uF 25V 10% 0.1uF 25V 10% 1uF 25V 10% 220K 33pF 50V 5% 0.1uF 25V 10%

G
EDP_AUX_SOC_DN C8218 0.1uF 10V 10% EDP_AUX_C_DN A1 A2 EDP_AUX_CONN_DN X5R X5R X5R 5% NPO X5R
3 EDP_AUX_SOC_DN C0402_N X5R I C0603_N C0402_N C0603_N R0402_N C0402_N C0402_N
L9507 I I I I I I
67ohm 320mA +-25%
R9776 0R R8201
R0402_N I 5% 80.6K
R0402
1%
I

D Q8201
2N7002 250mA 60V
EDP_VDD_EN R8202 0R EDP_VDD_EN_R sot_323_dgs
G S I
R0402_N I 5%
R8203
100K
5%
R0402_N
EDP2 DSI BRIDGE CONTROL SIGNAL BREAKEOUT
I

+VSYS +VSYS 59,60,61,63,67,70


+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,35,43,46,50,75

Project: 320S-13
Engineer: Jason
Size Title:DISPLAY Rev
Custom V01
Date: Monday, May 15, 2017 Sheet 36 of 81
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

USB2.0

D
D

+V5P0A

+V3P3A
CBD1 1.5A/Stack Port
10uF 10V 20% CBD2 +VCC_USB1 R10086
X5R 1uF 10V 10% 100K
C0603_N UBD1 5%
0402
I 5 IN OUT 1 R0402_N
I
FLG* 3
USB2_P3_WP2_OC_N 9
R10103 0R 5%R0402_N I 4 EN GND 2 +VCC_USB1

8
JBD1
C 4/5 add R10103 WS4601E-5/TR C

GND2

GND4
sot_23_5 1
I VCC

1
CR9053 CB4 DB_USB_PN3_R 2
D-
6/28 remove EMC 0603 PAD CB3 100uF 6.3V +/-20%

+
0.1uF 10V 10% SMD3.5X2.8mm DB_USB_PP3_R 3
0402 D+
AZ5725-01F.R7GR 1uA 5V
DFN1006p2x 5/22 change to 100uF 4

GND1

GND3
GND

2
I
RBD1 0R 0402 5% I
DB_USB_PP3_R WUSF8204-0A00

7
9 USB2_P6_WP3_DP CON_USB20_4P_DIP_8204
I
LBD1 5/25 need change 150uF
1 2
4 3

90 Ohm@100MHz 20V +/-25% EMC_NI

USB CONN
DB_USB_PN3_R
9 USB2_P6_WP3_DN
RBD2 0R 0402 5% I

B B

DB_USB_PP3_R
DB_USB_PN3_R

DBD1

10
9
7

6
NC
NC

NC
NC
1 I/O1 I/O3 4
2 I/O2 I/O4 5

GND

GND
AZ1045-04F.R7G

3
lcc10_ns_2p5x1p0_p65h
EMC_I

A A

+V5P0A +V5P0A 10,11,50,54,61,62,63,65,66,67,69,70,75


+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,42,50,55,56,60,62,65,66,70

Project: 320S-13
BPAGE DRAWING Engineer: Jason
Size Title:USB2.0 Rev
apl_ff.GND
Fri May 27 06:47:32 2016 Custom V01
Date: Wednesday, June 28, 2017 Sheet 37 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

Sensors

D LID Sensor D

Working voltage 2.4/ 2.7/ 5.5


max current 2.5mA typ:3uA

C C

3/16 Change to +V3.3AL

+V3.3AL

C8003
0.1uF 10V 10% R8000
X5R U8001 100K 5/9 change to 100K
C0402_N 5%
I 1 R0402_N
NC0 I
4
VDD
2
GND
5 LID_INT_N
OUT LID_INT_N 8,50
3
B NC1 B

BU52012HFV
HVSOF5 C10027
I 100pF 50V 5%
NPO
C0402_N
I

A A

Project: 320S-13
+V3.3AL +V3.3AL 11,42,46,50,51,58,60
Engineer: Jason
Size Title:LID Rev
Custom V01
Date: Tuesday, June 20, 2017 Sheet 38 of 81
8 7 6 5 4 3 2 1
Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 39 of 81
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev

Wed Jun 03 11:22:59 2015 Custom V01


Date: Monday, April 10, 2017 Sheet 40 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY
Size Title:NA Rev
sky_y_mrd.+V3P3.41
Wed Jun 03 11:22:59 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 41 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

USB3.0 +V5P0A
+V3P3A
+V5P0A 10,11,37,50,54,61,62,63,65,66,67,69,70,75
+V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70

+V5CP_R
+V5CP +V5CP_R 3/29 Del CAP
4/20 change rating
D +V3P3A
R10060 0R D
5/23 change to 110K.
R0805_N 5% I CC452 C3900
22uF 6.3V 20% 0.1uF 10V 10% R3902 R3903 R3904
X5R X7R 20K 110K 1% 100K
C0603_N C0402_N 5% 5%
I I R0402_N R0402 I R0402_N
I I

USB2_P1_WP0_OC_N 9

17
16
15
14
13
U3900 +V5P0A_USB_WP2

PwPd

GND
ILIM_HI

FAULT
ILIM_LO
1 12
IN OUT
2 11 USB2_P1_DN
9 USB2_P1_WP1_DN DM_OUT DM_IN +V3.3AL
3 10 USB2_P1_DP 4/7 change from +V3P3A to +V3.3AL.
9 USB2_P1_WP1_DP DP_OUT DP_IN
4 9
ILIM_SEL STATE#
R3958
D+/D- ESD +V3.3AL 100K

CTL1
CTL2
CTL3
5%

EN
R0402_N
C R3900 TPS2546RTER I
C

5
6
7
8
USB2_P1_WP1_DP_CONN 100K I USB_STATUS#
5% USB_STATUS# 50
R0402
TPS2546_CTL3 50

EC_USB_PWR_EN_R
USB2_P1_WP1_DN_CONN I
R3961 0R TPS2546_CTL2 50
50 EC_ACDET R0402_N 5% I
TPS2546_CTL1 50
R3901
0R
R0402_N
1

CR9012 CR9013 5%
NI

R3960 +V5P0A_USB_WP2
AZ5725-01F.R7GR 1uA 5V AZ5725-01F.R7GR 1uA 5V 0R
DFN1006p2x DFN1006p2x R0402_N
2

EMC_I EMC_I 5%
I
50 EC_USB_PWR_EN
5/22 add ESD

1
CR9054
5/22 change to 100uF
CR9081
C9006 C9007
C10022 0R 5%
470pF 50V 5% 4.7uF 10V 10%
B 100uF 6.3V +/-20%

+
B
COG X5R AZ5725-01F.R7GR 1uA 5V NI R0603_N
SMD3.5X2.8mm

12

13
C0402_N C0603_N DFN1006p2x JUSB3-1

2
I I I

GND3

GND4
USB3_P1_TX_DP_CONN
R9007 0R
USB3_P1_TX_DN_CONN R0402_N I 5%
1
VBUS

USB3_P1_RX_DN_CONN
USB2_P1_DN L9003 A1 A2 NI USB2_P1_WP1_DN_CONN 2
D-
USB2_P1_DP B1 B2 USB2_P1_WP1_DP_CONN 3
D+
USB3_P1_RX_DP_CONN
67ohm 320mA +-25%
CO-CH_L4_PH0P8_H1_AB 4
GND

R9006 0R USB3_P1_RX_DN_CONN 5
STDA_SSRX-
R0402_N I 5%
USB3_P1_RX_DP_CONN 6
STDA_SSRX+
R9853 0R
7
CR9006 R0402_N I 5% GND_DRAIN
10

CO-CH_L4_PH0P8_H1_AB USB3_P1_TX_DN_CONN 8
9
7

67ohm 320mA STDA_SSTX-


A1 A2 +-25%
9 USB3_P1_RX_DN
NC
NC

NC
NC

USB3_P1_TX_DP_CONN 9
STDA_SSTX+
B1 B2
9 USB3_P1_RX_DP L9508
A NI A

GND1

GND2
1 I/O1 I/O3 4
2 I/O2 I/O4 5
R9852 0R
W-90-USB3-H082

10

11
R0402_N I 5% con_usb3_9p_DIP_H6p9
I
GND

GND

R9012 0R
AZ1045-04F.R7G
8

R0402_N I 5%
lcc10_ns_2p5x1p0_p65h
EMC_I CO-CH_L4_PH0P8_H1_AB
C1271 0.1uF 10V 10% USB3_P1_TX_DN_C 67ohm 320mA
A1 A2 +-25%
9 USB3_P1_TX_DN C0402_N I
X5R

+V3.3AL +V3.3AL 11,38,46,50,51,58,60


9 USB3_P1_TX_DP
C1270
C0402_N
0.1uF 10V 10%
I
X5R
USB3_P1_TX_DP_C
L9002
B1 B2
NI
Project: 320S-13
+V5CP +V5CP 10,60 Engineer: Jason
+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,42,50,55,56,60,62,65,66,70 R9011 0R Size Title:USB3.0 CONN Rev
R0402_N I 5%
Custom V01
Date: Tuesday, May 23, 2017 Sheet 42 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

WIFI & BT Module

+V3P3SX +V3P3SX_CWS
SH4302

D 0R
I D
2/16 change CONN
R0603_N
5% THIS DESIGN SUPPORTS STONE PEAK ONLY

+V3P3SX_CWS
CIS ok
+V3P3SX_CWS
JWLAN1
1
GND_1
3 SLOT A KEY E 2
C4320 C4321 C4322 C4323 9 USB2_P4_BT_DP USB_D+ 3.3V_2
5 4
4.7uF 6.3V 10% 4.7uF 6.3V 10% 0.1uF 10V 10% 0.1uF 10V 10% 9 USB2_P4_BT_DN USB_D- 3.3V_4
X5R X5R X5R X5R 7 6 TP9992
GND_7 LED1_N
9 8
C0603_N C0603_N C0402_N C0402_N SDIO_CLK PCM_CLK/I2S_SCK
11 10
I I I I SDIO_CMD PCM_SYNC/I2S_WS
13 12
SDIO_DATA0 PCM_IN/I2S_SD_IN
C6001 & C6003 FOR PIN 72 &73 15 14
SDIO_DATA1 PCM_OUT/I2S_SD_OUT
C6002 & C6000 FOR PIN 4 & 5 17 16 TP9993
SDIO_DATA2 LED2_N
19 18
SDIO_DATA3 GND_18
21 20 WIFI/BT_SLOT_TX TP9976
SDIO_WAKE_N UART_WAKE_N
23 22 WIFI/BT_SLOT_RX TP9977
SDIO_RESET_N UART_RX
C KEY E C
PLATFORM PIN OUT
C4318 0.1uF 10V 10%
33 32
PCIE_WLAN_LN0_TX_SOC_DP
C4319 0.1uF 10V 10% PCIE_WLAN_LN0_TX_DP
GND_33 UART_TX
35 34
9 PCIE_WLAN_LN0_TX_SOC_DP PCIE_WLAN_LN0_TX_SOC_DN C0402_N X5R PCIE_WLAN_LN0_TX_DN
PETP0 UART_CTS
37 36
9 PCIE_WLAN_LN0_TX_SOC_DN C0402_N
I
X5R PETN0 UART_RTS
I 39 38
GND_39 RESERVED_38
9 PCIE_WLAN_LN0_RX_SOC_DP 41 40 R4320
PERP0 RESERVED_40
9 PCIE_WLAN_LN0_RX_SOC_DN 43 42 0R
PERN0 RESERVED_42 R0402_N
45 44
PCIE_REFCLK_WLAN_DP GND_45 COEX3
R9890 0R R0402_N5%I 47 46 5%
7 PCIE_REFCLK_WLAN_DP_R PCIE_REFCLK_WLAN_DN REFCLKP0 COEX2
R9889 0R R0402_N5%I 49 48 I
7 PCIE_REFCLK_WLAN_DN_R REFCLKN0 COEX1 SUS_CLK_R
51 50
WLAN_CLK_REQ_N
GND_51 SSCLK WLAN_RST_R SUS_CLK 7,50
53 52
7 WLAN_CLK_REQ_N CLKREQ0_N PERST0_N
55 54
7 PCIE_WAKE_PCH_N PEWAKE0_N RESERVED_W_DISABLE2_N BT_RF_KILL_N 3
57 56
GND_57 W_DISABLE1_N SM_BAT_DATA_DEBUG WIFI_DISABLE_N 6
59 58
5,50 LPC_FRAME_N RESERVED_2ND_PETP1 I2C_DATA SM_BAT_CLK_DEBUG TP10009
61 60
5,50 LPC_AD3 RESERVED_2ND_PETN1 I2C_CLK TP10010
63 62
GND_63 ALERT
65 64
5,50 LPC_AD2 RESERVED_2ND_PERP1 RESERVED_64
67 66 4/21 Add SM_BAT_DATA connect to JWLAN1.58,
5,50 LPC_AD1 RESERVED_2ND_PERN1 UIM_SWP/PERST1_N
Add SM_BAT_CLK connect to JWLAN1.60,
69 68
GND_69 UIM_PWR_SNK/CLREQ1_N Debug card need.
71 70
5,50 LPC_AD0 RESERVED/REFCLKN1 UIM_PWR_SRC/GPIO1/PEWAKE1_N
R4319 0R 73 72
B 5 LPC_CLK_PRT80 RESERVED/REFCLKP1 3.3V_72 B
R0402_N I 5%
75 74 4/21 Add R4325,R4326 0ohm for Debug card
GND_75 3.3V_74

GND76

GND77
6/27 R4325,R4326 change to NI,
APCI0147-P011A because WLAN card "Intel 2x2AC 8260" I2C is 1.8V,
CON_75P_PH05_SMD_51736_RVS_E mother board I2C is 3.3V

76

77
I

+V3P3SX_CWS

WLAN PCIE AC CAPS


R4321
10K
5%
R0402_N
I
WLAN_CLK_REQ_N

A A

Difference with armour


Reserve PLT_RST_N to reset pin and install

WLAN_RST_R R4323 0R
PLT_RST_N 7,26,27,50,74
R0402_N I 5%
R4324 0R
WLAN_RST 8
R0402_N NI 5%
+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,35,36,46,50,75

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY
Size Title:WLAN WIFI BT MODULE Rev
sky_y_mrd.+V3P3.43
Wed Jun 03 11:23:00 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 43 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 44 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title:NA Rev
sky_y_mrd.GND
Wed Jun 03 11:23:01 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 45 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

Notes: +V3.3AL 4/13 remove +V3P3SX_AUDIO


1. Codec VDD_IO pin must be connected +V3P3SX +V3P3SX_AUDIO
VREF_1V65
to same HDA bus power supply that is used for
ICH/PCH bus controller (3.3V or 1.5V). CA21 RA90
R7065 CA20 CA18 CA19
1uF 10V 10%
47R 0.1uF 10V 10% X5R 2.2uF 6.3V 10% 0.1uF 10V 10% 5%
1% X5R X5R X5R 0R
C0603_N
+V3P3SX_AUDIO R0402_N C0402_N C0603_N C0402_N R0603_N I
D I
I I I I +V5P0S +V5P0A_AUDIO
+V3P3SX_AUDIO D
AVDD_HP +V5P0A_AUDIO
RA91
CA26 AUDIO_AGND
AUDIO_AGND
2.2uF 6.3V 10% 5%
X5R CA17 0R
C0603_N 0.1uF 10V 10% R0603_N I
2

I X5R
C0402_N
+V5P0A_AUDIO
I
+V3P3SX_AUDIO
RA18
CA24
3

DA1 1uF 10V 10%


X5R 0R 5%
BAT54C 200mA 30V R0603_NCA23
I
SOT_23 C0603_N CA15 CA16 CA13 CA14
I 0.1uF 10V 10%
I
X5R 0.1uF 10V 10% 0.1uF 10V 10% 4.7uF 10V 10% 4.7uF 10V 10%
X5R X5R X5R X5R
C0402_N
AVDD_HP C0402_N C0402_N C0603_N C0603_N
I
I I I I

CA22 CA2
CA25
4.7uF 6.3V 10% 0.1uF 16V 10%
C 1uF 10V 10% X5R X5R
C
X5R
C0603_N C0402_N
C0603_N
I I
I

UA1

18

24

29

27

28

13
16

11
3

2
7
FILT_1.8V

AVDD_HP

FILT_1.65V

AVDD_3.3V

AVDD_5V
TPA5

VDD_IO

CLASS-D_REF
VDDO33

DVDD33

LPWR5.0
RPWR5.0
TPA4
TPA3
TPA2
TPA1
HDA_RST_N 9
6 HDA_RST_N RESET#
38 JSENSE
JSENSE JSENSE 48
35
HDA_BCLK_R
MICBIASC
5 34
6HDA_BCLK_R HDA_SYNC
BIT_CLK MICBIASB
8
6HDA_SYNC RA19 HDA_SDI0_R SYNC
6 33
6 HDA_SDI0 SDATA_IN PORTB_R_LINE
4 32
6 STRAP_HDA_SDO 33R 5% SDATA_OUT PORTB_L_LINE
R0402_N I
26
HGNDB HGNDB 48
25
B HGNDA HGNDA 48 B
39 31
50 EC_MUTE# SPKR_MUTE# PORTD_B_MIC PORTD_B 48
30
CA7 PORTD_A_MIC PORTD_A 48
10
6 HDA_SPKR PCBEEP PORTA_R
23
0.1uF 10V 10% X5R PORTA_R PORTA_L PORTA_R 48
22
C0402_N I PORTA_L PORTA_L 48
DMIC_DATA 1
36 DMIC_DATA DMIC_CLK
RA7 DMIC_DAT / GPIO1
40
36 DMIC_CLK DMIC_CLK / MUSIC_REQ / GPIO0
21
33R 5% AVEE
20
R0402_N I FLY_N CA1
19
FLY_P 2.2uF 6.3V 20%
37
GPIO1 / PORTC_R_MIC X5R
36 CA8 C0402_N
MUSIC_REQ / GPIO0 / PORTC_L_MIC
I
1uF 25V 10% X5R
C0402_N I
EP_GND
RIGHT+
RIGHT-
LEFT+

LEFT-

RA89 0R
R0805_N 5% I
CX11802-33Z I AUDIO_AGND See design guide for
12

14

15

17

41

ground connections.
A A
SPK_LN SPK_RN
47 SPK_LN SPK_RN 47
SPK_LP SPK_RP
47 SPK_LP SPK_RP 47

RA9 RA8 RA10 RA11


15R 15R 15R 15R
1% 1% 1% 1%
R0402_N R0402_N R0402_N R0402_N
I I I I
CA9 CA10 CA11 CA12 EMI COMPONENTS:
220pF 50V 5% 220pF 50V 5% 220pF 50V 5% 220pF 50V 5% 1. Place snubber networks (C70-73, R70-73) very close to codec pins.
NPO NPO NPO NPO 2. Recommended trace widths from codec to speakers are
+V3P3SX_AUDIO +V3P3SX_AUDIO 48
C0402_N
I
C0402_N
I
C0402_N
I
C0402_N
I
40 mils for 4 ohms speakers, 25 mils for 8 ohms. Project: 320S-13
+V3.3AL +V3.3AL 11,38,42,50,51,58,60
+V5S BPAGE DRAWING Engineer: Jason
+V5P0S 10,30,35 INTERNAL ONLY
+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,35,36,43,50,75
Size Title:<AUDIO CODEC> Rev
apl_ff.8A
Fri May 27 06:47:22 2016 Custom V01
Date: Thursday, April 13, 2017 Sheet 46 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

Speaker

D
D

SPK_LP
RA5 SPK_LP_R
RA6 SPK_LP_CONN
46 SPK_LP
0R 5% 0R 5%

1
CA4 CA29
R0603_N I R0603_N I
47pF 50V 2%
NPO
C0402_N
NI AZ5725-01F.R7GR 1uA 5V
DFN1006p2x
CIS ok

2
NI

G2
RA2 RA3 50278-0040N-001
C SPK_LN SPK_LN_R SPK_LN_CONN C
46 SPK_LN

PAD1
0R 5% 0R 5% 1

1
CA31 1
R0603_N I CA6 R0603_N I
47pF 50V 2% 2
NPO 2
C0402_N 2/16 change CONN
3
NI AZ5725-01F.R7GR 1uA 5V 3
DFN1006p2x
4

2
NI

PAD2
4

JSPK1

G1
SPK_RP
RA21 SPK_RP_R
RA1 SPK_RP_CONN
46 SPK_RP
0R 5% 0R 5%
1

CA3 CA28 6/21 JSPK1 footprint CON_FPC4P_PH0P8_H1P7


R0603_N I R0603_N I
2200pF 25V 10% change to con_wtb_4p_ph0p8_h1p7_50208
X7R
C0402_N
NI AZ5725-01F.R7GR 1uA 5V
DFN1006p2x
2

NI
B B

SPK_RN
RA20 SPK_RN_R
RA4 SPK_RN_CONN
46 SPK_RN
0R 5% 0R 5%
1

CA5 CA30
R0603_N I R0603_N I
2200pF 25V 10%
X7R
C0402_N
NI AZ5725-01F.R7GR 1uA 5V
DFN1006p2x
2

NI

A A

Project: 320S-13
Engineer: Jason
BPAGE DRAWING
INTERNAL ONLY Size Title:Speaker Rev
sky_y_mrd.GND
Custom V01
Wed Jun 03 11:23:02 2015
Date: Monday, April 10, 2017 Sheet 47 of 81

8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

HEADSET JACK (Supports CTIA and OMTP headsets)


Important:
To ensure reliable headset detection for all
fast/slow plug-in scenarios use a jack with
the detect switch all the way at the end so
that the switch is tripped only when the jack
is plugged all the way in.

+V3P3SX_AUDIO

R7055
5.1K
1%
R0402_N
I
R7056 SENSE_PORT_A
C 46 JSENSE JSENSE C
39.2K 1%
R0402_N I

2/22 change CONN

46 HGNDB
JHP1

46 PORTD_A R7057 100R 5% R0402_NI C7031 1uF 10V 10% C0603_NX5R I 1


MIC~GND

RA15 34.8R 1% R0402_N I HPOUT_R_CONN 3


46 PORTA_R R

RA16 34.8R 1% R0402_N I HPOUT_L_CONN 2


46 PORTA_L L

C10034 C10035
4/14 change to 34.8 ohm 100pF 50V 5% 100pF 50V 5%
NPO NPO
C0402_N C0402_N
NI NI
SENSE_PORT_A 5
L_1
B B
AUDIO_AGND 6
DET

46 PORTD_B R10052 100R 5% R0402_NI C10030 1uF 10V 10% C0603_NX5R I 4


GND~MIC

46 HGNDA
AUDIO_AGND 91PJ3-0352-30000H
<PACKAGE>

HGNDB
HGNDA
HPOUT_L_CONN SENSE_PORT_A
HPOUT_R_CONN ESD3203
10
9
7

A 6 A

1
DR5
NC
NC

NC
NC

1 I/O1 I/O3 4 AZ5725-01F.R7GR 1uA 5V


2 I/O2 I/O4 5 DFN1006p2x

2
EMC_NI
GND

GND

AZ1045-04F.R7G
8

lcc10_ns_2p5x1p0_p65h
EMC_NI
Project: 320S-13
AUDIO_AGND
+V3P3SX_AUDIO +V3P3SX_AUDIO 46
BPAGE DRAWING Engineer: Jason
INTERNAL ONLY Size Title:<AUDIO_HEADSET> Rev
apl_ff.8A
Fri May 27 06:47:24 2016 Custom V01
Date: Wednesday, May 24, 2017 Sheet 48 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
BPAGE DRAWING Engineer: Jason
Size Title:NA Rev
sky_y_mrd.+VCHG.49
Wed Jun 03 11:23:03 2015 Custom V01
Date: Monday, April 10, 2017 Sheet 49 of 81
8 7 6 5 4 3 2 1
5 4 3 2 1

EC controller

+V3P3A +V3P3A_EC +V3.3AL


SH5501 0R SH5502 0R
R0603_N 5% NI R0603_N 5% I

+V3P3A_EC RI53 0R 0402 5%

CI3 VCC_LPC
D 0.1uF 10V 10% 0402 D
UI2 +V3P3A_EC +V3P3A_EC

VCC_LPC 9 FBI1
VCC_LPC EC_AVCC 2 1
5 LPC_SERIRQ
LPC_SERIRQ 3 1.8V/3.3V 111
+V3P3A_EC LPC_FRAME_N SERIRQ VCC0
4
5,43 LPC_FRAME_N LFRAME# CI18 120 Ohm@100MHz 300mA +/-25%
LPC_AD3 5 22 C5505 C5506 C5507 C5508 C9570
5,43 LPC_AD3 LAD3 VCC1 0.1uF 10V 10% I
LPC_AD2 7 3.3V 33 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10%
5,43 LPC_AD2 LAD2 VCC2 X7R X7R X7R X7R X7R 0402
5,43 LPC_AD1
LPC_AD1 8 LPC 96
LAD1 VCC3
LPC_AD0 10 125 C0402_N C0402_N C0402_N C0402_N C0402_N
EC_AGND FBI2
5,43 LPC_AD0 LPC_CLK_EC LAD0 VCC4 EC_AVCC I I I I I
2 1
12 67

C
R5510 5 LPC_CLK_EC PCICLK AVCC
6
100K CR5500 75 GPIO12_AC_DETECT GPIO04 120 Ohm@100MHz 300mA +/-25%
5% RB521C30 100mA 30v PLT_RST_N 13 69 EC_AGND I

A
R0402_N 7,26,27,43,74 PLT_RST_N GPIO05/PCIRST# AGND
SOD-923 38 11
I 5 PM_CLKRUN_N GPIO1D/CLKRUN# GND1
I SMC_RUNTIME_SCI_N 20 24
3 SMC_RUNTIME_SCI_N GPIO0E/SCI# GND2
29 EC_WRST#
EC_WRST_N 37
ECRST#
MISC GND3
35
94
VCC_IO2 GND4
C5510 +V3P3A_EC RI90 I 124 113
VCC_IO2 GND5
1uF 6.3V 10% 0R 0402
59 5%
BAT_PRES 1 1.8V/3.3V
X5R GPIO00/GA20 2/18 add connect to charger
0R 0402 5% RI15 2
C0402_N 7,43 SUS_CLK EC_CK32K 5 EC_KBRST# GPIO01/KBRST# +V3P3A_EC
100K 0402 1% I RI16 122
I GPIO5D/(XCLKI) 5/9 change to 200K ohm
CI27 20pF 50V 5% DIS
I 0402 121 63 VERSION_ID0 UMA
GPIO57/XCLK32K GPIO38/AD0 RI13 200K 1% R0402_N VERSION_ID0 RI20 10K 1% 0402
117 64 VERSION_ID1
7 AC_PRESENT GPXIOD06/GPIO7E GPIO39/AD1 +V3P3A_EC
123 65
GPIO5E/(XCLKO) GPIO3A/AD2 BAT_I 59
R10094 0R 5%R0402_N NI 127 66 3/16 add PU R
8,74 DGPU_HOLD_RST# GPIO59 GPIO3B/AD3 BATT_ID# 58
ADC 75
TPS2546_CTL1 42
GPIO42/AD4
R9901 0R 5%R0402_N I FLASH_SPI_MISO_EC 119 76 VERSION_ID1
5,24 FLASH_SPI_MISO GPIO5B/MISO GPIO43/AD5 ADP_I 59 RI21 549K 1%R0402_N I RI25 470k 1% R0402_N I
5,24 FLASH_SPI_MOSI R9902 0R 5%R0402_N I FLASH_SPI_MOSI_EC 120 73 SYS_PWROK
SYS_PWROK 7
GPIO5C/MOSI GPIO40/CIR_RX/AD6
5,24 FLASH_SPI_CLK R9903 0R 5%R0402_N I FLASH_SPI_CLK_EC 126 SPI 74
EC_TYPEC_CTL 55 R5513 R5512 R5528 R5527 R10081 R10082 R10101 R10102
GPIO58/SPICLK GPIO41/CIR_RLC_TX/AD7
5,24 FLASH_SPI_CS0_N R9904 0R 5%R0402_N I FLASH_SPI_CS0_N_EC 128 4.7K 4.7K 2.2K 2.2K 4.7K 4.7K 4.7K 4.7K 5/9 change to 549K ohm 5/9 change to 470K ohm
GPIO5A/SPICS# 5% 5% 5% 5% 5% 5% 5% 5%
68
GPIO3C/DA0 EC_ACDET 42 R0402_N R0402_N R0402_N R0402_N R0402_N R0402_N R0402_N R0402_N
21 70
6 ME_Flash_EN EC_BKLTEN GPIO0F/PWM0 GPIO3D/DA1 SRTCRST_EC 7
23 71 I I I I I I I I
GPIO10/PWM1 GPIO3E/DA2 USB_STATUS# 42
+V3P3A_EC 4/5 change pin 25 DAC 72
ALLSYSPWRGD 66
GPIO11/PWM2 GPIO3F/DA3
75 GPU_OVERT#
34 PWM
GPIO19/PWM3
26 77 SMB0_GFX_CLK_R R9812 0R 5%R0402_N I
30 EC_FAN_PWM1
30 EC_FAN_PWM2 27
GPIO12/FANPWM0
GPIO13/FANPWM1
GPIO44/SCL0
GPIO45/SDA0
78 SMB0_SMB3_GFX_DATA_R
SMB1_CHG_CLK_R
R9813 0R 5%R0402_N I
SMB0_GFX_CLK 75
SMB0_GFX_DATA 75
GFX
28 79 R9810 0R 5%R0402_N I
R10097
30
30
FAN_SPEED1
FAN_SPEED2
29
GPIO14/FANFB0
GPIO15/FANFB1
SM
GPIO46/SCL1/IEDI_SCL
GPIO47/SDA1/IEDI_SDA
80 SMB1_CHG_DATA_R R9811 0R 5%R0402_N I
SMB1_CHG_CLK 59
SMB1_CHG_DATA 59
Charger
100K 100
5% GPXIOA03/GPIO63/FANFB2/POWER_FAIL0 SMB2_THM_CLK_R
101 83 R10079 0R 5%R0402_N I
R0402_N 10,60 EC_ALW_EN GPXIOA04/GPIO64/FANFB3 GPIO4A/PSCLK1/SCL2/SMBD_CLK
GPIO4B/PSDAT1/SDA2/SMBD_DAT
84 SMB2_THM_DATA_R R10080 0R 5%R0402_N I
SMB2_THM_CLK 29
SMB2_THM_DATA 29
Thermal
I 32 85 SMB3_BAT_CLK_R R10083 0R 5%R0402_N I
SMC_RUNTIME_SCI_N
GPIO18/POWER_FAIL1
PS2
GPIO4C/PSCLK2/SCL3
GPIO4D/PSDAT2/SDA3
86 SMB3_BAT_DATA_R R10084 0R 5%R0402_N I
SMB3_BAT_CLK 58
SMB3_BAT_DATA 58
Battery
KSO0 39 87
TPS2546_CTL2 42
GPIO20/KSO0/HW TRAP GPIO4E/PSCLK3
KSO1 40 88 R10090 0R 5%R0402_N NI DGPU_PWR_EN 8,75
GPIO21/KSO1/HW TRAP GPIO4F/PSDAT3
C +V3P3A_EC KSO2 41
C
GPIO22/KSO2/HW TRAP
KSO3 42
GPIO23/KSO3/TP_EN
KSO4 43 97
GPIO24/KSO4 GPXIOA00/GPIO60/SHICS#/SDICS# +V3.3A_PWRGD 11,60
KSO5 44 98
CPPWR_EN 60
GPIO25/KSO5/UART_SOUT GPXIOA01/GPIO61/SHICLK/SDICLK
KSO6 45 SHDI 99
PM_BATLOW_N 7
5/24 change to NI GPIO26/KSO6/UART_SIN GPXIOA02/GPIO62/SHIDO/SDIDI
KSO7 46 109 PROCHOT_N
PROCHOT_N 3,59,66
GPIO27/KSO7/UART_RTS GPXIOD00/GPIO78/SHIDI/SDIDO/VCIN0 SLP_S4_N 10,60
R10100 KSO8 47 104
GPIO28/KSO8/UART_CTS GPXIOA07/GPIO67/VCOUT0 LID_INT_N 8,38
10K KSO9 48
5% GPIO29/KSO9/UART_CLK
KSO10 49 UART V C 102 D Q5500
R0402_N GPIO2A/KSO10 GPXIOA05/GPIO65/VCIN1 GC6_FB_EN_3.3 8,75
KSO11 50 103
EC_USB_PWR_EN 42 PJA138K
NI GPIO2B/KSO11/UART_DSR GPXIOA06/GPIO66/VCOUT1/PROCHOT_1#
KSO12 51 15 EC_PROCHOT EC_PROCHOT
I
GPIO2C/KSO12/UART_DTR GPIO08/PROCHOT_0# PWR_LED_N
PM_PWRBTN_R_N KSO13 52 IKB 14 G S
GPIO2D/KSO13/UART_DCD GPIO07
KSO14 53
GPIO2E/KSO14/UART_RI
KSO15 54 R5511
GPIO2F/KSO15/(E51_RXD)
81 10K
51 RECOVERY GPIO48/KSO16 5%
82 110
GPIO49/KSO17 GPXIOD01/GPIO79/AC_IN# AC_PRES 7,59 R0402_N
112
GPXIOD02/GPIO7A/ALW_PWE_EN# PWR_SWIN#
KSI0 55 PLC 114 I
GPIO30/KSI0/(E51_TXD)/HW TRAP GPXIOD03/GPIO7B/ON_OFF_BTN#
KSI1 56 115
GPIO31/KSI1 GPXIOD04/GPIO7C/LID_IN
KSI2 57 116
GPIO32/KSI2 GPXIOD05/GPIO7D/PLC_IN
KSI3 58
GPIO33/KSI3
KSI4 59 16
+V3P3A_EC GPIO34/KSI4/EDI_CS GPIO0A/OWM/RLC_RX2 PM_PWRBTN_R_N
GND KSI5 60 OWM 19
PM_PWRBTN_R_N 7
GPIO35/KSI5/EDI_CLK GPIO0D/RLC_TX2 GPU_ALERT
KSI6 61 108
GPIO36/KSI6/EDI_DIN GPXIOA11/GPIO6B/GWG
KSI7 62 GWG 118 PECI_EC
GPIO37/KSI7/EDI_DO GPIO7F/PECI PECI_EC 3
R10092 PECI
10K GND I
42 TPS2546_CTL3 89 30 TXD TP10006
5% CON_FPC32_PH0P8_H2_40815W90 GPIO50/(Ext.Lock) GPIO16/E51TXD LID_INT_N_TP
105 31 TP10007
7 SLP_S5_SOC
34

R0402_N GPXIOA08/GPIO68 GPIO17/E51_CLK/E51RXD


40815W90-32PN-SHL2ETCR 106 90
I 10,60 SLP_S3_N GPXIOA09/GPIO69 GPIO52 CAPS_LED# IMVP_PCH_PWRGD 7
32
46 EC_MUTE# 107 8051 91
GND2

PWR_SWIN# 32 GPXIOA10/GPIO6A GPIO53/E51TMR1/CAPSLED# EC_PWR_LED_W#


31 92
PWR_LED_N 31 GPIO54/E51TMR0/WDT_LED# EC_PWR_LED_W# 51
R10077 0R 5%R0402_N NI 30 93
OK_LED 51
30 GPIO55/E51INT0/SCROLED#
EC_PWR_LED_W# 29 95
R10078 0R 5%R0402_N I 29 GPIO56/E51INT1 RSMRST_N 7 +V3P3A
28 17
28 7 SLP_S4_SOC GPIO0B/ESB_CLK
27
27 7 SLP_S3_SOC
18
GPIO0C/ESB_DAT
ESB GPIO1A/NUMLED#
36
EC_CHAR_LED#_A 51
KSI1 26
26 1V8_AON
KSI7 25
25
KSI6 24
24 R10054
KSO9 23 KB9028Q C
23 10K
KSI4 22
22 2/21 change MOS 5%
KSI5 21 R0402_N
21
KSO0 20 2/17 change mos

G
20 I
KSI2 19
19 GPU_ALERT
KSI3 18
18 75 GPU_ALERT#
KSO5 17

D
17
KSO1 16
KSI0 15
16 QX14
15 PJA138K
KSO2
KB connector
14
14
KSO4 13 DIS
13
KSO7 12 12/29 power request pull high with EE
12
B KSO8 11 Populate for OVERT#/ALERT# 100% FAN RPM Control B
11 OVERT#/ALERT# = 1: PWM Controls Fan RPM
KSO6 10
10 +V3P3A +V3P3A OVERT#/ALERT# = 0: Fan RPM = 100%
KSO3 9
9
KSO12 8
8
KSO13 7
7
KSO14 6 R2015 R9878
3/16 Change to +V3P3A_EC 6
KSO11 5 100K 100K
5
KSO10 4 5% 5%
+V3P3A_EC 4
KSO15 3 R0402_N R0402_N
CAPS_LED# 3 I I
2
GND1

2 61 DDR_PWRGD
R9919 330R 1% 1
R0402 NI 1
63 V1.0_POK
2/17 change 330 ohm' J2
33

+V3P3A
6/20 Del MOS
R10107 330R 1%
R0402 I
GND

5/19 reserve V3P3A

Q8925
con_fpc4p_ph0p6_h1p55I
50505-00401-001 +V5P0A_KBL DMP3160L-7 -2.7A -30V
sot23_gsd
+V5P0A Touch Pad +V3P3SX_PAD
JBL1 +V3P3SX
8

I
SH8203 Power Supply Voltage 5.0 Volt ㊣ +V3P3SX_PAD
G2

4 D S 10% I
D

3 R9976 C9958 0R Power Supply Current:3 mA nominal R10106 FFC_6P_1MM_90_SMD_1P9MM_SL


41005W90- 6PN-SHL2ETBR
G

3 10K
100K 1uF 25V 10% I +V3P3SX_PAD

8
5%
G

2 5% X5R R0603_N
2 R0402_N 6
R0402_N C0603_N

GND2
5% 6
I I C9594 C8206 I
1 LID_INT_N_TP
1 +V3.3AL +V3.3AL 11,38,42,46,51,58,60 0.1uF 10V 10% 4.7uF 10V 10% 5
A X5R X5R 5 A
G1

+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,42,55,56,60,62,65,66,70 TOUCH_PAD_INT


R9975 C0402_N C0603_N 4
+V5P0A 8 TOUCH_PAD_INT 4
10K +V5P0A 10,11,37,54,61,62,63,65,66,67,69,70,75 I I
7

5% TOUCH_PAD_DAT0 3
+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,35,36,43,46,75 8 TOUCH_PAD_DAT0 3
3/16 Change Pin define R0402_N
I 1V8_AON 1V8_AON 74,75,76,79 TOUCH_PAD_CLK0 2
+V3P3SX_PAD 8 TOUCH_PAD_CLK0 2

GND1
Q8924 D
1
2N7002 250mA 60V 1
sot_323_dgs EC_BKLTEN R10044
R2520
I S G
R2521 J3 3/16 Change Pin define

7
4.7K R 0402
4.7K R 0402
4.7K R 0402
TOUCH_PAD_CLK0 I I
I
TOUCH_PAD_DAT0
TOUCH_PAD_INT
Project: 320S-13
Engineer: Jason
Size Title:EMBEDDED CONTROLLER Rev
D V01
Date: Tuesday, June 20, 2017 Sheet 50 of 81
5 4 3 2 1
5 4 3 2 1

+V3P3A_EC

R10099
10K
5%
R0402_N
DBSW1 I
D D
1 2
RECOVERY 50

3 DBC5
TS-1121E-2

1
DBCR5 0.1uF 10V 10%
I X5R
C0402_N
I
AZ5725-01F.R7GR 1uA 5V
DFN1006p2x

N O V O BT N

2
I

C C

+V3.3AL +V3.3AL 11,38,42,46,50,58,60 INTERNAL ONLY

Amber
Charger LED
LED3
R10053 330R 1% 2 1
R0402 I * EC_CHAR_LED#_A 50
LTST-C193KFKT-5A I
LED1 White
R9778 330R 1% 2 1
*
R0402 I OK_LED 50

B LTW-C193SN5 B
LED_0603
I

SYS LED

+V3.3AL

LED2 White
R9918 330R 1% 1 2
*
R0402 NI EC_PWR_LED_W# 50

LTW-C193SN5
LED_0603
+V3P3A I

R10108 330R 1%
R0402 I

5/19 reserve V3P3A

A A

Project: 320S-13
Engineer: Jason
Size Title:BUTTON & LED Rev
Custom V01
Date: Tuesday, May 23, 2017 Sheet 51 of 81

5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 52 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:NA Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 53 of 81

2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

R4619 0R
9,55 USB2_P2_WP1_OC_N
R0402_N I 5%

OCP_DET
+V5P0A +V5P0A_TypeC_SW 3/30 Remove reserve ESD
55 VBUS_EN

VMON
SH9520 GND

I
C
2
0
m
A
0R 5%

15
16

17
D R0603_N I U1
D

OCP_DET
VBUS_EN

VMON
CR100 CR101
220pF 50V 5% 220pF 50V 5%
NPO NPO
Swap P/N for USB3.1 GEN2 C0402_N C0402_N
SSRX/TX no via layout. I I
12 CC1
2/22 change to 5448 CC1 CC1 55
14 CC2
CC2 CC2 55
Zdiff=90ohm
Swap P/N for USB3.1 GEN2 11 C_TX2_N_C C4532 0.1uF 10V 10% X5R C0402_NI
SSRX/TX no via layout. C_TX2_1P/2N C_TX2_P_C C_TX2_N 55 B3
10 C4533 0.1uF 10V 10% X5R C0402_NI
C_TX2_1N/2P C_TX2_P 55 B2
C4530 0.1uF 10V 10% X5R C0402_NI USB3_P2_WP2_RX_C_DN 4 24 A10
9 USB3_P2_WP2_RX_DN USB3_P2_WP2_RX_C_DP SSRX_1P/2N C_RX2_1P/2N C_RX2_N 55
C4531 0.1uF 10V 10% X5R C0402_NI 5 1 A11
9 USB3_P2_WP2_RX_DP SSRX_1N/2P C_RX2_1N/2P C_RX2_P 55
C4518 0.1uF 10V 10% X5R C0402_NI USB3_P2_WP2_TX_C_DN
10Gbps 2:1 MUX C_TX1_N_C C4534 0.1uF 10V 10% X5R C0402_NI
6 8
9 USB3_P2_WP2_TX_DN USB3_P2_WP2_TX_C_DP SSTX_1P/2N C_TX1_1P/2N C_TX1_P_C C_TX1_N 55 A3
C4519 0.1uF 10V 10% X5R C0402_NI 7 9 C4535 0.1uF 10V 10% X5R C0402_NI
9 USB3_P2_WP2_TX_DP SSTX_1N/2P C_TX1_1N/2P C_TX1_P 55 A2
2
C_RX1_1P/2N C_RX1_N 55 B10
3
C_RX1_1N/2P C_RX1_P 55 B11
C C
Zdiff=90ohm

GPIO4 23 Realtek
GPIO
M1 21
CURRENT_M1 +V5P0A_TypeC_SW
M0 22 RTS5448
CURRENT_M0

P
o
w
e
r
S
w
i
t
c
h
H
i
g
h
E
n
a
b
l
e
VCON_IN
LDO_3V3
18 R4701

E-PAD

5V_IN
REXT
4.7K
R4700 5%
6.2K RTS5448-GR R0402_N

25

20

19

13
1% I +V5P0A_TypeC_SW NI
R0402_N 3/20 change net name +V5P0A_TypeC_SW VBUS_EN
I VBUS_EN 55
LDO_3V3
GND GND C4700 R4702
4.7uF 16V 10% 10K Power switch enable pin Note
X5R C4701 C4702 C10031 5%
C0603_N 0.1uF 10V 10% 0.1uF 10V 10% 10uF 6.3V 20% R0402_N Low Active R4701/R4702 mount
I X7R X7R X5R I
C0402_N C0402_N C0402_N High Active R4702 mount,R16 don't mount
B GND I I I GND B

For C_VBUS
GND
power switch enable pin

+V5P0A_TypeC_SW

O
C
P
L
o
w
E
n
a
b
l
e
R4703
4.7K
5%
R0402_N
LDO_3V3 LDO_3V3 I
+VBUS_TYPEC OCP_DET

R4708 R4706 R4704 Note


10K 10K R4710 10K Power switch OCP pin
5% 5% M1 M0 Note 200K1% 5%
R0402_N R0402_N R0402 R0402_N Low Active R4704/R4703 mount
A I I Rp:900mA 0 1 R11/R12 mount,R10/R13 don't mount I VMON I A
M1 M0 High Active R4704 mount,R4703 don't mount
Rp:1.5A 1 0 R10/R13 mount,R11/R12 don't mount GND
R4705
Rp:3.0A 1 1 R10/R12 mount,R11/R13 don't mount 10K
R4709 R4707 1% For C_VBUS
10K 10K R0402_N
5% 5% power switch OCP pin
I
R0402_N R0402_N
NI NI
Rp:1.5A (now) GND
GND GND

Rp configuration
+VBUS_TYPEC +VBUS_TYPEC 55 Project: 320S-13
+V5P0A_TypeC_SW +V5P0A_TypeC_SW 55
+V5P0A +V5P0A 10,11,37,50,61,62,63,65,66,67,69,70,75 Engineer: Jason
Size Title:TYPE-C Switch Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 54 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

+VBUS_TYPEC

+V5P0A_TypeC_SW
+VBUS_TYPEC
CC1
5/22 change to 100uF C4301 C10004 C10006

0.1uF 10V 10%


D
CC2 0.1uF 25V 10% 10uF 25V 10% 10uF 25V 10%
C10007 C10005 1.5A~3A/Stack Port D
100uF 6.3V +/-20%
X5R
X5R X5R

+
1

1
CR9055 CR9056 CR9057 SMD3.5X2.8mm X5R +V3P3A
C0402_N
C0805 C0805
C0402_N
I
I I
I
R10085 U9003
AZ5725-01F.R7GR 1uA 5V AZ5725-01F.R7GR 1uA 5V AZ5725-01F.R7GR 1uA 5V 100K 6 1
DFN1006p2x DFN1006p2x DFN1006p2x 5% IN OUT

2
I I I R0402_N
I
3 5
9,54 USB2_P2_WP1_OC_N FLAG SET
R10020 R10021
8.2K 21K
4 2
54 VBUS_EN EN GND 5% 1%
R0402_N R0402_N
G518B1TP1U I I DC ONLY : OCP SET TO 1.5A
I
AC IN: OCP SET TO 3A
D
Q8211
2N7002KW 115mA 60V
R10024 1K R0402_N
G
50 EC_TYPEC_CTL I 5%
sot_323_dgs
R10026 I
54 C_TX2_N
C 0R 5% S C
R0402_N NI
L9509 SSTX2-_CONN
A1 A2

B1 B2 SSTX2+_CONN
67ohm 320mA +-25% DP_CON
CO-CH_L4_PH0P8_H1_AB
R10027 I DM_CON
54 C_TX2_P
0R 5% CR9515

10
9
7

6
R0402_N NI
R10028 SSRX2-_CONN

NC
NC

NC
NC
54 C_TX1_N SSRX2+_CONN
0R 5%
R0402_N NI
SSRX1+_CONN
L9510 I
SSTX1-_CONN 1 I/O1 I/O3 4
B1 B2
SSRX1-_CONN 2 I/O2 I/O4 5

A1 A2 SSTX1+_CONN CR9048

10
9
7

6
67ohm 320mA +-25%
CO-CH_L4_PH0P8_H1_AB

NC
NC

NC
NC

GND

GND
R10029
54 C_TX1_P ESD5344D
0R 5%

3
B R0402_N NI 1 4 DFN10_PH0P5_ESD B
I/O1 I/O3
R10030 2 I/O2 I/O4 5 EMC_I
54 C_RX2_N
0R 5%
R0402_N NI I
<PACKAGE>
L9511 USB11126-A5A0B-1H

GND

GND
A1 A2 SSRX2-_CONN

ESD5344D +VBUS_TYPEC +VBUS_TYPEC


B1 B2 SSRX2+_CONN 18

3
DFN10_PH0P5_ESD GND_10
67ohm 320mA +-25% 17 GND_9 22
CO-CH_L4_PH0P8_H1_AB EMC_I 16 GND_14 21
GND_8
R10031 I 15 GND_7
GND_13 20
54 C_RX2_P SSTX2-_CONN 14 GND_12 19
0R 5% GND_6
13 GND_11
R0402_N NI SSTX2+_CONN GND_5
R10032 SSTX1-_CONN
54 C_RX1_N
0R 5%
SSTX1+_CONN A12 GND_2 GND_3
B1
R0402_N NI SSRX2+_CONN A11 B2 SSTX2+_CONN
SSRXp2 SSTXp2
L9512 CR9050 SSRX2-_CONN A10 B3 SSTX2-_CONN
SSRX1-_CONN SSRXn2

10
A1 A2 SSTXn2

9
7

6
A9 VBUS_2 B4
VBUS_3
SBU1

NC
NC

NC
NC
A8 B5
B1 B2 SSRX1+_CONN RFU1 CC2 CC2 54
DM_CON A7 Dn1 B6 DP_CON
67ohm 320mA +-25% DP_CON Dp2
DM_CON
A6 Dp1 B7
CO-CH_L4_PH0P8_H1_AB Dn2
A5 CC1 B8 SBU2
R10033 I 1 I/O1 I/O3 4 54 CC1 RFU2
A4 VBUS_1 B9
54 C_RX1_P 2 I/O2 I/O4 5
SSTX1-_CONN VBUS_4
SSRX1-_CONN
A 0R 5% A3 SSTXn1 SSRXn1
B10 A
R0402_N NI SSTX1+_CONN A2 SSTXp1 B11 SSRX1+_CONN
SSRXp1
R10034 A1 GND_1 GND_4
B12

GND

GND
0R 5%
R0402_N I
ESD5344D J1
L9513
8

3
A1 A2 DM_CON DFN10_PH0P5_ESD 2/22 change CONN
9 USB2_P2_WP2_DN
EMC_I
B1 B2 DP_CON
9 USB2_P2_WP2_DP
67ohm 320mA +-25%
CO-CH_L4_PH0P8_H1_AB
R10035 NI

0R
R0402_N
5%
I +VBUS_TYPEC +VBUS_TYPEC 54
Project: 320S-13
+V5P0A_TypeC_SW +V5P0A_TypeC_SW 54 Engineer: Jason
Size Title:TYPE-C CONN Rev
Custom V01
Date: Wednesday, May 24, 2017 Sheet 55 of 81
8 7 6 5 4 3 2 1
<XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

+1.8V_PRIM +V3P3A
+V3P3A
R9859 CIS ok
D
R9858 0R
0R R0402

G1
D
R0402 5% JUART1
R9720 R9721 5% I

SH1
49.9K 49.9K I +V3P3A_UART 6 40506W90-6PA-SHLOATCR
1% 1% 6 CON_FPC6p_PH0P5_H1P2_50696
R0402_N R0402_N +V1P8A_UART 5 NI
I I 5

R9856 0R R0402 5% I UART2_TXD_R 4


8 UART2_TXD 4
2/24 SIV:JUART1 uninstall
R9857 0R R0402 5% I UART2_RXD_R 3
8 UART2_RXD 3

2
2

1
1

SH2
DEBUG

G2
+V3P3A
+1.8V_PRIM
+V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,42,50,55,60,62,65,66,70
+1.8V_PRIM 10,11,65 CONN
C C

Shielding Holes 3/30 chnage screw

HOLE1 HOLE2 HOLE3 HOLE6 HOLE7 HOLE8 HOLE11 HOLE19


MHT6B6D2P8 MHT6B6D2P8 MHT6B6D2P8 MHT6B6D2P8 MHT6B6D2P8 MHT6B6D2P8 MHT6B6D2P8 MHT6B6D2P8
CLIP2 CLIP3 CLIP4 NI NI NI NI NI NI NI NI
Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000
pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I

2
.
8
m
m
1
2
3

1
2
3

1
2
3

PTH PTH PTH PTH PTH PTH PTH PTH


1
2
3

1
2
3

1
2
3

1
CLIP14 CLIP15
Z00L-4G7U1-11000 Z00L-4G7U1-11000
pbzjz_4x1_3p I pbzjz_4x1_3p I
HOLE9
B HOLE5 HOLE4 B
mthO290X240D180X130
1
2
3

1
2
3
MHT6B6D3P5 NI MHT6B6D3P3 HOLE12
NI NI MTHT8B8D7P5
1
2
3

1
2
3
NI

CLIP18 CLIP19 CLIP20 CLIP21 CLIP22 CLIP23 CLIP24 PTH


Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 PTH PTH
pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I PTH
1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3
1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
1

1
CLIP25 CLIP26 CLIP27 CLIP28 CLIP29 CLIP30 CLIP31 CLIP32
Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000 Z00L-4G7U1-11000
pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I pbzjz_4x1_3p I 5/3 change to DIS

HOLE13 HOLE14 HOLE15 HOLE16 HOLE17 HOLE18


1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

THC188D118 THC188D118 THC188D118 THC188D118 THC188D118 MHT6B6D2P8H2_SMD


1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

I I I DIS DIS I

A A
PTH PTH PTH PTH PTH PTH

1
Project: 320S-13
Engineer: Jason
Size Title:UART CONN & HOLE & CLIP Rev
Custom V01
Date: Friday, May 12, 2017 Sheet 56 of 81
8 7 6 5 4 3 2 1
Rev
V01
81 of
320S-13
Jason

57
Sheet
Engineer:
Project:

HW Change list
Monday, April 10, 2017
Title:
Size

Date:
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LC CCTIrCA
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o
N1234567891
0
5 4 3 2 1

1 1

58: BATTERY CONNECTOR

BATT+

D5801
1N4148WS 200mA 100V
SOD_323
I

5A

11
12
2 2
R5803 1

SH3
SH4
1
100R 5%
+V3.3AL R0402 2
2
I BATT_CLK 3
50 SMB3_BAT_CLK 3
BATT_DAT 4
50 SMB3_BAT_DATA 4
R5804
BATT_TS
5/9 change to 100K 100K
1%
R5802 5
5
R0402_N
100R 5%
I
R0402 6
6
I 7
50 BATT_ID# 7
BATT+ BATT+ 59
R5801

SH1
SH2
8
8
100R 5% +V3.3AL +V3.3AL 11,42,46,50,51,60
R0402

9
10
I CN5801 DCIN DCIN 59
WWAA1208-1D00
wtb_8p_1d25_h2d0_dip
I

3 3

CN5802
50278-0040N-001
CON_WTB4_PH1P25_H1P9_W1251
I

G1
DCIN

3A

PAD2
4
4

3
3

2
2
C5801
0.1uF 25V 10%
1
X7R

PAD1
1
C0603
I
2/16 change CONN

G2

4 4

Project: 320S
Engineer: Frank
Size Title: Rev
C
BATT CONN V01
Date: Tuesday, June 20, 2017 Sheet 58 of 81
5 4 3 2 1
A B C D

59: BATTERY CHARGER

Q5901
PK5C8EA 82A 30V Q5902 R5903 Q5903
+VSYS
1 1

PPAK5x6 PE5E4BA 20A 30V 0.01R 1% PE5E4BA 20A 30V


I powerpak5_1212_1p12 R1206 powerpak5_1212_1p12
I I I

D
D

S
5 3 1 2
DCIN 2
1

4
R5901 R5902

CHG_CSIP_R
G
G

G
4.7R 5% 4.7R 5% 4
R0603 R0603
I I
JP5901 C5913
JUMP 0.1uF 25V
R5906 R5907 JUMP_43X118 X5R
C5901 0R 5% 2R 1% NOBOM C0402
2.2uF 25V R0402 R0402 NI
X5R I I 1 2
C0402 R5904 R5905
I 4.02K 1% 4.02K 1%
R0402 R0402 C5910 C5911 R5929
I I 10uF 25V 10uF 25V 0R 5%
X5R X5R R0402
C0603 C0603 I
C5902 C5903 I I
0.1uF 25V 0.22uF 10V R5908
X5R X5R 100R 5%
C0402 C0402 R0402
DCIN I I I
BATT+ DCIN DCIN 58

+VSYS +VSYS 36,60,61,63,67,70

BATT+ BATT+ 58
CHG_CMSRC
2
R5910 +V3P3A_EC +V3P3A_EC 50,51 2

10K 5%
R0402 CHG_ASGATE
I

CHG_BGATE
CHG_QPCN

CHG_QPCP

CHG_VBAT
R5909

CHG_CSIN
CHG_CSIP
3M 5% D5903
R0402 1N4148WS +VSYS DCIN
I SOD_323
I

32

31

30

29

28

27

26

25
D D5901 R5912 AC Det 5 6 7 8 9

CHG_BOOT_R
1N4148WS 392K 1% C5914

VBAT
CSIP

ASGATE

QPCP

BGATE
CSIN

CMSRC

QPCN
Max:18.16V
Q5904 SOD_323 R0402 Typ :17.98V R5930 0.22uF 25V Q5905
2N7002 250mA 60V I I 0R 5% X5R D
PE636BA 33A 30V
G
sot_23_dgs Min :17.8V R0603 C0402 dfn8p_ph0p65_3p3X3p3_h0p8
S
I CHG_ACIN 1 24 CHG_BOOT
I I 4 G
S
I
ACIN BOOT
R5911 R5935
1M 5% CHG_ACOK CHG_UGATE 1 2 3 L5901 0.01R 1%
R0402 2
ACOK UGATE
23
4.7uH 6.5A R1206
I +VSYS +V3P3A_EC C5904 R5913 7X7X3 I
0.01uF 16V 49.9K 1% CHG_SDA CHG_PHASE
I
X7R R0402 3
SDA PHASE
22 1 2
BATT+
C0402 I
I CHG_SCL CHG_LGATE
4
SCL LGATE
21
R5938

4
U5901 5 6 7 8 9 2.2R 5%
Change to EC VCC R5914 CHG_PROCHOT#
ISL95521AHRZ CHG_VDDP
R0805
100K 5% 5
QFN32_PH0P4_4X4_H0P9 20
NI C5922 C5923

CHG_CSOP_R
PROCHOT# VDDP
R0402 I D
CHG_SNUB
10uF 25V 10uF 25V
I CHG_AMON CHG_VDD
X5R X5R
7,50 AC_PRES 6
AMON VDD
19 4 G
C5917 C0603 C0603
R5915 0R 5% R0402 I S
2.2nF 50V I I
50 SMB1_CHG_DATA CHG_BMON CHG_DCIN
R5931 X7R
7
BMON DCIN
18
4.7R 5% 1 2 3 C0603
R5916 0R 5% R0402 I R0402 NI
50 SMB1_CHG_CLK
I
3 8
PSYS NTC
17
C5915 C5916 3

R5917 0R 5% R0402 I 1uF 10V 1uF 10V Q5906 R5936 R5937

CHG_NTC
3,50,66 PROCHOT_N X5R X5R PE636BA 33A 30V 2R 1% 0R 5%
33
GND BATGONE C0402 C0402 dfn8p_ph0p65_3p3X3p3_h0p8 R0402 R0402
R5918 0R 5% R0402 I I I I I I
CCLIM

ACLIM
COMP
PROG

CSON

CSOP
FSET

50 ADP_I
R5919 0R 5% R0402 I HPB
9

10

11

12

CHG_BATGONE 13

14

15

16
50 BAT_I 3‐CELL R5934
100K1% R5932
CHG_CCLIM

CHG_ACLIM
CHG_COMP
CHG_PROG

CHG_CSON

CHG_CSOP
R5920 0R 5% R0402 I RS1=10mohm R0402 4.7R 5% C5919 C5920
CHG_FSET

CHG_PSYS
66 PSYS
RS2=10mohm I R0603 0.1uF 25V 0.1uF 25V
I X5R X5R
C0402 C0402
I NI
C5905 C5906
2200pF 50V 2200pF 50V R5925
X7R X7R 182K1% R5927 R5933
C0402 C0402 R0402 102K1% 4.7R 5%

3
I I I R0402 R0603
I I D5902
C5918 BAT54C 200mA 30V
1uF 25V SOT_23
CHG_VDD
R5926 X5R I
C5907 100R1% C0402

1
560pF 50V R0402 I
X7R I
C0402
R5921 R5922 I C5908
200K1% 200K1% 0.022uF 25V BATT+ DCIN
R0402 R0402 X7R
I I C0402
I

Charging current X 1.5


4 4

Adapter rating X 1.1

BAT_PRES 50
R5923 R5924
115K 1% 68.1K 1% R5928
R0402 R0402 100K5%
I I R0402
C5909 NI
R5939 10pF 50V
100K 5% NPO
R0402 C0402 Project: 320S
I NI
Engineer: Frank
Size Title: Rev
C
CHARGER V01
Date: Monday, June 05, 2017 Sheet 59 of 81
A B C D
5 4 3 2 1

60: +V5P0A / +V3P3A POWER SUPPLY


D D

R6001
2R2 5%
R0402
I V5A_BST_R

V5A_BST
C6006 L6001 JP6002
JP6001 0.22uF 25V 0.68uH 15.5A 20% JUMP
JUMP X5R SML6673_H3 JUMP_43X118

12

8
JUMP_43X118 C0402 I NOBOM
NOBOM IV5A_SW

BST
ENLDO
7 1 2 V5A_OUT 1 2
1 2 V5A_VSYS 1
SW +V5CP
+VSYS VIN V5A_OUT
VOUT
5
C6010 C6011 C6012 C6013
C6001 C6002 C6003 C6004 R6003 22uF 6.3V 22uF 6.3V 22uF 6.3V 22uF 6.3V Imax=6A
C6005 10uF 25V 10uF 25V 10uF 25V 10uF 25V 4
NC C6009 2.2R 5% X5R X5R X5R X5R
68uF 25V X5R X5R X5R X5R U6001 0.1uF 10V R0805 C0603 C0603 C0603 C0603
+

ct_7p3x4p3x2p8 C0603 C0603 C0603 C0603 NB679GD X5R NI I I I I


NI NI I I I QFN12_PH0P5_2X3_H1 C0402
I I
5CP_EN
2
PGND C6031
11
EN
2017/3/8 2.2nF 50V 5%

1
V5A_LDO
JS6005 X7R
6
SHORT PAD C0603

21
LDO
NOBOM NI
C6007 60X30Mil

2
C6033 C6034 C6035 C6036 0.1uF 25V C6015 C6016 C6017 C6018

VCC
10

PG
AGND
1uF 25V 1uF 25V 1uF 25V 1uF 25V X5R 5V_AGND 22uF 6.3V 22uF 6.3V 22uF 6.3V 22uF 6.3V
X5R X5R X5R X5R C0402 X5R X5R X5R X5R

V5A_VCC 9
C0402 C0402 C0402 C0402 I C0603 C0603 C0603 C0603
NI I I I I I I I
C C

C6008
1uF 10V
X5R
10,50,60 EC_ALW_EN 1
C0402
5CP_EN
I
3
R6006
2R2 5%
50 CPPWR_EN 2
R6023 R0402
10K 1% I V3.3A_BST_R
D6601 R0402
I
BAT54C 200mA 30V R6024

V3.3A_BST
SOT_23 10K 1%
I R0402
I
C6022 L6002 JP6004
JP6003 0.22uF 25V 1.5uH 9.5A 20% JUMP
JUMP X5R SML6673_H3 JUMP_43X118

12

8
JUMP_43X118 C0402 I NOBOM
NOBOM IV3.3A_SW

BST
ENCLK
7 1 2 V3.3A_OUT 1 2
1 2 V3.3A_VSYS 1
SW +V3P3A
+VSYS VIN V3.3A_OUT
C6026 C6027 C6028 C6039 C6040
22uF 6.3V Imax=6A
5
VOUT
R6007 22uF 6.3V 22uF 6.3V 22uF 6.3V 22uF 6.3V
4
CLK C6025 2.2R 5% X5R X5R X5R X5R X5R
C6019 C6020 U6002 0.1uF 10V 10% R0805 C0603 C0603 C0603 C0603 C0603
10uF 25V 10uF 25V NB680GD X5R NI I I I NI NI
X5R X5R QFN12_PH0P5_2X3_H1 C0402
C0603 C0603 I I
I I V3.3A_EN
2
PGND C6032
11
EN
2017/3/8 2.2nF 50V

1
JS6006 X7R
+V3.3AL 6
SHORT PAD C0603

21
LDO V3.3A_EN
NOBOM NI 29 SHUTDOWN#
C6023 60X30Mil

2
4.7uF 10V R6011 R6012 C6030
VCC

10
PG

B AGND B
C6037 C6038 X5R 3.3V_AGND 0R 5% R6008 0R 5% 100pF 50V
1uF 25V 1uF 25V C0603 R0402 10K 1% R0402 NPO
3

V3.3A_VCC 9

X5R X5R I +V3.3AL I R0402 I C0402


C0402 C0402 I KBC_PWR_ON_PWR
NI
I I 10,50,60 EC_ALW_EN

R6010 R6009
100K5% 10K 1% R6014
R0402 R0402 0R 5%
I C6024 I R0402
11,50,60 +V3.3A_PWRGD 1uF 10V NI
X5R 61,62 SLP_S4#_3R_PWR +V3.3AL
C0402
I R6015
10,50 SLP_S4_N 0R 5%
R0402
HOLE6001 HOLE6002 R6016 NI
pth_ob28x60dob18x50 pth_ob28x60dob18x50 1K 5%
NOBOM NOBOM R0402
I
61 SLP_S3#_3R_PWR

+VSYS +VSYS 36,59,61,63,67,70 R6017


PTH PTH 10,50 SLP_S3_N 0R 5%
+V3.3AL +V3.3AL 11,42,46,50,51,58 R0402
R6018 NI
+V5CP +V5CP 10,42 1K 5%
R0402
+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,38,42,50,54,55,56,62,65,66,70 I
1

65 +V3.3A_PWRGD_R

R6019
11,50,60 +V3.3A_PWRGD 0R 5%
V5A_VSYS R0402
R6020 NI
1K 5%
R0402
A I A
63 +1.8V_PWRGD_R

R6021
65 +1.8V_PWRGD 0R 5%
R0402
R6022 NI
1K 5%
R0402
I 5CP_EN
Project: 320S
R6025
0R 5% Engineer: Frank
R0402
NI Size Title: Rev
C
System Power V01
Date: Tuesday, June 27, 2017 Sheet 60 of 81
5 4 3 2 1
5 4 3 2 1

D D

61: DDR POWER SUPPLY

JP6102 +V5P0A +V5P0A 10,11,37,50,54,62,63,65,66,67,69,70,75


JUMP Imax=0.5A
43X39 +V0.6S_VTT +V0.6S_VTT 19,20,21
1
NOBOM2
1 2 +V0.6S_VTT +V1P2U_VDDQ +V1P2U_VDDQ 4,10,19,20,21

DDR_BST_R_P
C6102 JS6103 2017/3/8 +VSYS +VSYS 36,59,60,63,67,70
+VSYS 10uF 6.3V SHORT PAD
X5R 60X30Mil
C6100 C6101 R6100 C0603 NOBOM
22uF 6.3V 0.1uF 25V 0R 5% I 2
21
1
C6104
1

X5R X7R R0402 0.1uF 10V


JP6100 C0603 C0603 I C6103 X5R
1

JUMP I I 10uF 6.3V C0402

DDR_VTT_20
DDR_BST_P
DDR_LX_20
C 43X39 X5R C0603 I C
NOBOM I R6102
2

6.04K 1%
2

R0402
SGND_DDR I DDR_OUT

DDR_VTTREF_10

DDR_VDDQSNS
C6107 C6117

25

26

27

28

29

31

30

35
4
1uF 25V 1uF 25V
X5R X5R R6103

BST

VTT

VTTSNS
LX4

VTTGND2

VTTGND1
NC

VLDOIN

VTTGND
1

JS6100 C0402 C0402 34


V+4 10K 1%
SHORT PAD I I R0402
21

10X8Mil +VSYS_DDR
I
NOBOM 24
V+3 GND
32
2

SM_PG_CTRL 4
C6105 C6106
10uF 25V 10uF 25V 23
V+2 VTTREF
1 SGND_DDR SGND_DDR R6109
X5R X5R 0R 5%
C0603 C0603 R0402
I I 22
V+1 VDDQSNS
2
I
SLP_S3#_3R_PWR 60
JP6101 L6100 U6100
JUMP 1.0uH 12A +/-20% 21
V+ G5388K11U VDDQSET
3
C6108 R6104
JUMP_43X118 LCHK_6P6x6P6x3_5P35 tqfn_P04_32P_4X4_H1MM 0.1uF 10V 0R 5%
NOBOM DDR_OUT
I DDR_LX_P
I DDR_S3
X5R R0402
+V1P2U_VDDQ
1 2 20
LX3 S3
5
C0402 NI
NI
C6109 C6110 C6111 DDR_S5
Imax=6A 22uF 6.3V 22uF 6.3V 470pF 50V 19
LX2 S5
6
SLP_S4#_3R_PWR 60,62
JP6104 X5R X5R X7R
JUMP C0603 C0603 C0603 DDR_TON +VSYS_DDR
R6105
JUMP_43X118 I I I 18
LX1 TON
7
C6112 0R 5%
NOBOM DDR_SNB 0.1uF 10V R0402
1 2
R6106 X5R I
17
LX PGOOD
8
511K 1% C0402
R0402 NI
R6101 I
C6114 C6115 2.2R 5%
PGND5

PGND4

PGND3

PGND2

PGND1
33

PGND
LX5 DDR_PWRGD 50
22uF 6.3V 22uF 6.3V R0805

VCC
CS
B B
X5R X5R I R6107
C0603 C0603 10R 5%
16

15

14

13

12

11

10

9
I I R0603
DDR_VCC
I
+V5P0A
DDR_CS

R6108
5.11K 1% C6116
R0402 1uF 10V
I X5R
C0402
I

SGND_DDR

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C
DDR Power V01
Date: Wednesday, May 31, 2017 Sheet 61 of 81
5 4 3 2 1
5 4 3 2 1

D
62: +V2P5U_VPP POWER SUPPLY D

+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,38,42,50,54,55,56,60,65,66,70

+V5P0A +V5P0A 10,11,37,50,54,61,63,65,66,67,69,70,75


+V3P3A
+V2P5U_VPP +V2P5U_VPP 19,20,21

U6201
C6201 G9661-25ADJF11U
10uF 6.3V SOP8_PH1P27_4X5_H1P6_G1
X5R I
C0603
I 2.5V_VIN 3 1
VIN POK
2.5V_EN 2 6 2.5V_OUT 1 2
60,61 SLP_S4#_3R_PWR VEN VO 1 2 +V2P5U_VPP
2.5V_ADJ
R6201 C6202 5
NC ADJ
7
C6204 JP6201
0R 5% 1uF 10V 2.5V_VPP
R6202 10uF 6.3V JUMP
R0402 X5R +V5P0A 4
VPP GND
8
21.5K 1% X5R 43X39 Imax=0.5A
I C0402 R0402 C0603 NOBOM

TP
NI I I
C6203

9
1uF 10V R6203
X5R 10K 1%
C0402 R0402
I I
C C

B B

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C +V2P5U_VPP V01
Date: Thursday, June 01, 2017 Sheet 62 of 81
5 4 3 2 1
5 4 3 2 1

D D

63: +1.0V_PRIM POWER SUPPLY


R6301 R6308
10R 5% 0R 5%
R0603 R0603
I I
+V5P0A
C6300 C6302
1uF 10V 0.1uF 25V
X5R X7R
C0402 C0603
I I

V1.0_BOOT
V1.0_VCC
V1.0_VIN
C6301

V1.0_SS
V1.0_LX
0.01uF 25V
V1.0_AGND X7R
C0402
I

23

22

21

20

19

18

25
C C
60 +1.8V_PWRGD_R

BST
SS

VIN2

PGND4

LX4

LX5
VCC
R6302
0R 5%
R0402 C6303 50 V1.0_POK
1
PGOOD LX3
17
I 1uF 6.3V
X7R V1.0_EN
C0402 2
EN LX2
16
NI
V1.0_PFM
+V5P0A 3
PFM# U6300 PGND3
15
G5335QT1U
R6309 R6303 TQFN23_PH0P5_4X4_H0P8
0R 5% 100K 5% V1.0_AGND 4
AGND I PGND2
14
JP6300
R0402 R0402 JUMP
NI I V1.0_FB
JUMP_43X118
5
FB PGND1
13
NOBOM
V1.0A_OUT
6 12
1 2
+1.0V_PRIM
TON PGND0
V1.0_AGND
Imax=8A

VIN0

VIN1

VIN3

LX0

LX1
NC
7

24

10

11
1 2
12

2017/3/8 L6300
JS6302 1.0uH 12A +/-20%
SHORT PAD LCHK_6P6x6P6x3_5P35
60X30Mil V1.0_TON V1.0_LX
I
NOBOM V1.0_AGND
C6304 C6305 C6306 C6307
R6304 R6307 R6305 22uF 6.3V 22uF 6.3V 22uF 6.3V 22uF 6.3V
80.6K 1% 2.2R 5% 2.55K 1% X5R X5R X5R X5R
R0402 R0805 R0402 C0603 C0603 C0603 C0603
I I I I I I I
B B
1 2 V1.0_VIN
+VSYS 1 2
C6312 R6306
JP6303 470pF 50V 10.2K 1%
JUMP C6309 C6310 C6311 C6317 X7R R0402 C6313 C6314 C6315 C6316
43X39 10uF 25V 10uF 25V 1uF 25V 1uF 25V C0603 I 22uF 6.3V 22uF 6.3V 22uF 6.3V 22uF 6.3V
NOBOM X5R X5R X5R X5R I X5R X5R X5R X5R
C0603 C0603 C0402 C0402 C0603 C0603 C0603 C0603
I I I I I I I I
V1.0_AGND

+VSYS +VSYS 36,59,60,61,67,70

+V5P0A +V5P0A 10,11,37,50,54,61,62,65,66,67,69,70,75

+1.0V_PRIM +1.0V_PRIM 10,11,14,75

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C
+1.0V_PRIM V01
Date: Wednesday, May 31, 2017 Sheet 63 of 81
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C
NA V01
Date: Monday, May 15, 2017 Sheet 64 of 81
5 4 3 2 1
5 4 3 2 1

D
65: +1.8V_PRIM POWER SUPPLY D

+V3P3A

+V3P3A
U6501
C6501 G9661-25ADJF11U
10uF 6.3V SOP8_PH1P27_4X5_H1P6_G1 R6502
X5R I 100K 5%
C0603 R0402
I 1.8V_VIN 3 1
I
VIN POK +1.8V_PWRGD 60
1.8V_EN 2 6 1.8V_OUT 1 2
60 +V3.3A_PWRGD_R VEN VO 1 2 +1.8V_PRIM
1.8V_ADJ
R6501 C6502 5
NC ADJ
7
R6503 C6504 JP6501
0R 5% 1uF 10V 1.8V_VPP
12.7K 1% 10uF 6.3V JUMP
R0402 X5R +V5P0A 4
VPP GND
8
R0402 X5R 43X39
I C0402 I C0603 NOBOM

TP
NI I
C6503

9
C 1uF 10V R6504 C
X5R 10K 1%
C0402 R0402
I I

+V3P3A +V3P3A 3,4,5,6,7,8,9,10,11,24,29,35,37,38,42,50,54,55,56,60,62,66,70

+1.8V_PRIM +1.8V_PRIM 10,11,56

B B

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C
+1.8V_PRIM V01
Date: Thursday, June 01, 2017 Sheet 65 of 81
5 4 3 2 1
5 4 3 2 1

D D

66: CPU POWER SUPPLY


C6602
1000pF 50V
X7R C6603
Local sense in EE side R6602 C0402 0.01uF 25V R6604
0R 5% I X7R 1K 1%
R0402 C0402 R0402
I I I
10 VCCSA_SENSE
R6605 C6601 R6603 1.87K 1% R0402 I
0R 5% 1000pF 50V
R0402 X7R
I C0402 R6606 1K 1% R0402 I C6604
I 15pF 50V
10 VSSSA_SENSE
NPO
C0402
R6610 I
C6605 20K 1% R6608 C6606
R6611 59 PSYS 1000pF 50V R0402 16.5K 1% 1000pF 50V
0R 5% X7R I R0402 X7R
R0402 C0402 I C0402
I I I

PSYS
12 VCCSENSE CSN_SA 67

1
R6612 C6607 R6613 C6635
0R 5% 1000pF 50V 1K 1% 2200pF 50V C6608 C6609 RT6603

NTC
R0402 X7R R0402 R6665 X7R 10nF 50V 3300pF 50V R6615 100K(NTC) 1%
I C0402 I 10R 1% C0402 X7R X7R 14K 1% R0402
C I R0402 I C0402 C0402 R0402 I C
12 VSSSENSE
I I I I
+V3P3A

2
R6618
C6610 60.4K 1%
1000pF 50V R0402 SW_SA 67
R6617 X7R I R6616 R6659
49.9R 1% C0402 7.5K 1% 10K 5%
R0402 R6619 I R0603 R0402
I 1K 1% I I
R6661 RT6601 C6612 R0402 C6611
174K 1% 100K(NTC) 1% 270pF 50V I C6613 470pF 50V VR_PWRGD 7,29
R0603 R0402 X7R 470pF 50V COG ALLSYSPWRGD 50 +1.0V_VCCST
NI I C0402 R6658 COG C0402 R6660 0R 5% R0402 I
CSP2_IA 2 1 I 28K 1% C0402 I R6627
NTC R0402 I 7.5K 1%

49

48
47
46
45
44
43
42
41
40
39
38
37
R6628 C6614 R6620 I PWM_SA 67 C6619 R0603 R6625
174K 1% 10pF 50V 3K 1% R6624 R6626 R6621 C6617 470pF 50V I 14K 1%

TAB

VSN_2ph
VSP_2ph
PSYS
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
VR_RDY
EN
R0603 NPO R0402 DRVON 67 45.3R 1% 75R 1% 100R 1% 0.1uF 16V COG R0402
I C0402 I R0402 R0402 R0402 X5R C0402 I SW_GT 67
CSP1_IA I C6615 1 36 I NI I C0402 I
IOUT_2ph PWM_1b
R6630 3300pF 50V 2 35 I
DIFFOUT_2ph DRVON

1
R6622 R6623 C6616 C6618 11K 1% X7R 3 34 R6629 49.9R 1% R0402 I
FB_2ph SCLK SOC_SVID_CLK 12
R6634 165K 1% 73.2k 1% 390pF 50V 1000pF 50V R0402 C0402 4 33 R6631 0R 5% R0402 I R6635 C6620 C6621 RT6604
COMP_2ph ALERT# SOC_SVID_ALERT#_R 12

NTC
10R 1% R0402 R0402 X7R X7R I I 5 32 R6632 10R 1% R0402 I 32.4K 1% 10nF 50V 2200pF 50V 100K(NTC) 1%
ILIM_2ph SDIO SOC_SVID_DAT 12
R0402 I I C0402 C0402 6 U6601 31 R6633 75R 1% R0402 I R0402 X7R X7R R0402
CSCOMP_2ph VR_HOT# PROCHOT_N 3,50,59
I I NI 7 NCP81208MNTXG 30 I C0402 C0402 I
CSSUM_2ph IOUT_1a
8 QFN48_PH0P4_6X6_H1_G1 29 I I
CSREF_2ph CSP_1a

2
67 CSN1_IA 9 I 28
CSP2_2ph CSN_1a CSN_GT 67
R6662 C6634 C6622 10 27
CSP1_2ph ILIM_1a
10R 1% 0.022uF 25V 0.022uF 25V 11 26 R6666
TSENSE_2ph COMP_1a

ROSC_COREGT
R0402 X7R X7R 12 25 C6624 1000pF 50V X7R C0402 I 10R 1% C6626
+VSYS_CPU

ADDR_VBOOT
VRMP VSN_1a
NI C0402 C0402 RT6602 R6636 R0402 0.01uF 25V

TSENSE_1ph
ROSC_SAUS

ICCMAX_2ph
ICCMAX_1a
ICCMAX_1b
PWM1_2ph
PWM2_2ph
1

I NI 100K(NTC) 0R 5% C6625 R6637 R6639 1K 1% R0402 I C6636 I X7R

PWM_1a
67 CSN2_IA VSSGT_SENSE12

VSP_1a
R0402 R0402 0.1uF 16V 1k 1% 2200pF 50V C0402 C6629
NTC

R0603

VCC
1% I R6641 I X5R C6628 R6640 X7R C6627 I R6642 1000pF 50V
+V5P0A C6623 13K 1% C0402 I R6644 1000pF 50V 0R 5% C0402 15pF 50V 16.9K 1% X7R
10nF 50V R0402 I C6630 1.58K 1% X7R R0402 I NPO R0402 C0402

13
14
15
16
17
18
19
20
21
22
23
24
B B
X7R I 10nF 50V R0402 C0402 I C0402 R6646 I I
2

R6643 R6664 C0402 X7R I I I 1K 1%


3.48k 1% 10K 5% I C0402 VCCGT_SENSE 12 R0402
R0402 R0402 I R6645 I
NI I 0R 5% Local sense in EE side
R6647 C6631 R0402
67 CSP2_IA +V5P0A 2K 1% 1000pF 50V I
R6649 R0402 X7R
R6663 2.2R 5% C6632 I C0402
3.48k 1% R0603 1uF 10V I
R0402 I X5R
I C0402
I R6651
67 CSP1_IA

1
R6650 39.2K 1% C6633 R6652
30.1K 1% PWM_GT 67 0.1uF 16V 10% 0R 5% RT6605
R0402

NTC
R0402 I X5R R0402 R6653 100K(NTC) 1%
I C0402 I 13K 1% R0402
I R0402 I
I

2
R6654 R6655 R6656 R6657
51.1K 1% 97.6K 1% 18.7k 1% 35.7K 1%
R0402 R0402 R0402 R0402
I I I I

U22
R6658 28K 1% R0402 PWM2_IA 67
+V5P0A +V5P0A 10,11,37,50,54,61,62,63,65,67,69,70,75
PWM1_IA 67
R6630 11K 1% R0402 +VSYS

+V3P3A
+VSYS

+V3P3A
36,59,60,61,63,67,70

3,4,5,6,7,8,9,10,11,24,29,35,37,38,42,50,54,55,56,60,62,65,70
R6654 51.1K 1% R0402 +1.0V_VCCST +1.0V_VCCST 3,7,10,12,14

A
R6643,C6622,R6662,R6661 NI A

R6664 I

Project: 320S
Engineer: Frank
Size Title: Rev
C CPU VR IC V01
Date: Thursday, June 22, 2017 Sheet 66 of 72
5 4 3 2 1
5 4 3 2 1

67: VCC_CORE/GT/SA POWER SUPPLY


+VSYS_CPU

1 2
+VSYS +VSYS +VSYS 36,59,60,61,63,70

JP6701 +VSYS_CPU +VSYS_CPU 66,69


JUMP
JUMP_43X118 C6703 C6704 C6705 C6701 C6702 +V5P0A +V5P0A 10,11,37,50,54,61,62,63,65,66,69,70,75

+
NOBOM 10uF 25V 10uF 25V 10uF 25V 68uF 25V 33uF 25V
X5R X5R X5R ct_7p3x4p3x2p8 cap_7p3X4p3_h1p9 +VCC_CORE +VCC_CORE 12,15
D
1 2
C0603 C0603 C0603 I NI D
I I I +VCC_GT +VCC_GT 12,15
JP6702
JUMP +VCC_SA +VCC_SA 10,15
JUMP_43X118
NOBOM

C6729 C6730 C6731 R6703


1uF 25V 1uF 25V 1uF 25V +V5P0A 3.9R 5%
X5R X5R X5R R0603
C0402 C0402 C0402 I
I I I
R6701 C6708

25
26
27
28
29
30

33

35
1
2R 1% 0.22uF 25V
HOLE6701 HOLE6702 HOLE6703 R0402 X7R L6701

VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
THWN

GH

BOOT
VCCCORE_VCC1 6
pth_ob28x60dob18x50pth_ob28x60dob18x50pth_ob28x60dob18x50 I VCC C0603 0.15uH 30A 20%
NOBOM NOBOM NOBOM PHASED
34
I MHCI06030-R15M-R8A2R07
7
VCCD PHASEF
32
SML7668_H3
C6709 I
1uF 10V C6710 VSW1
12 1 2
+VCC_CORE
X5R 1uF 10V VSW2
13
PTH PTH PTH C0402 X5R 5
CGND U6701 VSW3
14
JS6701 JS6702

1
I C0402 NCP81382MNTXG
QFN36_PH0P4_4X6_H1P2_G2
VSW4
15
R6704
R6702 0R 5% R0402 I IVCCCORE_PWM1 VSW5
16
2.2R 5% SHORT PAD SHORT PAD C6739

+
66 PWM1_IA
4
PWM I VSW6
17
R0805 0.65X0.65 0.65X0.65 220uF 2.5V
R6705 0R 5% R0402 I VSW7
18
I NOBOM NOBOM cap_7p3X4p3_h1p9

2
VCCCORE_DISB#1 2
DISB# C6712 I
1

66,67 DRVON
2.2nF 50V CSN1_IA 66 2017/03/07
+V5P0A 36
ZCD_EN X7R
+VSYS_CPU +VSYS_CPU +VSYS_CPU C0603 CSP1_IA 66

PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
3
I

TEST
SMOD#
HOLE6704 HOLE6705

GL1
GL2
GL3
GL4
pth_ob28x40dob18x30pth_ob28x40dob18x30
NOBOM NOBOM

8
9
10
11
38

19
20
21
22
23
24
31
37
PTH PTH

+VSYS_CPU
1

C6742 C6743 C6747 C6752


+

10uF 25V 10uF 25V 10uF 25V 33uF 25V


X5R X5R X5R cap_7p3X4p3_h1p9
C0603 C0603 C0603 NI
U42 U42 U42

C
C6745 C6748 C6751 R6718 C
1uF 25V 1uF 25V 1uF 25V +V5P0A 3.9R 5%
X5R X5R X5R R0603
C0402 C0402 C0402 U42
U42 U42 U42
R6719 C6746
25
26
27
28
29
30

33

35
1

2R 1% 0.22uF 25V
HOLE6706 HOLE6707 HOLE6708 R0402 X7R L6704
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
THWN

GH

BOOT

VCCCORE_VCC2 6
pth_ob28x60dob18x50pth_ob28x60dob18x50pth_ob28x60dob18x50 U42 VCC C0603 0.15uH 30A 20%
NOBOM NOBOM NOBOM PHASED
34
U42 MHCI06030-R15M-R8A2R07
7
VCCD PHASEF
32
SML7668_H3
C6741 U42 2
1uF 10V C6755 VSW1
12 1
X5R 1uF 10V VSW2
13
PTH PTH PTH C0402 X5R 5
CGND U6704 VSW3
14
JS6708 JS6707

1
U42 C0402 NCP81382MNTXG VSW4
15
R6716
R6715 0R 5% R0402 U42 U42
VCCCORE_PWM2 QFN36_PH0P4_4X6 VSW5
16
2.2R 5% SHORT PAD SHORT PAD C6744

+
66 PWM2_IA
4
PWM U42 VSW6
17
R0805 0.65X0.65 0.65X0.65 220uF 2.5V
R6717 0R 5% R0402 U42 VSW7
18
U42 NOBOM NOBOM cap_7p3X4p3_h1p9

2
DRVON VCCCORE_DISB#2 2
DISB# C6750 NI
1

2.2nF 50V CSN2_IA 66 2017/03/07


+V5P0A 36
ZCD_EN X7R
C0603 CSP2_IA 66
PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8

3
U42
TEST

SMOD#
+VSYS_CPU +VSYS_CPU +VSYS_CPU
GL1
GL2
GL3
GL4
8
9
10
11
38

19
20
21
22
23
24
31
37

HOLE6709 HOLE6710 HOLE6711


pth_ob28x60dob18x50pth_ob28x60dob18x50pth_ob28x60dob18x50
NOBOM NOBOM NOBOM

PTH PTH PTH


+VSYS_CPU
1

C6713 C6714 C6715


10uF 25V 10uF 25V 10uF 25V
X5R X5R X5R
C0603 C0603 C0603
I I I

R6706
C6733 C6734 C6735 +V5P0A 3.9R 5%
1uF 25V 1uF 25V 1uF 25V R0603
X5R X5R X5R I
C0402 C0402 C0402
I I I
C6719
25
26
27
28
29
30

33

35
1

B
R6707 0.22uF 25V B
2R 1% VCCGT_VCC X7R L6702
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
THWN

GH

BOOT

R0402 6
VCC C0603 0.15uH 30A 20%
I PHASED
34
I MHCI06030-R15M-R8A2R07
7
VCCD PHASEF
32
SML7668_H3
C6718 I
1uF 10V C6720 VSW1
12 1 2
+VCC_GT
X5R 1uF 10V VSW2
13
C0402 X5R 5
CGND U6702 VSW3
14
JS6703 JS6704
1

I C0402 NCP81382MNTXG VSW4


15
R6708
R6709 0R 5% R0402 I I VCCGT_PWM QFN36_PH0P4_4X6 VSW5
16
2.2R 5% SHORT PAD SHORT PAD C6721
+

66 PWM_GT
4
PWM I VSW6
17
R0805 0.65X0.65 0.65X0.65 220uF 2.5V
R6710 0R 5% R0402 I VSW7
18
I NOBOM NOBOM cap_7p3X4p3_h1p9
2

DRVON VCCGT_DISB# 2
DISB# I
2017/03/07
C6722 CSN_GT 66
+V5P0A 36
ZCD_EN 2.2nF 50V
X7R SW_GT 66
PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8

3
C0603
TEST

SMOD#
I
GL1
GL2
GL3
GL4

HOLE6712 HOLE6713 HOLE6714 HOLE6715


pth_ob28x60dob18x50 pth_ob28x60dob18x50 pth_ob28x60dob18x50 pth_ob28x60dob18x50
8
9
10
11
38

19
20
21
22
23
24
31
37

NOBOM NOBOM NOBOM NOBOM

PTH PTH PTH PTH

+VSYS_CPU
1

+VSYS_CPU +VSYS_CPU +VSYS_CPU +VSYS_CPU


HOLE6716 HOLE6717 HOLE6718
pth_ob28x60dob18x50 pth_ob28x60dob18x50 pth_ob28x60dob18x50
NOBOM NOBOM NOBOM C6723 C6724 C6737 C6738
10uF 25V 10uF 25V 1uF 25V 1uF 25V
X5R X5R X5R X5R
C0603 C0603 C0402 C0402
I I I I
PTH PTH PTH
5 6 7 8 9

Q6701
D
PE606BA 8.5A 30V
dfn8p_ph0p65_3p3X3p3_h0p8
1

VCCSA_DRVH 4 G
S
I
L6703
1 2 3 0.47uH 16A 20%
R6714 C6726 SML7668_H3
8

2.2R 5% 0.22uF 25V I


R0603 X7R 1 2
+VCC_SA
DRVH

VCCSA_BST I C0603
R6711 0R 5% R0402 I VCCSA_PWM BST
1
I
JS6705 JS6706
1

66 PWM_SA
2
PWM VCCSA_SW R6713
DRVON
R6712 0R 5% R0402 I VCCSA_EN SW
7
2.2R 5% SHORT PAD SHORT PAD
A
3
EN 5 6 7 8 9 R0805 0.65X0.65 0.65X0.65 A
I NOBOM NOBOM
2

Q6702
D
PE606BA 8.5A 30V C6728 CSN_SA 66
+V5P0A 4
VCC VCCSA_DRVL dfn8p_ph0p65_3p3X3p3_h0p8 2.2nF 50V
GND
PAD

DRVL
5 4 G
I X7R SW_SA 66
S
C0603
C6727 U6703 I
9
6

2.2uF 25V NCP81253MNTBG 1 2 3


X5R DFN8_PH0P5_2X2_H1
C0402 I
I

Project: 320S
Engineer: Frank
Size Title: Rev
Custom VCC_CORE/GT/SA V01
Date: Tuesday, June 27, 2017 Sheet 67 of 81
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C
NA V01
Date: Monday, May 15, 2017 Sheet 68 of 81
5 4 3 2 1
5 4 3 2 1

D D

69: VRAM POWER SUPPLY


R6901 R6902
10R 5% 0R 5%
R0603 R0603
DIS DIS
+V5P0A
C6901 C6902
1uF 10V 0.1uF 25V
X5R X7R
C0402 C0603
DIS VRAM_SS
DIS

VRAM_BOOT
VRAM_VCC
VRAM_VIN
C6903 VRAM_LX
0.01uF 25V
VRAM_AGND X7R
C0402
DIS
C C

23

22

21

20

19

18

25
75 1.35V_VGA_EN

BST
SS

VIN2

PGND4

LX4

LX5
VCC
R6903
2K 1%
R0402 C6904 1
PGOOD LX3
17
DIS 1uF 6.3V
X7R VRAM_EN
C0402 2
EN LX2
16
DIS
VRAM_PFM
+V5P0A 3
PFM# U6901 PGND3
15
G5335QT1U
R6904 R6905 VRAM_AGND QFN23_4X4_H1
0R 5% 100K 5% 4
AGND DIS PGND2
14
JP6903
R0402 R0402 JUMP
NI DIS VRAM_FB
JUMP_43X118
5
FB PGND1
13
NOBOM
VRAM_OUT 1 2
6 12
FBVDDQ_GPU
TON PGND0
VRAM_AGND
Imax=6A

VIN0

VIN1

VIN3

LX0

LX1
NC
1 2

24

10

11
1
12
2
JP6904
JUMP
L6901 JUMP_43X118
JS6901 2017/3/8 1.0uH 12A +/-20% NOBOM
SHORT PAD LCHK_6P6x6P6x3_5P35
60X30Mil VRAM_TON VRAM_LX
DIS
NOBOM VRAM_AGND
C6905 C6906 C6907 C6908
R6906 R6907 22uF 6.3V 22uF 6.3V 22uF 6.3V 22uF 6.3V
110K 1% 2.2R 5% R6908 X5R X5R X5R X5R
R0402 R0805 6.98K 1% C0603 C0603 C0603 C0603
B DIS DIS R0402 DIS DIS DIS DIS B
DIS
1 2 VRAM_VIN
+VSYS_CPU 1 2
C6909
JP6902 470pF 50V R6909
JUMP C6910 C6911 C6912 C6913 X7R 10K 1% C6914 C6915
43X39 10uF 25V 10uF 25V 1uF 25V 1uF 25V C0603 R0402 22uF 6.3V 22uF 6.3V
NOBOM X5R X5R X5R X5R DIS DIS X5R X5R
C0603 C0603 C0402 C0402 C0603 C0603
DIS DIS DIS DIS DIS DIS
VRAM_AGND

+VSYS_CPU +VSYS_CPU 66,67

+V5P0A +V5P0A 10,11,37,50,54,61,62,63,65,66,67,70,75

FBVDDQ_GPU FBVDDQ_GPU 76,78,79,80

A A

Project: 320S
Engineer: Frank
Size Title: Rev
C VRAM POWER SUPPLY V01
Date: Wednesday, May 31, 2017 Sheet 69 of 81
5 4 3 2 1
1 2 3 4 5

A A

70: GPU POWER NVVDD

JP7001
+VSYS_GPU JUMP
JUMP_43X118
NOBOM
1 2
+V5P0A +VSYS
C7001
4.7UF 10V C7011 C7012 C7013 C7014 C7015
X5R 10uF 25V 10uF 25V 10uF 25V 33uF 25V 33uF 25V

+
5
6
7
8
9
C0402 X5R X5R X5R cap_7p3X4p3_h1p9 cap_7p3X4p3_h1p9
DIS C0603 C0603 C0603 NI NI
DIS DIS DIS
NVVDD_LG1 NVVDD_LG2 2017/3/8
NVVDD_HG1
NVVDD_SW1 NVVDD_SW2
4
Q7001
EN can't float AON6414A 50A 30V L7001 NVVDD
DFN8_PH1P27_5X6_H1P1 0.22uH 23A 20%
R7001 R7002 C7002 C7003 DIS SML6673_H3
0R 5% 47K 5% 0.22uF 25V 0.22uF 25V DIS 2

3
2
1
NVVDD_SW1
R0402 R0402 X7R U7001 X7R 1
B DIS NI C0603 NCP81278TMNTXG C0603 B

75 NVVDD_EN DIS QFN20_3X3 DIS +V3P3A

5
6
7
8
9
20 DIS R7027
19

18

17

16
R7003 R7004 2.2R 5%
2.2R 5% 2.2R 5% R0805
PH1

LG1

LG2

PH2
PVCC
R0603 R0603 DIS
NVVDD_SNUB1
DIS
NVVDD_BST1 NVVDD_BST2
DIS R7009 NVVDD_LG1
1
BST1 BST2
15
10K 5% 4
C7016
NVVDD_HG1 NVVDD_HG2
R0402 2.2nF 50V 5%
2
HG1 HG2
14
DIS Q7002 X7R
NVVDD_EN_R
AON6324 85A 30V C0603
3
EN PGOOD
13
DFN8_PH1P27_5X6_H1P1 DIS

3
2
1
NVVDD_PGOOD 75
NVVDD_PSI 4 12 NVVDD_COMP
DIS
75 DGPU_PSI PSI COMP/OPT
NVVDD_VID
Pull high on EE side 75 PS_NVVDD_PWMVID 5
VID FB
11
R7011 R7010 2017/3/8 2017/3/8
R7007 51.1K 1% 69.8k 1% C7017 C7018
VIDBUF

10K 5% R7008 R0402 R0402 330uF 2V 330uF 2V

+
FBRTN
REFIN

VREF

DIS
GND

R0402 0R 5% DIS 7.3X4.3X2 7.3X4.3X2


FS

NI R0402 C7023 C7005 DIS DIS


DIS 4700pF 50V C7004 22pF 50V +VSYS_GPU
21

10

Avoid high dV/dt X7R 220pF 50V NPO


C0402 NPO C0402
NI C0402 DIS
NVVDD_FS

DIS
NVVDD_FB
NVVDD_VIDBUF NVVDD_FBRTN
C7019 C7020 C7021

5
6
7
8
9
R7013 10uF 25V 10uF 25V 10uF 25V
49.9R 1% X5R X5R X5R
R7014 R7012 R0402 C0603 C0603 C0603
39.2K 1% 10K 1% DIS DIS DIS DIS
R0402 R0402 C7009 NVVDD_HG2 4
2017/3/8
DIS DIS 47pF 50V Q7003
R1 R3 R4 NVVDD_VREF
NPO AON6414A 50A 30V L7002
C0402 DFN8_PH1P27_5X6_H1P1 0.22uH 23A 20%
R7016 R7017 R7018 C7006 DIS DIS SML6673_H3
6.19K 1% 4.32K 1% 16.5K1% 4700pF 50V DIS 2

3
2
1
C NVVDD_SW2 C
R0402 R0402 R0402 X7R C7007 C7008 1
DIS DIS DIS C0402 10nF 50V 1000pF 50V
DIS X7R X7R

5
6
7
8
9
C0402 C0402 R7028
R5 DIS DIS 2.2R 5%
R7022 R7023 R0805
R7021 0R 5% 0R 5% R7025 DIS
NVVDD_SNUB2
309R 1% R0402 R0402 100R5% NVVDD_LG2 4
R0402 DIS DIS R0402 C7022
DIS DIS 2.2nF 50V 5%
NVVDD Q7004 X7R
R2 AON6324 85A 30V C0603
DFN8_PH1P27_5X6_H1P1 DIS

3
2
1
GPU_NVVDD_SENSE 76 DIS
R7024 Avoid high dV/dt
C 20.5K 1%
C7010 R0402 GPU_NVVDD_FBRTN 76
4700pF 50V DIS
X7R
C0402
NI R7026
100R5%
R0402
DIS
Place close to GPU

D D

Project: 320S
Engineer: Frank
Size Title: Rev
C
GPU NVVDD V01
Date: Wednesday, May 31, 2017 Sheet 70 of 81
1 2 3 4 5
1 2 3 4 5

A A

B B

C C

D D

Project: 320S
Engineer: Frank
Size Title: Rev
C
NA V01
Date: Monday, May 15, 2017 Sheet 71 of 81
1 2 3 4 5
1

Rev
V01
81 of
Frank

72
320S

PWR Change List


Sheet
Engineer:
Project:
E

E
Monday, May 15, 2017
Title:
Size

Date:
C
D

D
C

C
B

B
.
e
u
s
s
i
l
a
m
r
o
n
b
a
s )
i 2
2
U
POWER CHANGE LIST

K (
O .
C t
A n
e .
i .F.
x. s
iH n .. KpK .
fu a .KK 404 K
r. K78 .0. 8
7 tK 1.5 220
. 2 .
o.
t4
8..1 . 8 .
111 K3 6 9
6
r2KK5
o 11 ooo
co fo 1 oootttI o
it .
K to t ott t N t
t 5 C tt o K F K
a .1
mH.m R K KK 9p8 K
eu 1 5R 0 K.85K . 0 . 1
h30h 6.50 89 2 .
c.Ro C.0 4K05 .1 3662 1
s320o I5260
A

A
2111 6 5
SDV to SIV
t mmC 6
rmoo Rmmmmmmo mmooo, m
eottK Vo o o o rrr3 o
gr 9 roorrrrfff4 .r
rf
a 00. frrffff Pf
h RR0 U ff 6
c1119 P
Ceeeeeed ddd6 C
eeeeR , Oe
0
9mmm. gg
nn gggggggg2
n n n n n n g
n
6.ne5o oo .ehaanahahaan ahaaa6 6
.eha
/9u Lr rrI 6nc hhc hh hh6 0nc
ffN 6u
t cc
ccc cccR I 7u
45t f ,
t
/ e
7eeg 6730 890464651814 0
1g n3322 ee513554432166 ee1
0a na9999 gn666666666666 gn0
ih5555 ai666666666666 ai7
2PFCRRRC PFRRRRRRRRCRRR PFR

4
5 4 3 2 1

D D

C C

B B

A A

Project: 520S-13
Engineer: Jason
Size Title:NA Rev
B V01
Date: Monday, April 10, 2017 Sheet 73 of 81
5 4 3 2 1
1 2 3 4 5

1V8_AON
G1A
1/14 PCI_EXPRESS PEX_VDD
R10041
10K
5% Place between
R0402_N Place under GPU Place near GPU GPU and PS
DIS PEX_DVDD AA22
PEX_GPU_RST# RG6 0R GPU_RST# AC7 PEX_RST PEX_DVDD AB23
R0402 5% DIS
PEX_DVDD AC24 C552 C546 C541 C535 C536 C540 C539
GPU_CLKREQ#_R AC6 PEX_CLKREQ PEX_DVDD AD25 1uF 6.3V 10% 4.7uF 10V 10% 4.7uF 10V 10% 4.7uF 10V 10% 10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%
AE26 X7R X5R X5R X5R C0402_N C0402_N C0402_N
PEX_DVDD
AE8 AE27 C0402 C0603_N C0603_N C0603_N X5R X5R X5R
7 CLK_PCIE_GPU PEX_REFCLK PEX_DVDD
AD8 DIS DIS DIS DIS DIS DIS DIS
+1.8VS_VGA_MAIN 7 CLK_PCIE_GPU# PEX_REFCLK
A A
X5RC0402_N 0.22uF
DIS 10V 10% CG1 PCIE_CRX_GTX_C_P0 AC9 PEX_TX0
9 PCIE_CRX_GTX_P0 X5RC0402_N 0.22uF PCIE_CRX_GTX_C_N0
DIS 10V 10% CG2 AB9 PEX_TX0
9 PCIE_CRX_GTX_N0
All caps are required by DG
G2 AG6
9 PCIE_CTX_GRX_P0 PEX_RX0 GND
AG7 PEX_RX0 PEX_HVDD AA10
9 PCIE_CTX_GRX_N0
PEX_HVDD AA12
X5RC0402_N 0.22uF
DIS 10V 10% CG3 PCIE_CRX_GTX_C_P1 AB10 PEX_TX1 PEX_HVDD AA13
7 GPU_CLKREQ# D2 S2 GPU_CLKREQ#_R 9 PCIE_CRX_GTX_P1 X5RC0402_N 0.22uF
DIS 10V 10% CG4 PCIE_CRX_GTX_C_N1 AC10 PEX_TX1 PEX_HVDD AA16
9 PCIE_CRX_GTX_N1
PEX_HVDD AA18
AF7 PEX_RX1 PEX_HVDD AA19
9 PCIE_CTX_GRX_P1
QX17B 9 PCIE_CTX_GRX_N1
AE7 PEX_RX1 PEX_HVDD AA20
LBSS138DW1T1G 200mA 50V PEX_HVDD AA21
X5RC0402_N 0.22uF
DIS 10V 10% CG5 PCIE_CRX_GTX_C_P2 AD11 PEX_TX2 PEX_HVDD AB22
SOT363M 9 PCIE_CRX_GTX_P2 X5RC0402_N 0.22uF PCIE_CRX_GTX_C_N2
DIS 10V 10% CG6 AC11 PEX_TX2 PEX_HVDD AC23 +1.8VS_VGA_MAIN
DIS 9 PCIE_CRX_GTX_N2
PEX_HVDD AD24
AE9 PEX_RX2 PEX_HVDD AE25
9 PCIE_CTX_GRX_P2
AF9 PEX_RX2 PEX_HVDD AF26
9 PCIE_CTX_GRX_N2
AF27
Place under GPU Place near GPU
PEX_HVDD
X5RC0402_N 0.22uF
DIS 10V 10% CG7 PCIE_CRX_GTX_C_P3 AC12 PEX_TX3
9 PCIE_CRX_GTX_P3 X5RC0402_N 0.22uF PCIE_CRX_GTX_C_N3
DIS 10V 10% CG8 AB12 PEX_TX3 C580 C571 C578 C564 C572 C561 C615 C617 C616
9 PCIE_CRX_GTX_N3
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 4.7uF 10V 10% 4.7uF 10V 10% 10uF 6.3V 20%
10uF 6.3V 20% 22uF 6.3V 20%
AG9 X7R X7R X7R X7R X5R X5R C0402_N C0402_N X5R
9 PCIE_CTX_GRX_P3 PEX_RX3
AG10 C0402 C0402 C0402 C0402 C0603_N C0603_N X5R X5R C0603_N
9 PCIE_CTX_GRX_N3 PEX_RX3
CG50 DIS DIS DIS DIS DIS DIS DIS DIS DIS
0.1uF 10V 10% AB13 PEX_TX4
1V8_AON C0402 AC13 PEX_TX4
X5R
Place between
DIS AF10 PEX_RX4 GPU and PS
AE10 PEX_RX4 +1.8VS_VGA_MAIN
GND
5

AD14 PEX_TX5
AC14 PEX_TX5 PEX_PLL_HVDD AA8
UG6B PEX_PLL_HVDD AA9
SN74LVC1G08DBV AE12 PEX_RX5
B DIS B
AF12 PEX_RX5
C595
3

AC15 PEX_TX6 0.1uF 10V 10%


AB15 PEX_TX6 C0402_NX5R
DIS R572
PEX_SVDD_3V3
AG12 PEX_RX6 OUT 77
AG13 PEX_RX6 0R
R0603_N Stuff for GM108
AB16 5% NI
PEX_TX7
AC16 PEX_TX7 GND

AF13 PEX_RX7
UG6A
AE13 PEX_RX7
SN74LVC1G08DBV
DIS
AD17 PEX_TX8
1
8,50 DGPU_HOLD_RST# PEX_GPU_RST# AC17 PEX_TX8
4 R10069 0R
R0402_N 5% PEX_GPU_RST# 75
2
7,26,27,43,50 PLT_RST_N DIS AE15 PEX_RX8
AF15 PEX_RX8
R10047
100K
AC18 PEX_TX9
5% R10049
AB18 PEX_TX9
R0402_N 100K
DIS 5%

PEX LANES 15 - 4 ARE DEFEATURED


R0402_N
AG15 PEX_RX9
DIS
AG16 PEX_RX9

AB19 PEX_TX10
AC19 PEX_TX10

G1J AF16 PEX_RX10


4/14 IFPAB AE16 PEX_RX10

DVI HDMI DP AD20 PEX_TX11


SL/DL AC20 PEX_TX11
C C
IFPA_L3 AC4 AE18 PEX_RX11
TXC/TXC IFPA_L3 AC3 AF18 PEX_RX11

R720 1K IFPAB_RSET AA6 AC21


GND IFPAB_RSET PEX_TX12
R0402_N 1% NI TXD0/0 Y3 AB21
IFPA_L2 PEX_TX12
IFPA_L2 Y4
AG18 PEX_RX12
AG19 PEX_RX12
R542 TXD1/1 IFPA_L1 AA2
CORE_PLLVDD IFPAB_PLLVDD_R W7 AA3 AD23
IN 75 IFPAB_PLLVDD IFPA_L1 PEX_TX13
NI 0R AE23 PEX_TX13
R0603_N
5% AA1 AF19
TXD2/2 IFPA_L0 PEX_RX13
Place under GPU
C597 IFPA_L0 AB1 AE19 PEX_RX13
0.1uF 10V 10%
C0402_NX5R
AF24 PEX_TX14
NI AA5 AE24
IFPA_AUX_SDA PEX_TX14
IFPA_AUX_SCL AA4
AE21 PEX_RX14
GND AF21 PEX_RX14
IFPB_L3 AB4
TXC IFPB_L3 AB5 AG24 PEX_TX15
AG25 PEX_TX15
Place under GPU
Place near GPU
W6 IFP_IOVDD TXD0/3 IFPB_L2 AB2 AG21 PEX_RX15
PEX_VDD
IFPB_L2 AB3 AG22 PEX_RX15
C649 C650 C603 C628 Y6 IFP_IOVDD
4.7uF 10V 10% 4.7uF 10V 10% 1uF 6.3V 10% 4.7uF 10V 10% C608 C599
X5R X5R X7R X5R AD2
0.1uF 10V 10%0.1uF 10V 10% TXD1/4 IFPB_L1 PEX_TERMP AF25
C0603_N C0603_N C0402 C0603_N AD3
C0402_NX5R C0402_NX5R IFPB_L1
NI NI NI NI NI NI R714
N17S-LG-A1 DIS 2.49K
TXD2/5 AD1 1%
IFPB_L0
PLACE CLOSE R0402_N
IFPB_L0 AE1
D TO GPU DIS D

DG Requirement GND
GND IFPB_AUX_SDA AD5
IFPB_AUX_SCL AD4
GND

IFPAB (DEFEATURED 0N GM108)

N17S-LG-A1 DIS Project: 320S-13


PEX_VDD PEX_VDD 75,77
1V8_AON
Engineer: Jason
1V8_AON 50,75,76,79
+1.8VS_VGA_MAIN +1.8VS_VGA_MAIN 75,76,78,79
Size Title:NV N17S(1/5)_PCIE/DP Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 74 of 81
1 2 3 4 5
1 2 3 4 5

JTAG DEBUG PORT 1V8_AON

1V8_AON G1K
10/14 MISC2
R736
10K
5%
R729 10K JTAG_TDI R0402_N NI 1V8_AON
R0402_N 5% NI D12 ROM_CS* TP10001
ROM_CS
50OHM_NETCLASS2
JTAG_TMS ROM_SI
R190 10K ROM_SI B12 TP10002
R0402_N 5% NI ROM_SO
ROM_SO A12 TP10003
STRAP0 ROM_SCLK
D1 STRAP0 ROM_SCLK C12 TP10004
STRAP1 R870 R878 R874
D2 STRAP1
STRAP2 100K 100K 100K
E4 STRAP2 5% 5% 5%
STRAP3 E3
R721 180R 1% R0402_N NIJTAG_TCLK STRAP3 50OHM_NETCLASS2 R0402_N R0402_N R0402_N
STRAP4 D3
GPU_STRAP5
STRAP4 DIS DIS DIS
STRAP5 R636 0R C1 STRAP5 NC GM108 50OHM_NETCLASS2
50OHM_NETCLASS2
R0402 5% DIS ROM_SI
1V8_AON ROM_SO
ROM_SCLK
GPU_BUFRST*
JTAG_TCLK BUFRST D11 TP10000
A
R142 270R 1%R0402_N NI RESERVED A

50OHM_NETCLASS2 R872 R880 R876


R189 10K JTAG_TRST* 100K 100K 100K
R0402_N 5% DIS R869 R873 R877 R194 R193 R192 50OHM_NETCLASS2
5% 5% 5%
100K 100K 100K 100K 100K 100K R0402_N R0402_N R0402_N
5% 5% 5% 5% 5% 5% NI NI DIS
R0402_N R0402_N R0402_N R0402_N R0402_N R0402_N
GND NI NI NI NI NI NI
STRAP0
STRAP1 Only one cap is required by DG CORE_PLLVDD_GPU
MEM SEL STRAP2 R536 0R 5%R0603_N DIS
N17S-LG-A1 DIS 0.400
GND
C610 C609 C604 C606 C598
0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10% 0.1uF 10V 10%
STRAP3 C0402_N X5R C0402_NX5R C0402_N X5R C0402_N X5R C0402_NX5R
STRAP4
Place under GPU NI NI DIS NI DIS

STRAP5

30ohm@100MHz 3A 25% OU T 74
R871 R875 R879 R183 R182 R181 L0603
100K 100K 100K 100K 100K 100K DIS 3/16 Install
5% 5% 5% 5% 5% 5% LB505 GND
CORE_PLLVDD VID_PLLVDD_GPU_AW27
R0402_N R0402_N R0402_N R0402_N R0402_N R0402_N +1.8VS_VGA_MAIN 1 2 R574 0R 5%R0603_N DIS
0.400 G1L
DIS DIS DIS DIS DIS DIS 0.400 9/14 XTAL_PLL
VID_PLLVDD_GPU_AW28
C640 C636 R537 0R 5%R0603_N DIS
0.400 GM108
22uF 6.3V 20% 4.7uF 10V 10% Place under GPU L6 XS_PLLVDD 1V8_AON
X5R X5R PLLVDD
M6 SP_PLLVDD PU/PD for desired fan curve
C0603_N C0603_N F11 GPCPLL_AVDD NC
DIS DIS C582 C601 N6 VID_PLLVDD SET XTALOUTBUF
NC R223
0.1uF 10V 10% 0.1uF 10V 10%
0V DISABLE
GND C0402_NX5R C0402_N X5R 100K
DIS DIS 5% 1.8V 33%
1V8_AON 0.9V 66%
R0402_N

GND
NI
XTALOUTBUFF_R
A10 XTALSSIN XTALOUTBUFF C10
R221
GND 10K

LP
el
na
on
v
o
5%
R0402_N C11 XTALIN XTALOUT B10
NI R228
XTALSSIN 50OHM_NETCLASS1 N17S-LG-A1 DIS 10K
5%
R0402_N
Y1
R222 R229 95DIFF_NETCLASS1 XTALOUT
DIS
4 G ND 3 95DIFF_NETCLASS1
10K 10K
Y4 Y3
XTAL GND
5% 5%
XTALIN
XTAL
R0402_N R0402_N 1 Y1 Y2 2
G ND GND
NI DIS GND
27MHZ 10PPM

XTALSSIN_RC
1V8_AON 1V8_AON C83 CRY4_3225 C80
B
33pF 50V 5% DIS 33pF 50V 5%
C78 NPO NPO
B
1000pF 50V 10% C0402_N C0402_N
X7R GND DIS DIS
QX13A C0402_N
RG14 RG15
LBSS138DW1T1G 200mA 50V NI 27MHZ Ctystal
2.2K 2.2K SOT363M
5% 5%
G1 DIS
R0402_N R0402_N GND GND
DIS DIS

1V8_AON GPU_SMBCLK S1 D1 GND


+V5P0A +V1P8S +1.8VS_VGA_MAIN SMB0_GFX_CLK 50
G1M G2
8/14 MISC1
1V8_AON
R734 GPU_SMBDATA S2 D2
SMB0_GFX_DATA 50
CG20 CG21 CG22 10K GPU_ALERT# R10093 10K 5%R0402_N DIS
1uF 6.3V 10% 1uF 6.3V 10% 0.1uF 10V 10% 5%
GPIO12_AC_DETECT_D
X5R X5R X5R R0402_N GPU_SMBCLK R10074 100K 5% R0402_N DIS
I2CS_SCL D9 QX13B DGPU_PSI R10073 10K 5%R0402_N DIS
C0402 C0402 C0402 DIS GPU_SMBDATA
I2CS_SDA D8 GPU_SMBCLK_B R10068 10K 5%R0402_N DIS
DIS DIS DIS GPU_OVERT#_1.8 A6 LBSS138DW1T1G 200mA 50V
OVERT GPU_SMBDATA_B R10067 10K 5%R0402_N DIS
AE2 GPU_SMBCLK_C SOT363M
TS_VREF I2CC_SCL A9 GPU_SMBCLK_C R10066 10K 5%R0402_N DIS
UG5 GPU_SMBDATA_C DIS
I2CC_SDA B9 GPU_SMBDATA_C R10065 10K 5%R0402_N DIS
1 14
GND GND VIN1 VOUT1 GND
2 13
VIN1-1 VOUT1-1
E12 THERMDN
NVVDD_EN_R GPU_SMBCLK_B
GPIO16_PEXRSTMON R155 10K 5%R0402_N DIS
RG89 0R 3 12 CG25 1000pF 50V 10% I2CB_SCL C9 GPIO5_FL_INT_GPU
R0402 5% DIS ON1 CT1 C0402 X7R DIS GPU_SMBDATA_B R741 10K 5%R0402_N DIS
F12 THERMDP I2CB_SDA C8 GPU_EVENT# R749 10K 5%R0402_N DIS
4 11
VBIAS GND TS_VREF 1V8_MAIN_EN R747 10K 5%R0402_N DIS
8,50 DGPU_PWR_EN DGPU_PWR_EN RG87 0R 5 10 CG26 1000pF 50V 10%
ON2 CT2 GC6_FB_EN R123 10K 5%R0402_N DIS
R0402 5% DIS C0402 X7R DIS 1V8_AON C605 GPIO19_STEREO_OUT_SRV_HEAD
R147 10K 5%R0402_N DIS
+V1P8S 6 9 0.1uF 10V 10%
VIN2 VOUT2-1 GPIO22_MEM_VDD_CTL2 R826 10K 5%R0402_N NI
7 8
VIN2-1 VOUT2 X5RC0402_N GPIO0_NVVDD_PWM_GPU
NI C6 R168 0R 5%R0402 DIS
GPIO0 GPIO1_GC6FBEN PS_NVVDD_PWMVID 70
15 Stuff for GM108 B2 R122 0R 5%R0402 DIS GC6_FB_EN G1N
GPAD GND GPIO1 GPIO2_GPUEVENT* GPU_EVENT#
CG27 CG28 GPIO2 D6 R773 0R 5%R0402 DIS 3/14 JTAG
GPIO3_NVVDDS_PWM_GPU GPU_EVENT# 8
1uF 6.3V 10% EM5209VF 0.1uF 10V 10% GPIO3 C7 TP10008
X5R dfn14p_ph0p4_3x2_h0p8 X5R GPIO4_1V8MAINEN
GND GPIO4 F9 R772 0R 5%R0402 DIS 1V8_MAIN_EN
C0402 DIS C0402 GPIO5_FL_INT_GPU JTAG_TCLK
GPIO5 A3 AE5 JTAG_TCK
DIS DIS DGPU_PSI_R GND JTAG_TDI
GPIO6 A4 R10098 0R 5%R0402 DIS DGPU_PSI 70 AE6 JTAG_TDI
JTAG_TDO
GPIO7 B6 AF6 JTAG_TDO
GND GPIO8_MEM_VDD_CTL_R JTAG_TMS
GPIO8 E9 TP10005 AD6 JTAG_TMS
GPU_ALERT# JTAG_TRST*
GPIO9 F8 AG4 JTAG_TRST
GND GND GPIO10_FBVREF_SEL GPU_ALERT# 50 NVJTAG_SEL
GPIO10 C5
OU T 80 TP5600 AD9 NVJTAG_SEL
GPIO11_PPEN_R
GPIO11 E7
D7 GPIO12_AC_DETECT_D R752
GPIO12 GPIO12_AC_DETECT 50
GPIO13 B4 DIS SOD_323 BAT54WS D6608 10K
GPIO14 B3 R748 R751 5%
GPIO15 C3 100K 10K R0402_N
GPIO16_PEXRSTMON 5% 5% DIS
GPIO16 D5
C C
D4 R0402_N R0402_N
+V5P0A +1.0V_PRIM GPIO17
C2 DIS DIS
GPIO18 GPIO19_STEREO_OUT_SRV_HEAD
F7
GPIO19 GPIO20_GC5_MODE_GPU GND
E6 TP5601
GPIO20
+V3P3SX GM108 C4
3/16 Change low switch GPIO21 GPIO22_MEM_VDD_CTL2
CG51 PEX_VDD A7
GND
I2CA_SDA GPIO22 GPIO23_PEXRSTHOLD DGPU_RST_HOLD#
CG88 1uF 6.3V 10% B7 R10048 0R 5%R0402 DIS
I2CA_SCL GPIO23
0.1uF 10V 10% X5R UBD2 N17S-LG-A1 DIS
X5R C0402 1 8
DGPU_PWR_EN D6605 BAT54WS SOD_323 DIS C0402 DIS 2
VIN1
VIN2
VOUT3
N17S-LG-A1 DIS
R10061 DIS 7 R10070
VOUT2 CG52
5% 10K 3/16 add CG88 9 100K
NVVDD_EN_R D6604 BAT54WS SOD_323 DIS R0402_N VIN thermal 0.1uF 10V 10% 5%
6
DIS VOUT1 X5R
3 R0402_N
2/16 Nv change name VBIAS C0402
DIS
DIS
D6603 BAT54WS SOD_323 DIS PEX_EN RG90 0R 4
ON GND
5
70,75 NVVDD_PGOOD R0402 5% DIS

TPS22961DNYR GND
tps22961_8P_h0p8
DIS

GND

FC
Bo
Vn
Dt
Do
PEX_VDD

r
l
+V3P3SX
R10088
Nc
Vo
Vn
Dr
Dl
R10091 2.2R 5%
5% 10K R0805 +V3P3SX
R10089 R0402_N DIS t
o
DIS
5% 10K
R0402_N
DIS 5/10 Install discharge
D2 QX18B +V3P3SX
2N7002KDW 115mA 60V
GC6_FB_EN_3.3 8,50
R10072
G2 S2 74 PEX_GPU_RST# GPU_OVERT# D6606 BAT54WS SOD_323 DIS 5% 10K D6602 close to Power
SOT363V
D1 QX18A DIS
DIS
R10055 R10071 R0402_N 1
2N7002KDW 115mA 60V R10076 +V3P3SX
PEX_EN 10K 5% 10K D2
10K 5% 5% 3 RG91 0R
G1 S1 R0402_N DIS 1.35V_VGA_EN 69
R0402_N R0402 5% DIS
DIS R0402_N
SOT363V G1 DIS 2
DIS 70,75 NVVDD_PGOOD
2/22 change to 10K
R10062 D1
G2
QX16B R10058 CG54
10K 5% 2/17 change mos
LBSS138DW1T1G 200mA 50V BAT54C 200mA 30V 200K1% 0.1uF 10V 10%
GPU_OVERT#_1.8 S1 D1 GPU_OVERT#
GPU_OVERT# 50 R0402_N DIS QX16A SOT_23
R0402 X5R
D
QX17A
S2 200mA 50V
LBSS138DW1T1G DIS DIS C0402 D
GND NVVDD_EN_R NVVDD_EN GC6_FB_EN G1 SOT363M NI
LBSS138DW1T1G 200mA 50V NVVDD_EN 70 DIS
SOT363M DIS R10096 D2 RG92
2/17 change mos 5% 10K 5.1K 1% CG56 GND
DIS R0402_N
DIS 0.1uF 10V 10% S1 GND
R0402_N QX9B C0402 X5R SOT363M
G2 DIS 4/14 change to 200K ohm
RG93 0R D1
DIS 4/17 change RC.
R0402 5% NI LBSS138DW1T1G 200mA 50V
PEX_VDD PEX_VDD 74,77 QX9A GND
LBSS138DW1T1G 200mA
S2 50V GND
1V8_AON 1V8_AON 50,74,76,79 1V8_MAIN_EN
CG57 G1 SOT363M
+1.8VS_VGA_MAIN DIS 2/17 change to AND gate
+1.8VS_VGA_MAIN 74,76,78,79 0.1uF 10V 10%
X5R
+V3P3SX +V3P3SX 5,6,7,8,9,10,26,27,30,35,36,43,46,50 C0402
+V1P8S S1
+V1P8S 10 NI
SOT363M
+V5P0A +V5P0A 10,11,37,50,54,61,62,63,65,66,67,69,70 DIS
Project: 320S-13
+1.0V_PRIM +1.0V_PRIM 10,11,14,63 GND
GND Engineer: Jason
Size Title:NV N17S(2/5)_MSIC Rev
D V01
Date: Wednesday, May 10, 2017 Sheet 75 of 81

1 2 3 4 5
1 2 3 4 5

NVVDD

G1C FBVDDQ_GPU
11/14 NVVDD G1D
0.400 K10 VDD 12/14 FBVDDQ
K12 VDD 40A
K14 VDD B26 FBVDDQ G1F
K16 VDD C25 FBVDDQ NVVDD 1.3V
K18 E23 7/14 VDDS
VDD FBVDDQ
L13 VDD E26 FBVDDQ 0.400
L15 VDD F14 FBVDDQ
A L11 VDDS A
M10 VDD F21 FBVDDQ L17 VDDS
M12 VDD G13 FBVDDQ M14 VDDS
M16 VDD G14 FBVDDQ P10 VDDS
M18 VDD G15 FBVDDQ P12 VDDS
N11 VDD G16 FBVDDQ P16 VDDS
N13 VDD G18 FBVDDQ P18 VDDS
N15 VDD G19 FBVDDQ T14 VDDS
N17 VDD G20 FBVDDQ U11 VDDS
P14 VDD G21 FBVDDQ U17 VDDS
R11 VDD L22 FBVDDQ
R13 VDD L24 FBVDDQ
R15 VDD L26 FBVDDQ
R17 VDD M21 FBVDDQ
T10 VDD N21 FBVDDQ
T12 VDD R21 FBVDDQ GM108
T16 VDD T21 FBVDDQ
95DIFF_NETCLASS1
T18 VDD V21 FBVDDQ
RSVD VDDS_SENSE F4 GPU_NVVDDS_SENSE TP10011
U13 VDD W21 FBVDDQ
RSVD GNDS_SENSE F3 GPU_NVVDDS_FBRTN TP10012
U15 VDD H24 FBVDDQ
V10 VDD H26 FBVDDQ
V12 VDD J21 FBVDDQ N17S-LG-A1 DIS
V14 VDD K21 FBVDDQ
V16 VDD
V18 VDD

VDD_SENSE F2 GPU_NVVDD_SENSE 70
GND_SENSE F1 GPU_NVVDD_FBRTN 70

B B

N17S-LG-A1 DIS

MINIMIZE WIRE STUB

FBVDDQ_GPU

FBCAL_VDDQ R682 40.2R 1% R0402_N


FB_CAL_PD_VDDQ D22
DIS
FBCAL_GND R689 40.2R 1% R0402_N
FB_CAL_PU_GND C24
DIS
FBCAL_TERM
FB_CALTERM_GND B25 R507 60.4R 1%R0402_N
DIS

Change to 60.4 ohm

N17S-LG-A1 DIS GND

C +1.8VS_VGA_MAIN C
G1E
14/14 VDD18

1V8_AON
VDD18 G8
VDD18 G9
1V8_AON G10
1V8_AON G12

N17S-LG-A1 DIS

1V8_AON 1V8_AON 50,74,75,79


+1.8VS_VGA_MAIN +1.8VS_VGA_MAIN 74,75,78,79
D D
NVVDD NVVDD 70,77,79
FBVDDQ_GPU FBVDDQ_GPU 69,78,79,80

Project: 320S-13
Engineer: Jason
Size Title:NV N17S(3/5)_Power/GND Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 76 of 81
1 2 3 4 5
1 2 3 4 5

NVVDD

PEX_VDD

G1H DEFAULTR538
13/14 GND
0R
A R0603_N NI A
G1G A2 GND GND K11 5%
C570
6/14 XVDD AB17 GND GND K13 CYA
1uF 6.3V 10%
AB20 GND GND K15 X7R
AB24 GND GND K17 GM108 PEX_PLLVDD C0402
G1 XVDD XVDD N4 AC2 GND GND L10 PLACE NEAR BGA
NI
G2 XVDD XVDD N5 AC22 GND GND L12 Under GPU Near GPU CLOSE TO CAPS
G3 XVDD XVDD N7 AC26 GND GND L14
G4 XVDD XVDD P3 AC5 GND GND L16 1x0402 0.1uF 1x0603 1uF + 1x0805 4.7uF
GND
G5 XVDD XVDD P4 AC8 GND GND L18
G6 XVDD XVDD P6 AD12 GND GND L5
G7 XVDD XVDD R1 AD13 GND GND M11
H3 XVDD XVDD R2 A26 GND GND M13
H4 XVDD XVDD R3 AD15 GND GND M15
H6 XVDD XVDD R4 AD16 GND GND M17
J1 XVDD XVDD R5 AD18 GND GND N10
J2 XVDD XVDD R6 AD19 GND GND N12
J3 XVDD XVDD R7 AD21 GND GND N14 PLACE NEAR BALL
J4 XVDD XVDD T1 AD22 GND GND N16 PEX_PLLVDD_GPU PLACE NEAR BGA
1.05V
J5 XVDD XVDD T2 AE11 GND GND N18
0.300
J6 XVDD XVDD T3 AE14 GND GND P11
C575 C573
J7 XVDD XVDD T4 AE17 GND GND P13
C581 1uF 6.3V 10% 4.7uF 10V 10%
K1 XVDD XVDD T5 AE20 GND GND P15 X7R X5R
K2 T6 AB11 P17 0.1uF 10V 10%
XVDD XVDD GND GND C0402 C0603_N
K3 T7 AF1 P23 C0402_NX5R
XVDD XVDD GND GND NI NI NI
K4 XVDD XVDD U3 AF11 GND GND P26
K5 XVDD XVDD U4 AF14 GND GND R10
K6 XVDD XVDD U6 AF17 GND GND R12
K7 XVDD XVDD V1 AF20 GND GND R14
L3 XVDD XVDD V2 AF23 GND GND R16
Stuff for GM108 GND
L4 XVDD XVDD V3 AF5 GND GND R18
M1 XVDD GM108 XVDD V4 AF8 GND GND T11
M2 XVDD XVDD V5 AG2 GND GND T13
M3 XVDD XVDD V6 AG26 GND GND T15
M4 V7 SNN_XVDD_V7 AB14 T17
B XVDD RSVD XVDD GND GND B
M5 XVDD XVDD W1 B1 GND GND U10
G1I
M7 XVDD XVDD W2 B11 GND GND U12
5/14 NC
N1 XVDD XVDD W3 B14 GND GND U14
N2 XVDD XVDD W4 B17 GND GND U16
N3 B20 U18
GM108
XVDD GND GND AA14
B23 U23 NC PEX_PLLVDD
GND GND 0.300 AA15 NC
B27 GND GND U26 SNN_G1_AB6 PEX_PLLVDD
AB6 NC
B5 GND GND V11 PEX_SVDD_3V3 AB8 NC
B8 GND GND V13 74 IN SNN_G1_AD10 PEX_SVDD_3V3
AD10 NC
E11 GND GND V15 SNN_G1_AD7 AD7 NC
E14 GND GND V17 GM108_PEX_PLL_CLK_OUT AE22 NC
N17S-LG-A1 DIS E17 GND GND Y2 SNN_G1_AE3 PEX_TSTCLK*
R898 AE3 NC
E2 GND GND Y23 SNN_G1_AE4
200R AE4 NC
E20 GND GND Y26 5% SNN_G1_AF2 AF2 NC
E22 GND GND Y5 R0402_N GM108_PEX_PLL_CLK_OUT* AF22 NC
E25 GND GND AA7 NI SNN_G1_AF3 PEX_TSTCLK
AF3 NC
E5 GND GND AB7 SNN_G1_AF4
Stuff for GM108 AF4 NC
E8 GND SNN_G1_AG3 AG3 NC
SNN_G1_D10 D10 NC
SNN_G1_E10 E10 NC
SNN_G1_F10 F10
Stuff for GM108 R897 SNN_G1_F5
NC
OPTIONAL GND: F5 NC
GM108_STRAP_REF0 F6 NC MLS_REF0
SNN_G1_W5 W5 NC
XVDD AREA 40.2R
SNN_GNDOPT_H2 SNN_GNDOPT_P2 DESIGNS MUST
H2 GND_OPT GND_OPT P2 NI GM108 COMPATIBLE
SNN_GNDOPT_H5 H5 P5 SNN_GNDOPT_P5 PINS
GND_OPT GND_OPT R0402_N LEAVE NC FLOATING EXCEPT
SNN_GNDOPT_L2 L2 U2 SNN_GNDOPT_U2
GND_OPT GND_OPT 1% FOR THOSE SHOWN
U5 SNN_GNDOPT_U5
GND_OPT N17S-LG-A1 DIS
GND

PCB ADR/CMD
PWR REFERENCE
C C
H23 GND_OPT GND_OPT L23
H25 GND_OPT GND_OPT L25

N17S-LG-A1 DIS

GND GND

D D

Project: 320S-13
NVVDD NVVDD 70,76,79 Engineer: Jason
PEX_VDD PEX_VDD 74,75 Size Title:NV N17S(4/5)_Power Rev
Custom V01
Date: Monday, April 10, 2017 Sheet 77 of 81

1 2 3 4 5
1 2 3 4 5

FB_DATA
FBA_D[63..0] G1B
80 BI
2/14 FBA
FBA_D0 E18
0 FBA_D0
FBA_D1 F18
1 FBA_D1
FBA_D2 E16
2 FBA_D2
FBA_D3 F17
3 FBA_D3
FBA_D4 D20
4 FBA_D4
FBA_D5 D21
A 5 FBA_D5 A
FBA_D6 F20
6 FBA_D6
FBA_D7 E21
7 FBA_D7
FBA_D8 E15
8 FBA_D8
FBA_D9 D15
9 FBA_D9
FBA_D10 F15
10 FBA_D10
FBA_D11 F13
11 FBA_D11
FBA_D12 C13
12 FBA_D12
FBA_D13 B13
13 FBA_D13
FBA_D14 E13
14 FBA_D14
FBA_D15 D13
15 FBA_D15
FBA_D16 B15
16 FBA_D16
FBA_D17 C16
17 FBA_D17
FBA_D18 A13
18 FBA_D18
FBA_D19 A15
19 FBA_D19
FBA_D20 B18
20 FBA_D20
FBA_D21 A18
21 FBA_D21
FBA_D22 A19
22 FBA_D22
FBA_D23 C19
23 FBA_D23
FBA_D24 B24
24 FBA_D24
FBA_D25 C23
25 FBA_D25
FBA_D26 A25
26 FBA_D26
FBA_D27 A24
27 FBA_D27
FBA_D28 A21
28 FBA_D28
FBA_D29 B21
29 FBA_D29
FBA_D30 C20
30 FBA_D30 FB_CMD
FBA_D31 C21 FBA_CMD[31..0]
31 FBA_D31 BI 80
FBA_D32 R22
32 FBA_D32
FBA_D33 R24 C27 FBA_CMD0
33 FBA_D33 FBA_CMD0 0
FBA_D34 T22 C26 FBA_CMD1
34 FBA_D34 FBA_CMD1 1
FBA_D35 R23 E24 FBA_CMD2
35 FBA_D35 FBA_CMD2 2
FBA_D36 N25 F24 FBA_CMD3
36 FBA_D36 FBA_CMD3 3
FBA_D37 N26 D27 FBA_CMD4
37 FBA_D37 FBA_CMD4 4
FBA_D38 N23 D26 FBA_CMD5
38 FBA_D38 FBA_CMD5 5
FBA_D39 N24 F25 FBA_CMD6
39 FBA_D39 FBA_CMD6 6
FBA_D40 V23 F26 FBA_CMD7
40 FBA_D40 FBA_CMD7 7
FBA_D41 V22 F23 FBA_CMD8
41 FBA_D41 FBA_CMD8 8
FBA_D42 T23 G22 FBA_CMD9
B 42 FBA_D42 FBA_CMD9 9 B
FBA_D43 U22 G23 FBA_CMD10
43 FBA_D43 FBA_CMD10 10
FBA_D44 Y24 G24 FBA_CMD11
44 FBA_D44 FBA_CMD11 11
FBA_D45 AA24 F27 FBA_CMD12
45 FBA_D45 FBA_CMD12 12
FBA_D46 Y22 G25 FBA_CMD13
46 FBA_D46 FBA_CMD13 13
FBA_D47 AA23 G27 FBA_CMD14
47 FBA_D47 FBA_CMD14 14
FBA_D48 AD27 G26 FBA_CMD15
48 FBA_D48 FBA_CMD15 15
FBA_D49 AB25 M24 FBA_CMD16
49 FBA_D49 FBA_CMD16 16
FBA_D50 AD26 M23 FBA_CMD17
50 FBA_D50 FBA_CMD17 17
FBA_D51 AC25 K24 FBA_CMD18
51 FBA_D51 FBA_CMD18 18
FBA_D52 AA27 K23 FBA_CMD19
52 FBA_D52 FBA_CMD19 19
FBA_D53 AA26 M27 FBA_CMD20
53 FBA_D53 FBA_CMD20 20
FBA_D54 W26 M26 FBA_CMD21
54 FBA_D54 FBA_CMD21 21
FBA_D55 Y25 M25 FBA_CMD22
55 FBA_D55 FBA_CMD22 22
FBA_D56 R26 K26 FBA_CMD23
56 FBA_D56 FBA_CMD23 23
FBA_D57 T25 K22 FBA_CMD24
57 FBA_D57 FBA_CMD24 24
FBA_D58 N27 J23 FBA_CMD25
58 FBA_D58 FBA_CMD25 25
FBA_D59 R27 J25 FBA_CMD26
59 FBA_D59 FBA_CMD26 26
FBA_D60 V26 J24 FBA_CMD27
60 FBA_D60 FBA_CMD27 27
FBA_D61 V27 K27 FBA_CMD28
61 FBA_D61 FBA_CMD28 28
FBA_D62 W27 K25 FBA_CMD29
FBA_D62 FBA_CMD29
62 FBA_D63 W25 FBA_D63 FBA_CMD30 J27 FBA_CMD30 29
1.35V
63 FBA_CMD31 30
FBA_CMD31 J26 FBVDDQ_GPU
SNN_FBA_CMD<32> 31
FBA_CMD32 B19
FBA_DEBUG0
D19 FBA_DQM0 FBA_CMD34 F22 R540 60.4R 1%R0402_N
80 FBA_DBI0 FBA_DEBUG1 NI
D14 FBA_DQM1 FBA_CMD35 J22 R539 60.4R 1%R0402_N
80 FBA_DBI1 NI
C17 FBA_DQM2
80 FBA_DBI2
C22 FBA_DQM3
80 FBA_DBI3
P24 FBA_DQM4
80 FBA_DBI4
W24 FBA_DQM5
80 FBA_DBI5
AA25 FBA_DQM6
80 FBA_DBI6
U25 FBA_DQM7
80 FBA_DBI7

E19 FBA_DQS_WP0
80 FBA_EDC0
C15 FBA_DQS_WP1
80 FBA_EDC1 FBA_CLK0_P
B16 FBA_DQS_WP2 FBA_CLK0 D24 DP_FBA_CLK0_RC FB_CLK
80 FBA_EDC2 FBA_CLK0_N OUT 80
B22 FBA_DQS_WP3 FBA_CLK0 D25 DP_FBA_CLK0_RC FB_CLK
80 FBA_EDC3 FBA_CLK1_P OUT 80
C R25 FBA_DQS_WP4 FBA_CLK1 N22 DP_FBA_CLK1_CM FB_CLK C
80 FBA_EDC4 FBA_CLK1_N OUT 80
W23 FBA_DQS_WP5 FBA_CLK1 M22 DP_FBA_CLK1_CM FB_CLK
80 FBA_EDC5 OUT 80
AB26 FBA_DQS_WP6
80 FBA_EDC6
T26 FBA_DQS_WP7
80 FBA_EDC7

F19 D18 FBA_WCK01_P


FBA_DQS_RN0 FBA_WCK01 DP_FBA_WCK01 FB_WCK OUT 80
C14 C18 FBA_WCK01_N
FBA_DQS_RN1 FBA_WCK01 DP_FBA_WCK01 FB_WCK
OUT 80
A16 D17 FBA_WCK23_P
FBA_DQS_RN2 FBA_WCK23 DP_FBA_WCK23 FB_WCK
OUT 80
A22 D16 FBA_WCK23_N
FBA_DQS_RN3 FBA_WCK23 DP_FBA_WCK23 FB_WCK
OUT 80
P25 T24 FBA_WCK45_P
FBA_DQS_RN4 FBA_WCK45 DP_FBA_WCK45 FB_WCK
OUT 80
W22 U24 FBA_WCK45_N
FBA_DQS_RN5 FBA_WCK45 DP_FBA_WCK45 FB_WCK OUT 80
AB27 V24 FBA_WCK67_P
FBA_DQS_RN6 FBA_WCK67 DP_FBA_WCK67 FB_WCK
OUT 80
T27 V25 FBA_WCK67_N
FBA_DQS_RN7 FBA_WCK67 DP_FBA_WCK67 FB_WCK
OUT 80 +1.8VS_VGA_MAIN

Place under GPU


R524 LB502
F16 0.300 FB_PLL_AVDD FB_PLLVDD 1 2
FB_PLL_AVDD
DIS 0R 1.5A
FBVDDQ_GPU R0603_N
FB_PLL_AVDD P22 30ohm@100MHz 3A 25%
5%
L0603
FB_REFPLL_AVDD H22 C544 C545 C547 DIS
0.1uF 10V 10% 0.1uF 10V 10% 22uF 6.3V 20%
R261 R260 X5R
X5RC0402_N C0402_N X5R
10K 10K DIS DIS C0603_N
5% 5% DIS
R0402_N R0402_N
FBA_CMD14 DIS DIS
FBA_CMD30

GND
FBA_CMD13
T132 FB_VREF_PROBE D23 FB_VREF
GND
FBA_CMD29

R523
R257 R256 N17S-LG-A1 DIS 0.300 FB_REFPLL_AVDD_GPU FB_PLLVDD
10K 10K DIS 0R
5% 5% R0603_N
R0402_N R0402_N 5%
C557 C558
DIS DIS
D
0.1uF 10V 10% 0.1uF 10V 10% D
X5RC0402_N C0402_N X5R
DIS DIS

GND
Place under GPU
Only one cap is required by DG

GND
FBVDDQ_GPU FBVDDQ_GPU 69,76,79,80

+1.8VS_VGA_MAIN +1.8VS_VGA_MAIN 74,75,76,79


Project: 320S-13
Engineer: Jason
Size Title:NV N17S(5/5)_MEM Rev
C V01
Date: Monday, April 10, 2017 Sheet 78 of 81

1 2 3 4 5
5 4 3 2 1

FBVDDQ_GPU
FBVDDQ
NVVDD

NVVDD
Under GPU 8x0402_1uF 2x0603_10uF

C556 C551
C553 C555 C554 C576 C563 C559 C566 C548 Place under GPU
10uF 6.3V 20%10uF 6.3V 20%
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% C0402_N C0402_N
X7R X7R X7R X7R X7R X7R X7R X7R
X5R X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
DIS DIS
DIS DIS DIS DIS DIS DIS DIS DIS C583 C588 C567 C565 C590 C586 C593 C592 C574 C577 C569
1uF 6.3V 10% 1uF 6.3V 10% 1uF 6.3V 10% 4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%
D X7R X7R X7R X5R X5R X5R X5R X5R X5R X5R X5R D
C0402 C0402 C0402 C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N C0603_N
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS

GND GND
Close to GPU 1x0603_10uF 3x0603W_22uF

C550 C549 C542 C538


10uF 6.3V 20% 22uF 6.3V 20%22uF 6.3V 20%22uF 6.3V 20%
C0402_N X5R X5R X5R
X5R C0603_N C0603_N C0603_N GND
DIS DIS DIS DIS
Place near GPU

C64 C63 C65 C70 C620 C614 C622 C613 C67 C66 C69
4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%22uF 6.3V 20%22uF 6.3V 20%22uF 6.3V 20%
GND GND DG Requirement X5R X5R X5R X5R C0402_N C0402_N C0402_N C0402_N X5R X5R X5R
C0603_N C0603_N C0603_N C0603_N X5R X5R X5R X5R C0603_N C0603_N C0603_N
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS

Close to GPU For Test Only

C543 C537
22uF 6.3V 20% 22uF 6.3V 20% Place near GPU Place near VRM GND
X5R X5R
C0603_N C0603_N
NI NI C508 C507
10uF 6.3V 20% 10uF 6.3V 20%
C0402_N C0402_N
X5R X5R
DIS DIS

GND
C C

GND
DG Requirement

near GPU = within 35mm of GPU center

NVVDD NVDD Place near GPU For Test Only

C596 C602 C612 C611 C607


Place under GPU 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
X5R X5R X5R X5R X5R
C0603_N C0603_N C0603_N C0603_N C0603_N
NI NI NI NI NI
C562 C585 C584 C591 C560 C568
1uF 6.3V 10% 1uF 6.3V 10% 4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%4.7uF 10V 10%
X7R X7R X5R X5R X5R X5R
C0402 C0402 C0603_N C0603_N C0603_N C0603_N
DIS DIS DIS DIS DIS DIS
GND

B GND B

Place near GPU

C913 C914 C924 C923 C921 C920 C3994 C922


10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%10uF 6.3V 20%22uF 6.3V 20% +1.8VS_VGA_MAIN
C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N X5R
X5R X5R X5R X5R X5R X5R X5R C0603_N
DIS DIS DIS DIS DIS DIS DIS DIS

VDD_MAIN
VDD18 Place under GPU Place near GPU

C660 C662
C594 C600 1uF 6.3V 10% 4.7uF 10V 10%
GND X7R X5R
0.1uF 10V 10%0.1uF 10V 10%
C0402 C0603_N
C0402_N X5R C0402_N X5R
DIS DIS DIS DIS

GND

1V8_AON
DG Requirement

VDD_AON Place under GPU Place near GPU


Place under GPU For Test Only
A A
C630 C631
C589 C587 1uF 6.3V 10% 4.7uF 10V 10%
C579 X7R X5R
22uF 6.3V 20% 0.1uF 10V 10%0.1uF 10V 10%
C0402 C0603_N
X5R C0402_N X5R C0402_N X5R
DIS DIS DIS DIS
C0603_N
NI
1V8_AON 1V8_AON 50,74,75,76
+1.8VS_VGA_MAIN +1.8VS_VGA_MAIN 74,75,76,78
NVVDD NVVDD 70,76,77
GND
Project: 320S-13
FBVDDQ_GPU FBVDDQ_GPU 69,76,78,80
GND Engineer: Jason
Size Title:NV N17S (DECOUPLING) Rev
C V01
Date: Monday, April 10, 2017 Sheet 79 of 81

5 4 3 2 1
5 4 3 2 1

FBA_D[31..0]
GDDR5 FBVDDQ_GPU FBA_D[63..32]
78 BI
U7 78 BI
FBVDDQ_GPU
FBA_D28 M2 B1 GDDR5
28 FBA_D31 DQ31 VDDQ_1 U8
M4 B3 FBA_D56
31 FBA_D29 DQ30 VDDQ_4 M2 B1
N2 B12 56 FBA_D63 DQ31 VDDQ_1
29 FBA_D30 DQ29 VDDQ_2 M4 B3
N4 B14 63 FBA_D57 DQ30 VDDQ_4
30 FBA_D27 DQ28 VDDQ_3 N2 B12
T2 D1 57 FBA_D62 DQ29 VDDQ_2
27 FBA_D26 DQ27 VDDQ_5 N4 B14
T4 D3 62 FBA_D58 DQ28 VDDQ_3
26 FBA_D24 DQ26 VDDQ_8 T2 D1
U2 D12 58 FBA_D61 DQ27 VDDQ_5
24 FBA_D25 DQ25 VDDQ_6 T4 D3
U4 D14 61 FBA_D59 DQ26 VDDQ_8
25 FBA_D21 DQ24 VDDQ_7 U2 D12
M13 E5 59 FBA_D60 DQ25 VDDQ_6
21 FBA_D23 DQ23 VDDQ_10 U4 D14
M11 E10 60 FBA_D50 DQ24 VDDQ_7
23 FBA_D20 DQ22 VDDQ_9 M13 E5
N13 F1 50 FBA_D55 DQ23 VDDQ_10
20 FBA_D22 DQ21 VDDQ_11 M11 E10
N11 F3 55 FBA_D48 DQ22 VDDQ_9
22 FBA_D19 DQ20 VDDQ_14 N13 F1
T13 F12 48 FBA_D54 DQ21 VDDQ_11
19 FBA_D17 DQ19 VDDQ_12 N11 F3
T11 F14 54 FBA_D51 DQ20 VDDQ_14
17 FBA_D18 DQ18 VDDQ_13 T13 F12
D U13 G2 51 FBA_D53 DQ19 VDDQ_12 D
18
FBA_D16 DQ17 VDDQ_16 T11 F14
U11 G13 53 FBA_D49 DQ18 VDDQ_13
16 FBA_D14 DQ16 VDDQ_15 U13 G2
F13 H3 49 FBA_D52 DQ17 VDDQ_16
14 FBA_D10 DQ15 VDDQ_18 U11 G13
F11 H12 52 FBA_D45 DQ16 VDDQ_15
10 FBA_D15 DQ14 VDDQ_17 F13 H3
E13 K3 45 FBA_D41 DQ15 VDDQ_18
15 FBA_D8 DQ13 VDDQ_20 F11 H12
E11 K12 41 FBA_D44 DQ14 VDDQ_17
8 FBA_D13 DQ12 VDDQ_19 E13 K3
B13 L2 44 FBA_D43 DQ13 VDDQ_20
13
FBA_D9 DQ11 VDDQ_22 E11 K12
B11 L13 43 FBA_D47 DQ12 VDDQ_19
9 FBA_D12 DQ10 VDDQ_21 B13 L2
A13 M1 47 FBA_D40 DQ11 VDDQ_22
12 FBA_D11 DQ9 VDDQ_23 B11 L13
A11 M3 40 FBA_D46 DQ10 VDDQ_21
11 FBA_D3 DQ8 VDDQ_26 A13 M1
F2 M12 46 FBA_D42 DQ9 VDDQ_23
3 FBA_D4 DQ7 VDDQ_24 A11 M3
F4 M14 42 FBA_D33 DQ8 VDDQ_26
4 FBA_D6 DQ6 VDDQ_25 F2 M12
E2 N5 33 FBA_D34 DQ7 VDDQ_24
6 FBA_D1 DQ5 VDDQ_28 F4 M14
E4 N10 34 FBA_D35 DQ6 VDDQ_25
1 FBA_D7 DQ4 VDDQ_27 E2 N5
B2 P1 35 FBA_D32 DQ5 VDDQ_28
7 FBA_D2 DQ3 VDDQ_29 E4 N10
B4 P3 32 FBA_D36 DQ4 VDDQ_27
2 FBA_D5 DQ2 VDDQ_32 B2 P1
A2 P12 36 FBA_D37 DQ3 VDDQ_29
5
FBA_D0 DQ1 VDDQ_30 B4 P3
A4 P14 37 FBA_D38 DQ2 VDDQ_32
0 DQ0 VDDQ_31 A2 P12
T1 38 FBA_D39 DQ1 VDDQ_30
VDDQ_33 A4 P14
T3 39 DQ0 VDDQ_31
VDDQ_36 T1
FBA_CMD[31..0] T12 VDDQ_33
VDDQ_34 T3
78,80 IN T14 VDDQ_36
VDDQ_35 FBVDDQ_GPU FBA_CMD[31..0] T12
VDDQ_34
FBA_CMD9 78,80 IN T14
J5 VDDQ_35 FBVDDQ_GPU
9 FBA_CMD6 RFU/A12/NC
K4 C5 FBA_CMD25
6 FBA_CMD7 A7/A8 VDD_2 J5
K5 C10 25 FBA_CMD22 RFU/A12/NC
7 FBA_CMD4 A6/A11 VDD_1 K4 C5
K10 D11 22 FBA_CMD23 A7/A8 VDD_2
4 FBA_CMD3 A5/BA1 VDD_3 K5 C10
K11 G1 23 FBA_CMD20 A6/A11 VDD_1
3 FBA_CMD1 A4/BA2 VDD_4 K10 D11
H10 G4 20 FBA_CMD19 A5/BA1 VDD_3
1 FBA_CMD2 A3/BA3 VDD_7 K11 G1
H11 G11 19 FBA_CMD17 A4/BA2 VDD_4
2 FBA_CMD11 A2/BA0 VDD_5 H10 G4
H5 G14 17 FBA_CMD18 A3/BA3 VDD_7
11 FBA_CMD10 A1/A9 VDD_6 H11 G11
H4 L1 18 FBA_CMD27 A2/BA0 VDD_5
10 A0/A10 VDD_8 H5 G14
L4 27 FBA_CMD26 A1/A9 VDD_6
VDD_11 H4 L1
L11 26 A0/A10 VDD_8
VDD_9 L4
L14 VDD_11
FBA_WCK01_P VDD_10 L11
D4 P11 VDD_9
78 IN FBA_WCK01_N WCK01 VDD_12 L14
D5 R5 FBA_WCK45_P VDD_10
78 IN WCK01# VDD_14 D4 P11
R10 78 IN FBA_WCK45_N WCK01 VDD_12
C FBA_WCK23_P VDD_13 D5 R5 C
P4 78 IN WCK01# VDD_14
78 IN FBA_WCK23_N WCK23 R10
P5 VDD_13
78 IN WCK23# FBA_WCK67_P P4
A1 78 IN
FBA_WCK67_N WCK23
VSSQ_1 P5
R2 A3 78 IN WCK23#
78 FBA_EDC3 EDC3 VSSQ_4 A1
R13 A12 VSSQ_1
78 FBA_EDC2 EDC2 VSSQ_2 R2 A3
C13 A14 78 FBA_EDC7 EDC3 VSSQ_4
78 FBA_EDC1 EDC1 VSSQ_3 R13 A12
C2 C1 78 FBA_EDC6 EDC2 VSSQ_2
78 FBA_EDC0 EDC0 VSSQ_5 C13 A14
C3 78 FBA_EDC5 EDC1 VSSQ_3
VSSQ_9 C2 C1
P2 C4 78 FBA_EDC4 EDC0 VSSQ_5
78 FBA_DBI3 DBI3# VSSQ_10 C3
P13 C11 VSSQ_9
78 FBA_DBI2 DBI2# VSSQ_6 P2 C4
D13 C12 78 FBA_DBI7 DBI3# VSSQ_10
78 FBA_DBI1 DBI1# VSSQ_7 P13 C11
D2 C14 78 FBA_DBI6 DBI2# VSSQ_6
78 FBA_DBI0 DBI0# VSSQ_8 D13 C12
E1 78 FBA_DBI5 DBI1# VSSQ_7
VSSQ_11 D2 C14
E3 78 FBA_DBI4 DBI0# VSSQ_8
VSSQ_14 E1
E12 VSSQ_11
FBA_CMD12 VSSQ_12 E3
G3 E14 VSSQ_14
12 FBA_CMD15 RAS# VSSQ_13 E12
L3 F5 FBA_CMD28 VSSQ_12
15 CAS# VSSQ_16 G3 E14
F10 28 FBA_CMD31 RAS# VSSQ_13
VSSQ_15 L3 F5
H2 31 CAS# VSSQ_16
FBA_CMD14 VSSQ_18 F10
J3 H13 VSSQ_15
FBA_CLK0_N 14 CKE# VSSQ_17 H2
J11 K2 FBA_CMD30 VSSQ_18
78 IN FBA_CLK0_P CK# VSSQ_20 J3 H13
J12 K13 FBA_CLK1_N 30 CKE# VSSQ_17
78 IN CK VSSQ_19 J11 K2
M5 78 IN FBA_CLK1_P CK# VSSQ_20
VSSQ_22 J12 K13
M10 78 IN CK VSSQ_19
R251 R252 FBA_CMD0 VSSQ_21 M5
1% 40.2R 1% G12 N1 VSSQ_22
40.2R 0 FBA_CMD5 CS# VSSQ_23 M10
R0402_N R0402_N L12 N3 R250 R249 FBA_CMD16 VSSQ_21
5 WE# VSSQ_26 1% 1% G12 N1
DIS DIS N12 40.2R 40.2R 16 FBA_CMD21 CS# VSSQ_23
VSSQ_24 R0402_N R0402_N L12 N3
N14 21 WE# VSSQ_26
1% VSSQ_25 DIS DIS N12
R8002 121R J13 R1 VSSQ_24
FBA_CLK0_RC R0402_N DIS ZQ VSSQ_27 N14
J10 R3 1% VSSQ_25
SEN VSSQ_31 R255 121R J13 R1
R4 FBA_CLK1_RC R0402_N DIS ZQ VSSQ_27
VSSQ_32 J10 R3
C100 FBA_CMD13 VSSQ_28
R11 SEN VSSQ_31
R4
10nF 50V 13
J2
RESET# VSSQ_29
R12
C101
VSSQ_32
R11
X7R J1
MF VSSQ_30
R14
10nF 50V
FBA_CMD29 J2
VSSQ_28
R12
C0402 VSSQ_33
U1
X7R
29
J1
RESET# VSSQ_29
R14
DIS VSSQ_36
U3
U12 C0402
MF VSSQ_30
U1
VSSQ_33
B
VSSQ_34
U14 DIS VSSQ_36
U3
U12
B
VSSQ_35
FBVDDQ_GPU GND A5 VSSQ_34
Vpp/NC_1 U14
U5 VSSQ_35
Vpp/NC_2 GND A5
B5 Vpp/NC_1
VSS_2 U5
A10 B10 Vpp/NC_2
VREFD_1 VSS_1 B5
R263 U10 D10 VSS_2
VREFD_2 VSS_3 A10 B10
549R G5 VREFD_1 VSS_1
1% VSS_5 U10 D10
G10 VREFD_2 VSS_3
R0402_N VSS_4 G5
H1 VSS_5
DIS VSS_6 G10
H14 VSS_4
VSS_7 H1
0.099 K1 VSS_6
FBA_VREFC VSS_8 H14
J14 K14 VSS_7
VREFC VSS_9 K1
L5 FBA_VREFC VSS_8
VSS_11 J14 K14
L10 IN VREFC VSS_9
VSS_10 L5
R259 R258 C109 P10 VSS_11
FBA_CMD8 VSS_12 L10
1.33K 931R 820pF 50V 10% J4 T5 VSS_10
1% 1% X7R
8 ABI# VSS_14 C110 P10
T10 FBA_CMD24 VSS_12
R0402_N R0402_N C0402_N VSS_13 820pF 50V 10% J4 T5
X7R
24 ABI# VSS_14
DIS DIS DIS T10
C0402_N VSS_13
SGRAM_BGA-170P_2GBIT DIS
DIS
SGRAM_BGA-170P_2GBIT
DIS
GND GND
FBVDDQ_GPU
0.099 FBA_VREF_Q GND

D Q23 Around DRAM


GPIO10_FBVREF_SEL
PJA138K
75 IN
S
DIS
G
C114 C117 C523 C105
22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20% 22uF 6.3V 20%
X5R X5R X5R X5R
C0603_N C0603_N C0603_N C0603_N
NI NI DIS DIS
FBVDDQ_GPU
GND
Around DRAM
Close to DRAM
FBVDDQ_GPU
A A
Close to DRAM
C8013 C8004 C10018 C10019 C10020 C10021
10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20% 10uF 6.3V 20%
X5R X5R X5R X5R X5R X5R
C8005 C8006 C8007 C8008 C8009 C8010 C8011 C8012 C8014 C8015 C0603 C0603 C0603 C0603 C0603 C0603
1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% 1uF 10V 10% DIS DIS DIS DIS DIS DIS
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N C0402_N
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS

Project: 320S-13
Engineer: Jason
FBVDDQ_GPU FBVDDQ_GPU 69,76,78,79 Size Title:VRAM (GDDR5) Rev
C V01
Date: Monday, April 10, 2017 Sheet 80 of 81

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Project: 320S-13
Engineer: Jason
Size Title:RSVD Rev
D V01
Date: Monday, April 10, 2017 Sheet 81 of 81
5 4 3 2 1

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