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Roll No ..................................
CS/CI-404-CBGS
B.Tech., IV Semester
Examination, June 2020
Choice Based Grading System (CBGS)
Computer Organisation and Architecture
Time : Three Hours
Maximum Marks : 70
Note: i) Attempt any five questions.
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ii) All questions carry equal marks.
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iii) In case of any doubt or dispute the English version
question should be treated as final.
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o« r ^mfm
Ho$ àíZ H$mo A§{V‘ ‘mZm Om¶oJm&
1. a) Explain the purpose of General register, Memory register
and instruction register with example. 7
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a{OñQ>a H$m CÔoí¶ ñnï> H$a|&
b) Explain sequencing and execution of micro instruction.
7
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2. a) Explain the concepts of instruction and describe
instruction cycle with neat diagram. 7
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{ZX}e MH«$ H$m dU©Z H$a|&
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b) With the help of a block diagram, explain the basic


organization of a computer system. 7
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H$s ì¶m»¶m H$a|&

3. a) Write short notes on: 7


i) PCI Bus
ii) SCSI Bus
iii) USB
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i) nr gr AmB© ~g
ii) SCSI ~g
iii) ¶w Eg ~r
b) Explain in detail, the different modes of data transfer
between the processor/memory and I/O devices in a
computer system. 7
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4. a) Discuss in detail any two mapping methods in cache


memory. 7
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H$a|&
b) With a diagram, explain address translation in virtual
memory. 7
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§ boeZ H$s ì¶m»¶m H$a|&

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5. a) Convert the following pairs of decimal numbers to 5-bit


signed 2’s complement binary numbers and add them, state
whether overflow has occurred. 7
i) –5 and 7
ii) –10 and –13
iii) –14 and 11
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i) –5 Am¡a 7
ii) –10 Am¡a –13
iii) –14 Am¡a 11
b) Explain Booth’s algorithm, multiply +15 and –6 using
Booth’s multiplication. 7
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+15 Am¡a –6 H$mo JwUm H$a|&

6. a) Explain the concept of carry-save addition for the


multiplication operation M × Q = P for 4-bit operands,
with diagram and suitable example. 7
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g‘PmBE&
b) Explain the structure of general purpose multiprocessors
with diagrams. 7
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o a H$s g§aMZm H$mo
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7. Explain the following: 14


i) Vector processing
ii) Array processing
iii) RISC and CISC
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ii) gaUr àg§ñH$aU
iii) RISC Am¡a CISC

8. a) Explain concept of pipelining in multiprocessors. 7


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b) Explain mechanisms direct memory Access and interrupt
handling. 7
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******

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