ESD5302N

ESD5302N

2-Lines, Uni-directional, Ultra-low Capacitance http//:www.sh-willsemi.com

Transient Voltage Suppressors

Descriptions

The ESD5302N is an ultra-low capacitance TVS (Transient

Voltage Suppressor) array designed to protect high speed
data interfaces. It has been specifically designed to protect
sensitive electronic components which are connected to data DFN1006-3L (Bottom View)
and transmission lines from over-stress caused by ESD
(Electrostatic Discharge).
2
The ESD5302N incorporates two pairs of ultra-low
capacitance steering diodes plus a TVS diode.

The ESD5302N may be used to provide ESD protection up to

±20kV (contact and air discharge) according to 3
IEC61000-4-2, and withstand peak pulse current up to 4A
(8/20μs) according to IEC61000-4-5.

The ESD5302N is available in DFN1006-3L package.

Standard products are Pb-free and Halogen-free. 1

Circuit diagram
Features

 Stand-off voltage: 5V max.

 Transient protection for each line according to 2
IEC61000-4-2 (ESD): ±20kV (contact and air discharge)
IEC61000-4-4 (EFT): 40A (5/50ns) 1
3* 3

IEC61000-4-5 (surge): 4A (8/20μs)

 Ultra-low capacitance: CJ = 0.4pF typ.
3 = Device code
 Ultra-low leakage current: IR <1nA typ.
* = Month code ( A~Z)
 Low clamping voltage: VCL = 17. 5V @ IPP = 16A(TLP)
Marking (Top View)
 Solid-state silicon technology

Applications
Order information
 USB 2.0 and USB 3.0
 HDMI 1.3 and HDMI 1.4 Device Package Shipping
 SATA and eSATA ESD5302N-3/TR DFN1006-3L 10000/Tape&Reel
 DVI
 IEEE 1394
 PCI Express
 Portable Electronics and Notebooks

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 ESD5302N
Absolute maximum ratings

Parameter Symbol Rating Unit

Peak pulse power (tp = 8/20μs) Ppk 60 W
Peak pulse current (tp = 8/20μs) IPP 4 A
ESD according to IEC61000-4-2 air discharge ±20
VESD kV
ESD according to IEC61000-4-2 contact discharge ±20
o
Operation junction temperature TJ 125 C
o
Lead temperature TL 260 C
o
Storage temperature TSTG -55~150 C

Electrical characteristics (TA = 25 oC, unless otherwise noted)

Parameter Symbol Condition Min. Typ. Max. Unit

Reverse maximum working voltage VRWM 5.0 V

Reverse leakage current IR VRWM = 5V <1 100 nA

Reverse breakdown voltage VBR IT = 1mA 7.0 8.0 9.0 V

Forward voltage VF IT = 10mA 0.6 0.9 1.2 V

1)
Clamping voltage VCL IPP = 16A, tp = 100ns 17.5 V

Ω
1)
Dynamic resistance RDYN 0.53

IPP = 1A, tp = 8/20μs 11 V

2)
Clamping voltage VCL
IPP = 4A, tp = 8/20μs 15 V
VR = 0V, f = 1MHz
0.40 0.65 pF
Pin1 or 2 to Pin3
Junction capacitance CJ
VR = 0V, f = 1MHz
0.25 0.40 pF
Between Pin1 and Pin2
Notes:
1) TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 2ns, averaging window from 60ns to 80ns. RDYN is calculated from 4A to
16A.
2) Non-repetitive current pulse, according to IEC61000-4-5.

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o
Typical characteristics (TA = 25 C, unless otherwise noted)

110 100
Front time: T1= 1.25 × T = 8µs
100 90
Time to half-value: T2= 20µs
Peak pulse current (%)

90
80

Current (%)
70
60
50
40
T2
30
20
10 10
0 60ns t
0 5 T 10 15 20 25 30 35 40 30ns
T1 Time (µs) tr = 0.7~1ns
Time (ns)
8/20μs waveform per IEC61000-4-5 Contact discharge current waveform per IEC61000-4-2

0.50
CJ - Junction capacitance (pF)

Pulse waveform: tp = 8/20µs f = 1MHz

14 0.45
VC - Clamping voltage (V)

Pin1 or 2 to Pin3
0.40
12
0.35

0.30
10
Between Pin1 and Pin2
0.25

8 0.20
0 1 2 3 4 5 0 1 2 3 4 5
IPP - Peak pulse current (A) VR - Reverse voltage (V)
Clamping voltage vs. Peak pulse current Capacitance vs. Reveres voltage

1000
100
Peak pulse power (W)

80
100
% of Rated power

60

40
10

20

1 0
1 10 100 1000 0 25 50 75 100 125 150
o
Pulse time (µs) TA - Ambient temperature ( C)
Non-repetitive peak pulse power vs. Pulse time Power derating vs. Ambient temperature

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o
Typical characteristics (TA = 25 C, unless otherwise noted)

ESD clamping ESD clamping

(+8kV contact discharge per IEC61000-4-2) (-8kV contact discharge per IEC61000-4-2)

20
18
16
14
TLP current (A)

12
10
8
6 Z0 = 50 Ω
4
tr = 2ns
2
tp = 100ns
0
-2
0 2 4 6 8 10 12 14 16 18 20 22
TLP voltage (V)

TLP Measurement

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Application Information

The ESD5302N is designed to protect two high speed line against ESD. Fig1 is shown the connection and
Fig2 is shown PCB Layout guide for USB interface ESD protection

VBUS

DM

DP VBUS

ID
DM
GND
DP

ID

GND

Fig1 Fig2

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Package outline dimensions
DFN1006-3L

Top View Bottom View

Side View

Dimensions in millimeter
Symbol
Min. Typ. Max.
A 0.40 - 0.50
A1 0.00 - 0.05
A3 0.125 REF
D 0.95 1.00 1.05
E 0.55 0.60 0.65
b1 0.10 0.15 0.20
b2 0.20 0.25 0.30
L1 0.20 0.30 0.40
L2 0.40 0.50 0.60
e1 0.350 BSC
e2 0.675 BSC

Recommend land pattern (Unit: mm)

0.45 0.45
0.25

Notes:
0.70

0.20

This recommended land pattern is for reference

purposes only. Please consult your manufacturing
group to ensure your PCB design guidelines are met.

0.25
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Tape and Reel Specification

Dimensions in millimeter
Symbol
Min. Typ. Max.
A0 0.65 0.70 0.75
B0 1.10 1.15 1.20
K0 0.50 0.55 0.60
F 3.45 3.50 3.55
P1 1.90 2.00 2.10
W 7.90 8.00 8.10

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