VLSI LAB Record

JNTU-GV COLLEGE OF ENGINEERING
VIZIANAGARAM (A)
Department of Electronics and Communication Engineering
Name of the Student:
Branch:
Roll Number:
Name of the Lab:
Academic Year:
INDEX :
Page Marks
S. No Date of Name of The Experiment Remarks
Number Awarded
Experiment
1
10
11
12
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY GURAJADA,VIZIANAGARAM
JNTU-GV COLLEGE OF ENGINEERING VIZIANAGARAM (A)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
III - B.TECH - II SEMESTER
VLSI DESIGN LAB DAY TO DAY EVALUATION SHEET
1. NAME OF THE STUDENT :

2. ROLL NO :
Date of Experiment
S. No Activity 1 2 3 4 5 6 7 8 9 10 11 12
Initial Preparation (4M)
1
Observations, Model Graphs Etc., (4M)

2
Tidiness Of His/ Her Working Area

3 After The Experiment(2M)
MAXIMUM MARKS 10 10 10 10 10 10 10 10 10 10 10 10
FINAL MARKS
SIGNATURE OF THE STUDENT SIGNATURE OF THE STAFF

Circuit Diagram:
Symbol Generated:
Exp.No: 1 Date:
INVERTER
AIM:
SOFTWARE TOOLS : Tanner EDA tools
1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
The Logic NOT Gate is the most basic of all the logical gates and is often referred to as
an Inverting Buffer or simply an Inverter. A CMOS inverter contains a PMOS and a NMOS
transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source
terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the
gate terminals and VOUT is connected to the drain terminals. the voltage at the input of the
CMOS device varies between 0 and 5 volts, the state of the NMOS and PMOS varies
accordingly. When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly
charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is on”:
draining the voltage at VOUT to logic low.
PROCEDURE:
Schematic Procedure:
1. Open S-Edit and create a new design file following the path:
File > new > new design, and save the file.
2. Add the library files by following the path:
Add > tanner EDA > tanner tools v14.1 > libraries > all > all tanner.
3. Open the new schematic view by following the path:
Cell > new view > ok.
4. Create the design and save the schematic layout of the design.
5. Now go to the simulation and select the preferred library file and select the type
of the simulation and now click on run simulation to simulate it in T-Edit.
6. Now observe the waveforms of the design in W-Edit.
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
1. Open the L-edit and create a new cell.
2. Create the layout design and save it.
3. Check the design rule errors by running DRC check.
4. Extract the layout design by going to tools.
5. Run extract for the extraction of the layout.
6. Generate the netlist on T-Spice by forcing the input and run the netlist and observe
the waveforms in W-Edit.
PRECAUTIONS:
1. Make sure while making the connections.
2. Verify the circuit before simulating.
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp.No: 2a Date:
2 INPUT NAND GATE

AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
The NAND or “Not AND” function is a combination of the two separate logical
functions, the AND function and the NOT function connected in series. The logic NAND
function can be expressed by the Boolean expression of A.B. The Logic NAND Function only
produces an output when “ANY” of its inputs are not present and in Boolean Algebra terms the
output will be TRUE only when any of its inputs are FALSE. A LOW (0) output results only if
both the inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output
results.
PROCEDURE:
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp.No: 2b Date:
2 INPUT NOR GATE

AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
The Logic NOR Gate is a combination of the digital logic OR gate and an inverter or
NOT gate connected in series. The inclusive NOR (Not-OR) gate has an output that is
normally at logic level “1” and only goes “LOW” to logic level “0” when ANY of its
inputs are at logic level “1”. The Logic NOR Gate is the reverse or “Complementary”
form of the inclusive OR gate. The logic or Boolean expression given for a logic NOR
gate is that for Logical Multiplication which it performs on the complements of the
inputs. It’s symbol shape is that of a standard OR gate with a circle, sometimes called
an “inversion bubble” at its output to represent the NOT gate symbol with the logical
operation of the NOR gate.
PROCEDURE:
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp.No : 3 Date:
FULL ADDER
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
An adder is a digital logic circuit in electronics that implements addition of numbers. In
many computers and other types of processors, adders are used to calculate addresses,
similar operations and table indices in the ALU and also in other parts of the processors.
These can be built for many numerical representations like excess-3 or binary coded
decimal. Adders are classified into two types: half adder and full adder. The half adder
circuit has two inputs: A and B, which add two input digits and generate a carry and sum.
The full adder circuit has three inputs: A and C, which add the three input numbers and
generate a carry and sum. This article gives brief information about half adder and full
adder in tabular forms and circuit diagrams.
The first two inputs are A and B and the third input is an input carry as C-IN. When a
full-adder logic is designed, you string eight of them together to create a bytewide adder
and cascade the carry bit from one adder to the next. When all inputs bits are 0, the output
is 0. The sum output is equal to 1 when only one input is equal to 1 or when all three
inputs are equal to 1. The carry output has a carry of 1 if two or three inputs are equal to
PROCEDURE:
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp. No: 4 Date:
FULL SUBTRACTOR
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
A full subtractor is a combinational circuit that performs subtraction of two bits, one
is minuend and other is subtrahend, taking into account borrow of the previous
adjacent lower minuend bit. This circuit has three inputs and two outputs. The three
inputs A, B and Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference and output borrow,
respectively
PROCEDURE:
5. Now go to the simulation and select the preferred library file and select the type of
the simulation and now click on run simulation to simulate it in T-Edit.
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp.No: 5 Date:
DECODER
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of
2noutput lines. One of these outputs will be active Low based on the combination of
inputs present. That means decoder detects a particular code. The outputs of the decoder
are nothing but the min terms of ‘n’ input variables (lines).
2 to 4 Decoder has two inputs A1 & A0 and four outputs D3, D2, D1 & D0. One of these
four outputs will be ‘0’ for each combination of inputs. Therefore, the outputs of 2 to 4
decoder are nothing but the min terms of two input variables A 1 & A0,
PROCEDURE:
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout :
Result :
Circuit Diagram:
CMOS CIRCUIT DIAGRAM:

Exp.No: 6 Date:
2*1-Multiplexer
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
When S=0, it is applied directly as an input to the second AND gate, and inverted S that
is 1 is applied as a second input to the first AND gate. Now, we know that for AND gate
if any one input is zero, the output is zero. So, the output of the second AND gate is zero.
Since the second input to the first AND gate is 1, its output is equal to its first input, which
is Y = D0.When S=1, Exactly the reverse happens. In this case, the second AND gate
output is equal to its first input, that is Y = D1 and the first AND gate output is 0.So, by
applying either a logic ‘0’ or a logic ‘1’ at the select input S, we can select the appropriate
input, D0 or D1 with the circuit act like a single pole double throw (SPDT) switch.
PROCEDURE:
WAVE FORMS:
Transient Analysis
Layout:
Layout Procedure:
10.Extract the layout design by going to tools.
11.Run extract for the extraction of the layout.
12.Generate the netlist on T-Spice by forcing the input and run the netlist and observe
PRECAUTIONS:
Result :
Circuit Diagram:
Symbol Generated:
Exp.No: 7 Date:
RS LATCH
AIM:

5. S-EDIT
6. T-EDIT
7. W-EDIT
8. L-EDIT
THEORY:
When using static gates as building blocks, the most fundamental latch is the simple
SR latch, where S and R stand for set and reset. It can be constructed from a pair of
cross-coupled NAND logic gates. The stored bit is present on the output marked Q.
While the R and S inputs are both high, feedback maintains the Q and QB outputs in
a constant state. If S (Set) is pulsed high while R (Reset) is held low, then the Q output
is forced low, and stays low when S returns to high; similarly, if R is pulsed high
while S is held low, then the Q output is forced high.
The R = S = 0 combination is called a restricted combination or a forbidden state

because, as both NAND gates then output 1’s, it breaks the logical equation Q =
not Q
PROCEDURE:
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp.No: 8 Date:
D-LATCH
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
The D-type latch uses two additional gates in front of the basic NAND-type RS-
flipflop, and the input lines are usually called C (or clock) and D (or data). The
function of the D-latch is as follows:
First, note that the clock signal is connected to both of the front NAND gates.
Therefore, if the clock signal is zero, the outputs of the NAND gates are both 1, and
this implies that the RS flipflop stores the previous value. Therefore, if the C input is
0, the flipflop stores its value.
On the other hand, if the clock signal is 1, the output of the first NAND gate is the
inverse of the D input signal, and the output of the second nand gate is not(not(D)) =
D. This leads to the input values R=0/S=1 or R=1/S=0 on the RSflipflop, which in
turns enters the corresponding state. Therefore, if the C input is 1, the flipflop output
value follows to the value on its D input (the latch is 'transparent').
PROCEDURE:
Test Bench:
Waveforms:
DC Analysis
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Symbol Generated:
Exp.No: 9 Date:
STATIC RAM CELL

AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
A typical SRAM cell is made up of 2 inverters and 2 NMOSFETS. Each bit in an
SRAM is stored on two cross-coupled inverters. This storage cell has two stable
states which are used to denote 0 and 1. Two additional access transistors serve to
control the access to a storage cell during read and write operations. Access to the
cell is enabled by the word line (WL in figure) which controls the two access
transistors which, in turn, control whether the cell should be connected to the bit
lines: BL and BL. They are used to transfer data for both read and write operations.
An SRAM cell has three different states: standby (the circuit is idle), reading (the data
has been requested) or writing (updating the contents). The three different states work as
follows:
Standby:
If the word line is not asserted, the access transistors M5 and M6 disconnect
the cell from the bit lines. The two cross-coupled inverters will continue to reinforce
each other as long as they are connected to the supply.
Reading:
In theory, reading only requires asserting the word line WL and reading the
SRAM cell state by a single access transistor and bit line, e.g. M6, BL. The read cycle
is started by precharging both bit lines BL and BLB, i.e. driving the bit lines to a
threshold voltage (midrange voltage between logical 1 and 0) by an external module.
Then asserting the word line WL, enabling both the access transistors M 5 and M6
which causes the bit line BL voltage to either slightly drop or rise. It should be noted
Test Bench:
Waveforms:
DC Analysis
will sense which line has the higher voltage and thus determine whether there was 1
or 0 stored.
that if BL voltage rises, the voltage drops, and vice versa. Then the BL and lines will
have a small voltage difference between them. A sense amplifier
Writing:
The write cycle begins by applying the value to be written to the bit lines. If we wish
to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and to 0. A 1
is written by inverting the values of the bit lines. WL is then asserted and the value
that is to be stored is latched in.
PROCEDURE:
10.Create the design and save the schematic layout of the design.
11.Now go to the simulation and select the preferred library file and select the type of
12.Now observe the waveforms of the design in W-Edit.
Layout Procedure:
PRECAUTIONS:
Transient Analysis
Layout:
Result:
Circuit Diagram:
Test Bench:
Exp.No: 10 Date:
DYNAMIC RAM CELL
AIM:

5. S-EDIT
6. T-EDIT
7. W-EDIT
8. L-EDIT
THEORY:
Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-

access semiconductor memory that stores each bit of data in a memory cell, usually
consisting of a tiny capacitor and a transistor, both typically based on metal–oxide–
semiconductor (MOS) technology. While most DRAM memory cell designs use a
capacitor and transistor, some only use two transistors. In the designs where a capacitor
is used, the capacitor can either be charged or discharged; these two states are taken to
represent the two values of a bit, conventionally called 0 and 1. The electric charge on
the capacitors gradually leaks away; without intervention the data on the capacitor would
soon be lost. To prevent this, DRAM requires an external memory refresh circuit which
periodically rewrites the data in the capacitors, restoring them to their original charge.
This refresh process is the defining characteristic of dynamic random-access memory, in
contrast to static random-access memory (SRAM) which does not require data to be
refreshed. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory),
since it loses its data quickly when power is removed. However, DRAM does exhibit
limited data remanence.
DRAM typically takes the form of an integrated circuit chip, which can consist of
dozens to billions of DRAM memory cells. DRAM chips are widely used in digital
electronics where low-cost and high-capacity computer memory is required. One of the
largest applications for DRAM is the main memory (colloquially called the "RAM") in
modern computers and graphics cards (where the "main memory" is called the graphics
memory). It is also used in many portable devices and video game consoles. In contrast,
Waveforms:
Write and Hold Operation
Read Operation
SRAM, which is faster and more expensive than DRAM, is typically used where speed is
of greater concern than cost and size, such as the cache memories in processors.
The need to refresh DRAM demands more complicated circuitry and timing than SRAM.
This is offset by the structural simplicity of DRAM memory cells: only one transistor and
a capacitor are required per bit, compared to four or six transistors in SRAM. This allows
DRAM to reach very high densities with a simultaneous reduction in cost per bit.
Refreshing the data consumes power and a variety of techniques are used to manage the
overall power consumption.
PROCEDURE:
13.Open S-Edit and create a new design file following the path:
14.Add the library files by following the path:
15.Open the new schematic view by following the path:
16.Create the design and save the schematic layout of the design.
17.Now go to the simulation and select the preferred library file and select the type of
18.Now observe the waveforms of the design in W-Edit.
Layout Procedure:
13.Open the L-edit and create a new cell.
14.Create the layout design and save it.
15.Check the design rule errors by running DRC check.
PRECAUTIONS:
Layout:
Result:
Circuit Diagram:
T-Latch Schematic
Asynchronous schematic
Exp.No: 11 Date:
ASYNCHRONOUS COUNTER
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
Asynchronous counters are those whose output is free from the clock signal. Because the
flip flops in asynchronous counters are supplied with different clock signals, there may be
delay in producing output.
The required number of logic gates to design asynchronous counters is very less. So they
are simple in design. Another name for Asynchronous counters is “Ripple counters”.
The number of flip flops used in a ripple counter is depends up on the number of states of
counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called
“Modulus” or “MOD” of the counter. The maximum number of states that a counter can
have is 2n where n represents the number of flip flops used in counter.
For example, if we have 2 flip flops, the maximum number of outputs of the counter is 4
i.e. 22. So it is called as “MOD-4 counter” or “Modulus 4 counter”.
PROCEDURE:
Waveforms:
2 bit asynchronous down counter
TransientAnalysis
Layout Procedure:
PRECAUTIONS:
LAYOUT:
Result:
Circuit Diagram:
Exp.No: 12 Date:
SYNCHRONOUS COUNTER
AIM:

1. S-EDIT
2. T-EDIT
3. W-EDIT
4. L-EDIT
THEORY:
The synchronous counter can be defined as, a counter which uses a clock signal
for transforming their transition. So, these counters mainly depend on the input of
the clock to modify state values. In this counter, all flip flops (FFs) are associated
with the same clock signal to activate simultaneously. An alternate name of this
counter is a simultaneous counter where there is no ripple effect & propagation
delay in these counters.
As compared to synchronous, asynchronous type designing is very simple but the
asynchronous counter has a limitation of maximum operating frequency. To
overcome this limitation, these counters are mainly designed by providing
simultaneous clocking so, the output changes in synchronization through the input
of the clock.
PROCEDURE:
Waveforms:
Layout Procedure:
PRECAUTIONS:
LAYOUT:
Result:

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JNTU-GV COLLEGE OF ENGINEERING

Name of the Student:

Name of the Lab:

III - B.TECH - II SEMESTER

VLSI DESIGN LAB DAY TO DAY EVALUATION SHEET

1. NAME OF THE STUDENT :

Observations, Model Graphs Etc., (4M)

Tidiness Of His/ Her Working Area

SIGNATURE OF THE STUDENT SIGNATURE OF THE STAFF

SOFTWARE TOOLS : Tanner EDA tools

2 INPUT NAND GATE

SOFTWARE TOOLS : Tanner EDA tools

2 INPUT NOR GATE

SOFTWARE TOOLS : Tanner EDA tools

SOFTWARE TOOLS : Tanner EDA tools

SOFTWARE TOOLS : Tanner EDA tools

SOFTWARE TOOLS : Tanner EDA tools

CMOS CIRCUIT DIAGRAM:

SOFTWARE TOOLS : Tanner EDA tools

SOFTWARE TOOLS : Tanner EDA tools

The R = S = 0 combination is called a restricted combination or a forbidden state

SOFTWARE TOOLS : Tanner EDA tools

STATIC RAM CELL

SOFTWARE TOOLS : Tanner EDA tools

SOFTWARE TOOLS : Tanner EDA tools

Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-

Write and Hold Operation

SOFTWARE TOOLS : Tanner EDA tools

2 bit asynchronous down counter

SOFTWARE TOOLS : Tanner EDA tools

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