MANIPAL UNIVERSITY JAIPUR

School of Computing and IT

Department of Computer Science and Engineering
Course Hand-out
Computer Organization | CS 2203 | 4 Credits | 3 0 1 4
Session: Jan 23 – May 23 | Faculty: Dr Umashankar Rawat | Dr. S.S. Shekhawat | Mr. Shishir Singh Chauhan | Dr. Amit
Garg | Dr. Anurag Singh Tomar | Ms. Sushma Tanwar | Mr. Girish Sharma | Ms. Shweta Sharma

Class: IV Semester

A. Introduction: This course is offered by Dept. of Computer Science and Engineering for fourth semester
students. The core objective of this course is to describe the organization and architecture of a computer
system. It covers in detail processor datapath and control unit, pipelining, and input-output organization.

B. Course Outcomes: At the end of the course, students will be able to

[2203.1]. Build sequences of control signals for a given instruction and model the control unit design.
[Level 3: Apply]
[2203.2]. Identify the speed-up with instruction pipeline and effect of various pipeline hazards.
[Level 3: Apply]
[2203.3]. Make use of various cache mapping techniques for improving performance.
[Level 3: Apply]
[2203.4]. Compare various I/O data transfer techniques.
[Level 2: Understanding]
[2203.5]. Explain the various methodologies for parallel processing.
[Level 2: Understanding]

C. PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES

[PO.1] Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.
[PO.2] Problem analysis: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
[PO.3] Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
[PO.4] Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
[PO.5] Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
 [PO.6] The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal, and cultural issues, and the consequent responsibilities relevant to
the professional engineering practice.
[PO.7] Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
[PO.8] Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practices
[PO.9] Individual and teamwork: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings
[PO.10] Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions
[PO.11] Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
[PO.12] Life-long learning: Recognize the need for and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

[PSO.1] Will be able to design, develop and implement efficient software for a given real life problem.
[PSO.2] Will be able to apply knowledge of AI, Machine Learning and Data Mining in analyzing big data
for extracting useful information from it and for performing predictive analysis.
[PSO.3] Will be able to design, manage and secure wired/ wireless computer networks for transfer and
sharing of information.

D. Assessment Plan:

Criteria Description Date (Tentative) Maximum Marks

MTE (Closed Book) March 15 30
Internal Assessment Assignment --- 5
(Summative) Quizzes (3) Regularly 15
Tutorial --- 10
End Term Exam End Term Exam (Closed May 1 40
(Summative) Book)
Total 100
Attendance A minimum of 75% Attendance is required to be maintained by a student to be
(Formative) qualified for taking up the End Semester examination. The allowance of 25%
includes all types of leaves including medical leaves.
Make up Assignments. Students who miss a class will have to report to the teacher about the absence. A
(Formative) makeup assignment on the topic taught on the day of absence will be given which
has to be submitted within a week from the date of absence. No extensions will be
given on this. The attendance for that day of absence will be marked blank, so that
the student is not accounted for absence. These assignments are limited to a
maximum of 5 throughout the entire semester.
Homework/ Home There are situations where a student may have to work in home, especially before a
Assignment/ Activity flipped classroom. Although these works are not graded with marks. However, a
Assignment student is expected to participate and perform these assignments with full zeal since
(Formative) the activity/ flipped classroom participation by a student will be assessed and marks
will be awarded.

E. SYLLABUS
F. Processor Datapath and Control: Logic Design Conventions, Building a Datapath,
Microprogramming, Microprogram Control Unit, Hardware Control Unit. Pipelining: Overview,
Pipelined Datapath, Pipelined Control, and Forwarding, Pipeline Performance, Data Hazards and
Stalls, Branch Hazards. Memory Hierarchy: Basics of Memory, Basics of Caches, Measuring
and Improving Cache Performance, Cache hit/miss, Virtual Memory, Address Translation.
Storage and Other Peripherals: Disk Storage and Dependability, Networks, Connecting I/O
Devices to Processor and Memory, Interfacing I/O Devices to the Memory, Processor, and
Operating System, I/O Performance Measures. Multicores, Multiprocessors and Clusters:
Shared Memory Multiprocessors, Clusters and other Message-Passing Multiprocessors, Hardware
Multithreading, SISD, MIMD, SIMD, SPMD and Vector Processors
G. TEXTBOOKS
T1. D. Carl, Hamacher Computer Organization, McGraw Hill Education (5e), 2011.

T2. M. W. Stallings, Computer Organization and Architecture –Designing for Performance, (9e), Pearson, 2013.

H. REFERENCE BOOKS
R1. D. A. Patterson, J. L. Hennessy, Computer Organization and Design: The Hardware and Software Interface,
(5e), Elsevier, 2014.

R2. J. L. Hennessy, D. A. Patterson, Computer Architecture: A Quantitative Approach, (6e), Morgan Kaufmann
Publishers, 2019.

R3. John P. Hayes, “Computer Architecture and Organization”, TMH, 3rd Edition, 1998.
 H. Lecture Plan:

L. No. Unit Topics Session Outcome Mode of Corresponding

Delivery CO
1 Memory Memory: Some basic Describe about byte addressable Lecture CS2203.3
concepts memory, MAR and MDR
2 Speed, Size, and Cost Describe Memory Hierarchy Lecture CS2203.3
3 Direct Mapping Make use of direct mapping Lecture CS2203.3
techniques
4 Associative Mapping Make use of associative Lecture CS2203.3
mapping techniques
5 Set-Associative Make use of set-associative Tutorial CS2203.3
Mapping mapping techniques
6 Performance Make use of various cache Lecture CS2203.3
Considerations mapping techniques for
improving performance
7 Virtual Memory Describe the concept of virtual Lecture CS2203.3
memory
8 Tutorial Make use of various cache Tutorial CS2203.3
mapping techniques for
improving performance
9 Processor Single Bus Explain Single Bus Organization Lecture CS2203.1
10 Datapath Organization of the
Register transfer, of the sequences
Build processor datapath
of control Lecture CS2203.1
11 and Performing an from
Fetching a Word signals
Build sequences ofinstruction
for a given control Lecture CS2203.1
Control Memory, Storing
12 Execution of a a signalssequences
Build for a givenofinstruction
control Lecture CS2203.1
13 complete instruction,
Multiple bus signals for a given
Explain multiple Bus instruction Lecture CS2203.1
14 organization
Tutorial Organization
Build sequences of the processor
of control Tutorial CS2203.1
15 Hardwired control signals
Model thefor hardwired
a given instruction
control Lecture CS2203.1
16 Microprogrammed unit design
Model the microprogrammed Lecture CS2203.1
17 Control
Microinstructions control unit design Vertical and
Model Horizontal, Lecture CS2203.1
18 Tutorial Hybrid microprogrammed
Model Horizontal, Vertical and Tutorial CS2203.1
19 Pipelining Basic concepts of Hybrid microprogrammed
Identify the speed-up with Lecture CS2203.2
pipelining instruction pipeline and effect of
various pipeline hazards.
20 Role of cache memory Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
21 Pipeline performance Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
22 Data hazard (Operand Identify the speed-up with Lecture CS2203.2
forwarding) instruction pipeline and effect of
various pipeline hazards.
23 Tutorial Identify the speed-up with Tutorial CS2203.2
instruction pipeline and effect of
various pipeline hazards.
24 Hazard handling Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
25 Side effects Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
26 Instruction Hazard Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
27 Instruction Hazards, Identify the speed-up with Lecture CS2203.2
 Types of Hazards instruction pipeline and effect of
various pipeline hazards.
28 Instruction Hazards, Identify the speed-up with Lecture CS2203.2
Solutions instruction pipeline and effect of
various pipeline hazards.
29 Tutorial Identify the speed-up with Tutorial CS2203.2
instruction pipeline and effect of
various pipeline hazards.
30 Influence on instruction Identify the speed-up with Lecture CS2203.2
sets instruction pipeline and effect of
various pipeline hazards.
31 Datapath and Control Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
32 Tutorial Identify the speed-up with Lecture CS2203.2
instruction pipeline and effect of
various pipeline hazards.
33 I/O INPUT-OUTPUT Describe I/O module schematic Lecture CS2203.4
System ORGANIZATION, I/O
Module Schematic
34 Memory-Mapped and Compare Memory-Mapped and Lecture CS2203.4
I/O Mapped Device I/O Mapped Device Interface
Interface
35 Data Transfer Compare various I/O data Lecture CS2203.4
Techniques transfer techniques.
36 Programmed I/O Compare various I/O data Lecture CS2203.4
transfer techniques.
37 Interrupt driven data Compare various I/O data Lecture CS2203.4
transfer transfer techniques.
38 Interrupt Handling Compare various I/O data Lecture CS2203.4
transfer techniques.
39 Direct memory access Compare various I/O data Lecture CS2203.4
transfer techniques.
40 Tutorial Compare various I/O data Tutorial CS2203.4
transfer techniques.
41 Multicore Superscaler Operation Describe superscaler operation Lecture CS2203.5
42 and GPU Vector Processor Describe Vector Processor Lecture CS2203.5
Architecture
43 Shared Memory Need of Multi-core architecture Lecture CS2203.5
Multiprocessors
44 Clusters Describe distributed architecture Lecture CS2203.5
45 Multicore Processors Need and designing of Multi- Lecture CS2203.5
core Processors
46 GPU Describe the advantages of GPU Lecture CS2203.5
 I. Course Articulation Matrix: (Ma/pping of COs with POs)

CORRELATION WITH PROGRAM OUTCOMES CORRELATION WITH

CO PROGRAM SPECIFIC
STATEMENT OUTCOMES
PO PO PO PO PO PO PO PO PO PO PO PO PSO 1 PSO 2 PSO 3
1 2 3 4 5 6 7 8 9 10 11 12
[2203.1] Build sequences of control signals for a given 3 2 1 1 1 1 2 1
instruction and model the control unit design.
[2203.2] Identify the speed-up with instruction pipeline and 3 2 1 1 1 1 1 2 1 1
effect of various pipeline hazards.
[2203.3] Make use of various cache mapping techniques for 3 2 1 1 1 1 1 2 1 1
improving performance.
[2203.4] Compare various I/O data transfer techniques. 3 2 1 1 1 1 1 1
[2203.5] Explain the various methodologies for parallel 3 2 1 1 1 1 1 1 1 1
processing.
1- Low Correlation; 2- Moderate Correlation; 3- Substantial Correlation