ACADEMY OF TECHNOLOGY

AEDCONAGAR, HOOGLY – 712121

Subject Name: Microprocessor & Microcontroller Discipline: ECE

Subject Code: EC 403 Semester: 4TH

Course Outcomes (COs) defined by Subject-teachers:

At the end of the course, a student will be able to:
CO.01: Define and characterize the internal architecture and operation of various Microprocessors
(8085/ 8086) and Microcontrollers (8051/ ARM) and RISC & CISC processors.

CO.02: Compare and choose appropriate Microprocessor (8085/ 8086) and Microcontroller
(8051/ARM) to meet specified performance requirements for a system design.

CO.03: Apply knowledge for interfacing memory devices and DMA with processor as well as
controller.

CO.04: Implement microprocessor/microcontroller based complex system with required peripheral

devices such as, 8255 PPI, 8254, serial I/O, parallel I/O, A/D and D/A converters, timer and
arithmetic coprocessor.

CO.05: Execute and analyze the performance of the microprocessor/microcontroller-based system

using assembly language programming.

CO.06: Develop concepts on virtual memory and cache memory by identifying architecture of
advanced Coprocessors (286, 486, Pentium).

Module I: Introduction to Microprocessor 8085 and 8086

Bloom’s Taxonomy Level: I

Sl Questions Marks CO
No. No.
1. A stack is 1 1

a. an 8 bit register in the microprocessor.

b. a 16 bit register in the microprocessor.
c. a set of memory locations in R/WM reserved for storing
information temporarily during the execution of a program.
d. a 16-bit memory address stored in the PC.
2. A stack pointer is 1 1

a. a 16-bit register in the microprocessor that indicates the

beginning of the stack memory.
b. a register that decodes and executes 16-bit arithmetic
expressions.
c. the first memory location where a subroutine address is
stored.
d. a register in which flag bits are stored.
3. What is the memory word addressing capability of 8085 μP. 1 1

a. 32 K b.64 K c.255 K d.512 K.

4. The ASCII is an input output code 1 1

a. It is a two bit code

b. It is a four bit code
c. It is a seven bit code
d. It is an eight bit code
5. What is clock frequency for 8085? – 1 1
i) 3 MHz ii) 2 MHz iii) 2.2 MHz iv) 2.5 MHz
6. PC contain – 1 1
i) address of present instruction ii) address of previous instruction

iii) address of next instruction iv) none of these.

7. What is the length of temporary register of 8085 μP 1 1

a. 6 bits b. 8 bits
c.12 bits d.16 bits.

8. In a sign magnitude representation, the leading bit 1 1

a. Is a part of the number itself

b. Is unity for positive
c. Is always unity
d. Stands for the sign
9. In 8085 which is the 16 bit register? – 1 1
i) Stack pointer ii) Accumulator register
iii) Instruction registeriv) Temporary register
10. Which interrupt has the highest priority? – 1 1
i) TRAP ii) RST7.5
iii) RST6.5 iv) RST5.5
11. What is the restart address for TRAP 1 1
i) 0024H ii) 0034H iii) 003CH
iv) 0038H
12. Which of the following instruction in 8085 is used for exchange stack top 1 1
with HL pair?
i) SPHL ii) XTHL
iii) PCHL iv) none of these
13. If a DMA request is sent to the microprocessor with a high signal to the 1 1,3
HOLD pin , the microprocessor acknowledges the request
i) after completing the present cycle
ii) immediately after receiving the signal
iii) after completing the program
iv) none of these
14. Clock signal of 8086 is with duty cycle 1 1
i)20% ii) 33% iii)50% iv) 66%
15. 8086 exchanges data byte with odd memory bank when 1 1,3
a) BHE¯=0 and A0 = 0 b) BHE¯=0 and A0 = 1
c) BHE¯=1 and A0 = 0 d) BHE¯=1 and A0 = 1
 16. Direction flag is used for 1 1
a) arithmetic operation b)transfer operation
c)string operation d)logical operation
17. The instruction NEG is the 1 1
a) data transfer instruction b) branch instruction
c)arithmetic instruction d) logical instruction
18. If ready pin is grounded, it will introduce -------------states into the bus 1 1
cycle of 8086/8088p.
a) wait b) idle
c) wait and remain idle d) all of these
19. In the interrupt instructions of the type INT n, the maximum value of n is 1 1
a) 31 b)127 c)63 d)255
20. Memory space required to store one interrupt in 8086 is 1 1
a) 1byte b) 2byte c) 4 byte d) 8 byte
21. IP and SP in 8086 architecture are within --- 1 1
a) BIU only b) EU only
c) BIU and EU respectively d) None
22. Tristate buffers are often used to make sure the unselected devices have 1 1
their data outputs placed in
i)High impedance state ii)Logic 1 state
iii)Logic 0 state iv)Input state
23. TEST input in 8086 p is used by the instruction 1 1
a) WAIT b) LOCK c) Both of these d) None
24. What is the vector location for NMI? 1 1
a) 00000H b) 00008H c) 00010H d) 00014H
25. Define instruction cycle, machine cycle& T states. 6 1

26. Describe the function of the following pins in 8085 MPU – READY, 5 1,3
HOLD, INTR, SOD, TRAP

27. What do you mean by addressing mode? 2 1

28. Discuss the role of DT/R and DEN signals of 8086. 4 1

Module I: Introduction to Microprocessor 8085 and 8086

Bloom’s Taxonomy Level: II

Sl Questions Marks CO
No. No.
1. How does the microprocessor know what operation to perform first 1 1

a. Read/Write memory
b. Opcode fetch
c. Read/Write I/O
d. none.
2. How many I/O ports can be accessed by direct method of 8085 μP 1 1
 a. 8 b.256 c.32 K d.64 K.
3. What is the addressing mode used in instruction MOV M, C? 1 1,2,5

a. Direct b. Indirect
c. Induced d. Immediate
4. When a subroutine is called, the address of the instruction following the 1 1
Call instruction is stored in/on the
a. stack pointer c.accumulator
b. program counter d.stack.
5. When the RET instruction at the end of a subroutine is executed, 1 1
a. the information where the stack is initialized is transferred to the
stack pointer.
b. the memory address of the RET instruction is transferred to the PC.
c. two data bytes stored in the top two locations of the stack are
transferred to the PC.
d. two data bytes stored in the top two locations of the stack are
transferred to the SP.
6. Whenever the POP H instruction is executed, 1 1
a. data bytes in the HL pair are stored on the stack.
b. two data bytes at the top of the stack are transferred to the HL reg.
Pair.
c. two data bytes at the top of the stack are transferred to the PC.
d. two data bytes from the HL register that were previously stored on
the stack are transferred back to the HL registers.
7. The addressing modes used in PUSH B is 1 1
i)direct ii) register
iii) immediate iv) register indirect
8. Which instruction is equivalent to 1 byte unconditional jump instruction? 1 1
i) SPHL ii) XTHL
iii) PCHL iv) none of these
9. Recursive subroutine is 1 1
i)multiple calling subroutine ii) multiple ending subroutine
iii)nested subroutine iv)re-entrant subroutine
10. Apart from certain arithmetic operations, RAR/RAL is useful for 1 1,3
i)DMA controlling ii) Serial data transfer
iii)Decimal adjust operations iv) Prioritizing interrupts

11. For the 8086 instruction MOV AX, [BP+SI], the default segment used is 1 1,2,5
i)CS ii) DS iii) SS iv) ES
12. The instruction ‘MOV AX, 04 [BP] [DI]’ is a best example for which 1 1,2,5
one of the following addressing modes?
a) register addressing b) immediate addressing,
c) based indexed memory addressing d) none of these
13. What are the conditions that BIU to suspend fetching instructions? 1 1
a) Current instruction requires access to memory or I/O port
b) A transfer control (Jump or call) instruction occurs.
c)Instruction queue is full
d) All of these.
14. Which one of the following segments is used by the ‘CMPSB’ string 1 1,2,5
instruction for the destination?
 a) CS b) DS c) ES d) SS
15. Briefly explain about different flags available in 8085 microprocessor. 5 1

16. Discuss the functions of the following instructions—RAR, LHLD 5 1

C020H, DAD H, CALL D050H, DCX B.

17. Discuss the functions performed by SIM instruction. Also draw the bit 5 1
pattern.

18. Draw pin diagram of 8085 µp. Explain the function of the pins of Intel 6 1
8085A microprocessor.

19. Discuss with diagram how various control signals are generated in 8085 4 1
microprocessor.

20. Sketch the internal functional block diagram of architecture of the 8085 8 1
and discuss the function of all the blocks.

21. Write down the steps of DMA operation. 4 1,3

22. What is the difference between level sensitive and edge sensitive 3 1
interrupts.

23. What is subroutine? What is the difference between CALL & JMP 5 1
instructions?

24. How does ALE signal demultiplex the AD0-AD7 bus? Explain with diagram. 5 1,2,5

25. Discuss the operations performed by the PUSH& POP instructions. 4 1

26. What do you understand by conditional& unconditional CALL 5 1

instruction? Discuss briefly about the different conditional call
instructions.

27. What is function of RIM and SIM? 5 1

28. Briefly explain the function of RST instruction. Also write down the 5 1
restart addresses of different interrupts.

29. What are the different addressing modes supportedby 8085 5 1

microprocessor? Explain each of them with suitable examples.

30. Draw and discuss in brief about the architecture of 8086. 5 1

31. Discuss ODD and EVEN Bank Memory Organization of 8086. 5 1,2,5

32. Discuss Pipelined Architecture of 8086/88. 5 1,2,5

33. Name and explain the different flags of 8086 microprocessor. 5 1

 34. Draw & discuss a typical Minimum/Maximum mode 8086 computer system. 6 1

35. What do you mean by addressing mode? What are the different addressing 5 1
modes supported by 8086 microprocessor? Explain each of them with suitable
examples.

36. What is the function of TEST, LOCK and MN/MX pin in 8086? 5 1

37. What is the purpose of the Queue?How many words do the queue store in the 5 1
8086?

38. Discuss the functions performed by BX, BP, and CX in addition to the function 5 1
of general-purpose register? What are the functions of IP &SP?

39. What is the Off-set Address and Physical Address? How is Physical Address 5 1,2,5
computed in case of 8086?

40. Explain the concept of segmented memory.What is the purpose of memory 5 1,2,5
segmentation and its advantages?

41. What do you mean by interrupt I/O? Briefly explain about different interrupts 5 1
available in 8086 microprocessor.

42. What is the role of execution unit of 8086 microprocessor? Explain the working 4 1,2,5
of its each section.

43. Explain the differences between I/O mapped I/O and memory mapped I/O. 2+3 1,3
Discuss the differences between absolute decoding and partial decoding with
example.

Module I: Introduction to Microprocessor 8085 and 8086

Bloom’s Taxonomy Level: III

Sl Questions Marks CO
No. No.
1. Whenever the instruction LHLD is executed, number of T-States 1 1,2,5
required are
a. 10 b.13 c.16 d.12.
2. If the crystal with 8085 is 2 MHz, the time required to execute an 1 1,2,5
instruction of 20 T states is?
i) 20µs ii) 10µs iii) 40µsiv) 5µs
3. What is the width of data bus and address bus for 4096 X 8 memory? 1 1,3
i)16 and 12 ii) 8 and 12
iii)12 and 32 iv) 32 and 16
4. In a partial decoding scheme using 8 bit addressing, two address lines 1 1,3
A1&A0 are not connected to the decoding NAND gate. Which addresses
are made redundant?
 i)00H,01H,03H,04H ii)00,02,13,14
iii)13,05,03,04 iv)00,01,02,03
5. What is the vector location for INT3 0f 8086? 1 1
a) 0006H b) 0008H c) 0012H d) 0014H
6. An 8255 is interfaced with 8086 the port A address is 070H. What will 1 1,4
be the address of port C?
a) 074H b) 0744H c) 0745H d) 0746H
7. What physical address is represented by 4370: 561EH? 1 1,2,5
a) 4370EH b) 0561EH c) 48D1E d) 5A550H
8. Specify the register contents and the flag status (S, Z, CY) after the instruction 4 1,2,5
ORA A is executed.
MVI A, A9H
MVI B, 57H
ADD B
ORA A
RST 1
9. Explain how many times the following loop will be executed. 5 1,2,5
LXI B, 0007H
LOOP: DCX B
MOV A, B
ORA C
JNZ LOOP
HLT
10. The following sequences of instructions are executed by 8085μP 5 1,2,5
C000 LXI SP, D050
POP H
XRA A
MOV A, H
ADD L
MOV H, A
PUSH H
PUSH PSW
HLT
What are the contents of SP, PC registers, Accumulator, HL pair?
11. Calculate the COUNT for the following program to obtain 100 microsecond 3 1,2,5
loop delay, and express the value in HEX. Use the clock of your system
T state
MVI B, COUNT
LOOP: NOP 4
NOP 4
DCR B 4
JNZ LOOP 10/7

12. Read the following program and answer the questions. 5 1,2,5
Line No. Mnemonics

1 LXI SP,0400H
2 LXI B,2055H
 3 LXI H,22FFH
4 LXI D,2090H
5 PUSH H
6 PUSH B
7 MOV A, L
. .
. .
. .

20 POP H
What is stored in SP after the execution of line 1?
What is memory location of stack where the first data byte will be stored?
What is stored in memory location 03FE H when line 5 is executed?
After the execution of line 6, what is address of the SP register, and what is
stored in stack memory location 03FD H?
Specify the contents of register pair HL, after the execution of line 20?
13. Write an ALP for 8086 for the addition of a series of 8 bit numbers. The series 5 1
contains 100 numbers.

14. Determine the memory address accessed by each of the following instructions 5 1,2,5
in real

mode operation, if DS=1000H, SS= 2000H, BP= 1000H, BX= 0200H &
DI=0100H.

i)MOV AL,[BP+DI]

ii)MOV CX,[DI]

iii)MOV AL,[1234H]

iv)MOV DL,[BX+1000H]

15. What is the function of Type-2 interrupt in 8086 microprocessor? If an 8086 4 1,2,5
Type-2 interrupt service routine starts from 5000H:0100H memory, how will
this address be stored in interrupt vector table?

16. Write 8086 instruction to perform the following operation: 6 1,2,5

a) Inversion of lower 4 significant bits of AL keeping other bits unaffected.

b) Copy the content of BX to a memory location in the DS with offset 0234H.

c) Increment the content of CX by 1

d)Multiply AX with 16-bit data 2467H

e) Rotate left the content of AL by two bits.

17. From memory location 00490H successively 0AH, 9CH, B2H, 78H are stored 4 1,2,5
respectively. What does AX contain after the execution of each following
instructions. Assume that SI contains 00490H and BP contains 0002H.
MOV AX, (SI)
 MOV AX, (SI+1)
MOV AX, (SI) (BP)
18. Write an assembly language program to add 10 bytes of data in the DS starting 5 1,2,5
from 2000H:2000H and store the result in 3000H:2000H.

19. The memory address of the last location of an 8K byte memory chip is FFFFH 5 1,3
then finds the starting address. How many address lines are used to identify an
I/O port in the I/O mapped I/O and in the memory mapped I/O methods.

20. If the memory chip size is 2048 * 8 bits, how many chips are required to make 2 1,3
up 16K byte memory?
21. If the memory address range of 6116 R/W memory chip(2048X8) is 8800H - 6 1,3
8FFFH, draw the interfacing scheme of the same using 74LS138 3to 8 decoder
with 8085 MPU. Assume output line of the decoder is identified as MSEL.
Module: II Peripherals Interfacing
Bloom’s Taxonomy Level: I

Sl No. Questions Marks CO

No.

1. No. of ports in 8255A are- 1 4,5

i) 2 ii) 3 iii) 4 iv) 5
2. No. of modes in 8255A are- 1 4,5
i) 2 ii) 3 iii) 4 iv)5
3. Strobe signal of 8255A is 0 when- 1 4,5
i) external device write data into 8255A ii) external device read data from 8255A iii)
8085 m/p write data into 8255A iv) none of these

4. Port B of 8255A can be used either in – 1 4,5

i) mode 0 or 1 ii) mode 2 or 1
iii) mode 0 or 2 iv) mode 0 or BSR mode
5. For 8255 PPI, the bidirectional mode of operation is supported in Mode 1 4,5
i) 1 ii) 2 iii) 0 iv)either 1 or 2
6. 8253 has- 1 4,5
i) 2 counters ii) 3 counters iii)1 counter iv)4 counters
7. Mode 4 of 8253 is- 1 4,5
i) Square wave generator ii) Rate generator
iii) Software trigger strobe iv) Hardware triggers strobe.
8. Mode 3 of 8253 is- 1 4,5
i) Square wave generator ii) Rate generator
iii) Software trigger strobe iv) Hardware triggers strobe.
9. Mode 5 of 8253 is- 1 4,5
i) Square wave generator ii) Rate generator
iii) Software trigger strobe iv) Hardware triggers strobe.
10. Mode 0 of 8253 is- 1 4,5
i) Square wave generator ii) Terminal count
iii) Software trigger strobe. iv) Hardware triggers strobe.
11. Data terminal equipment and data communication equipment are both associated with 1 4
a) asynchronous serial communication b) asynchronous Parallel communication
c) synchronous Parallel communication d) synchronous serial communication
Module: II Peripherals Interfacing
Bloom’s Taxonomy Level: II

Sl No. Questions Marks CO

No.

1. An 8 bit A/D converter has a resolution of 1 4

i)1/28 -1 ii)1/28 iii)1/212-1 iv) 1/216
2. How many possible outputs values are there in case of 10-bit D/A converter 1 4
i) 1000 ii) 1023 iii) 1024 iv) 1224
3. In mode 2 of IC 8253, if N is loaded as the count value, then after (N-1) cycles, the 2 4
output becomes low for
i) 1 clock cycle ii) 2 clock cycles iii) 3 clock cycles iv) 4 clock cycles

4. Specify the conditions to start the timer 8254 5 4,5

5. Describe the different modes of operation of 8254 timer 5 4

6. Draw the block diagram of 8254 timer and describe its different section. 5 4

7. Describe the operating modes of 8255A PPI. 5 4

8. Specify the bit of a control word for the 8255A, which differentiates between the I/O 5 4,5
mode and BSR mode.

9. What is USART? Why is USART used?what are the functions of command word and 5 4,5
status word in 8251?Differentiate between synchronous and asynchronous serial data
transfer.

10. Explain DMA operation. 5 4

11. Describe the block diagram of 8251. 5 4

Module: II Peripherals Interfacing
Bloom’s Taxonomy Level: III

Sl No. Questions Marks CO

No.

1. In BSR mode of 8255 if the control word is initialized with 0FH, then which bit of port 1 4,5
C is set or reset?
a)Only PC0 is set,others are reset b) PC0 is reset
c)Only PC7 is set,others are reset d)All are set
2. An 8255 is interfaced with 8086 the port A address is 070H. What will be the address 2 4
of port C?
a) 074H b) 0744H c) 0745H d) 0746H
3. Set up the 8254A as a square-wave generator with 1ms period, if the i/p frequency is 1 5 4,5
MHz.

4. Write initialization instruction for the 8255A to set up- 5 4,5

1. Port A as an o/p port in mode 0.
2. Port Bas an o/p port in mode 1 for interrupt I/O.
3. Port C (upper) as an O/P in mode 0.

5. In mode 1 operation of 8255 PPI, what are the control signals when ports A&B act as 5 4,5
output ports? Discuss the control signals.

6. List the necessary conditions to generate INTR when port A of the 8255A is set up as 5 4,5
an o/p port in Mode 1.

7. An I/O peripheral device shown in figure2 below is to be interfaced to an 8086 5 1,4

microprocessor. To select the I/O device in the I/O address range D4 H – D7 H,
its chip-select (CS) should be connected to the which output of the decoder
shown in figure 1 below:

Figure 1
 Discuss your answer.

8. An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped 5 1,4

I/O as shown in the figure. The address lines A0 and A1 of the 8085 are used
by the 8255 chip to decode internally its three ports and the Control register.
The address lines A3 to A7 as well as the IO/Mʹ signal are used for address
decoding. Determine the range of addresses for which the 8255 chip would get
selected.

9. With the help of a block diagram explain a microprocessor-based system point out the 5 2,4
role of microprocessor and other peripheral blocks.
Module: III Coprocessor and microcontroller
Bloom’s Taxonomy Level: I

Sl No. Questions Marks CO No.

1. No. Of SFR (special function register) in 8051 microcontroller is 1 1,2

a) 20 b) 25 c) 21 d) 27
2. How many bottom locations of internal memory of 8051 contain the register banks? 1 1,2
a) 23 b) 32 c)25 d)33
3. Which of the following pins is used for external access enable pin? 1 1,2
a)PSEN b)EA/VPP c)XTAL1 d)none of
these
4. The no of interrupts presents in 8051 microcontroller is 1 1,2
i)2 ii)5 iii) 4 iv) none of those
5. Number of bit addressable location for RAM in 8051 microcontroller 1 1,2
a) 256 b) 128 c) 64 d) 512
6. The process of making the physical memory free by storing the portion of program and 1 6
partial results in the secondary storage called
i)mapping iii) swapping out
ii) swapping in iv) pipelining
7. The memory that is considered as a large logical memory space, that is not available 1 6
physically is
i) logical memory iii) auxiliary memory
ii) imaginary memory iv) virtual memory
8. Memory management deals with 1 6
i) data protection iii) unauthorized access prevention
ii) segmented memory iv) all of the mentioned
9. The memory management and protection mechanisms are disabled when the 80286 is 1 6
operated in
i) normal mode iii) real address mode
ii) virtual address mode iv) all of the mentioned
10. The memory management and protection mechanisms are enabled with advanced 1 6
instruction set when 80286 is operated in
i) normal mode iii) real address mode
ii) protected virtual address mode iv) all of the mentioned
11. In real addressing mode, the 80286 operates at a speed 1 6
i) faster than that of 8086 iii) half of that of 8086
ii) slower than that of 8086 iv) same as that of 8086

12. The 80286 in real addressing mode performs 1 6

i) initialization of IP iii) enables interrupts
ii) sets up descriptor table iv) all of the mentioned
13. The ability of 80286 to address the virtual memory per task is 1 6
i) 1MB ii) 1GB iii) 1TB iv) none of the mentioned
14. A descriptor contains information of 1 6
i) program segment iii) page
ii) regarding segment and its access rights iv) all of the mentioned
15. A segment with low privilege level is not allowed to access another segment of 1 6
 i) low privilege level iii) high privilege level
ii) low and high privilege level iv) none of the mentioned
16. The memory that maintains the most frequently required data for execution, in a high- 1 6
speed memory is called
i) virtual memory iii) physical memory
ii) cache memory iv) main memory
17. The management of the virtual memory of the system and adequate protection to data or 1 6
codes in the physical memory is provided by
i) segmentation unit iii) paging unit
ii) attribute PLA iv) all of the mentioned

18. The datatype that the 80486 does not support is 1 6

i) Signed and unsigned iii) ASCII
ii) Floating point iv) None
19. The on-chip cache of the 80486 is used for storing 1 6
i) addresses of data iii) opcodes and data
ii) data and their addresses iv) opcodes and their addresses
20. Which is the first member of the family of advanced microprocessors designed by Intel 1 6
with memory management and protection unit
i)8086 ii) 80186 iii) 80286 iv) 80386
21. Which of the following is a cache of Pentium? 1 6
i) data cache iii) data cache and instruction cache
ii) instruction cache iv) none of the mentioned
22. The main new features included in the 80486 are 1 6
i)built-in 8Kbyte code/data cache ii) memory-management unit
iii)32 bit floating-point-unit iv) both (i) & b(iii)
23. Enlist the data types supported by 80486. 5 6

24. Draw and discuss the flag register of 80486. 5 6

25. Briefly discuss the functions of TMOD, TCON, PCON, SBUF, SCON registers. 5 1,2

26. Enlist the salient features of 8051 microcontroller. 2 1,2

27. Enlist the various flags in PSW register & discuss them. 5 1,2
Module: III Coprocessor and microcontroller
Bloom’s Taxonomy Level: II

Sl No. Questions Marks CO

No.

1.1. How can port 0 (P0) of 8051 microcontroller be used as input output port? 2 1,2
i) MOV A, #0FFH & Then MOV P0, A iii) MOV A, #00H & Then MOV P0, A
ii) MOV A, @0FFH &Then MOV A,P0 iv) MOV A, @00H &Then MOVA,P0
2. The 80286 CPU operates in 1 6
i)Real address mode ii)all of these
iii) Protected virtual address mode iv) none of these
3. The salient feature of Pentium is 1 6
i) superscalar architectureii) super pipelined architecture
iii) superscalar and super pipelined architectureiv) none of the mentioned
4. The number of stages of the integer pipeline, U, of Pentium is 1 6
i) 2 ii) 4 iii) 3 iv) 6
5. The speed of integer arithmetic of Pentium is increased to a large extent by 1 6
i) on-chip floating point unit iii) superscalar architecture
ii) 4-stage pipelines iv) all of the mentioned
6. In the real mode, the memory that is reserved for system initialization is 1 6
i) from 004FFH to 0FFFFH iii) from 004FFH to 05FFFH
ii) from FFFF0H to FFFFFH iv) from FFF00H to FFFFFH
7. Draw and discuss the internal block diagram of 80286. 5 6

8. Explain the flag register of 80286. 5 6

9. Describe the different sources of interrupt in 8051. 5 1,2

10. What is the use of register banks in 8051? How bank switching be done? 5 1,2

11. What is meant by saying that a register is bit addressable? 5 1,2

12. Is the 8051 stack a LIFO or FIFO stack? Explain with example. What is the value of SP 2 1,2
on reset?

13. Draw the internal data memory organization of 8051 family of micro-controllers 5 1,2,4
indicating the areas of registers banks, bit addressable RAM, general purpose RAM &
code memory.

14. With suitable illustration, discuss various addressing modes supported by 8051. 2 1,2,5

15. Explain the cache memory management unit of 80486. 2 6

16. Briefly discuss on-chip data memory organization of 8051 microcontroller. 5 1,2

17. Draw and discuss the internal architecture of 8051. 3 1,2

18. Discuss the following signals of 8051: 5 1,2

(i)ALE/PROG, (ii) EA/VP, (iii) PSEN, (iv) T0 and T1

19. What is the difference between LJMP, SJMP, AJMP instructions in 8051? 5 1,2,5

20. Briefly discuss PUSH & POP instructions of 8051 5 1,2,5

21. What is the function of PSW in 8051 microcontroller? 5 1,2

22. Explain the concept of virtual memory. 5 6

23. What do you mean by swapping in and swapping out? 5 6

24. Discuss the salient features of 80286 in real address mode. 5 6

25. Explain the physical address formation in real address mode. 5 6

26. Discuss the salient features of 80286 in virtual address mode. 5 6

27. Briefly explain task switch operation of 80286. 5 6

28. Enlist the features of 80486. 5 6

29. Distinguish between microprocessor & microcontroller. 5 1,6

Module: III Coprocessor and microcontroller
Bloom’s Taxonomy Level: III

Sl No. Questions Marks CO

No.

1. What will be the contents of registers A & B and overflow flag after execution of the 2 1,2
following codes by the 8051:
MOV A, #0FEH
MOV B, #02H
MUL AB
i)A=FCH, B=01H, OV=1 iii)A=FCH, B=00H, OV=1
ii)A=FFH, B=01H, OV=1 iv)A=FCH, B=01H, OV=0
2. Determine the operation performed by the following codes in 8051: 2 1,2
MOV A, 90H
ORL A, 0A0H
i)OR the contents of port 1 and port 2 iii)OR the contents of A and port 2
ii)OR the contents of port 1 and A iv)OR the contents of A and immediate data
3. Write a program to obtain logical AND of (A) and any (SFR) and with a byte of data 5 1,2,5
indicated by the string

4. What is the addressing mode that is suitable for look up table access in 8051? 5 1,2,5

5. State the addressing mode used in each of the following instructions: 5 1,2,5

i) MOV A, #0ADH ii) MOVX @DPTR, A iii) ORL 34H, #34H iv) DEC R2

6. What would be the content of accumulator after executing the following sequence? 5 1,2,5

MOV 35H, #45H

MOV 35H, #47H
MOV A,35H.

7. Using 8051 ALP find square root of E1H. 5 1,2,5

8. Explain the physical address formation in protected virtual address mode. 5 6

9. Describe the use of TEST and DEBUG facility of 80486 5 6

10. What do you mean by cache memory? How does it speed up the program execution? 5 6
Module: IV Advance Microcontroller
Bloom’s Taxonomy Level: I

Sl Questions Marks CO
No. No.

1. The instructions set of RISC processor is: 1 1

i)Simple and lesser in number
ii)Complex and lesser in number
iii)Simple and larger in number
iv)Complex and larger in number
2. Which of the following is true about CISC processors? 1 1
i)Fixed length instructions
ii)The number of general-purpose registers is limited
iii)Instructions are micro in nature
iv)Orthogonal
3. What is nature of the instruction size in RISC processors? 1 1
Fixed b) Variable c) Both a and b d). Depends on applications.
4. ARM Processor is a.......... bit core. 1 1
a) 8 b) 16 c) 32 d) 64.
5. Maximum supported memory size by ARM is 1 1
a) 64KB b) 1 MB c) 32 MB d) 4GB.
6. R14 register of ARM processor acts as 1 1
a)stack pointer b)program counter
c)link register d)control register.
7. ARM bus architecture uses Advanced System Bus(ASB) for connecting …... system 1 1
modules
a)high-performance b)low-performance c)low powered d)high speed.
Module: IV Advance Microcontroller
Bloom’s Taxonomy Level: II

Sl Questions Marks CO
No. No.

1. Compare Harvard and Princeton (Von-Neumann) memory organization. 5 1

2. Compare RISC and CISC architectures 5 1

3. Name two aspects in the design of ARM which has made it a processor with ‘low- 5 1
power dissipation’.
4. List out the important features that make ARM ideal for embedded applications. 5 1

5. Explain the function of the load and store instructions of ARM with examples. 5 1
Module: IV Advance Microcontroller
Bloom’s Taxonomy Level: III

Sl Questions Marks CO
No. No.

1. Now-a-days high performance embedded systems use either an RISC processor or a 5 1,2
processor with an RISC core with a code-optimized CISC instruction set. Why?
Explain.

2. Briefly discuss ARM interfacing with LCD controller. 5 1,4

3. Design the interfacing circuit to display different patterns of LEDs using ARM. 5 1,4