The 14th International Conference on
Computer Science & Education (ICCSE 2019)
August 19-21, 2019. Toronto, Canada
Multi-Cycle CPU Design With FPGA for Teaching
of Computer Organization Principle
Xing Liu
Computer Science and Technology School Computer Science and Technology School Computer Science and Technology
Wuhan University of Technology Wuhan University of Technology
Wuhan, China Wuhan, China
liu.xing@whut.edu.cn fulinghao@whut.edu.cn
Xiongmin Lin * Mingxi Liao
Electrical and Computer Engineering Computer Science and Technology School Computer Science and Technology School
University of Victoria Wuhan University of Technology
Victoria, Canada Wuhan, China
xiongminlin@uvic.ca cs lmx@whut.edu.cn
Abstract—CPU design with programmable FPGA has become
a significant solution for the experiment teaching of computer
organization principle. In this paper, the design concept, im-
plementation technique and verification method of a multi-
cycle MIPS CPU are presented. To decrease the CPU design
complexity, the hierarchical division approach which divides the
CPU into a serial of easy-to-implement modules is proposed. To
help the students master the intricate FPGA development process
in an easy-to-understand way, the easy-to-hard progressive imple-
mentation technique is investigated. To verify the functionality of
each CPU module, the variable-control approach which verifies
the CPU modules progressively by comparing with the standard
ones is explored. The experiment cases have been carried out
for six years, and the course survey results showed that the
new experiment design with the new implementation approaches
had improved the teaching quality of the computer organization
experiment significantly.
Index Terms—Computer organization, experiment, CPU,
FPGA.
I. I NTRODUCTION
Computer organization principle is accepted as one of the
key hardware courses in the computer science curricula [1],
[2]. To improve the teaching quality of computer organization,
a decent experimental design is significant as it can deepen
the students’ understanding to the theoretical knowledge and
strengthen their ability in applying what they have learned.
Traditional computer organization experiments are con-
ducted on the integrated experiment platform which has so-
lidified all the chip elements such as controller, arithmetic
logic unit (ALU), memory and I/O devices. The students only
need to configure the circuit manually by connecting the chips
with wires, and then verify the functionality of the circuits
by uploading a program and controlling the I/O devices
such as switches and buttons. This experimental scheme is
conductive to improve the students’ hands-on skills. Yet, it
has several limitations: On the one hand, the chips on the
*Corresponding author: Mingxi Liao. Email: cs lmx@whut.edu.cn
978-1-7281-1846-8/19/$31.00 ©2019 IEEE
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Linghao Fu Wenbi Rao
Wuhan University of Technology
Wuhan, China
wbrao@whut.edu.cn
Bing Shi
Wuhan University of Technology
Wuhan, China
bingshi@whut.edu.cn
experiment platform are solidified and cannot be expanded or
reprogrammed. Therefore, the students have few opportunities
to redesign the experimental programs independently by their
own knowledge. In most situations, they can only follow
the instructions of the pre-designed experiment cases, and
observe the executing results. On the other hand, the hands-on
wire connection is tedious and difficult to debug, especially
when the physical damage occurs. As a result, not only is
the experiment teaching efficiency decreased, but also the
students’ experimental interests are reduced.
To address the above challenges, it is significant to imple-
ment an experiment program which has the following features:
(1) the hardware of the experiment platform can be extended
or reprogrammable flexibly, so that the students can have
enough free space to design the experiment from their own
viewpoints. (2) a user-friendly development tool needs to be
selected, so that the students can keep away from the tedious
hands-on connection operations and implement the complex
circuits more efficiently.
One solution to satisfy the above requirements is to require
the students to develop a MIPS CPU with the reprogrammable
FPGA. With the reconfigurability of FPGA, the students
can design their own experimental cases independently and
flexibly by their own knowledge. Moreover, they can design
the circuit system by drawing the schematic diagram with
the FPGA development tool, rather than build the circuit
system by the hands-on wire connection. Currently, the above
experiment design concept has been researched and realized
by many institutions. Taking the computer organization exper-
iment course as an example, Lee et al. [3] presented the work
of designing a five-stage pipelined 32-bit MIPS CPU which
supported 21 MIPS instructions on the Altera DE2 FPGA
board, for the purpose of teaching the computer architecture
more effectively. Wang et al. [4] proposed a method to design
the data path and controller of a multi-cycle MIPS CPU on the
Nexys-4 FPGA board, for the purpose of reducing the CPU
472

design and implementation difficulty. Qin et al. [5] investigated
a method on how to design both the static and dynamic
pipelined CPU on the Nexys-4 FPGA board by improving a
single-cycle CPU, while Wan et al. [6] explored a simulation
methodology which can help the students understand the MIPS
system more easily.
In this paper, we present the experiment teaching of com-
puter organization on how to design and implement a multi-
cycle MIPS CPU with FPGA platform. This paper is organized
as follows: In Section II, the lab environment is introduced. In
Section III, the design concept of a multi-cycle MIPS CPU is
presented. In Section IV, the CPU technical implementation
scheme is explained. In Section V, the CPU verification
mechanism is investigated. In Section VI, the application
development for the designed CPU is presented. In Section
VII, the course survey and evaluation work are introduced.
Finally in Section VIII, the conclusion to this paper is given.
II. L AB E NVIRONMENT
To serve the experimental teaching, the SWORD (Simple
While Organic aRc Design) board is developed and used as the
experimental platform for the computer organization teaching,
depicted in Figure 1. SWORD is equipped with Xilinx Kintex-
7 XC7K160T-1FFG676 FPGA, 512M bytes DDR3 memory,
32M bytes NOR FLASH and 6M bytes SRAM memory. It
has abundant peripheral interfaces such as the SPI, VGA,
HDMI, SFP+, MicroSD, RS232, SATA, Pmod and USB, as
well as a set of GPIO interfaces such as the seven-segment
LEDs, buttons and switches. SWORD can connect to the host
machine by JTAG interface, and can be developed by the
software such as the ISE design suite 14.7 or the Vivado design
suite.
In the following sections, we will present our computer
organization experiment work on how to design and implement
a multi-cycle MIPS CPU with the SWORD FPGA platform
and the ISE design suite.
RS232 USB-OTG/HID
VGA
MicroSD Ethernet
SATA
interface
NOR SPI
HDMI
PmodTM Arduino
Extension
FPGA SRAM
SFP+
interface
SDRAM
HDMI
SATA
interface Seven-Segment LEDs
Buttons
Switches
Fig. 1. The SWORD FPGA board for MIPS CPU design and implementation.
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III. CPU D ESIGN BY H IERARCHICAL D IVISION S CHEME
The objective of the experiment is to enable the students to
design and implement a multi-cycle MIPS CPU independently
based on the SWORD FPGA platform. Since the multi-cycle
CPU architecture has a certain complexity, it is difficult for
some students to complete this work. To solve this problem,
the hierarchical division approach which divides the CPU from
top to bottom into a series of easy-to-implement modules is
applied. Then, these modules can be implemented and verified
one by one. And when all the modules pass the verification
test, they can be assembled to build a completed CPU. In
Figure 2, the project overview for this experiment is shown.
Project 1 and 2 require students to integrate a SOC system
by using the CPU Intellectual Property (IP) cores. This SOC
system can provide a debugging and evaluation environment
for the CPU development later. Although the objective of the
experiment is to develop a CPU. Yet, if there is only one
CPU, without any other auxiliary peripheral devices, the CPU
cannot operate effectively. To provide a decent development
environment for CPU, the CPU needs to be embedded into
a SOC system. This SOC system, depicted as it is shown in
Figure 3, consists of the core CPU as well as the peripheral
components such as the ROM, RAM, Multiple IO (MIO) bus,
counter, seven-segment LEDs, buttons and switches. To build
this SOC system, the auxiliary elements such as the counter,
clock division, MIO bus, mechanical anti-jitter are developed
in project 1 firstly. Then, in project 2, these elements are
integrated with the CPU, ROM and RAM so that a complete
SOC system can be built.
From project 3 to project 8, the experiment focuses on
the multi-cycle MIPS CPU development. Since the CPU
architecture has a certain complexity, the hierarchical division
development approach is applied. First, in project 3, the CPU
is divided into two modules: CPU controller and CPU data
path. The controller is responsible for parsing the instruction
opcode, while the data path is responsible for parsing the
instruction address. Then, in project 4 and 5, the experiment
focuses on designing and implementing the CPU data path
and CPU controller respectively. In project 4, the hierarchical
division approach is applied further. With this approach, the
CPU data path is divided into a set of easy-to-implement ele-
ments, including the Arithmetic Logical Unit (ALU), register
set and transfer circuits. These elements are implemented and
Power
verified one by one, and then integrated to build the data
path. Similar to project 4, project 5 also uses the hierarchical
division approach to develop the CPU controller. It divides
the controller into a series of elements such as the opcode
parser and the function code parser. Then, it implements these
elements and integrate them to build the CPU controller.
On completion of project 5, the students are capable of
USB JTAG
building a single-cycle MIPS CPU. Next, in project 6, the
students are required to extend the architecture of the CPU
controller and CPU data path so as to make the CPU support
more MIPS instructions. After this extension, the students
also need to make assembly programs in which the extended
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Project 2 CPU Project 4 Extension Project 6 Project 8

CPU Design of single-cycle Extension of CPU Multi-cycle MIPS
Build SOC by IP cores Datapath
division CPU Datapath instructions CPU Design
CPU (IP core) division
Extension of CPU Multi-cycle CPU
Project 3 Transfer Circuit
RAM (IP core) Datapath Datapath Design
Project 1

…
Build CPU by IP cores
Early-stage Preparation ROM (IP core) Registers
Extension of CPU Multi-cycle CPU
CPU Datapath Controller Controller Design
MIO Bus MIO Bus Built by IP cores ALU





Counter Counter CPU Controller Project 7
Built by IP cores Project 5 CPU interruption
Clock Division Clock Division
Design of single-cycle Illegal instruction
Anti Jitter Anti Jitter interruption
CPU Controller Extension
CPU Arithmetic overflow
Seven-segment LED Seven-segment LED Opcode parsing interruption
Controller
Buttons/ Switches Buttons/ Switches division FunCode parsing External interruption

Fig. 2. Project overview for multi-cycle MIPS CPU design.

       

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instructions are used, and then run the programs on the buffer. In Figure 4, the data path of the extended multi-cycle
extended CPU so as to verify whether the extension is correct. CPU is shown. In addition to the datapath, the CPU controller
Project 7 extends the functionality of CPU further by also need to be redesigned, and this can be achieved by
enabling the CPU to process the interrupts such as illegal designing an instruction state machine and converting this state
instructions, arithmetic overflow and some other external in- table into the VHDL programming. In Figure 5, the instruction
terrupts. This extension involves the work of extending the state machine for the extended CPU controller is shown.
CPU controller by adding some elements such as the interrupt
detection circuit, anomaly detection circuit and interrupt re- IV. CPU D EVELOPMENT BY E ASY- TO - HARD
sponse control circuit. It also involves the work of extending I MPLEMENTATION T ECHNIQUE
the CPU data path by adding some registers and instruction Different technical solutions can be applied to implement
paths. the CPU modules, including the IP core reuse, the schematic
Finally, in project 8, the students are required to extend the design and the VHDL programming. IP core reuse is the
controller and datapath of the single-cycle CPU so that a multi- simplest way to implement the modules. Yet, not every module
cycle CPU can be built. To perform this extension, the CPU can have the IP core. If not, the students should develop the
datapath needs to be extended by adding the Program Counter modules independently by VHDL programming.
(PC) transfer path, the register set transfer path as well as the In order to make it easier for the students to master the
transfer path between the instruction register and the memory CPU implementation technique with FPGA. We have designed

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V. CPU V ERIFICATION BY VARIABLE - CONTROL
M ECHANISM
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modules can be developed one by one, and then assembled
to build a complete CPU. However, before being assembled,
the functionality of each module needs to be verified. In this
Fig. 5. State machine design for CPU controller development.
section, we present two kinds of verification approaches. One
is the verification by the ISE simulation, and the other is
different levels of implementation strategies for the CPU the verification by the real-world variable-control testing. The
development, as it is shown in Table I. former approach can be used to verify the functionality of each
In project 3, the CPU is divided into two modules, and the independent module in the CPU, while the latter one can be
IP cores of these two modules are provided to the students used to verify the systematic functionality of the entire CPU.
directly. The students can load these IP cores to build a 1) Verification by simulation: Simulation is a common
CPU rapidly. This project is easy to be implemented, and its mechanism to verify the functionality of an independent
objective is to perform the first division of the CPU and enable module in the CPU. In Figure 6, a simulation to verify the
students to learn how to integrate a CPU with the IP cores. opcode parsing operations in the CPU controller is shown. By
From project 4, the IP cores are no longer allowed to be setting a serial of input values and checking the correctness
used. The students should remove the IP cores provided in of the output, whether the functionality of the register set is
project 3 one by one, and then develop these modules inde- correct or not can be determined.
pendently by VHDL programming. Compared with project 3, 2) Verification by variable-control approach: Variable-
the development difficulty is improved significantly. control approach refers to the strategy which substitutes only
In project 4, the schematic design technique is still allowed one of the many parameters in the system each time, and
to be used. With the support of the schematic diagram, the then check whether this substitution has changed the original

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Fig. 6. Verify the CPU opcode parsing circuit by ISE simulation.
functionality of the system, so as to judge whether this
substitution is correct or not.
In Figure 7, the verification process of the variable-control
mechanism is shown. Provide the system is composed of three
modules: A, B and C. First, the standard IP cores of these
modules are loaded, and a standard-compliant system is built.
Suppose a test program T is input to this system, and its output
is R. Next, the standard IP core of module A is removed, and
the students are required to develop this module independently
by themselves. Then, to check whether the development of
module A is correct or not, the test program T is input
again to the system, and its output O1 is compared with the
standard output R. If O1 is matched with R, it indicates
the module A has been developed properly. Likewise, the
following modules such as B and C can be developed and
verified in the same way until the entire system is built by the
students independently.
Currently, the above variable-control approach has been
applied in our CPU development work. First, the standard IP
cores of different CPU modules are provided to build a CPU.
Then, these IP cores are removed one by one. Once removed,
the students need to develop this module independently by
Verilog programming, and then verify whether this substitution
is correct by using the variable-control approach.
VI. A PPLICATION D EVELOPMENT ON CPU
After the CPU is built, the students are also encouraged to
develop some applications programed by assembly language,
and then run these applications on the pre-built CPU. By doing
this, the students can understand how do the CPU operate more
deeply. Currently, many applications have been developed by
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the students. In Figure 8, some application examples such as
snake game, Tetris game and ping-pong game are shown.
VII. C OURSE S URVEY AND E VALUATION
Before 2014, we conducted the computer organization ex-
periment on the traditional solidified experiment board which
used the hands-on connection. Yet, from 2015, we started to
do experiments by designing a multi-cycle MIPS CPU on
the SWORD FPGA board. In 2017, we started to apply the
new teaching methods such as variable-control verification and
analogous teaching to our teaching work.
To evaluate the teaching effect, we did two kinds of
survey to the students. One is whether the new experiment,
which design a multi-cycle CPU with FPGA, has helped
you understand the computer organization principle better
if compared with the old experiment which performs the
hands-on connection on the solidified board. The survey result
showed that almost all the students thought the new experiment
was more contributive. Precisely, 36% students thought the
new experiment was more contributive in a small degree, while
62% thought it was more contributive in a large degree.
The other survey is whether the variable-control verification
and analogous teaching methods have helped you conduct
the experiment better? We did this survey in the year 2016
and 2017, and the survey results are shown in Figure 9
and Figure 10, respectively. From the results, it is shown
that the new teaching method applied in 2017 has improved
the teaching quality positively if compared with the teaching
situation in 2016.
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 WedP1.4

Test Stage 1 Standard output R

Program T Module A Module B Module C
built by standard IP core built by standard IP core built by standard IP core

Stage 2 Module A
Module A Module B Module C R = O1 ?
Output O1 is built correctly
built by students built by standard IP core built by standard IP core

Stage 3
Module B
Module A Module B Module C R = O2?
Output O2 is built correctly
built by students built by students built by standard IP core

Stage 4 Module C
Module A Module B Module C R = O2?
Output O3 is built correctly
built by students built by students built by students

Fig. 7. Verification process by using variable-control approach.

   
    
    
 

Fig. 8. Application development by assembly on the pre-built CPU.

Fig. 9. Survey on how do the students master each project (in 2016).
Fig. 10. Survey on how do the students master each project (in 2017).
VIII. C ONCLUSION
The new computer organization experiment which target to
build a multi-cycle MIPS CPU with FPGA is presented in
this paper. In order to enable the students to develop the CPU
better, the hierarchical division approach and the easy-to-hard
progressive implementation technique are proposed. To verify
the functionality of each CPU module, the variable-control
approach which verifies the CPU modules progressively by
comparing with the standard ones is investigated. The survey
result showed that the new experiment design with the new
teaching approach had improve the teaching quality of the
computer organization experiment significantly.
ACKNOWLEDGMENT
This research is funded by National Natural Science
Foundation of China (Grant No. 61702387), Natural Sci-
ence Foundation of Hubei Province of China (Grant No.
2017CFB302), Computer Education Research Association of
Chinese Universities (CERACU2019R07), and Cooperation
Education Project of Huawei and Ministry of Education of
China (201802001024).
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