Rev 1 5

Menlow Platform Crown Beach
Customer Enabling Board

Schematics
November 2007
Revision 1.5
Intel Confidential
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Copyright © 2007 Intel Corporation. All rights reserved.
2 Intel Confidential Schematics

5 4 3 2 1
Menlow Platform
Crown Beach Validation Hooks
PG 50 Validation Vehicle and
D
Fan
Header
CK540 Customer Enabling Board D
Silverthorne CPU PG 24
PG 5
Thermal
USFF 441
CPU & SCH XDP
(Silverthorne / Poulsbo)
Sensors PG 3,4
LVDS / BLI / ALS
PG 17 PG 5
PG 29 Rev 1.5 (ES2) Voltage Rails POWER PLANE ON STATE
FSB +V1.05S_SCH S0
+V1.05S_VTT S0
+V1.05_SUS S0, S3 (IF NEEDED)
DDR2 +V1.5S S0
PG 6 SODIMM +V1.5_SUS S0, S3 (IF NEEDED)
PG 9
LVDS TEST ONLY +V1.8 S0, S3
PG 18, 19 +V3.3 S0, S3
PG 7
+V3.3S S0
+V3.3A S0, S3, S4/S5
SDVO SDVO
+V3.3_SCH S0, S3
x16 mechanically PCIE x1 PCIE SLOT 0 +V3.3S_SCH S0

+V3.3_SLOTS S0
ADD2-N x1 PG 22 +V5 S0, S3
+V5S S0
C PG 16 +V5A S0, S3, S4/S5
C
PATA PATA Poulsbo PCIE x1 MINI PCIe SLOT2 +V12 S0, S3
PG 31 SCH 1249 PCIE SLOT 1 PG 15 - Wireless Card
+V12S S0
+V12_ATX S0, S3, S4/S5
x1 PG 22 TEST ONLY +V12_SLOTS S0
USFF
PG 7
HD AUDIO
MINI PCIe SLOT Note: Requires rework to enable
PG 14 - Wireless Card and disables Slot1.
PG 8 TEST ONLY IMVP-6 VR
HD AUDIO / SD/SDIO/MMC PG 41,42,43
MDC INTERPOSER CE-ATA SLOT0 SDIO SLOT0 PG 25
HEADER PG 25 - TEST ONLY DDR2 VR
SD/SDIO/MMC
PG 21 SDIO SLOT1 PG 36
FPIO/DB USB PG 25
PG 23
SD/SDIO/MMC POULSBO 1.5V VR
FPIO FPIO DB/UPHAM USB 1.1/2.0
SDIO SLOT2 PG 25 PG 38
B B
2.0 2.0 1.1
2.0 +V1.05SUS &
USB7 USB6 USB5 8 USB ports total +V1.5SUS & DDR2 VREF
PG 7 PG 37
BACK BACK BACK BACK BACK
PANEL PANEL PANEL PANEL PANEL LPC, 33MHz TPM 1.2 HEADER POULSBO CORE 1.05V &
ATX POWER CONN FSBVTT 1.05V VR
1.1 1.1 1.1 1.1 1.1 PG 21
2.0 2.0 2.0 2.0 2.0 PG 44 PG 33
USB0 USB1 USB2 USB3 USB4
POWER SEQUENCING SYSTEM (3.3V & 5V) VR
[Client] PG 47 PG 39
BACK PANEL USB
PG 32 Port 80-83 FWH SMC/KSC
ENABLES & PWRGDs EV Margining
8 Mbit (H8)
PG 40 PG 48
PG 49 PG 20 PG 26, 27
A
Crown Beach Intel Confidential
A
SCN KB/ PS2 Title

PG 30 Title Page
Size Document Number Rev

A 1.5
Date: Wednesday, November 14, 2007 Sheet 1 of 64

5 4 3 2 1
5 4 3 2 1
CROWN BEACH VALIDATION VEHICLE

SMBUS DIAGRAM, JUMPER SETTINGS, LED / SWITCHES, AND MISC BOARD INFORMATION
D LEDs and Switches Header Shunt Settings D
Default Description Page
LED Page
Mini WWAN 14 1-2 H_THERMDA 5

Mini WLAN 14 3-4 H_THERMDC 5
Mini WPAN 14 1-X CMOS EN 4
SDIO Slot 0 25 1-X RTC Reset 7
PG 6 SDIO Slot 1 25
PG 9
EMA_ALS_* SDIO Slot 2 25 N/A MFG/TEST 8
LVDS / BLI / ALS SMC/KBC Caps lock 26 1-2 CPV MFG/TEST 8
PG 7
SMC/KSC LPC, 33MHz SMC/KBC Scroll lock 26 2-3 SCH CFG0 12
PG 16 SMC/KBC Num lock 26 2-3 SCH CFG1 12
(H8) PATA Active 31 1-2 Slot2 D2 Mini 14
VID 0 34 1-2 WiFi Host Wake 14
Thermal PG 25, 26 VID 1 34 1-2 V3.3 Mini PCIe 14
Sensors ADI_THRM_* Stuffing Option EC_THRM_* VID 2 34 1-2 PMU_1 14
VID 3 34 1-2 PMU_2 14
PG 26 VID 4 34 1-2 GPS UART CTS 14
PG 5 Poulsbo VID 5 34 1-2 GPS On 14
VID 6 34 1-2 EC_WiFi PD# 14
PCIE SLOT 0 SCH 1249 H_IEER# 35 1-2
1-2
PMU_3
PMU_4
14
14
CPU_MCERR# 35
USFF
PG 7
x1 PG 22 SMC On/Off 46 2-3 Mini PCIe Power 15
Reset 46 1-2 PMU_1 15
PM_RSMRST 46 1-2 PMU_2 15
SMB_*_PCIE ISO Switch "OFF" in S3 S0 State 46 1-2 PMU_3 15
PCIE SLOT 1 S3 State 46 1-2 PMU_4 15
PG 8 S4/S5 State 46 1-X RECOVERY 20
x1 PG 22 Always Powergood 46
1-2 VCCHDA SEL 21
PG 8
PM_DELAY_VR_PWRGD 46
2-3 BSEL2 24
C SCH_PWROK 46
1-X BSEL1 24 C
MINI PCIe SLOT SMBUS PM_RSMRST_PWRGD 46
1-X CE_ATA Select(TEST) 25
CPU & SCH XDP 1-X SDIO Slot1 CD 25
High nibble Port 80/82 49
PG 14 1-X SDIO Slot2 CD 25
Low nibble Port 80/82 49 1-2 EC_RST# 26
PG 29 High nibble Port 81/83 49 1-2 MDO 26
Low nibble Port 81/83 49 1-2 MD1 26
CK540 1-X KBC DISABLE (NO-OP) 26
TPM 1.2 HEADER SODIMM 1-X Normal Oper 26
PG 24 1-X H8 JTAG 26
PG 21 PG 18, 19 1-X LID JMPR 27
1-X VB JMPR 27
1-2 PM_SLP_S3# 27
Switch Page 1-X XDP TCK 0 to 1 29
1-2 XDP TDI 29
PG 7 1-2 XDP TDO to TDI 29
Lid 27 1-2 XDP TDE Reset 29
Virtual battery 27 1-2 BOOT BLOCK PROG 30
Power On/Off 44 1-2 PATA PRELOAD 31
2 Reset 44 1-X Enable 5V Load 40
I C / SMB Addresses
1-2 Disable 12V Load 40
1-2 IMVP-6 STRAP_VID6 41
Page Device Hex Address Bus 3-4 IMVP-6 STRAP_VID5 41
5 CPU Thermal Sensor 2E EC_THRM_CLK, EC_THRM_DATA 5-6 IMVP-6 STRAP_VID4 41
5 DDR Thermal Sensor 4C EC_THRM_CLK, EC_THRM_DATA 7-8 IMVP-6 STRAP_VID3 41
18 SO-DIMM0 A0 SMB_CLK, SMB_DATA 9-10 IMVP-6 STRAP_VID2 41
21 TPM MODULE N/A SMB_CLK, SMB_DATA 11-12 IMVP-6 STRAP_VID1 41
24 Clock Generator - CK540 D2/D3 SMB_CLK, SMB_DATA 13-14 IMVP-6 STRAP_VID0 41
29 XDP N/A SMB_CLK, SMB_DATA 1-2 SLPIOVR#C6 43
1-X PORT 80-81 49
1-2 Manara VIDs 50
B ADDITIONAL HOOKS FOR TEST ONLY B
1-2 Port1 RS232 Mode 56
Default Jumper Settings For Stuffed Jumpers

1-X means jumper is parked on one pin.
H8 KBC & SMC all refer to different functions & names of
embedded controller.
Wake Events
Wake Events State Supported

PCI Express wake event S3
LID switch attached to SMC S3
USB S3
Hot Key from Scan matrix keyboard S3
PS/2 Keyboard/mouse S3
PWRBTN# S3, S4, S5
A Crown Beach A
Intel Confidential
Title
Notes

A 1.5
Date: Friday, November 16, 2007 Sheet 2 of 64

5 4 3 2 1
5 4 3 2 1
CLK_CPU_BCLK#
+VCCP1.05_CPU_C6_OFF 4,43 CLK_CPU_BCLK
+V1.05S_VTT_CPU 4,11,29,33,43,48,50
6 H_A#[31:3]
U3E1A
H_A#3 E22 C26
A[3]# ADS# H_ADS# 6
ADDR GROUP 0
H_A#4 A22 H25 R3T10 R3T9
A[4]# BNR# H_BNR# 6
H_A#5 D21 G24 R3T8 R2E1 49.9 49.9
A[5]# BPRI# H_BPRI# 6
H_A#6 E24 1K 1K 1% 1%
H_A#7 A[6]# 1% 1% SMR0402 SMR0402
B17 A[7]# DEFER# B27 H_DEFER# 6
H_A#8 A18 W28 CPU CPU CPU CPU
A[8]# DRDY# H_DRDY# 6
H_A#9 B23 D29 . NO_STUFF NO_STUFF
A[9]# DBSY# H_DBSY# 6
H_A#10 A16 A[10]#
D H_A#11 E18 A[11]# BR0# C28 H_BREQ#0 6 D
H_A#12 D15 R3E7
CONTROL
H_A#13 A[12]# H_IERR_R# 0 5%
B19 A[13]# IERR# H1 H_IERR# 35
H_A#14 A20 F31 CPU
A[14]# INIT# H_INIT# 6,20,27
H_A#15 D17
H_A#16 A[15]# R2E5
B15 A[16]# LOCK# D25 H_LOCK# 6
D19 H_CPURST_R# 56 5%
6 H_ADSTB#0 ADSTB[0]# H_CPURST# 6,29
M5 CPU
6 H_REQ#[4:0] RESET# H_RS#[2:0] 6
H_REQ#0 B25 D27 H_RS#0
H_REQ#1 D23 REQ[0]# RS[0]#
REQ[1]# RS[1]# E28 H_RS#1
H_REQ#2 E20 E26 H_RS#2 U3E1B
REQ[2]# RS[2]# 6 H_D#[63:0] H_D#[63:0] 6
H_REQ#3 A24 F25 H_D#0 Y27 AE8 H_D#32
REQ[3]# TRDY# H_TRDY# 6 D[0]# D[32]#
H_REQ#4 B21 H_D#1 AH27 AD7 H_D#33
REQ[4]# H_D#2 D[1]# D[33]#
6 H_A#[31:3] HIT# E30 H_HIT# 6 Y31 D[2]# D[34]# AH15 H_D#34
H_A#17 B5 F29 H_D#3 AC30 AF9 H_D#35
A[17]# HITM# H_HITM# 6 D[3]# D[35]#
DATA GRP 0
ADDR GROUP 1
H_A#18 A12 H_D#4 AE30 AH9 H_D#36
4,43 +VCCP1.05_CPU_C6_OFF H_A#19 A[18]# +V1.05S_VTT_CPU 4,11,29,33,43,48,50 H_D#5 D[4]# D[36]#
D5 F1 AF29 AE10 H_D#37
DATA GRP 2
A[19]# BPM[0]# XDP_BPM#0 29,48 D[5]# D[37]#
H_A#20 E12 E2 H_D#6 AA26 AJ16 H_D#38
A[20]# BPM[1]# XDP_BPM#1 29 D[6]# D[38]#
4,11,29,33,43,48,50 +V1.05S_VTT_CPU H_A#21 B9 F5 H_D#7 AB31 AF13 H_D#39
A[21]# BPM[2]# XDP_BPM#2 29 D[7]# D[39]#
XDP/ITP SIGNALS
H_A#22 A6 D3 H_D#8 W30 AF7 H_D#40
A[22]# BPM[3]# XDP_BPM#3 29,48 D[8]# D[40]#
H_A#23 B13 E4 H_D#9 AC28 AF15 H_D#41
A[23]# PRDY# XDP_BPM#4 29 D[9]# D[41]#
R3T13 H_A#24 E14 F7 R3T1 H_D#10 AD31 AH13 H_D#42
A[24]# PREQ# XDP_BPM#5 29 D[10]# D[42]#
R2D5 R3E8 1K H_A#25 A10 L2 60.4 H_D#11 AF27 AJ14 H_D#43
1K A[25]# TCK XDP_TCK_0 29 D[11]# D[43]#
1K 1% H_A#26 B7 N2 SMR0603 H_D#12 AD27 AJ12 H_D#44
1% A[26]# TDI XDP_TDI 29 D[12]# D[44]#
1% . CPU H_A#27 D13 M1 CPU H_D#13 AG28 AH7 H_D#45
A[27]# TDO XDP_TDO_CPU 29 D[13]# D[45]#
CPU H_A#28 A8 P1 1% H_D#14 AB25 AJ8 H_D#46
A[28]# TMS XDP_TMS 8,29 D[14]# D[46]#
NO_STUFF H_A#29 C4 J4 H_D#15 AC26 AJ10 H_D#47
A[29]# TRST# XDP_TRST# 8,29 D[15]# D[47]#
H_A#30 A14 G26 AA28 AH11
A[30]# RSVD14 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_A#31 B11 TP_XDP_DBRESET# AA30 AF11
A[31]# 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
D11 H5 H_PROCHOT_R# 22.1 1% AE28 AE12
6 H_ADSTB#1 ADSTB[1]# PROCHOT# H_PROCHOT# 8,41,48,50 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
THERM
T5 R3T2 CPU
THRMDA H_THERMDA 5
27 H_A20M# G30 A20M# THRMDC U4 H_THERMDC 5 6 H_D#[63:0] H_D#[63:0] 6
C J28 FERR#
H_D#16 AE24 D[16]# D[48]# AH5 H_D#48 C
6 H_PBE# H_IGNNE# 0 5% H_IGNNE_R# H27 H_D#17 H_D#49
IGNNE# THERMTRIP# T1 PM_THRMTRIP# 6,50 AC24 D[17]# D[49]# AB5
R3E9 H_D#18 AJ20 AJ6 H_D#50
H_D#19 D[18]# D[50]# H_D#51
6,50 H_STPCLK# K1 STPCLK# SPARE[7-0], HFPLL: route to TP AE20 D[19]# D[51]# Y1
H31 via and place gnd via w/in H_D#20 AJ22 AF5 H_D#52
H CLK
6 H_INTR LINT0 D[20]# D[52]#
DATA GRP 1
L28 P29 H_D#21 AF25 AG4 H_D#53
6,21 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 24 100mils D[21]# D[53]#
H_D#22 H_D#54
DATA GRP 3
6,21,48 H_SMI# J26 SMI# BCLK[1] R28 CLK_CPU_BCLK# 24 AH25 D[22]# D[54]# AF3
H_D#23 AH23 AC6 H_D#55
H_D#24 D[23]# D[55]# H_D#56
AE16 RSVD7 AH19 D[24]# D[56]# AE6
+VCCP1.05_CPU_C6_OFF 4,43 AF17 K31 TP3F1 H_D#25 AF23 AE4 H_D#57
RSVD8 VSS0 NO_STUFF H_D#26 D[25]# D[57]# H_D#58
AD15 RSVD9 AE18 D[26]# D[58]# W4
AD17 H_D#27 AH17 AC2 H_D#59
0 5% RSVD10 H_D#28 D[27]# D[59]# H_D#60
D9 RSVD0 RSVD11 A26 CPU_MCERR# 35 Layout note: Zo=55 ohm, AD19 D[28]# D[60]# AE2
. R3E14 D7 E6 0.5" max for GTLREF. H_D#29 AJ24 AD1 H_D#61
NC
0 5% RSVD1 RSVD6 H_D#30 D[29]# D[61]# H_D#62

E8 RSVD2 AJ18 D[30]# D[62]# AA2
. R3E13 E10 G28 H_D#31 AF19 AC4 H_D#63
0 5% RSVD3 RSVD15 TP3F3 D[31]# D[63]#
L30 RSVD4 TEST4 U30 6 H_DSTBN#1 AF21 DSTBN[1]# DSTBN[3]# AB1 H_DSTBN#3 6
. R3E15 J30 NO_STUFF +VCCP1.05_CPU_C6_OFF 4,43 AH21 AA4
RSVD5 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
0 5% V27 AE22 Y5
TEST3 6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6
. R3E16 K29 AE26 CPU_CMREF
RSVD13 CMREF[1] R2F10 H_GTLREF COMP0 27.4 1%
AJ26 GTLREF COMP[0] AE14
SILVERTHORNE rev 1.04 1K TEST ONLY - MISC AD13 COMP1 R3T5 CPU 54.9 1%
D97330-004 --> E16641-001 1% COMP[1] COMP2 27.4 1% R3T4 CPU
TEST[2:1] should be left NC COMP[2] E16
4,11,29,33,43,48,50 +V1.05S_VTT_CPU CPU 50 ACLKPH R3F5 COMP3 R3T7 CPU 54.9 1%
COMP[3] F15
SMR0603 1 2 0 5% ACLKPH_R P31 R3T6 CPU
. R2F6 CPU TEST1
T31 TEST2 DPRSTP# G2 H_DPRSTP# 6,21,41,50
. C2F3 0 5% J3F2. R3F7 G6
DPSLP# H_DPSLP# 6,21,50
R3F2 0.1uF CPU 1 2 0 5% V31
DPWR# H_DPWR# 6
1K 10% NO_STUFF CPU DCLKPH_R R30 G4
BSEL[0] PWRGOOD H_PWRGD 6,21,50
1% 10V R2F9 J3F1. M31 J2
2K BSEL[1] SLP# H_CPUSLP# 6,21,50
CPU CPU U28 K27
SMR0603 1% 50 DCLKPH BSEL[2] RSVD12 R2E4
.
B 4,11,29,33,43,48,50 +V1.05S_VTT_CPU 24,50 CPU_BSEL0 SILVERTHORNE rev 1.04 1K 5% B
D97330-004 --> E16641-001 . H_PWRGD_XDP 29
24,50 CPU_BSEL1 .
R3F1 R3T11 24,50 CPU_BSEL2
XDP_TMS 56 5% 2K C3E1 2K R3T12
CPU R3E1 1% 0.1uF 1% 0 5%
. PSI# 41
XDP_TDI 56 5% CPU 10% R3F6 R3F4 CPU
CPU R3E2 SMR0603 . 10V CMOS_EN_Q 1K 1K SMR0402
3
XDP_TDO_CPU 56 5% CPU 1% 1% NO_STUFF R2B9

CPU R3E3 SMC0402 Q3U1 CPU CPU 1K
NO_STUFF BSS138 NO_STUFF NO_STUFF 5%
TEST ONLY - .
XDP_TCK_0 56 5% TEST3 Should be left NC 1
6 CMOS_EN
CPU R3E4
.
2
CMVREF MARGIN header - TEST ONLY +V1.05S_VTT_CPU 4,11,29,33,43,48,50

J2F4
2 R2F13
4,43 +VCCP1.05_CPU_C6_OFF G1 0 5%
S 1
CPU
G3
G4
3 G2 SMA_SMT 4,43 +VCCP1.05_CPU_C6_OFF R2E2 R2T2 R2E3 R2D6

C51931-001 1K 1K 402 1K Layout note:
4
XDP_BPM#4 56 5% 1% 1% 1% 1% Comp0,2 connect with Zo=27.4ohm, make

. . . .
CPU R1E9 R2F7 trace length shorter than 0.5".
XDP_BPM#3 56 5% NO_STUFF CAN BE PLACED AWAY FROM CPU 1K Comp1,3 connect with Zo=55ohm, make
H_CPUSLP# 6,21,50
CPU R1E8 1% trace length shorter than 0.5".
XDP_BPM#2 NO_STUFF 56 5% CPU
H_PWRGD 6,21,50
CPU R1E7 GTLREF MARGIN header - TEST ONLY . SMR0603
XDP_BPM#1 56 5% NO_STUFF J2F3
H_DPSLP# 6,21,50
CPU R1E6 2 R2F12
XDP_BPM#0 NO_STUFF 56 5% G1 0 5%
S 1 H_DPRSTP# 6,21,41,50
CPU R1E5 CPU C2F2 R2F8
G3
G4
3 G2
NO_STUFF SMA_SMT 0.1uF 2K
H_GTLREF_VREFIN
C51931-001 10% 1%
A Crown Beach A
4
XDP_BPM#5 56 5% 10V CPU

CPU R3T3
CAN BE PLACED AWAY FROM CPU .
CPU
SMC0402
SMR0603 Intel Confidential
H_IGNNE# 1K 5% Title
R3E10
J2F2 Silverthorne CPU (1 of 2)
1 2
.
. Size Document Number Rev
A 1.5
Date: Tuesday, November 20, 2007 Sheet 3 of 64

5 4 3 2 1
5 4 3 2 1
D TEST ONLY -
Note (assume fusing voltage is 1.5v)
D
U3E1D
Normal - 0 ohm installed or short pin1-2 A4 Y29
Fusing - remove 0 OHM, stuff jumper # & short pins 2-3 VSS1 / NCTF VSS162
A28 VSS2 / NCTF VSS161 Y25
assume fusing voltage is 1.5v
AA6 VSS4 VSS160 Y23
AA24 VSS5 VSS159 Y21
3,43 +VCCP1.05_CPU_C6_OFF AB3 Y19
VSS6 VSS158
AB27 VSS7 VSS157 Y17
AB29 VSS8 VSS156 Y15
0 5% AC8 Y13
CPU R3E12 +VCC_CORE 5,41..43 VSS9 VSS155
AC10 VSS10 VSS154 Y11
NO_STUFF U3E1C AC12 Y9
5,6,8,11,14,21,24,38 +V1.5S VSS11 VSS153
AC14 VSS12 VSS152 Y7
CON3_HDR AA14 L8 AC16 Y3
J2E1 VCCP35 VCC1 VSS13 VSS151
J16 VCCP36 VCC2 L10 AC18 VSS14 VSS149 W6
3 VCC3 L12 AC20 VSS15 VSS148 V29
3,11,29,33,43,48,50 +V1.05S_VTT_CPU 2 M27 L14 AC22 V25
0 5% C3T56 VCCPC60 VCC4 VSS16 VSS147
1 VCC5 L16 AD3 VSS17 VSS146 V23
CPU R3E11 0.1uF H7 L18 AD5 V21
NO_STUFF 10% VCCPC61 VCC6 VSS18 VSS145
H9 VCCPC62 VCC7 L20 AD9 VSS19 VSS144 V19
. J8 L22 AD11 V17
VCCPC63 VCC8 VSS20 VSS143
VCC9 L24 AD21 VSS21 VSS142 V15
0 5% N6 AD23 V13
R2E7 VCC10 VSS22 VSS141
VCC11 N8 AD25 VSS23 VSS140 V11
VCC12 N10 AD29 VSS24 VSS139 V9
VCC13 N12 AF1 VSS25 / NCTF VSS138 V7
VCC14 N14 AF31 VSS26 / NCTF VSS137 V5
VCC15 N16 AG2 VSS27 / NCTF VSS136 V3
VCC16 N18 AG6 VSS28 VSS135 T29
C VCC20 R6 AG14 VSS32 VSS131 T21 C
VCC21 R8 AG16 VSS33 VSS130 T19
3,43 +VCCP1.05_CPU_C6_OFF R18 AG26 T9
VCC26 VSS38 VSS125
AA8 VCCP1 VCC27 R20 AG30 VSS39 / NCTF VSS124 T7
AA10 VCCP2 VCC28 R22 AH3 VSS41 / NCTF VSS123 T3
AA12 VCCP3 VCC29 R24 AH29 VSS42 / NCTF VSS122 P27
AA16 VCCP4 VCC30 U6 AJ4 VSS45 / NCTF VSS121 P25
AA18 VCCP5 VCC31 U8 AJ28 VSS46 / NCTF VSS120 P23
AA20 VCCP6 VCC32 U10 B3 VSS48 / NCTF VSS119 P21
AA22 VCCP7 VCC33 U12 B29 VSS49 / NCTF VSS118 P19
AB7 VCCP8 VCC34 U14 C2 VSS51 / NCTF VSS117 P17
AB9 VCCP9 VCC35 U16 C6 VSS52 VSS116 P15
AB19 VCCP14 VCC40 W8 C16 VSS57 VSS111 P3
AB21 VCCP15 VCC41 W10 LAYOUT NOTE: PLACE C3T51 C18 VSS58 VSS110 N28
AB23 W12 +V1.5S 5,6,8,11,14,21,24,38 C20 M29
H11
VCCP16 VCC42
W14
NEAR PIN N30. C22
VSS59 VSS109
M25
VCCP17 VCC43 filter per PDBOM 0.5 VSS60 VSS108
H13 VCCP18 VCC44 W16 C24 VSS61 VSS107 M23
H15 VCCP19 VCC45 W18 C30 VSS62 / NCTF VSS106 M21
H17 W20 0.01 1% D1 M19
VCCP20 VCC46 R3F3 CPU VSS63 / NCTF VSS105
H19 VCCP21 VCC47 W22 D31 VSS64 / NCTF VSS104 M17
H21 W24 C3T51 C3T57 F3 M15
VCCP22 VCC48 0.1uF 10uF VSS65 VSS103
H23 VCCP23 F9 VSS66 VSS102 M13
J10 10% 0603 F11 M11
VCCP24 VSS67 VSS101
2
1
J12 N30 . 20% F13 M9
B VCCP25 VCCA J3F3 VSS68 VSS100 B
J14
J18
VCCP26 CPU 2X2HDR
2x2 PME header F17
F19
VSS69 VSS99 M7
M3
VCCP27 VSS70 VSS98
J20 P5 H_VID0 41,50 F21 L6
4
3
VCCP28 VID[0] . VSS71 VSS97
J22 VCCP29 VID[1] R4 H_VID1 41,50 F23 VSS72 VSS96 K25
L26 VCCP30 VID[2] N4 H_VID2 41,50 F27 VSS73 VSS95 K23
N26 VCCP31 VID[3] K5 H_VID3 41,50 G8 VSS74 VSS94 K21
R26 VCCP32 VID[4] L4 H_VID4 41,50 G10 VSS75 VSS93 K19
U26 R2 R3D3 G12 K17
VCCP33 VID[5] H_VID5 41,50 VSS76 VSS92
W26 U2 100 G14 K15
VCCP34 VID[6] H_VID6 41,50 LX1_FBK 41,42 VSS77 VSS91
1% G16 K13
VCCSENSE_R 50 VSS78 VSS90
CPU G18 K11
0 5% VSS79 VSS89
VCCSENSE W2 VCCSENSE 41 G20 VSS80 VSS88 K9
CPU R3E5 G22 K7
VSS81 VSS87
H3 VSS82 VSS86 K3
V1 0 5% H29 J24
VSSSENSE VSSSENSE 41 VSS83 VSS85
CPU R3E6 J6
SILVERTHORNE rev 1.04 VSS84
D97330-004 --> E16641-001. R3D4
VSSSENSE_R 50
100 SILVERTHORNE rev 1.04
1% Layout Note: D97330-004 --> E16641-001 .
CPU Route VCCSENSE and VSSSENSE
traces at 27.4 Ohms with 18mil trace,
7mil vccsense to vsssense spacing. 25
mil spacing from others.
REMOVE WHEN POWERME PLUGGED IN Place PU and PD within 1 inch of CPU.
A Crown Beach A
Intel Confidential
Title
Silverthorne CPU (2 of 2)

A 1.5

5 4 3 2 1
5 4 3 2 1
CPU Thermal Sensors

+V3.3S 6..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
C4P1 R4C4 R4P2

R4P6 R4R1 0.1uF 10K 10K
10K 10K 20% 5% 5%
5% 5% . .
.
. . +VCC_CORE 4,41..43
U4P1
1 24 ADT_THERM_PWM +V1.5S 4,6,8,11,14,21,24,38 J4D1
27 ADI_THRM_DATA SDA PWM1
2 23 +V12S 16,17,31,33,35,45 Default Stuffing: 1-2 3-4 CAD NOTE: Route all thermal diode signals on
27 ADI_THRM_CLK SCL VCCP
3 22 Option Stuffing: 1-X 3-X same layer w/ ground guard traces on each side.
GND +2_5V_IN
D NOTE: Option for hooking these 4 VCC +12_IN 21 D
to SCH SMBUS on Page 26. TP_7463_VID0 5 20
TP_7463_VID1 VID0 +5V_IN TP_7463_VID4
6 VID1 VID4 19
TP_7463_VID2 7 18 ADT_THERM_DXP 0 R4C5 THERM_DXP J4D1
TP_7463_VID3 VID2 D1+ ADT_THERM_DXN C4C6
8 VID3 D1- 17 2 1 H_THERMDA 3
9 16 ADT_THERM_D2P 1000pF 4 3
TP_7463_PWM2 TACH3 D2+ ADT_THERM_D2N 5% 0 R4C6 THERM_DXN H_THERMDC 3
10 PWM2 D2- 15
ADT_THERM_TACH 11 14 . 2X2HDR
TACH1 TACH4
12 TACH2 PWM3 13
NOTE: empty for tach circuit stuffed Layout Note:
ADI ADT7463 C4C5 Route H_THERMDA and
R4P4 R4P5 R4P3 1000pF H_THERMDC on same layer
10K 10K 10K 5% w/ 10 mil trace & 10 mil
5% 5% 5% C88861-001
. . . . spacing. Route away from
noise sources with ground
NOTE: Pin 13 also used to set SMBUS Address Enable. CAD NOTE: PLACE NEAR ADT guard tracks on each side.
Always pull high - Default address = 0x2E
3
J1E1
1 Q4C3 3Pin_Recepticle
2N3904
2 1
2 THERMDP THERMDN
PM_ADI_THERM# CAD NOTE: PLACE TOP SIDE GND0 GND2

UNDER SO-DIMM OUTLINE GND1 3 4 5 6 GND3
C83026-001
C C
Thermal Diode Connector
Vendor recommends no
connecting D+/D-, leaving EXTERNAL THERMAL SENSOR
resistor footprints just in case. THRM_REMOTE2_P
THRM_REMOTE1_P C7D3
C7D4 +V3.3S 6..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 1000pF 1
1 1000pF 10% THRM_REMOTE2_N 2
2 THRM_REMOTE1_N 10% . 3
3 .
Layout Note:
Place U8D1 R8D2 R7D3 J7D1
J7D2 R7D5 10K 10K
under DIMM 5%
10K . NO_STUFF
NO_STUFF U8D1
+V3.3S 6..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 1 10
VDD SCLK ADI_THRM_CLK 27
2 D1+ SDATA 9 ADI_THRM_DATA 27
R8D7 R8D6 3 8
0 D1- ALRT#/THM2#
4 THM# D2+ 7
5 GND D2- 6
8.2K .
R7D4 ADT7481ARMZ-1 TEMP MON
10K D46790-001
8,26 PM_THRM#
NO_STUFF R7D1
NOTE: SMBUS Address = 0x4C 10K
NO_STUFF
PM_ADI_EXTTS#
B R8D4 B
0
Fan Power Control PM_EXTTS# 7,18
+V3.3S 6..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
+V5S 12,17,31,33..35,40,41,44,45
R3C6
0 5%
C4C3 C4C1 . Place fan connector near CPU
0.1uF 4.7uF SMR0805
10% 10% 3
. . J4C1
CR4C1 1 1
12
10
11
BAT54 2 2
1
Stuff for FAN Always ON R3C7 Q4C2

1K CONN2_HDR
NO_STUFF 1 .
V+
8 _ 2
TF
EN OPA567_OUT
OPA567 OUT
R3C12 15K OPA567_POSIN 9 3 V5S_FAN
26,28 FAN_PWM + ISIF
HS
V- D17188-001
8
7
6
5
FAN_PWM needs to be driven NO_STUFF

low during S3, S4, and S5 by C4C4 R4P1 NO_STUFF
4
5
13
6
7
the EC. 1uF R4C2 0 4 ADT_THERM_PWM

10% 1.8K 5%
OPA567_ISIN_R
3
2
1
. . IRF7822
A SMR0805 Q4C1 Crown Beach A
OPA567_NEGIN
C4C2 Intel Confidential
IF STUFFED USE 2 OHM
ADT_THERM_TACH Title
R4C3
3.3K 10% CPU Thermal Sensor & Fan
R4C1 R4B16 0.01UF
20K 0.002 NO_STUFF
5% 1%
.
NO_STUFF NOTE: MAX FOR Icc = 500mA Size Document Number Rev
NOTE: USED FOR ADT FAN CONTROL
A 1.5
AND TACH MEASUREMENT

5 4 3 2 1
5 4 3 2 1
U5E1A
3 H_D#[63:0] H_A#[31:3] 3
D H_D#0 V8 H_D0# H_A3# M2 H_A#3 D
H_D#1 AF4 M8 H_A#4
H_D#2 H_D1# H_A4# H_A#5
V2 H_D2# H_A5# K4
H_D#3 AA1 P2 H_A#6
H_D#4 H_D3# H_A6# H_A#7
AC1 H_D4# H_A7# F4
H_D#5 AD2 G1 H_A#8
H_D#6 H_D5# H_A8# H_A#9
V4 H_D6# H_A9# M4
H_D#7 Y2 F6 H_A#10
H_D#8 H_D7# H_A10# H_A#11
U1 H_D8# H_A11# H6
H_D#9 Y8 D2 H_A#12
H_D#10 H_D9# H_A12# H_A#13
AB2 H_D10# H_A13# H2
H_D#11 AF2 J1 H_A#14
H_D#12 H_D11# H_A14# H_A#15
AB4 H_D12# H_A15# F2
H_D#13 AF8 D4 H_A#16
H_D#14 H_D13# H_A16# H_A#17
AE1 H_D14# H_A17# D12
H_D#15 AB8 H12 H_A#18
H_D#16 H_D15# H_A18# H_A#19
AJ1 H_D16# H_A19# G11
H_D#17 AH2 A7 H_A#20
H_D#18 H_D17# H_A20# H_A#21
AM8 H_D18# H_A21# A9
H_D#19 AN1 A11 H_A#22
H_D#20 H_D19# H_A22# H_A#23
AK4 H_D20# H_A23# B6
H_D#21 AG1 H8 H_A#24
H_D#22 H_D21# H_A24# H_A#25
AH8 H_D22# H_A25# F10
H_D#23 AK8 B10 H_A#26
H_D#24 H_D23# H_A26# H_A#27
AP8 H_D24# H_A27# D6
H_D#25 AK2 D10 H_A#28 +V1.05S_VTT_SCH 8,11,56 Separate GVREF and CGVREF by 15
H_D#26 H_D25# H_A28# H_A#29 mils for stripline and 16 mils for
AR1 H_D26# H_A29# B12
H_D#27 AT8 B4 H_A#30 microstrip. Try to place C5T68 and
H_D#28 H_D27# H_A30# H_A#31 C5T46 close to the pin even if the
AT2 H_D28# H_A31# D8
H_D#29 AH4 R4T14 resistors can’t be
H_D#30 H_D29# 100
AP4 H_D30# H_ADS# K6 H_ADS# 3 1%
H_D#31 AP2 H4 .
H_D31# H_ADSTB0# H_ADSTB#0 3
C H_D#32 AV4 H_D32# H_ADSTB1# B8 H_ADSTB#1 3
C
H_D#33 BB6 Y10
H_D33# H_GVREF H_GVREF 48
+V1.05S_VTT_SCH 8,11,56 H_D#34 AV6 R1 +V1.05S_VTT_SCH 8,11,56
H_D34# H_BNR# H_BNR# 3
H_D#35 AY8 P10
H_D35# H_BPRI# H_BPRI# 3
H_D#36 BA1 L1 C5T68 R4T13
H_D36# H_BREQ0# H_BREQ#0 3 200
H_D#37 AU1 M6 0.1uF R5T4
H_D37# H_CPURST# H_CPURST# 3,29 1% 100
R4T16 H_D#38 AT6 AD4 10% .
221 H_D#39 H_D38# H_CGVREF NO_STUFF 1%
1% AV8 H_D39# .
. H_D#40 BB4 K10
H_D#41 H_D40# H_CLKINN CLK_SCH_BCLK# 24
AT4 H_D41# H_CLKINP M10 CLK_SCH_BCLK 24 H_CGVREF 48
H_D#42 AY6 H10
H_D42# H_DBSY# H_DBSY# 3
H_D#43 AV10 AD6 C5T46
HOST
H_D43# H_DEFER# H_DEFER# 3 H_DINV#[3:0] 3
H_D#44 AV2 AD8 H_DINV#0 0.1uF R4T9 R4T8 +V12S_CPU 42,43,45
R4T15 C5T75 H_D#45 H_D44# H_DINV0# H_DINV#1 10% 200 200
BC1 H_D45# H_DINV1# AM2 1% 1%
100 0.1uF H_D#46 BB2 AY10 H_DINV#2 NO_STUFF
1% H_D46# H_DINV2# . .
. 20% H_D#47 AY2 BK8 H_DINV#3
. H_D#48 H_D47# H_DINV3# R3G2
BD2 H_D48# H_DPWR# P6 H_DPWR# 3
3
H_D#49 BH4 J9 10K
H_D49# H_DRDY# H_DRDY# 3 H_DSTBN#[3:0] 3 5%
H_D#50 BD10 Y4 H_DSTBN#0 Q4T1 .
H_D#51 H_D50# H_DSTBN0# H_DSTBN#1 BSS138
BK10 H_D51# H_DSTBN1# AL1
R4T17 H_D#52 BD6 AW1 H_DSTBN#2 1
H_D52# H_DSTBN2# CMOS_EN 3
24.9 H_D#53 BD4 BH8 H_DSTBN#3
H_D53# H_DSTBN3# H_DSTBP#[3:0] 3
2
1% H_D#54 BF2 W1 H_DSTBP#0 .
2
H_D#55 H_D54# H_DSTBP0# H_DSTBP#1 J3G1
BE1 H_D55# H_DSTBP1# AM4
H_D#56 BD8 AY4 H_DSTBP#2 Default [1-X]
H_D#57 H_D56# H_DSTBP2# H_DSTBP#3
BF4 BF8 .
1
H_D#58 H_D57# H_DSTBP3#
BH10 H_D58#
H_D#59 BK6 V10 R4R8 0
H_D59# H_HIT# H_HIT# 3
+V1.5S 4,5,8,11,14,21,24,38 H_D#60 BB8 T6 NO_STUFF
H_D60# H_HITM# H_HITM# 3
H_D#61 BF6 Y6
H_D61# H_LOCK# H_LOCK# 3 H_REQ#[4:0] 3
H_D#62 BF10 P4 H_REQ#0 +V3.3S 5,7,8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
R4T1 H_D#63 H_D62# H_REQ0# H_REQ#1
BH6 H_D63# H_REQ1# N1
B 60.4 1% K8 H_REQ#2 B
H_REQ2# H_REQ#3
3,21 H_NMI AB10 H_NMI H_REQ3# P8
R4T2 R4T12 0 H_SMI#_R AB6 K2 H_REQ#4 R4R7
3,21,48 H_SMI# H_SMI# H_REQ4# H_RS#[2:0] 3 75K H_PWRGD 3,21,50
60.4 1% R4T7 24.9 H_PBE#_R AH6 T4 H_RS#0
3 H_PBE# H_PBE# H_RS0# 5%
1% H_SWING V6 T2 H_RS#1 . 3
+V1.05S_VTT_SCH 8,11,56 H_SWING H_RS1# H_RS#2
H_PWRGD_SCH_Q
3,50 H_STPCLK# AD10 H_STPCLK# H_RS2# T8
R4T6 0 H_TESTIN#_R AK6 AH10 1 Q4R1
29 H_TESTIN# H_TESTIN# H_CPUSLP# H_CPUSLP# 3,21,50
R4T5 121 1% H_RCOMPO T10 F12 3 2N3904
H_RCOMPO H_TRDY# H_TRDY# 3
H_PLLMON1 TEST ONLY - RESERVED5 should be NC AT10
H_PLLMON1# TEST ONLY - RESERVED4 should be NC RESERVED5 H_PWRGD_SCH R4R9 Q4R2 2
AP10 RESERVED4 H_CPUPWRGD AP6 1
R4T4 PM_THRMTRIP#_R AM6 F8 1K 5% 2N3904
3,50 PM_THRMTRIP# H_THRMTRIP# H_DPSLP# H_DPSLP# 3,21,50 H8_CPU_PWRGD 26
24.9 1% AK10 H_DPRSTP#_R R4T3 0 .
H_DPRSTP# H_DPRSTP# 3,21,41,50 2
3,20,27 H_INIT# AF10 H_INIT#
3 H_INTR AF6 H_INTR
CFG0 J27 SCH_BSEL0 12
CFG1 B34 SCH_BSEL1 12
BSEL2 F28 SCH_BSEL2 24
POULSBO_1.03
D76284-004 --> E11512-002
A Crown Beach A
Intel Confidential
Title
Poulsbo (1 of 8)

A 1.5

5 4 3 2 1
5 4 3 2 1
20,21,26,28,49 LPC_AD[3:0]
R5U8 1 2 10 5%
28 CLK_LPC_ALTEC NO_STUFF
R5U17 22 5%
20 CLK_LPC_FWH
.
R5U11 22 5%
26 CLK_LPC_H8
.
R5U22 33 5%
NO_STUFF
C5U5
10pF
5%
NO_STUFF
R5U16 33 5%
49 CLK_LPC_PORT80
. CAD NOTE: Place all series resistors near the SCH
D R5U14 33 5% and place all 10 pF caps near farthest component clocked D
NO_STUFF by the LPC bus
C1J8 R5U15 33 5% (For EV testing)
10pF NO_STUFF
5% C1J7
NO_STUFF 10pF
5%
NO_STUFF
R5U29 33 5%
21 CLK_LPC_TPM
.
R5U26 33 5%
NO_STUFF
C1J5 R5U25 33 5%
10pF NO_STUFF
5% C1J6 U5E1B
NO_STUFF 10pF LPC_AD0 K38 LPC_AD0 BK50 SCH internal VR enable strap for +V1.5 & +V1.05 VRs
RESERVED8 SCH_DETECT# 56
5% LPC_AD1 J39 LPC_AD1
NO_STUFF LPC_AD2 A35 LPC_AD2 INTVRMEN R4H2 R4H1
LPC BUS
5,6,8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 LPC_AD3 L39 LPC_AD3
+V3.3S
R9C1 CLK_LPC_0 Enable (default) 1 STUFF UNSTUFF
F38 LPC_CLKOUT0
10K 5% CLK_LPC_1 B36
R5U37 . CLK_LPC_2 LPC_CLKOUT1 Disable UNSTUFF STUFF
D38 LPC_CLKOUT2
8.2K
MISC SIGNALS
D36 10,12 +V3.3A_RTC
21,26,28 PM_CLKRUN# LPC_CLKRUN#
21,26,28 INT_SERIRQ B38 LPC_SERIRQ
20,21,26,28,49 LPC_FRAME# K40 LPC_FRAME# R4H2

A33 10K
17 L_BKLTCTL L_BKLTCTL
A31 L_BKLTEN
17 L_BKLTEN Cap values depend on Xtal
D28 L_CTLA_CLK .
C 17 L_CLKCTLA SCH_INTVRMEN C
K26 L_CTLB_DATA
17 L_CLKCTLB C6F2
17 L_DDC_CLK A27 L_DDCCLK RESERVED0 E49 RESERVED0 12
H28 B32 10pF 27,34,37,39,40,44..46,57 +V3.3A
17 L_DDC_DATA L_DDCDATA RESERVED1 RESERVED1 12
D30 BE15 R4H1
L_VDDEN RESERVED2 RESERVED2 18
4
17 L_VDDEN
LVDS
BA21 0
RESERVED3 RESERVED3 18
AF48 R6F1 10,12 +V3.3A_RTC 2
17 LA_CLKP LA_CLKP 32.7680KHZ
AF50 10M NO_STUFF
17 LA_CLKN LA_CLKN Y6F1
AJ43 C4H2
1
17 LA_DATAN0 LA_DATAN0 1.0uF
AK48 LA_DATAN1
17 LA_DATAN1 C6F1 20% CR4H1
AH48 LA_DATAN2 3
17 LA_DATAN2 RTC_X1 10pF . BAT54C
AG45 F48
17 LA_DATAN3 LA_DATAN3 RTC_X1
F50 RTC_X2 RTC Circuitry SMC0402
RTC_X2
17
LA_DATAP0
AJ45
AK50
LA_DATAP0 SYSTEM MGMT RTC INTVRMEN F46
H48 RTC_RST# R5H7
17
LA_DATAP1 LA_DATAP1 RTCRST# 20K
AH50 LA_DATAP2
2
17
LA_DATAP2 C5H1 5% 1
AG43 LA_DATAP3
17
LA_DATAP3 J4H1 1.0uF
25 SLOT0_CD# EXTTS D32 PM_EXTTS# 5,18 .
R5F5 47 5% B18 20% BAT_D
25 SLOT0_CLK SD0_CD# .
R5U24 47 5%SLOT0_R_CLK D18 C49 .
25 SLOT0_CMD SCH_PWROK 26,28,46
1
SLOT0_R_CMD SD0_CLK PWROK PM_SLPRDY#_R R6T22 0 SMC0402 R5H6
25 SLOT0_LED J15 SD0_CMD SLPRDY# J49 PM_SLPRDY# 26,28
25 SLOT0_WP H18 . 1K
. SD0_LED PM_DPRSLPVR_R R5U36 0 R6U2
25,56 SD0PWR# F18 SD0_WP DPRSLPVR D34 PM_DPRSLPVR 21,41
R5U13 . 221 1%SLOT1_R_DATA5 H20 . 10K RTC Reset J4H1
25 SLOT0_DATA[7:0] SD0_PWR# BAT
SLOT0_DATA0 R5U23 .
47 5%SLOT0_R_DATA0 H16 L45 Clear RTC Shunt
SD0_DATA0 SLPMODE PM_SLPMODE 26,28
SLOT0_DATA1 R5F8 47 5%SLOT0_R_DATA1 A17 . Keep RTC Open 1-X (Default)
SLOT0_DATA2 R5U28 47 5%SLOT0_R_DATA2 SD0_DATA1 PM_RSMRST#_R R6U1 0
K18 SD0_DATA2 RSMRST# L43 PM_RSMRST# 26,28,46
2
SLOT0_DATA3 R5F6 47 5%SLOT0_R_DATA3 F16 .
SLOT0_DATA4 R5U20 . 47 5%SLOT0_R_DATA4 SD0_DATA3
K16 SD0_DATA4 SDVO_CTRLCLK F30 SDVO_CTRLCLK 16
SLOT0_DATA5 R5F9 . 47 5%SLOT0_R_DATA5 B16 A29
SD0_DATA5 SDVO_CTRLDATA SDVO_CTRLDATA 16
R5F10 .
SDIO / MMC
SLOT0_DATA6 47 5%SLOT0_R_DATA6 D16 AV48 SLPRDY# SLPMODE XBT5H1

SD0_DATA6 SDVOB_CLK SDVO_CLK 16
SLOT0_DATA7 R5U30 . 47 5%SLOT0_R_DATA7 K20 AV50 0 1 SCH ready to enter S3 Battery_Holder
B . SD0_DATA7 SDVOB_CLK# SDVO_CLK# 16 B
25,56 SLOT1_CD# SDVOB_INT AU47 SDVO_INT 16
R5U7 . 47 5% B22 AU49 0 0 SCH ready to enter S4/S5
25,56 SLOT1_CLK SD1_CD# SDVOB_INT# SDVO_INT# 16
R5F3 . 47 5%SLOT1_R_CLK H22 AN45
25,56 SLOT1_CMD SDVO_STALL 16
3
. SLOT1_R_CMD SD1_CLK SDVOB_STALL
25,56 SLOT1_LED F20 SD1_CMD SDVOB_STALL# AN43 SDVO_STALL# 16
A21 AP48
SDVO
25,56 SLOT1_WP . SD1_LED SDVOB_TVCLKIN SDVO_TVCLKIN 16

25,56 SD1PWR# B20 SD1_WP SDVOB_TVCLKIN# AP50 SDVO_TVCLKIN# 16
R5U12 . 221 1%SLOT1_R_DATA6 D20
25,56 SLOT1_DATA[7:0] SD1_PWR#
SLOT1_DATA0 R5F1 .
47 5%SLOT1_R_DATA0 F22 AM50
SD1_DATA0 SDVOB_RED SDVO_RED 16
SLOT1_DATA1 R5U19 47 5%SLOT1_R_DATA1 J19 AM48
SD1_DATA1 SDVOB_RED# SDVO_RED# 16
SLOT1_DATA2 R5U31 47 5%SLOT1_R_DATA2 K22 AT50
SD1_DATA2 SDVOB_GREEN SDVO_GREEN 16
SLOT1_DATA3 R5F2 47 5%SLOT1_R_DATA3 D22 AT48
. SD1_DATA3 SDVOB_GREEN# SDVO_GREEN# 16
25 SLOT2_CD# SDVOB_BLUE AR45 SDVO_BLUE 16
R5F15 . 47 5% K24 AR43
25 SLOT2_CLK SD2_CD# SDVOB_BLUE# SDVO_BLUE# 16
R5F12 . 47 5%SLOT2_R_CLK D26
25 SLOT2_CMD . SD2_CLK
SLOT2_R_CMD B24 AW45
25 SLOT2_LED SD2_CMD PCIE_RXN1 PCIE_RXN2_MINI_SLOT0 15
25 SLOT2_WP D24 SD2_LED PCIE_RXP1 AW43 PCIE_RXP2_MINI_SLOT0 15
. B26 BB48 PCIE_TXN2_SLOT0_C C6T1 0.1uF 10%
25,56 SD2PWR# SD2_WP PCIE_TXN1 PCIE_TXN2_MINI_SLOT0 15
R5U18 . 221 1%SLOT1_R_DATA7 A19 BB50 PCIE_TXP2_SLOT0_C C6T2 0.1uF 10%
25,57 SLOT2_DATA[7:0] SD2_PWR# PCIE_TXP1 PCIE_TXP2_MINI_SLOT0 15
SLOT2_DATA0 R5U6 .
47 5%SLOT2_R_DATA0 J23
SLOT2_DATA1 R5F11 47 5%SLOT2_R_DATA1 SD2_DATA0
A25 SD2_DATA1 PCIE_RXN2 BA43 PCIE_RXN2_MINI_SLOT1 14
SLOT2_DATA2 R5F14 47 5%SLOT2_R_DATA2 F26 BA45
SD2_DATA2 PCIE_RXP2 PCIE_RXP2_MINI_SLOT1 14
SLOT2_DATA3 R5F13 47 5%SLOT2_R_DATA3 A23 BE49 PCIE_TXN2_SLOT1_C C6D4 0.1uF 10%
SD2_DATA3 PCIE_TXN2 PCIE_TXN2_MINI_SLOT1 14
SLOT2_DATA4 R5U1 . 47 5%SLOT2_R_DATA4 F24 BD50 PCIE_TXP2_SLOT1_C C6D5 0.1uF 10%
SD2_DATA4 PCIE_TXP2 PCIE_TXP2_MINI_SLOT1 14
SLOT2_DATA5 R5U2 . 47 5%SLOT2_R_DATA5 H24
PCIE
SLOT2_DATA6 R5T7 . 47 5%SLOT2_R_DATA6 SD2_DATA5

H26 SD2_DATA6 PCIE_CLKINN AY48 CLK_PCIE_IN# 24
SLOT2_DATA7 R5U32 . 47 5%SLOT2_R_DATA7 E25 AY50
. SD2_DATA7 PCIE_CLKINP CLK_PCIE_IN 24
. BA47 +V1.5S_PCIE_SCH 10,11,48,56
25,56 SLOT1_DATA[7:0] PCIE_ICOMPI
SLOT1_DATA4 R5U9 . 47 5%SLOT1_R_DATA4 G21 BA49 PEG_COMP R6T3 24.9
. RESERVED18 PCIE_ICOMPO 1%
SLOT1_DATA5 R5U10 47 5%SLOT1_R_DATA5 Route PEG_COMP less than
NO_STUFF POULSBO_1.03 D76284-004 --> E11512-002 250 milliohm trace
A SLOT1_DATA6 R5F4 . 47 5%SLOT1_R_DATA6 impedance. Crown Beach A
SLOT1_DATA7 R5F7
NO_STUFF
47 5%SLOT1_R_DATA7
Intel Confidential
NO_STUFF Title
Test Only - Poulsbo (2 of 8)
Poulsbo SCH pin G21 should be left NC on production designs

A 1.5

5 4 3 2 1
5 4 3 2 1
+V1.05S_VTT_SCH 6,11,56
+V3.3S 5..7,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
U5E1C
15 USB_PN0 AE47 USB_DN0
AE49 R7J2
15 USB_PP0 USB_DP0 10K
AD48 MFG-TEST-JUMPER
32 USB_PN1 USB_DN1 5%
32 USB_PP1 AD50 USB_DP1 .
AB50 J7J2 J6J3
32 USB_PN2 USB_DN2
AB48 AW13 1 FWH_MFG_MODE 3 DEFAULT [1-2]
32 USB_PP2 USB_DP2 VTT_1
32 USB_PN3 AA49 USB_DN3 VTT_2 AV12 2 2
32 USB_PP3 AA47 USB_DP3 VTT_3 AU13 1
Y48 AT12 NO_STUFF
32 USB_PN4 USB_DN4 VTT_4
D 32 USB_PP4 Y50 USB_DP4 VTT_5 AR13 CON3_HDR D
14 USB_PN5 V50 USB_DN5 VTT_6 AP12
14 USB_PP5 V48 USB_DP5 VTT_7 AN13
USB I/F
23 USB_PN6 U47 USB_DN6 VTT_8 AM12
23 USB_PP6 U49 USB_DP6 VTT_9 AL13
23 USB_PN7 T50 USB_DN7 VTT_10 AK12
23 USB_PP7 T48 USB_DP7 VTT_11 AJ13
Termination Voltage
VTT_12 AH12
32 USB_OC#0 R43 USB_OC0# VTT_13 AG13
32 USB_OC#1 W45 USB_OC1# VTT_14 AF12
32 USB_OC#2 R45 USB_OC2# VTT_15 AE13
32 USB_OC#3 U43 USB_OC3# VTT_17 AC13
32 USB_OC#4 AA45 USB_OC4# VTT_18 AB12
23 USB_OC#5 AA43 USB_OC5# VTT_19 AA13
23 USB_OC#6 W43 USB_OC6# VTT_20 Y12
23 USB_OC#7 U45 USB_OC7# VTT_21 W13
VTT_22 V12
AC45 USB_RBIASN VTT_23 U13
USB_RBIAS_PN AC43 T12
LAYOUT NOTE: Place USB_RBIASP VTT_24
VTT_25 R13
R(RBIAS) within 500 mils of R6T11 J43 P12
31 IDE_PDDREQ PATA_DDREQ VTT_26
SCH. Route this trace 22.6 D46 N13
31 IDE_PDIORDY PATA_IORDY VTT_27
microstrip, 4 mils wide and 6 1% G45 M14
31 INT_IRQ14 PATA_IDEIRQ VTT_28
mils from other signals 31 IDE_PDDACK# B46 M12
PATA_DDACK# VTT_29
31 IDE_PDIOW# A37 PATA_DIOW# VTT_16 AD12
31 IDE_PDIOR# F44 PATA_DIOR#
31 IDE_PDCS3# C47 PATA_DCS3#
31 IDE_PDCS1# E47 PATA_DCS1# PLACE XDP (TDO AND TCK ONLY)RESISTORS CLOSE TO POULSBO
31 IDE_PDA[2:0]
IDE_PDA2 K42
IDE_PDA1 PATA_DA2
J45 PATA_DA1 XDP_TRST# 3,29
IDE_PDA0 H40 +V1.05S_SCH 11,12,33
C PATA_DA0 C
PATA/IDE
31 IDE_PDD[15:0] XDP_TMS 3,29
IDE_PDD15 B40
IDE_PDD14 PATA_DD15
E43 PATA_DD14 XDP_TDI_SCH 29
IDE_PDD13 H42
IDE_PDD12 PATA_DD13 R6T17 R6T20 R6T18 C6T16 C6T15
D42 PATA_DD12 XDP_TDO 29
IDE_PDD11 F40 56 56 56 0.1uF 0.1uF
IDE_PDD10 PATA_DD11 5% 5% 5% 10% 10%
A43 PATA_DD10 XDP_TCK_1 29 . . .
IDE_PDD9 A41 N49 . .
IDE_PDD8 PATA_DD9 TRST#
J41 PATA_DD8 TMS M50
IDE_PDD7 R5U48 0 IDE_R_PDD7 A39 K48
JTAG
IDE_PDD6 PATA_DD7 TDI
B42 PATA_DD6 TDO M48
IDE_PDD5 F42 N47
IDE_PDD4 PATA_DD5 TCK
D44 PATA_DD4
IDE_PDD3 L41
IDE_PDD2 PATA_DD3 R6T19
B44 PATA_DD2 STPCPU# H30 PM_STPCPU# 21,24
IDE_PDD1 G43 56
IDE_PDD0 PATA_DD1 PM_RSTRDY#_R R6T21 100 5%
D40 PATA_DD0 RSTRDY# H50 PM_RSTRDY# 26,28 .
RESET# BA41 RST# 16,21,22,26,27,49,50
RSTWARN K50 PM_RSTWARN 26,28
U41 +V3.3 11,12,14,15,21..23,26,32,37,40,45,46
GPIOSUS0 IDE_PATADET 31
SYSTEM GPIOs
GPIOSUS1 N43 L_BKLTSEL0_GPIO# 17
N45 5..7,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S
GPIOSUS2 PM_PWRBTN# 26,28
R41 R6T14
GPIOSUS3 SCH_GPIOSUS_3 32
1K
WAKE# N41 PCIE_WAKE# 14,22
B30 R6F3
SMI# SMC_EXTSMI# 26,28
THRMB F32 PM_THRM# 5,26 1 2 10K
P50 J7H2 1-X NO_STUFF
GPE# SMC_RUNTIME_SCI# 26,28
J7H2. (Default)
5%
GPIO0 G29 SCH_GPIO_0 56 CRB_DET# 26
K30 CRB_DET#
GPIO1 FWH_MFG_MODE
GPIO2 F34
B G33 SCH_GPIO_3 17,56
+V3.3S 5..7,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 B
GPIO3
GPIO4 K36 FWH_WP# 20
H36 R6F4
GPIO5 FWH_TBL# 20
GPIO6 F36 SCH_GPIO_6 58 1K
No-Connect
+V3.3S 5..7,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 J31

GPIO7 SLPIOVR# 29,43
H34 SCH_GPIO_8
GPIO8 R2E11 R2E10
GPIO9 K28 L_BKLTSEL1# 17 10K 10K
R7V1 +V3.3 11,12,14,15,21..23,26,32,37,40,45,46 R7V4 5% 5%
SPKR J35 HDA_SPKR 21 . .
2.2K 2.2K K14
HDA_CLK HDA_BITCLK 21
HD AUDIO
HDA_SYNC E13 HDA_SYNC 21

A13 3
SCH_GPIO8_GATE
HDA_RST# HDA_RST# 21
HDA_SDI0 F14 HDA_SDATAIN0 21
R7G10 R7V2 R7V3 B14 Q2E1 1 SCH_GPIO8_N
10K 10K 10K HDA_SDI1 HDA_SDATAIN1 21 2N3904
HDA_SDO D14 HDA_SDATAOUT 21
HDA_DOCKEN# E15 HDA_DOCK_EN# 21 3
+V1.5S 4..6,11,14,21,24,38 2
HDA_DOCKRST# H14 HDA_DOCK_RST# 21
Q2E2 1 R2E12
H_PROCHOT# 3,41,48,50
AU43 DB_PLLMON1# R6T2 60.4 1% 2N3904 1K
12,14,15,21,23,30,32,36,37,44,45 +V5 RESERVED6 DB_PLLMON1 R6T5 60.4 1%
RESERVED7 AU45
2
DA_REFCLKINN AL45 DREFCLK# 24
CLOCK I/F
U7V1 AL43
DA_REFCLKINP DREFCLK 24
U1_OE1# 1 8 AE45
OE1# VCC DB_REFCLKINNSSC DREFSSCLK# 24
SMB_CLK 2 7 AE43
1A OE2# DB_REFCLKINPSSC DREFSSCLK 24
14,22 SMB_CLK_PCIE 3 1B 2B 6 SMB_DATA_PCIE 14,22 CLKREQ# B28 CLK_SCH_OE# 24
4 GND 2A 5 CLK14 H32 CLK_REF_SCH 24
SMB_DATA W41
74CBT3306 R6V9 USB_CLK48 CLK_USB48 24
SUSCLK J47 SUS_CLK 14,15,26,28,49
0 . +V3.3S 5..7,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
R5U21 10K
R7V5 K32 SMB_ALERT#
10K SMB_ALERT# 5%
A NO_STUFF SMB_DATA
SMB_CLK
G37
H38
.
SMB_DATA 18,21,24,27..29,50
Crown Beach A
Intel Confidential
SMB
SMB_CLK 18,21,24,27..29,50
Title
3
Q6V1
BSS138 Poulsbo (3 of 8)
1 POULSBO_1.03 D76284-004 --> E11512-002
27,28,40,45,46 PM_SLP_S3#
. Size Document Number Rev
2
A 1.5

5 4 3 2 1
5 4 3 2 1
U5E1D
18 M_A_DQ[63:0]
M_A_DQ0 BG49 BC27
SM_DQ0 SM_BS0 M_A_BS0 18,19
M_A_DQ1 BG47 BE25
M_A_DQ2 BE45 BA35
M_A_DQ3 BC43
M_A_DQ4 SM_DQ3
BE47 SM_DQ4
M_A_DQ5 BC47
M_A_DQ6 SM_DQ5
BC45 SM_DQ6 SM_CK0 BG45 M_CLK_DDR0 18
D M_A_DQ7 BK44 SM_DQ7 SM_CK1 BE11 M_CLK_DDR1 18 D
M_A_DQ8 BK42
M_A_DQ9 SM_DQ8
BG41 SM_DQ9
M_A_DQ10 BK40 BJ45
SM_DQ10 SM_CK0# M_CLK_DDR#0 18
M_A_DQ11 BC41 BG11
SM_DQ11 SM_CK1# M_CLK_DDR#1 18
M_A_DQ12 BG43
M_A_DQ13 SM_DQ12
BJ43 SM_DQ13
M_A_DQ14 BJ39 BE39
SM_DQ14 SM_CKE0 M_CKE0 18,19
M_A_DQ15 BG39 BE37
SM_DQ15 SM_CKE1 M_CKE1 18,19
M_A_DQ16 BC39
M_A_DQ17 SM_DQ16
BK38 SM_DQ17
M_A_DQ18 BG37 SM_DQ18 M_A_DQS[7:0] 18
M_A_DQ19 BK36 BJ47 M_A_DQS0
M_A_DQ20 SM_DQ19 SM_DQS0 M_A_DQS1
BJ37 SM_DQ20 SM_DQS1 BJ41
M_A_DQ21 BG35 BC37 M_A_DQS2
BJ35 SM_DQ22 SM_DQS3 BK32
M_A_DQ23 BC35 BG27 M_A_DQS4
BK34 BE23
MEMORY
BG31 SM_DQ25 SM_DQS6 BK18
M_A_DQ26 BG33 BG13 M_A_DQS7
M_A_DQ27 SM_DQ26 SM_DQS7
BK30 SM_DQ27 M_A_A[14:0] 18,19
M_A_DQ28 BC33 BJ27 M_A_A0
M_A_DQ29 SM_DQ28 SM_MA0 M_A_A1
BJ33 SM_DQ29 SM_MA1 BA19
M_A_DQ30 BJ31 BA27 M_A_A2
BC31 SM_DQ31 SM_MA3 BA25
M_A_DQ32 BJ29 BE29 M_A_A4
BG29 SM_DQ33 SM_MA5 BC23
M_A_DQ34 BK28 BE31 M_A_A6
BC29 SM_DQ35 SM_MA7 BA31
M_A_DQ36 BE27 BA33 M_A_A8
SM_DQ36 SM_MA8
SYSTEM
M_A_DQ37 BK26 BA29 M_A_A9
BG25 SM_DQ38 SM_MA10 BE17
C M_A_DQ39 BJ25 SM_DQ39 SM_MA11 BE35 M_A_A11 C
M_A_DQ40 BC25 BE33 M_A_A12
BG23 SM_DQ41 SM_MA13 BE19
M_A_DQ42 BK22 BA37 M_A_A14
M_A_DQ43 SM_DQ42 SM_MA14 +V0.9S 18,19,36
BJ21 SM_DQ43
M_A_DQ44 BK24 BE43
SM_DQ44 SM_VREF M_VREF_SCH 37,48
M_A_DQ45 BJ23
M_A_DQ46 SM_DQ45 LAYOUT NOTE: Min 10mil
BG21 SM_DQ46 SM_RAS# BE21 M_A_RAS# 18,19
M_A_DQ47 BC21 BA13 trace, place R5T1 as close
SM_DQ47 SM_CAS# M_A_CAS# 18,19
M_A_DQ48 BK20 to pin SM_RCOMPOUT as
M_A_DQ49 SM_DQ48 possible R5T1
BJ19 SM_DQ49 SM_WE# BA17 M_A_WE# 18,19
DDR
M_A_DQ50 BG17 30.1 C5T1
M_A_DQ51 SM_DQ50 1% 0.1uF
BJ17 SM_DQ51 SM_CS0# BA23 M_CS#0 18,19
M_A_DQ52 BG19 BA15 10%
SM_DQ52 SM_CS1# M_CS#1 18,19
M_A_DQ53 BC19 NO_STUFF
M_A_DQ54 SM_DQ53 SM_RCOMPOUT
BC17 SM_DQ54 SM_RCOMPO BE13
M_A_DQ55 BK16
M_A_DQ56 SM_DQ55 MA_RCVENIN
BG15 SM_DQ56 SM_RCVENIN BA39
M_A_DQ57 BC15 BE41 MA_RCVENOUT
M_A_DQ58 SM_DQ57 SM_RCVENOUT R5T2
BJ13 SM_DQ58
M_A_DQ59 BK12 0
M_A_DQ60 SM_DQ59
BK14 SM_DQ60
M_A_DQ61 BJ15
M_A_DQ62 SM_DQ61
BC13 SM_DQ62
M_A_DQ63 BC11 SM_DQ63
POULSBO_1.03 Note: Place R5T2 within 1" of the SCH pins
D76284-004 --> E11512-002
B B
A Crown Beach A
Intel Confidential
Title
Poulsbo (4 of 8)

A 1.5

5 4 3 2 1
A
B
C
D
11,29,33,48,56
11,56 +V1.5S_DLVDS_SCH
11,56 +V1.5S_SDVO_SCH
7,11,48,56 +V1.5S_PCIE_SCH
11,48,56
5
5
+V1.05S_SCH_VCORE
+V1.8_SM_SCH
AT36
AT38
AT32
AT34
AK38
AV38
AP36
AP38
AE37
AH36
AH38
AJ37
AK36
AU37
AN37
AR37
AD36
AL37
AF36
AF38
AG37
AM36
D76284-004 --> E11512-002

POULSBO_1.03
U5E1E
AP16 VCCSM_43
AW35 VCCSM_100 VCC_79 V22
AW33 V20
VCCPCIE_3
VCCPCIE_2
VCCPCIE_1
VCCPCIE_9
VCCPCIE_8
VCCPCIE_7
VCCPCIE_6
VCCPCIE_5
VCCPCIE_4
VCCSM_101 VCC_80
VCCLVDS_3
VCCLVDS_2
VCCLVDS_1
AW31 VCCSM_102 VCC_81 V18
VCCPCIE_101
VCCPCIE_100
VCCLVDS_100
VCCLVDS_101
VCCSDVO_105
VCCSDVO_106
VCCSDVO_103
VCCSDVO_101
VCCSDVO_100
VCCSDVO_110
AW29 VCCSM_103 VCC_63 AB18
AW27 VCCSM_104 VCC_64 AB16
AW25 VCCSM_105 VCC_65 Y30
AW17 VCCSM_1 VCC_10 T34
AV36 VCCSM_2 VCC_9 T32
AV18 VCCSM_24 VCC_11 AK22
AV16 VCCSM_25 VCC_12 AK20
AT30 AK18
4
4
VCCSM_26 VCC_13
AT28 VCCSM_27 VCC_14 AK16
AT26 VCCSM_28 VCC_15 AH34
AT24 AH32
TEST ONLY -
VCCSM_29 VCC_16
Should be left NC
11
12
AP34 VCCSM_34 VCC_21 AH22
AP26 VCCSM_38 VCC_25 AF34
+V1.05_SUSBYP_SCH
VCC_30 AF24
N37 VCCSUSBYP_1 VCC_31 AF22
N35 AF20
+V3.3_SCH_SUS
VCCSUSBYP_2 VCC_32
AC37 AF18
+V1.05_SUSUSBBYP_SCH
VCCSUSUSBBYP_1 VCC_33
AB36 VCCSUSUSBBYP_2 VCC_34 AF16
Y38 AD30
VCC
VCCP33USBSUS_2 VCC_35
AA39 VCCP33USBSUS_1 VCC_36 AD28
W39 VCCP33USBSUS_3 VCC_37 AD26
T38 VCC33SUS_3 VCC_38 AD24
U37 VCC33SUS_2 VCC_39 AD22
R39 VCC33SUS_1 VCC_40 AD20
12
12
VCC_41 AD18
7,12
M18 AD16
11,21
VCC33_15 VCC_42
M20 AB30
11,12,48
VCC33_14 VCC_43
M22 VCC33_13 VCC_44 AB28
M24 VCC33_12 VCC_45 AB26
M26 VCC33_11 VCC_46 AB24
M28 VCC33_10 VCC_47 AB22
3
3
M30 VCC33_9 VCC_48 AB20

N19 VCC33_6 VCC_49 AM34
N15 VCC33_8 VCC_50 AM32
+VCCHDA
+V3.3A_RTC N17 VCC33_7 VCC_51 AM30
+V3.3S_SCH
N21 VCC33_5 VCC_52 AM28

N23 VCC33_4 VCC_53 AM26
N25 AM24
+V1.5S_HPLL_SCH
VCC33_3 VCC_54
N27 VCC33_2 VCC_55 AM22
N29 AM20
+V1.5S_AUSBPLL_SCH
VCC33_1 VCC_56
M16 VCC33_16 VCC_57 AM18
A45 VCC33RTC VCC_58 AM16
K12 VCCHDA_1 VCC_59 AK34
J11 VCCHDA_2 VCC_60 AK32
AC39 VCCAUSBPLL VCC_61 AK30
BB10 VCCDHPLL VCC_62 AK28
BA11 VCCAHPLL VCC_120 AK26
VCC_121 AK24
AC41 VSSAUSBBGSUS VCC_82 V16
AE41 VCCAUSBBGSUS VCC_71 Y18
VCC_72 Y16
VCC_73 V34
AE39 VCCADPLLA VCC_74 V32
AN49 VCCAPCIEPLL VCC_75 V30
AG39 V28
Title
Size
VCCADPLLB VCC_76
K34 V26
Date:
VCC5REF_1 VCC_77
V24
Custom
VCC_78
GND_VSSAUSBBGSUS
AA41 VCC5REFSUS VCC_70 Y20

RESERVED9
VCC15_9
VCC15_8
VCC15_7
VCC15_6
VCC15_5
VCC15_4
VCC15_3
VCC15_2
VCC15_1
RESERVED13
RESERVED11
RESERVED12
RESERVED10
VSSAPCIEBG
VCCAPCIEBG
VCC15_18
VCC15_17
VCC15_16
VCC15_15
VCC15_14
VCC15_13
VCC15_12
VCC15_11
VCC15_10
VCC15USB_6
VCC15USB_5
VCC15USB_4
VCC15USB_3
VCC15USB_2
VCC15USB_1
Y32
Y34
P36
P38
P32
P34
N31
N33
R15
R17
R19
R21
R23
R25
R27
R29
R31
R33
M32
M34
M36
M38
W37
AY42
AA37
AB38
AB32
AB34
AD32
AD34
AW41
+V3.3_SCH_SUS
2
2
+V5S_5REF_SCH
+V1.5S_DPLLA_SCH
+V1.5S_PCIEPLL_SCH
+V5_5REFSUS_SCH
+V1.5S_DPLLB_SCH
Crown Beach
11
12
12
12
12
12
Document Number
SH5T2
GND_VSSAUSBBGSUS
+V1.5S_SCH
+V1.5S_SCH
Poulsbo (5 of 8) VCC-PWR
GND_VSSAPCIEBG
+V3.3S_APCIEBG_SCH
+V1.5_SUSBYP_SCH
+V1.5USBSUSBYP_SCH
Tuesday, November 20, 2007

11,12,38,56
11,12,38,56
12
12
SH5T1
Sheet
GND_VSSAPCIEBG
TEST ONLY -
TEST ONLY -
Should be left NC
Should be left NC
10
1
1
of
for each pin and then connect
them straight to pcb gnd plane
Layout Note: Use dedicated via
64
Rev
Intel Confidential
1.5
A
B
C
D
5 4 3 2 1
All decoupling should be placed on the backside 10,29,33,48,56 +V1.05S_SCH_VCORE

8,12,33 +V1.05S_SCH
R6T7
0.01_1%
1
C6T7 C6T8 SMR1206 C5T41 C5T31 C5T32 C5T67 C5T52 C5T64 C5T40 C5T74 C5T29 C5T42 C5T30 C5T27 C5T39 C5T53 C5T51 C5T66 C6T9 C6T10 C5T33 C5T34 C6T14 C6T13 C6T11 C6T12 C5T38 C5T65
4.7uF 270uF 0.1uF 0.1uF 0.1uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 2.2uF 2.2uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF PH0201 PH0201
10% 20% 10% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 10% 10%
.
2
. . . . NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF . NO_STUFF NO_STUFF NO_STUFF NO_STUFF . . . . NO_STUFF NO_STUFF
SMC0603 SMC7343 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 0603 0603 0603 0603 SMC0805 SMC0805 SMC0805 SMC0805
D D
24,33,34 +V1.05S_VTT 6,8,56 +V1.05S_VTT_SCH
R5U35
0.01_1%
C5U8 C5U11 SMR1206 C5T36 C5T71 C5T56 C5T28 C5T47 C5T26 C5T63 C5T62 C5T50 C5T43 C5T37 C5T70 C5T78 C5T35 C5T24 C5T54 C5U7 C5U2 C5U4 C5U6
4.7uF 270uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 10uF 10uF 10uF 10uF
10% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
.
. NO_STUFF . NO_STUFF NO_STUFF . . NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF . NO_STUFF .
SMC0603 SMC7343 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0805 SMC0805 SMC0805 SMC0805
4..6,8,14,21,24,38 +V1.5S 10,12,38,56 +V1.5S_SCH

R5T6
C5U1 0.01 1%
4.7uF SMR0805
. C5T80 C5T72 C5T81 C5T57 C5T86 C5T79 C5T85
10% 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 24,33,34 +V1.05S_VTT +V1.05S_VTT_CPU 3,4,29,33,43,48,50
. 20% 20% 20% 20% 20% 20% 20%
SMC0603 . . . . . . . R3U1
SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402
1
.01 1% C3T17 C3T19 C2T1 C3T16 C2T3 C3T1 Place these inside socket
SMR2010 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF cavity on L8 ( North side
10,12,38,56 +V1.5S_SCH +V1.5S_PCIE_SCH 7,10,48,56 10% 10% .10% .10% .10% .10% Secondary)
2
R6T6 SMC0402
. SMC0402
.
0.01 1%
C SMR0805
. C5T25 C5T19 LAYOUT NOTE: PLACE CAPS NEXT C
1.0uF 1.0uF TO CPU PINS AG35 AND AG36
20% 20%
2
1
. .
SMC0402 SMC0402 J4F5
2X2HDR
2x2 PME header
4
3
.
10,12,38,56 +V1.5S_SCH +V1.5S_DLVDS_SCH 10,56

R6T9
0.01 1% C5T55 C5T48

SMR0805
. 1.0uF 1.0uF
20% 20% 8,12,14,15,21..23,26,32,37,40,45,46 +V3.3
. .
SMC0402 SMC0402 +V3.3_SCH_SUS 10
R6T13
10,12,38,56 +V1.5S_SCH +V1.5S_SDVO_SCH 10,56

R6T10 0.01 1%
SMR0805
.
10V C5T59 10V C5T60 10V C5T61 C5T58 10V C5T69
0.01 1% 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
SMR0805
. 10% 10% 10% 10% 10%
C5T44 C5T45 . . . . NO_STUFF
1.0uF 1.0uF SMC0402 SMC0402 SMC0402 SMC0402 SMC0402
B 20% 20% B
. . GND_VSSAUSBBGSUS
SMC0402 SMC0402
GND_VSSAUSBBGSUS
+V1.8_SM_SCH 10,48,56
18,36,37 +V1.8
R5T3
0.01 1%
C6T3 SMR0805
. C5T12 C5T23 C5T5 C5T21 C5T20 C5T15 C5T11 C5T9 C5T10 C5T22 C5T7 C5T18 C5T13 C5T6 C5T17 C5T16 C5T8
4.7uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF
10% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
. NO_STUFF NO_STUFF NO_STUFF . . NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF . NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
SMC0603 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402 SMC0402
+V3.3S 5..8,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
+VCCHDA 10,21
+V3.3S_SCH 10,12,48
R5T5
0.01 1%
C5T92 SMR0805
. C5T84 C5T87 C5T88 C5T90
4.7uF 1.0uF 1.0uF 1.0uF 1.0uF C5U3 C5T91
10% 20% 20% 20% 20% 1.0uF 1.0uF
. 20% 20%
SMC0603 SMC0402 SMC0402 SMC0402 SMC0402 . .
SMC0402 SMC0402
A Crown Beach A
Intel Confidential
Title
Poulsbo (6 of 8) SCH Decoupling

A 1.5

5 4 3 2 1
5 4 3 2 1
+V1.5S_DPLLA_SCH 10
L6T2
1 2
10uH 10%
1
C6T4 C6T6
470uF 0.1uF 37 +V1.05_SUS
.20% 10%
2
. +V1.05_SUSBYP_SCH 10
R6T16 0
+V1.5S_DPLLB_SCH 10 NO_STUFF C5T83 C5T82 C5T89

D L7E1 1.0uF 1.0uF 10uF D
1 2 20% 20% 20%
10uH 10% .402 .SMC0402 .
1
C6D3 C6T5
V1.5S_PLLS_SCH
470uF 0.1uF
.20% 10% 37 +V1.5_SUS
2
.
+V1.5_SUSBYP_SCH 10
10,11,38,56 +V1.5S_SCH R6T15 0
+V1.5S_PCIEPLL_SCH 10
R6T1 NO_STUFF
L6T1
1 2 C5T77 C5T76 C5T73
0.01 1% 1uH 20% 1.0uF 1.0uF 10uF
SMR0805
. C6R2 C5T14 20% 20% 20%
10uF 0.1uF .402 .402 .
20% 10%
. .
R6R4
0.5
1%
+V1.5S_HPLL_SCH 10
FB5T1
1 2
120ohm@100MHz C5T2 C5T4 AHPLL AND DHPLL CONNECTED TOGETHER

22uF 0.1uF 10,11,48 +V3.3S_SCH +V3.3S_APCIEBG_SCH 10
20% 10%
. .
C C
R6T4 0
+V1.5S_AUSBPLL_SCH 10 C5T3
0.1uF
R6T8 0 10%
.
PLACE BOTTOM SIDE OF PCB UNDER SCH C5T49
0.1uF
10% LAYOUT NOTE: Please
. place C5T49 near pin GND_VSSAPCIEBG
VCCA_USBPLL OF Poulsbo
5..8,11,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S
+V5 8,14,15,21,23,30,32,36,37,44,45 5,17,31,33..35,40,41,44,45 +V5S

+V5S_5REF_SCH 10
+V3.3 8,11,14,15,21..23,26,32,37,40,45,46
1
+V3.3S 5..8,11,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 1 +V5_5REFSUS_SCH 10
PLACE BOTTOM SIDE OF PCB UNDER SCH R5U3 CR5T1
R7U1 CR6F1 10 BAT54
+V3.3A_RTC 7,10 10 BAT54 5%
5% .
. 3
3
C5T93
R5H2 R5H5 C7U1 0.1uF
10K 10K 0.1uF 10% 10V
. . 10% 10V .
B . B
RESERVED1 7
RESERVED0 7
R5H1 R5H4 LPC_CLKOUT[0] Drive Strength

10K 10K
NO_STUFF NO_STUFF RESERVED1 RESERVED0 Value
0 0 Reserved
0 1 1 Load (Default)
1 0 Reserved
1 1 2 Loads
+V1.05S_SCH 8,11,33
NOTE: RESERVED0 has an integrated pull-up
and should be left NC
+V1.05S_SCH 8,11,33 R2 R1
100 100
5% 5%
. .
J7F2 J6F1
1 3
2 SCH_BSEL1_R R6F6 10K 2
SCH_BSEL1 6 SCH_BSEL0 6
3 CK_FSC_Q_SEL 1
R3 3
CON3_HDR CON3_HDR R6F5
CK_FSC_Q 1 Q1 10K
50 CK_FSC_CLK_RMUX
DEFAULT [2-3] 2N3904 DEFAULT [1-2]
1K 5%
A Graphics Core Frequency Select
.
2 Crown Beach A
FSB SCH_BSEL1 SCH_BSEL0 Gfx_Freq
Intel Confidential
100 0 0 200 Title
100 0 1 RESERVED
100 1 0 RESERVED Poulsbo (7 of 8) SCH-Pu/Pd
100 1 1 RESERVED
133 0 0 RESERVED
133 0 1 200
133 1 0 RESERVED Size Document Number Rev
133 1 1
Note: Clock Frequencies are in Mhz
RESERVED
A 1.5
Default Frequency determined by FSB speed
Position 1-2 = 1 Position 2-3 = 0
5 4 3 2 1
5 4 3 2 1
U5E1F
BH30 VSS_1 VSS_76 BB24

BH28 VSS_2 VSS_77 BB22
BH26 VSS_3 VSS_84 BA7
BH20 VSS_6 VSS_87 AY46
AG49
AG47
AG41
AG35
AG33
AG31
AG29
AG27
AG25
AG23
AG21
AG19
AG17
AG15
AG11
AH46
AH44
AH42
AH40
AH14
AD46
AD44
AD42
AD40
AD38
AD14
AC49
AC47
AC35
AC33
AC31
AC29
AC27
AC25
AC23
AC21
AC19
AC17
AC15
AC11
AE35
AE33
AE31
AE29
AE27
AE25
AE23
AE21
AE19
AE17
AE15
AE11
AB46
AB44
AB42
AB40
AB14
AA35
AA33
AA31
AA29
AA27
AA25
AA23
AA21
AF46
AF44
AF42
AF40
AF14
BH18 AY44
AG9
AG7
AG5
AG3
AC9
AC7
AC5
AC3
AE9
AE7
AE5
AE3
AJ3
VSS_7 VSS_88
BH16 VSS_8 VSS_89 AY40
BH14 AY38 U5E1G
VSS_9 VSS_90
D BH12 AY36 W35 BH34 D
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_10 VSS_91 VSS_293 VSS_1023
BH2 VSS_11 VSS_92 AY34 W33 VSS_294 VSS_263 AA19
BG9 VSS_12 VSS_93 AY32 W31 VSS_295 VSS_264 AA17
BF50 VSS_17 VSS_98 AY22 W21 VSS_300 VSS_269 AA5
BF48 VSS_18 VSS_99 AY20 W19 VSS_301 VSS_270 AA3
BF46 VSS_19 VSS_100 AY18 W17 VSS_302 VSS_271 Y46
BF38 VSS_23 VSS_104 AW49 W7 VSS_306 VSS_275 Y36
BF36 VSS_24 VSS_105 AW47 W5 VSS_307 VSS_276 Y14
BF34 VSS_25 VSS_106 AW39 W3 VSS_308 VSS_277 W49
BF32 VSS_26 VSS_107 AW15 V46 VSS_309 VSS_278 W47
BF30 VSS_27 VSS_108 AW11 V44 VSS_310 VSS_292 N9
BF28 VSS_28 VSS_109 AW9 V42 VSS_311 VSS_291 N7
BF26 VSS_29 VSS_110 AW7 AJ41 VSS_163 VSS_290 N5
BF24 VSS_30 VSS_111 AW5 AJ47 VSS_162 VSS_289 N3
BF22 VSS_31 VSS_112 AW3 AJ49 VSS_161 VSS_288 M46
BF20 VSS_32 VSS_113 AV46 AK14 VSS_160 VSS_287 M44
BF14 VSS_35 VSS_116 AV40 AJ5 VSS_179 VSS_284 L49
BF12 VSS_36 VSS_117 AV14 AJ7 VSS_178 VSS_283 L47
BE9 VSS_37 VSS_118 AU41 AJ9 VSS_177 VSS_282 L37
BD48 AU31 AJ19 L29
C BD46
BD44
VSS_41
VSS_42
VSS_43
VSS_122
VSS_123
VSS_124
AU29
AU27
AJ21
AJ23
VSS_173
VSS_172
VSS_171
VSS VSS_312
VSS_313
VSS_314
L27
L25
C
BD42 AU25 AJ25 L23
BD40
BD38
VSS_44
VSS_45
VSS_46
VSS VSS_125
VSS_126
VSS_127
AU23
AU21
AJ27
AJ29
VSS_170
VSS_169
VSS_168
VSS_315
VSS_316
VSS_317
L21
L19
BD36 VSS_47 VSS_128 AU19 AJ31 VSS_167 VSS_318 L17
BD28 VSS_51 VSS_132 AU9 L9 VSS_323 VSS_343 G19
BD20 VSS_55 VSS_136 AT46 K46 VSS_327 VSS_347 G9
BD18 VSS_56 VSS_137 AT44 K44 VSS_328 VSS_348 G7
BD16 VSS_57 VSS_138 AT42 J37 VSS_329 VSS_349 G5
BD14 VSS_58 VSS_139 AT40 J33 VSS_330 VSS_158 AK42
BD12 VSS_59 VSS_140 AT14 J29 VSS_331 VSS_404 E21
BC49 VSS_60 VSS_141 AR49 J25 VSS_332 VSS_403 E23
BC9 VSS_61 VSS_142 AR47 J21 VSS_333 VSS_383 E27
BC7 VSS_62 VSS_143 AR41 U27 VSS_709 VSS_378 E29
BC5 VSS_63 VSS_144 AR39 U25 VSS_710 VSS_379 E31
BC3 VSS_64 VSS_145 AR35 G47 VSS_335 VSS_380 E33
BB46 VSS_65 VSS_146 AR33 G41 VSS_336 VSS_381 E35
BB38 VSS_69 VSS_150 AR25 G27 VSS_340 VSS_882 A49
BB36 VSS_70 VSS_151 AR23 G25 VSS_341 VSS_881 B2
BB34 VSS_71 VSS_152 AR21 G23 VSS_342 VSS_1003 A15
BB32 VSS_72 VSS_153 AR19 C19 VSS_504 VSS_1000 A5
BB30 VSS_73 VSS_154 AR17 C17 VSS_503 VSS_1001 A3
B BB28 AR15 C15 BK48 B
VSS_74 VSS_155 VSS_502 VSS_1004
BB26 VSS_75 VSS_156 AR11 C13 VSS_501 VSS_1005 BK46
BA9 VSS_83 VSS_384 AR9 G3 VSS_505 VSS_1006 BK4
BB12 VSS_82 VSS_385 AR7 E45 VSS_506 VSS_1007 BK2
BB14 VSS_81 VSS_386 AR5 BJ1 VSS_1014 VSS_1008 BJ49
BB16 VSS_80 VSS_387 AR3 BH50 VSS_1015 VSS_1009 BJ11
BB18 VSS_79 VSS_388 AP46 BH48 VSS_1016 VSS_1010 BJ9
BB20 VSS_78 VSS_389 AP44 BH46 VSS_1017 VSS_1011 BJ7
AM44 VSS_420 VSS_390 AP42 BH44 VSS_1018 VSS_1012 BJ5
AM42 VSS_421 VSS_391 AP40 BH42 VSS_1019 VSS_1013 BJ3
AM40 VSS_422 VSS_392 AP14
VSS_1022
VSS_1024
VSS_1021
VSS_1020
AM38 AN47
VSS_701
VSS_702
VSS_703
VSS_704
VSS_705
VSS_706
VSS_707
VSS_708
VSS_736
VSS_737
VSS_738
VSS_800
VSS_801
VSS_802
VSS_803
VSS_804
VSS_805
VSS_806
VSS_807
VSS_711
VSS_712
VSS_713
VSS_714
VSS_715
VSS_716
VSS_717
VSS_718
VSS_719
VSS_720
VSS_721
VSS_722
VSS_723
VSS_724
VSS_725
VSS_726
VSS_727
VSS_728
VSS_729
VSS_730
VSS_731
VSS_733
VSS_734
VSS_735
VSS_732
VSS_850
VSS_851
VSS_852
VSS_853
VSS_854
VSS_751
VSS_750
VSS_749
VSS_748
VSS_747
VSS_746
VSS_745
VSS_744
VSS_743
VSS_742
VSS_741
VSS_740
VSS_739
VSS_700
VSS_855
VSS_856
VSS_857
VSS_858
VSS_859
VSS_860
VSS_861
VSS_862
VSS_863
VSS_864
VSS_865
VSS_866
VSS_867
VSS_868
VSS_869
VSS_870
VSS_871
VSS_872
VSS_873
VSS_874
VSS_875
VSS_876
VSS_877
VSS_878
VSS_879
VSS_880
VSS_883
VSS_423 VSS_393
AM14 VSS_424 VSS_394 AN41
AM10 AN39 POULSBO_1.03
VSS_425 VSS_395 D76284-004 --> E11512-002
AL49 VSS_426 VSS_396 AN35
AL41 AN31
BH36
V38
V36
V14
U39
U35
U33
U31
U29
P48
P46
P44
J17
J13
J7
J5
J3
H46
H44
G49
U23
U21
U19
U17
U15
U11
U9
U7
U5
U3
T46
T44
T42
T40
T36
T14
R49
R47
R37
R35
R11
R7
R5
R3
R9
E19
E17
E11
E9
E7
N11
N39
P14
P16
P18
P20
P22
P24
P26
P28
P30
P40
P42
V40
E5
E3
E1
D50
D48
C45
C43
C41
C39
C37
C35
C33
C31
C29
C27
C25
C23
C21
C11
C9
C7
C5
C3
C1
B50
B48
A47
BH32
BH38
BH40
VSS_521 VSS_398
AL9 VSS_415 VSS_413 AM46
A AK46
AL3
VSS_513
VSS_512
VSS_510
VSS_511
AL7
AL5 Crown Beach A
Intel Confidential
POULSBO_1.03 D76284-004 --> E11512-002 Title
Poulsbo (8 of 8) VSS-GND

A 1.5

5 4 3 2 1
5 4 3 2 1
+V5 8,12,15,21,23,30,32,36,37,44,45 +V1.5S 4..6,8,11,21,24,38
R7W9
J9G2 Default: 2-3
R7W16 0 5% Default: 2-3 J9F4 V1.5S_MINIPCIE
25 SLOT2_D3_MINI
NO_STUFF PIN11_MINIA Default: 1-2 1 GPS_UART_CTS 26
R7W13 0 5% J9G4 3 C7V3 C7V2 C7V1 C7W2 0.01 1% PIN28_MINIA 2
24 CLK_PCIE_MINICARDA#
. 2 PIN2_MINIA 0.1uF 22uF 0.1uF 0.1uF SMR0805
. 3 V1.5S_MINIPCIE
1 V3.3_MINIPCIE 1 20% 20% 20% 20%
26 WIFI_HOST_WAKE . . . .
2
3
8,22 PCIE_WAKE# R8Y6 0 5% J9G5
.
USIM_PWR 15 Default: 2-3
5..8,11,12,15..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
+V3.3S CONNECTOR A R7W15
.
R8W21
0 5%
0 5%
USIM_DATA 15
PIN48_MINIA 2
1 GPS_ON
V1.5S_MINIPCIE
26
USIM_CLK 15 3
C7W3 .
D R7W21
10K
Default: 2-3 10uF R8Y3 0 5%
USIM_RESET 15 D
J7H1 0603 .
5% J9F2 PIN1_MINIA 20% R8Y4 0 5%
. 1 WAKE# +3.3V_1 2
NO_STUFF PCM_DIN 15
25 SLOT2_D0_MINI 3 RSVD1 GND7 4
1 5 6 R7W14 0 5%
25 SLOT2_D2_MINI 25 SLOT2_D1_MINI RSVD2 +1.5V_1 PCM_DOUT 15 8,11,12,15,21..23,26,32,37,40,45,46 +V3.3
2 PIN7_MINIA 7 8 PIN8_MINIA NO_STUFF Default: 2-3 J9D4
CLKREQ# RSVD13 PIN10_MINIA R8W20 0 5%
3 9 GND1 RSVD14 10
24 CLKREQ_MINIPCIE# PIN11_MINIA PIN12_MINIA NO_STUFF PCM_CLK 15
11 REFCLK- RSVD15 12 1 EC_WIFI_PD# 26
R7W18 PIN13_MINIA 13 14 PIN14_MINIA R8Y5 0 5% 2
10K REFCLK+ RSVD16 NO_STUFF PCM_SYNC 15
5% 15 GND2 RSVD17 16 3 W_DISABLE# 15,26
MINICARDA_RSVD17 R7W10 0 5% R9F1
NO_STUFF KEY NO_STUFF SUS_CLK 8,15,26,28,49
0.01
GPS_TX# 17 18 J9E4 . 1%
GPS_RX# RSVD3 GND8 PIN20_MINIA SMR0805
19 RSVD4 RSVD18 20
WIFI_nINTR requested by Gopi 21 22 PIN22_MINIA R7W4 0 5% 1
GND3 PERST# BUF_RST# 15,20,26,27,31,46 PMU_3 15,26
PIN23_MINIA 23 24 PIN24_MINIA . 2
R7W11 0 5% PIN25_MINIA PER_N0 +3.3V_AUX V3.3_MINIPCIE
25 PER_P0 GND9 26 3
26 WIFI_nINTR NO_STUFF PIN28_MINIA
27 GND4 +1.5V_2 28
R7W12 0 5% 29 30 PIN30_MINIA Default: 2-3 C9F4 C9F5 C9F1 C9F2 C9F3
24 CLK_PCIE_MINICARDA GND5 SMB_CLK
. PIN31_MINIA 31 32 PIN32_MINIA 22uF 0.1uF 22uF 0.1uF 0.1uF
J9F3 PIN33_MINIA PET_N0 SMB_DATA 20% 20% 20% 20% 20%
33 PET_P0 GND10 34
Default: 2-3 35 36 USB_MINI_PN5
GND6 USB_D- USB_MINI_PP5
15,26 PMU_1 1 37 RSVD5 USB_D+ 38
2 PIN39_MINIA 39 40
V3.3_MINIPCIE PIN41_MINIA RSVD6 GND11 MINIA_42_LED#
3 41 RSVD7 LED_WWAN# 42
43 44 MINIA_44_LED#
BT_UART_RXD RSVD8 LED_WLAN# MINIA_46_LED# +V3.3S 5..8,11,12,15..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
45 RSVD9 LED_WPAN# 46
J9G1 BT_UART_RTS 47 48 PIN48_MINIA
BT_UART_CTS RSVD10 +1.5V_3
49 RSVD11 GND12 50
1 51 52 PIN52_MINIA
15,26 PMU_2 26 GPS_nINTR RSVD12 +3.3V_2
2 55 GNDM1 GNDM2 56
V3.3_MINIPCIE 3
2
C Default: 2-3 PCI-e_MINI_CARD C
C59768-002 Q7G2
PLACE NEAR SCH J8H1 1 SI2307DS
.
2
1 NC1 LATCH . Q7V1
3
R6E6 2 1 SI2307DS
USB_FP_PP5 23 NC2
2
0 NO_STUFF
R6E5 . USB_MINI_PP5 MINI_CARD_LATCH_LOTES Default: 2-3 . Q7V2
8 USB_PP5
3
0 D51601-001 1 SI2307DS
J9E1
R6E8 . USB_MINI_PN5 .
8 USB_PN5
3
0 1 PMU_4 15,26
R6E7 2 R7G8
USB_FP_PN5 23
0 NO_STUFF 3 V3.3_GPS 75 R7G7 R7G6
R7W6 75 75
GPS_RX#
R6D4 26 H8_SCIF_RXD 0 NO_STUFF
PCIE_TXP2_SLOT1 22 PP_MINIA_44_LED PP_MINIA_46_LED
0 NO_STUFF PP_MINIA_42_LED
.
R6D3 . PCIE_TXP2_MINI R7W7 V3.3_MINIPCIE GREEN GREEN GREEN
7 PCIE_TXP2_MINI_SLOT1
2
0 GPS_TX#
26 H8_SCIF_TXD
0 NO_STUFF L9E1 LED1 CR7G3 WLAN CR7G1 WPAN CR7G2
R6D1 . PCIE_TXN2_MINI 1 2
7 PCIE_TXN2_MINI_SLOT1
0 10uH 10%
1
R6D2 C9E2 C9E1
PCIE_TXN2_SLOT1 22
1
0 NO_STUFF PCIE_RXN2_MINI R7W3 0 5% 470uF 0.1uF
. PIN23_MINIA .20% 10%
2
R7W5 0 5% .
25 SLOT2_CLK_MINI
R6E4 NO_STUFF
0 NO_STUFF PCIE_RXP2_SLOT1 22
R6E3 . PCIE_RXP2_MINI PCIE_RXP2_MINI R7W2 0 5%
7 PCIE_RXP2_MINI_SLOT1 0 . PIN25_MINIA PCIE_TXN2_MINI R7V13 0 5% COM Port option
R7W1 0 5% . PIN31_MINIA
B 25 SLOT2_CMD_MINI B
R6E2 . PCIE_RXN2_MINI NO_STUFF R7V15 0 5% BT_UART_CTS R9H4 GPS_UART_CTS
7 PCIE_RXN2_MINI_SLOT1 26 WIFI_RESET#
0 NO_STUFF 0 .
R6E1 BT_UART_TXD R9H1 H8_SCIF_TXD
0 NO_STUFF PCIE_RXN2_SLOT1 22 PCIE_TXP2_MINI R7V11 0 5% 0 .
. PIN33_MINIA BT_UART_RTS R9H6 GPS_UART_RTS
PLACE NEAR SCH BT_UART_TXD R7V10 0 5% 0 .
NO_STUFF BT_UART_RXD R9J1 H8_SCIF_RXD
+V3.3 8,11,12,15,21..23,26,32,37,40,45,46 0 .
R8T15 H8_UART_RI
26,27 EC_THRM_DATA
0 5% C9J1
R8T16 . H8_UART_DSR 0.1uF C9J6
15,26 PMU_4 22UF
0 5% 20%
R8T17 . H8_UART_DCD . . J9G6
26,27 EC_THRM_CLK GND
0 5%
26
5
26 H8_PIN115 R8T18 . H8_UART_DTR U9J1 UART_RI_232 RI 9 RS232 bypass option
0 5% UART_DTR_232 DTR 4 Place near U6E4
VCC
. SERBUF_C1+ 28 27 SERBUF_V+ UART_CTS_232 CTS 8

C9J5 C1+ V+ C9J2 UART_TXD_232 TXD BT_UART_CTS R9H3 UART_CTS_232
3
0.1uF 0.1uF UART_RTS_232 RTS 7 0 NO_STUFF
10% SERBUF_C1- 24 10% UART_RXD_232 RXD 2 10 BT_UART_TXD R9H2 UART_TXD_232
. C1- . UART_DSR_232 DSR GND0 0 NO_STUFF
6
UART_DCD_232 DCD 1 11 BT_UART_RTS R9H5 UART_RTS_232
SERBUF_C2+ 1 3 SERBUF_V- GND1 0 NO_STUFF
C9J3 C2+ V- SERIAL BT_UART_RXD R9J2 UART_RXD_232
0.1uF C9J4 . 0 NO_STUFF
10% SERBUF_C2- 2 0.1uF A04514-006
8,11,12,15,21..23,26,32,37,40,45,46 . C2- 10%
+V3.3 20 .
BT_UART_CTS R2OUTB UART_CTS_232
19 R1OUT R1IN 4
H8_UART_RI 18 5 UART_RI_232
A
8,22 SMB_CLK_PCIE
R7V14
.
0 5%
PIN30_MINIA
BT_UART_RXD
H8_UART_DSR
17
16
R2OUT
R3OUT
R2IN
R3IN 6
7
UART_RXD_232
UART_DSR_232
A
R9D3 0 5% H8_UART_DCD R4OUT R4IN UART_DCD_232
26 GPS_UART_RTS 15 R5OUT R5IN 8
NO_STUFF
R9J4 R9J5 H8_UART_DTR UART_DTR_232
Title
14 T1IN T1OUT 9
1K 1K BT_UART_TXD UART_TXD_232
. . BT_UART_RTS
13
12
T2IN T2OUT 10
11 UART_RTS_232 Mini Card A For Wireless Testing
T3IN T3OUT
R7V12 0 5% SER_ON 23
8,22 SMB_DATA_PCIE
. PIN32_MINIA RS232_EN 22
FORCEON Size Document Number Rev
R7V9 0 5% FORCEOFF#
26 GPS_RESET#
NO_STUFF R9J3
21 INVALID# GND 25 A 1.5
1K NO_STUFF
MAX3243 C76308-001
. Date: Friday, November 16, 2007 Sheet 14 of 64
5 4 3 2 1
5 4 3 2 1
+V5 8,12,14,21,23,30,32,36,37,44,45
R2V3 14 USIM_CLK
8 C8Y2
7 3 V5S_MINIPCIE_B 4.7uF
14 USIM_RESET
6 2 10%
5 1 1% 0.01 C2V2 C2V6 C2V5 C3V1 .
14 USIM_PWR
Q4V5 SMR0805 0.1uF 0.1uF 22uF 0.1uF
IRF7811A NO_STUFF 20% 20% 20% 20% J8J1
NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
4
USIM_PWR C1 C6 USIM_VPP
+V12_ATX 28,40,44,45 VCC VPP
R4V8 USIM_RESET C2 C7
J1G1 10K RESET IO USIM_DATA 14
5%
D J9B2 NO_STUFF NO_STUFF USIM_CLK C3 CLK GND C5 D
PINK 2 1
3 2 USIM_SW1 S1 1
MIC
4 3
CONNECTOR B R2V1
USIM_SW2 S2
CD1
CD2
MECH1
MECH2 2
5 NO_STUFF J2G1 0 NO_STUFF

1 MIC_P 1 2 PIN2_MINIB R2G1 V3.3_MINIPCIE_B SIM_CONN .
WAKE# +3.3V_1 0 NO_STUFF C91074-003
3 RSVD1 GND7 4
JA13331-N112-4F SPK_P 5 6
RSVD2 +1.5V_1 USIM_PWR_R R8Y7 NO_STUFF
7 CLKREQ# RSVD13 8
J9B1 NO_STUFF 9 10 USIM_DATA_R R8W19 0 5% NO_STUFF
GREEN GND1 RSVD14 USIM_CLK_R R8Y2 0 5% NO_STUFF
2 11 REFCLK- RSVD15 12
3 13 14 USIM_RESET_R R8Y1 0 5% NO_STUFF
REFCLK+ RSVD16 USIM_VPP_R R8W22 0 5% NO_STUFF
4 15 GND2 RSVD17 16
0 5%
SPKR NO_STUFF KEY
5 USIM_SW2 R2F16 USIM_SW2_R 17 18
USIM_SW1 R2F15 0 5% USIM_SW1_R RSVD3 GND8 R2V5
1 19 RSVD4 RSVD18 20 W_DISABLE# 14,26
0 5% 21 22 BUF_RST_CONN_B#
GND3 PERST# BUF_RST# 14,20,26,27,31,46
JA13331-N142-4F NO_STUFF 23 24 PIN24_MINIB 0 5%
PER_N0 +3.3V_AUX NO_STUFF +V3.3S 5..8,11,12,14,16..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
25 PER_P0 GND9 26
27 28 R2V6
GND4 +1.5V_2 MINICARDB_CLK
29 GND5 SMB_CLK 30 SUS_CLK 8,14,26,28,49
31 32 TP_MINICARDB_DATA 0 5%
PET_N0 SMB_DATA NO_STUFF
33 PET_P0 GND10 34
26 WWAN_RESET# USB_MINI_PN0
35 GND6 USB_D- 36
2
37 38 USB_MINI_PP0
PIN39_MINIB RSVD5 USB_D+ Q2F4
39 RSVD6 GND11 40
PIN41_MINIB 41 42 MINI_B_WWAN_LED# 1 SI2307DS
RSVD7 LED_WWAN#
43 RSVD8 LED_WLAN# 44 WWAN_nINTR 26
45 46 TP_MINI_B_WPAN_LED# NO_STUFF
3
C 14 PCM_CLK RSVD9 LED_WPAN# C
47 RSVD10 +1.5V_3 48
Intentionally swizzled IN/OUT 14 PCM_DOUT PQ_WWANLED
49 RSVD11 GND12 50
14 PCM_DIN PIN52_MINIB
51 RSVD12 +3.3V_2 52
14 PCM_SYNC
55 GNDM1 GNDM2 56
R2F14
PCI-e_MINI_CARD 75
C59768-002 NO_STUFF
NO_STUFF
J2H1 PP_WWANLED
1 GREEN
NC1
2
LATCH WWAN
2 CR2F1
NC2 NO_STUFF
MINI_CARD_LATCH_LOTES
D51601-001
1
NO_STUFF
PLACE NEAR SCH
R2B2
USB_FP_PP0 32
0 5%
R2B3.
USB_MINI_PP0
8 USB_PP0
0 5%
NO_STUFF +V3.3 8,11,12,14,21..23,26,32,37,40,45,46
R2B5
USB_MINI_PN0
8 USB_PN0
0 5%
NO_STUFF
R2B4 R2V4
B USB_FP_PN0 32 0.01 B
0 5% 1%
. SMR0805
NO_STUFF
R7C9 V3.3_MINIPCIE_B
PCIE_TXP2_SLOT0 22
0 5% C2V7 C2V3 C2G1 C2V4 C3V2
.
R7C10 J1E4 J1E2 J1F2 J1F3 22uF 0.1uF 22uF 0.1uF 0.1uF
PCIE_TXP2_MINI_B 20% 20% 20% 20% 20%
7 PCIE_TXP2_MINI_SLOT0
0 5% 1 1 1 1 NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
NO_STUFF 2 PIN39_MINIB 2 PIN41_MINIB 2 PIN24_MINIB 2 PIN52_MINIB
R7C8 3 3 3 3
PCIE_TXN2_MINI_B NO_STUFF NO_STUFF NO_STUFF NO_STUFF
7 PCIE_TXN2_MINI_SLOT0
0 5%
NO_STUFF
R7C7
14,26 PMU_1 14,26 PMU_2 14,26 PMU_3 14,26 PMU_4
PCIE_TXN2_SLOT0 22
0 5%
.
R7C4
0 5% PCIE_RXP2_SLOT0 22
R7C5.
PCIE_RXP2_MINI_B
7 PCIE_RXP2_MINI_SLOT0 0 5%
NO_STUFF
R7C2
PCIE_RXN2_MINI_B
7 PCIE_RXN2_MINI_SLOT0 0 5%
NO_STUFF
R7C3
A
0 5% PCIE_RXN2_SLOT0 22 Crown Beach Intel Confidential
A
.
PLACE NEAR SCH

Title
Mini Card B for Wireless Testing
A 1.5

5 4 3 2 1
5 4 3 2 1
NOTE: Supports only ADD2-N cards in this slot. ADD2-R cards are
not supported. +V12S 5,17,31,33,35,45
D D
NOTE: 12V MAX Icc = 2.1A R7B3

3.3V Max Icc = 3.0A 0.01_1%
SMR1206
V12S_SDVO
5..8,11,12,14,15,17,18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S C7C1 C6B2 C7B1 C7B2 C7C4 C7C2

22UF 22UF 22UF 22UF 0.1uF 0.1uF
10% 10%
. .
J7C2 R7C1
B1 A1 0.01_1%
+12V1 PRSNT1# SMR1206
B2 +12V2 +12V4 A2
B3 +12V3 +12V5 A3
B4 A4 V3.3S_SDVO
GND1 GND6
B5 SMCLK JTAG2 A5
1
B6 A6 + C7C6 C7C5 C7C8
SMDAT JTAG3 100uF 0.1uF 0.1uF
B7 GND2 JTAG4 A7
B8 A8 10% 10%
2
+3.3V1 JTAG5 . .
B9 JTAG1 +3.3V2 A9
B10 3.3VAUX +3.3V3 A10
B11 WAKE# PWRGD A11 RST# 8,21,22,26,27,49,50
+V3.3S 5..8,11,12,14,15,17,18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
Key
B12 RSVD2 GND7 A12
C7C9 B13 A13
SDVO_REDP 0.1uF C7C10 SDVO_REDP_C GND3 REFCLK+
7 SDVO_RED B14 HSOP_0 REFCLK- A14
C 7 SDVO_RED#
SDVO_REDN 10% 0.1uF SDVO_REDN_C B15 HSON_0 GND8 A15 C
. 10% B16 A16
GND4 HSIP_0 SDVO_TVCLKIN 7
R7C6 . B17 A17
7 SDVO_CTRLCLK PRSNT2# HSIN_0 SDVO_TVCLKIN# 7
C7C11 B18 A18
SDVO_GREENP 0.1uF C7C12 SDVO_GREENP_C GND5 GND9
7 SDVO_GREEN B19 HSOP_1 RSVD5 A19
1M 5% SDVO_GREENN 10% 0.1uF SDVO_GREENN_C B20 A20
7 SDVO_GREEN# HSON_1 GND16
. 10% B21 A21
. GND10 HSIP_1 SDVO_INT 7
C7C13 . B22 A22
GND11 HSIN_1 SDVO_INT# 7
SDVO_BLUEP 0.1uF C7C14 SDVO_BLUEP_C B23 A23
7 SDVO_BLUE HSOP_2 GND17
SDVO_BLUEN 10% 0.1uF SDVO_BLUEN_C B24 A24
7 SDVO_BLUE# HSON_2 GND18
. 10% B25 A25
GND12 HSIP_2 SDVO_STALL 7
C7D1 . B26 A26
GND13 HSIN_2 SDVO_STALL# 7
SDVO_CLKP 0.1uF C7D2 SDVO_CLKP_C B27 A27
7 SDVO_CLK HSOP_3 GND19
SDVO_CLKN 10% 0.1uF SDVO_CLKN_C B28 A28
7 SDVO_CLK# HSON_3 GND20
. 10% B29 A29
. GND14 HSIP_3
B30 RSVD3 HSIN_3 A30
7 SDVO_CTRLDATA B31 PRSNT2#1 GND21 A31
R7D2 B32 A32
GND15 RSVD6
B33 HSOP_4 RSVD7 A33
B34 HSON_4 GND30 A34
1M 5% B35 A35
GND22 HSIP_4
B36 GND23 HSIN_4 A36
.
NOTE: ADD2N CARD HAS P/U'S TO 2.5V. SCH INPUT B37 A37
IS 3.3V BUT CLAMPS TO 2.5V ANYWAY. HSOP_5 GND31
B39 GND24 HSIP_5 A39
B41 HSOP_6 GND33 A41
B B47 A47 B
GND28 HSIP_7
B48 PRSNT2#2 HSIN_7 A48
B49 GND29 GND37 A49
B50 HSOP_8 RSVD8 A50
A B78
B79
HSOP_15
HSON_15
GND67
GND68
A78
A79 Crown Beach A
B80 GND52 HSIP_15 A80 Intel Confidential
B81 PRSNT2#3 HSIN_15 A81
B82 RSVD4 GND69 A82 Title
PCIE_X16 SDVO
C35285-004
A 1.5

5 4 3 2 1
5 4 3 2 1
D 5,12,31,33..35,40,41,44,45 +V5S +V12S 5,16,31,33,35,45 D
+V5S 5,12,31,33..35,40,41,44,45 R5V14 R5V17

0.01 0.01
1% 1%
. .
SMR0805 SMR0805
LVDS Panel Backlight
R5G3 BIOS Note: Disable both

10K BKLTSEL lines before
5% enabling one. C5V8 C5V9
.
0.1uF 0.1uF
L_BKLTSEL0# 20% 10%
R5H3 . .
10K +V3.3S 5..8,11,12,14..16,18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
5%
3
.
Q5H2
BSS138
1 5,12,31,33..35,40,41,44,45 +V5S
R5V22
3
. C5V13 470 R5V25 R5V27

2
Q5H1 0.1uF 5% 100K 470

. 5%
BSS138 U5V2 20% . C5V11
. 8 L_BKLTSEL1#
1 1 8 U5V1 0.1uF
8 L_BKLTSEL0_GPIO# OE1# VCC
7 L_BKLTCTL 2 7 1 5 20%
1A OE2# OE# VCC .
. 3 6
2
1B 2B
4 GND 2A 5 L_CLKCTLB 7 7 L_CLKCTLA 2 A
74CBT3306 GM_CLK_D Support 3 4
GM_Data_D Support GND Y
C 74CBTLV1G125 J5G2 C
SCH_PWM Support V12S_LVDSBKLT 1 VDD_BLI
2 VSS_BLI
3 VSS_DBC
V3.3S_LVDSBKLT 4
DBL_CLK VDD_DBC
5 DBL_CLK
L_BRIGHTNESS 6 DBL_DATA
7 L_BKLTEN 7 ENA_BL
5..8,11,12,14..16,18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S 5..8,11,12,14..16,18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S R5V20 8
100K NC1
9 VDD_ALS
10 VSS_ALS
R5V28 11
26,27 EMA_ALS_CLK ALS_CLK
R5V19 R5V18 12
SI2307DS
26,27 EMA_ALS_DATA ALS_DATA
2.2K 2.2K 13
0.01 1% 26,27 EMA_ALS_INTR# ALS_INTR
14 NC2
SMR0805 15
. +V3.3S_L V_3.3S_LVDS_VDL VSS_VDL
2 3 16 VDD_VDL1
17 VDD_VDL2
R5V26 Q5V1 C5V14 NO_STUFF V3.3S_LVDS_DDC 18
C5V12 C5W1 0.1uF R5V13 0 LVDS_RSVD_R VDD_VCL
. 8,56 SCH_GPIO_3 19 RSVD
1M 1000pF SI2307DS 22uF 20% 20
1
. 7 L_DDC_CLK VCL_CLK
10% 21
7 L_DDC_DATA VCL_DATA
R5V24 . 22
7 LA_DATAN0 A0M
L_VDDEN#
100K 23
7 LA_DATAP0 A0P
L_VDDEN_D# 24 VSS_SHIELD1
7 LA_DATAN1 25 A1M
7 LA_DATAP1 26 A1P
27 VSS_SHIELD2
7 LA_DATAN2 28 A2M
3
7 LA_DATAP2 29 A2P
Q4V6 30
BSS138 VSS_SHIELD3
7 LA_DATAN3 31 A3M
B 7 L_VDDEN 1 7 LA_DATAP3 32 B
A3P
33 VSS_SHIELD4
. 7 LA_CLKN 34
2
VDL_CLKAM
7 LA_CLKP 35 VDL_CLKAP
R5V23 36
100K VSS
37 B0M
5..8,11,12,14..16,18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S 38 B0P
39 VSS_SHIELD5
40 B1M
41 B1P
42 VSS_SHIELD6
R5V21 43
0.01 B2M
1% 44 B2P
. 45 VSS_SHIELD7
SMR0805 46 B3M
47 B3P
48 VSS_SHIELD8
49 VDL_CLKBM
50 VDL_CLKBP
C5V10
0.1uF LVDS,CONN50
20% .
. D27654-002
SR LVDS
Conn
A Crown Beach A
Intel Confidential
Title
LVDS

A 1.5

5 4 3 2 1
5 4 3 2 1
M_A_DQ[63:0] 9
J6D1A CON200_DDR2-SODIMM-STAN
9,19 M_A_A[14:0] M_A_A0 M_A_DQ0 36,37 +V1.8_DIMM
102 A0 DQ0 5
M_A_A1 101 M_A_DQ1
M_A_A2 A1 DQ1 7 M_A_DQ2 J6D1B CON200_DDR2-SODIMM-STAN
100 A2 DQ2 17
M_A_A3 99 M_A_DQ3
M_A_A4 A3 DQ3 19 M_A_DQ4
98 A4 DQ4 4 112 VDD1 VSS16 18
M_A_A5 97 M_A_DQ5
111 VDD2 VSS17 24
94 A6 DQ6 14 117 VDD3 VSS18 41
M_A_A7 92 M_A_DQ7
96 VDD4 VSS19 53
93 A8 DQ8 23 95 VDD5 VSS20 42
D M_A_A9 91 A9 DQ9 25
M_A_DQ9 118 VDD6 VSS21 54 D
M_A_A10 105 M_A_DQ10
M_A_A11 A10/AP DQ10 35 M_A_DQ11
81 VDD7 VSS22 59
90 A11 DQ11 37 82 VDD8 VSS23 65
M_A_A12 89 M_A_DQ12
M_A_A13 A12 DQ12 20 M_A_DQ13
87 VDD9 VSS24 60
116 A13 DQ13 22 103 VDD10 VSS25 66
M_A_A14 86 M_A_DQ14 5..8,11,12,14..17,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S
TP_A15 A14 DQ14 36 M_A_DQ15
88 VDD11 VSS26 127
84 A15 DQ15 38 104 VDD12 VSS27 139
85 M_A_DQ16
9,19 M_A_BS2 A16_BA2 DQ16 43 M_A_DQ17 VSS28 128
DQ17 45 M_A_DQ18
199 VDDSPD VSS29 145
9,19 M_A_BS0 107 BA0 DQ18 55 VSS30 165
106 M_A_DQ19 C4R1 C4R2
9,19 M_A_BS1 BA1 DQ19 57 M_A_DQ20 2.2uF 0.1uF
83 NC1 VSS31 171
9,19 M_CS#0 110 S0# DQ20 44 120 NC2 VSS32 172
115 M_A_DQ21 10% .10%
9,19 M_CS#1 S1# DQ21 46 M_A_DQ22 R6R1 0 .
50 NC3 VSS33 177
9 M_CLK_DDR0 30 CK0 DQ22 56 69 NC4 VSS34 187
M_A_DQ23 5,7 PM_EXTTS#
9 M_CLK_DDR#0 32 CK0# DQ23 58 163 NCTEST VSS35 178
164 M_A_DQ24 NO_STUFF PM_EXTTS#0_NC3
9 M_CLK_DDR1 CK1 DQ24 61 M_A_DQ25 VSS36 190
9 M_CLK_DDR#1 166 CK1# DQ25 63 37,48 M_VREF_DIMM0 1 VREF VSS37 9
79 M_A_DQ26
9,19 M_CKE0 CKE0 DQ26 73 M_A_DQ27 C6D1 C6D2 VSS38 21
9,19 M_CKE1 80 CKE1 DQ27 75 201 GND0 VSS39 33
113 M_A_DQ28 2.2uF 0.1uF
9,19 M_A_CAS# CAS# DQ28 62 10%
202 GND1 VSS40 155
9,19 M_A_RAS# 108 RAS# DQ29 64
M_A_DQ29 .10% VSS41 34
109 M_A_DQ30 .
9,19 M_A_WE#
SA0_DIM0 WE# DQ30 74 M_A_DQ31 VSS42 132
198 SA0 DQ31 76 47 VSS1 VSS43 144
SA1_DIM0 200 M_A_DQ32
SA1 DQ32 123 M_A_DQ33
133 VSS2 VSS44 156
8,21,24,27..29,50 SMB_CLK 197 SCL DQ33 125 183 VSS3 VSS45 168
195 M_A_DQ34
8,21,24,27..29,50 SMB_DATA SDA DQ34 135 M_A_DQ35
77 VSS4 VSS46 2
M_ODT_0 DQ35 137 M_A_DQ36

12 VSS5 VSS47 3
114 ODT0 DQ36 124 48 VSS6 VSS48 15
M_ODT_1 119 M_A_DQ37
ODT1 DQ37 126 M_A_DQ38 Provide TP VIAs on some DDR signals for EV.
184 VSS7 VSS49 27
R4R4 150 DM_7_0_R DQ38 134 M_A_DQ39

78 VSS8 VSS50 39
10 DM0 DQ39 136 71 VSS9 VSS51 149
R4R5 R4R6 26 M_A_DQ40
C 10K 10K DM1 DQ40 141 M_A_DQ41
72 VSS10 VSS52 161
C
52 DM2 DQ41 143 121 VSS11 VSS53 28
67 M_A_DQ42
DM3 DQ42 151 M_A_DQ43
122 VSS12 VSS54 40
130 DM4 DQ43 153 196 VSS13 VSS55 138
147 M_A_DQ44
DM5 DQ44 140 M_A_DQ45
193 VSS14 VSS56 150
170 DM6 DQ45 142 8 VSS15 VSS57 162
185 M_A_DQ46
DM7 DQ46 152 M_A_DQ47
9 M_A_DQS[7:0]
M_A_DQS0 DQ47 154 M_A_DQ48
13 DQS0 DQ48 157
M_A_DQS1 31 M_A_DQ49
M_A_DQS2 DQS1 DQ49 159 M_A_DQ50
51 DQS2 DQ50 173
131 DQS4 DQ52 158
169 DQS6 DQ54 174
R6R3 150 DQS#_7_0_R DQS7 DQ55 176 M_A_DQ56
11 DQS#0 DQ56 179
29 M_A_DQ57
DQS#1 DQ57 181 M_A_DQ58
49 DQS#2 DQ58 189
68 M_A_DQ59
DQS#3 DQ59 191 M_A_DQ60
129 DQS#4 DQ60 180
146 M_A_DQ61
DQS#5 DQ61 182 M_A_DQ62
167 DQS#6 DQ62 192
186 M_A_DQ63
DQS#7 DQ63 194
C42361-003
+V0.9S 9,19,36
B NO_STUFF R5R1 11,36,37 +V1.8 B

R5R4 56
RESERVED3 7 +V1.8_DIMM 36,37
0 5%
NO_STUFF R6R2
R5R31
R5R16 56
RESERVED2 7
0 5% 0.01_1%
NO_STUFF NO_STUFF SMR1206 C6R1 C5R21 C5R11 C5R10 C5R22 C5R20 C5R19 C5R8 C5R9
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10% 10% 10% 10% 10% 10%
ENABLE ODT DISABLE ODT R5P4 R5R30 . . . . . . . . .
10K 10K
5% 5%
UNSTUFF STUFF . .
R5P4, R5R30 R5P4, R5R30
Layout Note: Place these Caps near So-Dimm
STUFF R5R4, UNSTUFF R5R4,

R5R16 R5R16
Note: ODT implementation is for TEST ONLY

Production designs should follow the topologies
defined in the platform design guide with ODT disabled.
A Crown Beach A
Intel Confidential
Title
DDR2 SO-DIMM - Validation Only

A 1.5

5 4 3 2 1
5 4 3 2 1
D D
C C
Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9 and place it within 100 mils
+V0.9S 9,18,36
R5R29 121 1%
M_CKE0 9,18
C5R14 C5R5 C5R4 C5R18 C5R17 C5R7 C5R2 R5R15 121 1%
M_CKE1 9,18
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF .
10% 10% 10% 10% 10% 10% 10% .
. . . . . . . R5R20 121 1%
M_A_BS0 9,18
R5R7 121 1%
M_A_BS1 9,18
R5R28 . 121 1% M_A_BS2 9,18
.
R5R19 . 121 1% M_A_WE# 9,18
C5R1 C5R15 C5R6 C5R16 C5R12 C5R3 C5R13 R5R18 121 1%
M_A_CAS# 9,18
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R5R6 . 121 1% M_A_RAS# 9,18
10% 10% 10% 10% 10% 10% 10% .
. . . . . . . .
R5R5 121 1%
M_CS#0 9,18
R5R17 121 1%
M_CS#1 9,18
.
B . M_A_A[14:0] 9,18
B
R5R8 121 1% M_A_A0
R5R22 121 1% M_A_A1
R5R9 . 121 1% M_A_A2
R5R23 . 121 1% M_A_A3
R5R10 . 121 1% M_A_A4
R5R24 . 121 1% M_A_A5
R5R11 . 121 1% M_A_A6
R5R12 . 121 1% M_A_A7
R5R25 . 121 1% M_A_A8
R5R26 . 121 1% M_A_A9
R5R21 . 121 1% M_A_A10
R5R13 . 121 1% M_A_A11
R5R27 . 121 1% M_A_A12
R5R3 . 121 1% M_A_A13
R5R14 . 121 1% M_A_A14
.
.
A Crown Beach A
Intel Confidential
Title
DDR2 Termination

A 1.5

5 4 3 2 1
5 4 3 2 1
5..8,11,12,14..18,21,22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S
R7H5
0.01
+V3.3S_FWH 1% SMR0805
.
C7Y1 C7Y2
R6Y3 R6Y4 R6Y5 R6Y6 R6Y8 0.1uF C7H2 0.1uF
10K 10K 10K 10K 10K 20% 10UF 20%
5% 5% 5% 5% 5% XU6J1 . .
. . . . .
D FWH_INIT# 37 INIT# VPP 11 D

R6Y7 100 PLT_RST#_D 12 10
14,15,26,27,31,46 BUF_RST# RST# VCC2
VCC1 31
7 CLK_LPC_FWH 9 CLK VCCA 39
FGPI4 7
FGPI3 FGPI4 TBL# R6Y1 100
15 FGPI3 TBL# 20 FWH_TBL# 8
FGPI2 16 19 WP# R6Y2 100
FGPI1 FGPI2 WP# FWH_WP# 8
17 FGPI1
FGPI0 18 38
FGPI0 FWH4 . LPC_FRAME# 7,21,26,28,49
FWH3 28 LPC_AD3 7,21,26,28,49
TP_FWH_ID3 21 FWH 27 .
ID3 FWH2 LPC_AD2 7,21,26,28,49
Recovery Jumper TP_FWH_ID2 22 26
ID2 FWH1 LPC_AD1 7,21,26,28,49
2
2
TP_FWH_ID1 23 25
J7H3 1-X (Default) ID1 FWH0 LPC_AD0 7,21,26,28,49
J7H3 J5H3 J5H2 TP_FWH_ID0 24
1-2 Recover ID0 IC_R
IC 2
. . . TP_FWH_RSVD2 32
1
1
TP_FWH_RSVD1 RSVD2 TP_FWH_NC1
33 RSVD1 NC1 1
TP_FWH_RSVD5 34 3 TP_FWH_NC2
TP_FWH_RSVD4 RSVD5 NC2 TP_FWH_NC3
35 RSVD4 NC3 4
TP_FWH_RSVD3 36 5 TP_FWH_NC4
RSVD3 NC4 TP_FWH_NC5
NC5 6
29 8 TP_FWH_NC6
GND2 NC6 TP_FWH_NC7
30 GND1 NC7 13
40 14 TP_FWH_NC8 R6Y9
GNDA NC8 10K
5%
.
C95250-001
FWH (C75598-004) sits in the

FWH_TSOP_Socket
(C95250-001), Not on the
C board C
5..8,11,12,14..18,21,22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S
R5W16 R5W17
1K 1K
5% 5%
. .
FWH_INIT#
6
FWH_INIT 2 Q1C3B
3904
3 .
1
R5W15 1K H_INIT#_Q 5 Q1C3A
3,6,27 H_INIT#
. 5% 3904
.
4
B B
A Crown Beach A
Intel Confidential
Title
FWH

A 1.5

5 4 3 2 1
5 4 3 2 1
MDC Interposer Header

+VCCHDA 10,11
+V3.3 8,11,12,14,15,22,23,26,32,37,40,45,46
R8U3
D 5..8,11,12,14..18,20,22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S +V5 8,12,14,15,23,30,32,36,37,44,45 D
1%
0.01
VCCHDA_R
Layout Note: . SMR0805
Place all series
resistors 0.6 to 2.6
inches from the
SCH +V3.3S 5..8,11,12,14..18,20,22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
J9E2
R9E1
R8E2 39 HDA_MDC_BITCLK 16 15 1 +V1.5S 4..6,8,11,14,24,38
8 HDA_BITCLK R8E5 39 HDA_MDC_RST# VCC_MDC
8 HDA_RST# 14 13 2
R8E6 39 HDA_MDC_SYNC 12 11 3
8 HDA_SYNC R8E7 39 HDA_MDC_SDO +V12_SLOTS 22,45 1%
8 HDA_SDATAOUT 10 9 0.01
8 7 VBATS_MDC R9E2 0 DEFAULT [1-2]
8 HDA_SDATAIN0 . SMR0805
6 J8G1
8 HDA_SDATAIN1
4 3
2 1
2X8_HDR_KEY12
HDA_AUDIO_PWRDN_NET 1 2 HDA_SPKR 8
3 4
5 6
8 HDA_DOCK_RST# 7 8 HDA_DOCK_EN# 8
J9E3
R9E3 8Pin HDR
10K
. Layout Note:
C Place both headers C
in-line and exactly
200 mils from each
other, pin-to-pin.
Draw one
silkscreen box
around both parts.
NOTE: Use the 2x8 part of the header to cable

up to SDVO for HDMI capable ADD2N cards.
TPM HEADER
+V5 8,12,14,15,23,30,32,36,37,44,45
+V3.3S 5..8,11,12,14..18,20,22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58
R8P1 J9B4
7 CLK_LPC_TPM 1 2
3 R8N4
B 7,20,26,28,49 LPC_FRAME# B
0.01 C9P1 5 6 V5_TPM
8,16,22,26,27,49,50 RST#
1% 0.1uF 7 8
. 7,20,26,28,49 LPC_AD3 LPC_AD2 7,20,26,28,49
SMR0805 20% V3.3S_TPM 9 10 0.01
. LPC_AD1 7,20,26,28,49
8,11,12,14,15,22,23,26,32,37,40,45,46 +V3.3 11 12 C9N2 1%
7,20,26,28,49 LPC_AD0 . SMR0805
13 14 0.1uF
8,18,24,27..29,50 SMB_CLK SMB_DATA 8,18,24,27..29,50
V3.3A_TPM 15 16 20% NO_STUFF TP7G1
INT_SERIRQ 7,26,28 . PM_STPCPU# 8,24
R8P2 17 18 PM_CLKRUN# 7,26,28
19 20 NO_STUFF TP6H1
26 PM_SUS_STAT# PM_CLKRUN# 7,26,28
C9P2
0.01 0.1uF 2x10-HDR_P4KEY NO_STUFF TP2B1
H_DPRSTP# 3,6,41,50
1% 20%
.
SMR0805 . NO_STUFF TP5E1
H_DPSLP# 3,6,50
NO_STUFF TP2E1
H_CPUSLP# 3,6,50
Layout Note:Route these
signals without a stub. NO_STUFF TP2B2
PM_DPRSLPVR 7,41
NO_STUFF TP3F2
H_NMI 3,6
NO_STUFF TP2E3
H_SMI# 3,6,48
NO_STUFF TP2E2
H_PWRGD 3,6,50
A Crown Beach A
Intel Confidential
Title
High Definitition Audio / TPM

A 1.5

5 4 3 2 1
5 4 3 2 1
+V12_SLOTS 21,45
R8B1
V12S_PCIE_SLOT0
0.01_1% C8C1 C8C4 C7C3

SMR1206 22uF 0.1uF 0.1uF
10% 10%
. .
Slots don't support D3 Hot.

+V3.3_SLOTS 45
D D
R8C2
V3.3S_PCIE_SLOT0
0.01_1% C8C7 C7C7 C8C6 C8C9

SLOT 0
SMR1206 22uF 0.1uF 0.1uF 0.1uF
10% 10% 10% J7C1
. . . B1 A1 PRSNT#1_SLOT0
+12V1 PRSNT1#
B2 +12V2 +12V3 A2
B3 A3 R7B2
RSVD1 +12V4 0
B4 GND1 GND6 A4
+V3.3 8,11,12,14,15,21,23,26,32,37,40,45,46 B5 A5
8,14 SMB_CLK_PCIE SMCLK JTAG2
8,14 SMB_DATA_PCIE B6 SMDAT JTAG3 A6
B7 GND2 JTAG4 A7
B8 +3.3V1 JTAG5 A8
R8C6 B9 A9
V3.3_PCIE_SLOT0 JTAG +3.3V2
B10 3.3VAUX +3.3V3 A10
B11 WAKE# PWRGD A11 RST# 8,16,21,26,27,49,50
0.01 1% C8C16 C8C12 8,14 PCIE_WAKE#
SMR0805 22uF 0.1uF 5..8,11,12,14..18,20,21,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S Key
. 10% B12 A12
. RSVD2 GND7
B13 GND3 REFCLK+ A13 CLK_PCIE_SLOT0 24
R8C4 B14 A14
15 PCIE_TXP2_SLOT0 HSOP_0 REFCLK- CLK_PCIE_SLOT0# 24
10K B15 A15
15 PCIE_TXN2_SLOT0 HSON_0 GND8
B16 GND4 HSLP_0 A16 PCIE_RXP2_SLOT0 15
24 CLK_SLOT0_OE# . B17 PRSNT2# HSLN_0 A17 PCIE_RXN2_SLOT0 15
B18 GND5 GND9 A18
PCIE_X1
+V12_SLOTS 21,45
C C
R8B3
0.01_1%
SMR1206
V12S_PCIE_SLOT1
C8C5 C8C2 C8C3

22uF 0.1uF 0.1uF
10% 10%
. .
45 +V3.3_SLOTS
R8C5
0.01_1%
SMR1206
V3.3S_PCIE_SLOT1
C8C14 C8C11 C8C13 C8C8

22uF 0.1uF 0.1uF
10%
0.1uF SLOT 1
10% 10%
. . . J8C1
B1 A1 PRSNT#1_SLOT1
+12V1 PRSNT1#
B2 +12V2 +12V3 A2
B3 A3 R8B2
+V3.3 8,11,12,14,15,21,23,26,32,37,40,45,46 RSVD1 +12V4 0
B4 GND1 GND6 A4
8,14 SMB_CLK_PCIE B5 SMCLK JTAG2 A5
8,14 SMB_DATA_PCIE B6 SMDAT JTAG3 A6
B7 GND2 JTAG4 A7
B8 +3.3V1 JTAG5 A8
R8C7 B9 A9
B V3.3_PCIE_SLOT1 B10
JTAG +3.3V2
A10 B
3.3VAUX +3.3V3
B11 WAKE# PWRGD A11 RST# 8,16,21,26,27,49,50
0.01 1% C8C15 C8C10 8,14 PCIE_WAKE#
SMR0805 22uF 0.1uF 5..8,11,12,14..18,20,21,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S Key
. 10% B12 A12
. RSVD2 GND7
B13 GND3 REFCLK+ A13 CLK_PCIE_SLOT1 24
R8C3 B14 A14
14 PCIE_TXP2_SLOT1 HSOP_0 REFCLK- CLK_PCIE_SLOT1# 24
10K B15 A15
14 PCIE_TXN2_SLOT1 HSON_0 GND8
B16 GND4 HSLP_0 A16 PCIE_RXP2_SLOT1 14
24 CLK_SLOT1_OE# . B17 PRSNT2# HSLN_0 A17 PCIE_RXN2_SLOT1 14
B18 GND5 GND9 A18
PCIE_X1
NOTE: SLOTS
0 AND 1 ARE
PARALLEL TO
EACH OTHER
J8D2
24 CLK_PCIE_SRC3 1
2
24 CLK_PCIE_SRC3# 3
CON3_HDR
Probe Points for EV

Provide TP vias on the top layer for all PCIe signals half way between PCIe slots and Poulsbo.
Place headers close to PCIe midbus via probe points.
A A
Title
PCI Express Slots

Custom 1.5

5 4 3 2 1
5 4 3 2 1
D D
C C
8,11,12,14,15,21,22,26,32,37,40,45,46 +V3.3
8,11,12,14,15,21,22,26,32,37,40,45,46 +V3.3
+V5 8,12,14,15,21,30,32,36,37,44,45 +V5 8,12,14,15,21,30,32,36,37,44,45
R6H2 R6W1 R7H1 R6H3 R6H1

0.01 10K 10K 0.01 10K
1% 1%
. USB_OC#6 8 . USB_OC#5 8
SMR0805 U6H2 SMR0805 U6H3 .
1 8 FB6H2 1 8 FB6H3
+V5_USB_P6_P7 GND OC1# V_USBPWR_CONNG 50OHM +V5_USB_FPIO_P6_P7 +V5_USB_P5 GND OC1# +V5_USBPWR_CONNF 50OHM +V5_USB_FPIO_P5
2 IN OUT1 7 2 IN OUT1 7
5% 1K R6W5 EN1_P6P7 3 6 5% 1K R6W3 EN1_P5 3 6
5% 1K R6W4 EN2_P6P7 EN1 OUT2 5% 1K R6W2 EN2_P5 EN1 OUT2
4 EN2 OC2# 5 USB_OC#7 8 4 EN2 OC2# 5
. + C7H1 C6H8 . + C6H3
C6H7 TPS2052B C6H1 220uF 0.1uF TPS2052B C6H2 220uF
. 10% . 10%
0.1uF 470PF 10% 470PF
. . .
10%
.
B B
TEST ONLY - J6G3

J6G2
USB FPIO, Duck 1 2 TEST ONLY - 14 USB_FP_PN5
1
3
2
4
3 4 5 6
Bay and Upham 8
8
USB_PN6
USB_PP6 5 6
USB_PN7 8
USB_PP7 8 Duck Bay and Upham USB and 14 USB_FP_PP5
7 8
7 8 10
Sideband Header 10 Sideband header .
USB_2X5-Header
.
USB_2X5-Header
A Crown Beach A
Intel Confidential
Title
USB FPIO & Sideband

A 1.5

5 4 3 2 1
5 4 3 2 1
D +V3.3S 5..8,11,12,14..18,20..22,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 D
FB8U2
CK540
R8U1
V3.3S_CK505 1 2
0.01 1%
MLF56
SMR0805 C8U1 120ohm@100MHz C8U6 C8U3 C8U2 C8U4 C8U13
. 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 4..6,8,11,14,21,38 +V1.5S
20% 10% 10% 10% 10% 10%
. . . . . .
U8F1
VDD_CLK_SNG 3 35
FB8U1 VDDREFIO_3.3 VDDIO_SRC
10 VDDIO_PCI3.3 VDDIO_CPU 49
1 2 VDD_CLK_DIF 18 26 C8U8 C8U11 C8U9 C8U14 C8U7 Place the 0.1 uF caps as close as possible to each VDD_IO pin.
VDD48PLL_3.3 VDDI0_LCD 0.1uF 0.1uF 0.1uF 0.1uF 10uF Place the 10 uF cap on the VDD_IO plane.
17 VDD48IO_3.3 VDDIO_96MHz 19
120ohm@100MHz C8U10 C8U15 C8U5 27 10% 10% 10% 10% 20%
0.1uF 0.1uF 0.1uF VDDCDPLL_3.3 . . . . .
53 VDDCPUPLL_3.3
10% 10% 10% 40
J7F3 . . . VDDCORE_3.3
2 NO_STUFF 52 CPU0 R8F7 0 5%
G1 CPU0T_LPRS CLK_CPU_BCLK 3
1 XTAL_IN_D R7F4 0 XTAL_OUT 1 51 CPU#0 R8F9 . 0 5%
S X2 CPU0C_LPRS CLK_CPU_BCLK# 3
XTAL_IN .
G3
G4
3 G2 2 X1
SMA_SMT
C51931-001 R7F3 0 48 CPU1 R8F11 0 5%
CLK_SCH_BCLK 6
4
CPU1T_LPRS CPU#1 R8F12 . 0 5%

11 PCI0 CPU1C_LPRS 47 CLK_SCH_BCLK# 6
. 12 .
PCI1 CPU1TP R8F14 0 5%
13 PCI_F2 CPUITPT_LPRS 46 CLK_XDP 29
45 CPU1TP# R8F16 . 0 5%
CPUITPC_LPRS CLK_XDP# 29
.
Y7F1 31 SRC0 R8F18 0 5%
SRC0T_LPRS CLK_PCIE_SLOT0 22
1 2 30 SRC0# R8F17 . 0 5%
SRC0C_LPRS CLK_PCIE_SLOT0# 22
C R8U2 33 5% REF0_R 4 REF0 CLKREQ0# 29 CLKREQ0# R8U15 475 1%
CLK_SLOT0_OE# 22
. C
14.318MHZ 8 CLK_REF_SCH R8U17 475 1%
R8F6 CLKREQ_MINIPCIE# 14
8 CLK_USB48 . 33 5% USB48_R 16 USB_48MHz SRC1T_LPRS 33 SRC1 NO_STUFF R8F22 0 5%
CLK_PCIE_SLOT1 22
C7F2 C7F4 NO_STUFF 32 SRC1# R8F20 . 0 5%
SRC1C_LPRS CLK_PCIE_SLOT1# 22
33pF 33pF 28 CLKREQ1# R8F1 . 475 .
5% 5% R8F3 10K PCI_STOP# CLKREQ1# R8F2 475 CLK_SLOT1_OE# 22
9 PCI_STOP# CLKREQ_MINIPCIE# 14
. . 44
8,21 PM_STPCPU# CPU_STOP#
37 SRC2 R8F26 0 5% R8F19 33 5% NO_STUFF
SRC2T_LPRS CLK_PCIE_IN 7 CLK_PCIE_MINICARDA 14
6 36 SRC2# R8F24 . 0 5% R8F21 33 5% NO_STUFF
8,18,21,27..29,50 SMB_CLK SCLK SRC2C_LPRS CLK_PCIE_IN# 7 CLK_PCIE_MINICARDA# 14
5 42 .
8,18,21,27..29,50 SMB_DATA SDATA CLKREQ2# CLK_SCH_OE# 8
R8U10 10K 5%
39 SRC3 R8F23 . 0 5%
SRC3T_LPRS CLK_PCIE_SRC3 22
43 38 SRC3# R8F25 . 0 5%
50 CK_FSB_CLK FSLB SRC3C_LPRS CLK_PCIE_SRC3# 22
55 41 .
50 CK_FSC_CLK FSLC CLKREQ3#
R8F4 10K 8 20 DOT96 R8F8 0 5%

TEST_MODE DOT96C_LPRS DREFCLK 8
R8F5 10K 7 21 DOT96# R8F10 . 0 5%
TEST_SEL DOT96T_LPRS DREFCLK# 8
.
25 SS_CLK R8F15 0 5%
LCD100T_LPRS DREFSSCLK 8
24 SS_CLK# R8F13 . 0 5%
LCD100C_LPRS DREFSSCLK# 8
15 .
GND48
56 GNDREF
14 GNDPCI
34 GNDSRC
50 GNDCPU CK_PWRGD#/PD 54 VR_PWRGD_CLKEN# 41
23 GND
22 GND1 THERMGND 57
B B
CK540 (56pins MLF)
D82952-001
11,33,34 +V1.05S_VTT
R8G4
56
J8G2
NO_STUFF
3,50 CPU_BSEL0 1
2 CK_FSA 51
3
R8G3
R8G7 1K
56
J8G3
3,50 CPU_BSEL1 1
FSB Frequency Select: 2 CK_FSB 51
3
R8G6
CPU J8G3 -> 1 - 2 BSELS DRIVEN BY R8G5 1K
Driven J9G3 -> 1 - 2 PROCESSOR 56
A Crown Beach A
FSB
(Default) J9G3 Intel Confidential
Freq 400
3,50 CPU_BSEL2 1 Title
(100 MHz J8G3 -> Open CPU BSEL 1=0 2
(MHz) host clk) J9G3 -> 2 - 3 CPU BSEL 2=1 3
CK_FSC 51
Clock CK540
R8G2 R8G1 33 .5%
SCH_BSEL2 6
1K
533 J8G3 -> Open CPU BSEL 1=0 Size Document Number Rev
(133 MHz
host clk)
J9G3 -> Open CPU BSEL 2=0
A 1.5

5 4 3 2 1
5 4 3 2 1
5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S R6N1

V3.3S_SDIO0
C6N1 C6B1
0.01 1% 10uF 0.1uF
R5B6 SMR0805 20% 80%
. .
75 NO_STUFF
J6B1
VSS_1 1
SLOT0_LED_CR 2 SLOT0_DATA2
DAT2 SLOT0_DATA3 J6N1
DAT3 3
2
SUPPLY_V 4 4 VDD
CR5B1 5
CMD 7 SLOT0_DATA[7:0]
D GREEN
INTERFACE_V 6 SLOT0_DATA0 7 DAT0 D
7 SLOT0_DATA1 8
CLK SLOT0_DATA2 DAT1
8 9
1
VSS_2 SLOT0_DATA0 SLOT0_DATA3 DAT2
SLOT0_LED_Q DAT0 9 1 DAT3
TP6B3 10 SLOT0_DATA1 SLOT0_DATA4 10
DAT1 DAT4
3
11 SLOT0_DATA5 11
NO_STUFF Q5B1 VSS_3 SLOT0_DATA6 DAT5
RSVD 12 12 DAT6
BSS138 SLOT0_DATA7 13
CE-ATA DAT7
7 SLOT0_LED 1
7 SLOT0_CMD 2 CMD
. 7 SLOT0_CLK 5
2
CLK
TEST ONLY
14 CD#
15 WP SHLD1 16
7 SLOT0_CD# SHLD2 17
7 SLOT0_WP 3 VSS1 SHLD3 18
6 VSS2 SHLD4 19
.
5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S TP6B2 SDIO-MMC 8-bit
+V3.3S 5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58 NO_STUFF
C4B3
0.1uF
80% R5M1
7,56 SD2PWR# .
V3.3S_SDIO1
R4B14 R4B4 R3B2 R4B12 R4B11 R4B7 C4B2 C5N1
7,56 SD1PWR# 0.1uF
TP6B1 10K 10K 10K 10K 10K 10K 0.01 1% 10uF
NO_STUFF NO_STUFF NO_STUFF U4B1 SMR0805 20% 80%
7,56 SD0PWR# . .
NO_STUFF NO_STUFF J5B1
2 15 V3.3S_SDIO_SLOT0 4
SLOT0_CD# R4B13 1K 5% NO_STUFF SD0PWR# IN1 OUT1 V3.3S_SDIO_SLOT1 VDD
3 EN1# OUT2 14 7,56 SLOT1_DATA[7:0]
C SLOT1_CD#_R R4B9 1K 5% NO_STUFF SD1PWR# 4 EN2#
SLOT1_DATA0 R5B7 0 SLOT1_DATA0_R 7 DAT0
C
SLOT1_DATA1 R5B8 0 SLOT1_DATA1_R 8
V3.3S_SDIO_SLOT2 SLOT1_DATA2 R5N5 0 SLOT1_DATA2_R DAT1
6 IN2 OUT3 11 9 DAT2
SLOT2_CD# R4B2 1K 5% NO_STUFF SD2PWR# 7 SLOT1_DATA3 R5N4 0 SLOT1_DATA3_R 1
EN3# 2043_OC1# R4B15 4.7K SLOT1_DATA4 R5B9 0 NO_STUFF SLOT1_DATA4_R DAT3
OC1# 16 10 DAT4
2
2
13 2043_OC2# R4B10 4.7K SLOT1_DATA5 R5B10 0 NO_STUFF SLOT1_DATA5_R 11
J4B4 J4B3 J4B2 OC2# 2043_OC3# R4B8 4.7K SLOT1_DATA6 R5N3 0 NO_STUFF SLOT1_DATA6_R DAT5
OC3# 12 12 DAT6
Default 1-X Default 1-X Default 1-X SLOT1_DATA7 R5N2 0 NO_STUFF SLOT1_DATA7_R 13 DAT7
. . . 1 8
1
1
GND_1 NC_1 R5B11 0 SLOT1_CMD_R
5 GND_2 NC_2 9 7,56 SLOT1_CMD 2 CMD
10 R5B14 0 SLOT1_CLK_R 5
NC_3 7,56 SLOT1_CLK CLK
TPS2043B R5N1 0 SLOT1_CD#_R 14
7,56 SLOT1_CD# CD#
R5B12 0 SLOT1_WP_R 15 16
7,56 SLOT1_WP WP SHLD1
5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58 +V3.3S 17
Strap 1-2 for CE-ATA
SHLD2
3 VSS1 SHLD3 18
CAD NOTE: Place 6 19
near J6B1 to VSS2 SHLD4
TEST ONLY -
.
minimize stubs SDIO-MMC 8-bit
5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58
+V3.3S
R4B5
75
R4B1
V3.3S_SDIO2
SLOT1_LED_CR C4B1 C4N1
0.01 1% 10uF 0.1uF
80%
2
SMR0805 20% .
CR4B1 . NO_STUFF J4B1
B 4 B
GREEN VDD
SLOT2_D0_SDIO 7
1
SLOT2_D1_SDIO DAT0
SLOT1_LED_Q 8 DAT1
SLOT2_D2_SDIO 9 DAT2
3
SLOT2_D3_SDIO 1
7,57 SLOT2_DATA[7:0] DAT3
Q4B1 SLOT2_DATA4 10
BSS138 SLOT2_DATA5 DAT4
11 DAT5
R5N6 0 SLOT1_LED_R 1 R5U41 0 NO_STUFF SLOT2_DATA6 12
7,56 SLOT1_LED SLOT2_CMD_MINI 14 DAT6
5% SLOT2_DATA7 13
R5U40 0 SLOT2_CMD_SDIO DAT7
. 7 SLOT2_CMD
2
R4B3 5% 2
10K R5U44 0 SLOT2_CLK_SDIO CMD
7 SLOT2_CLK 5 CLK
5%
.
R5U45 0 NO_STUFF 14
SLOT2_CLK_MINI 14 7 SLOT2_CD# CD#
5% 15 16
. 7 SLOT2_WP WP SHLD1
SHLD2 17
3 VSS1 SHLD3 18
6 VSS2 SHLD4 19
+V3.3S 5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58
.
SDIO-MMC 8-bit
R4B6
75
+V3.3S 5..8,11,12,14..18,20..22,24,27,29,31,34,35,38,40,41,43..46,49..51,56..58
SLOT2_LED_CR R5U34 0 NO_STUFF
SLOT2_D0_MINI 14
5%
2
R5U33 0 SLOT2_D0_SDIO R5B5 10K SLOT0_WP

7 SLOT2_DATA0
CR4B2 5%
A GREEN 7 SLOT2_DATA1
R5U43
5%
0 SLOT2_D1_SDIO
R5B13 10K SLOT1_WP_R
Crown Beach Intel Confidential A
.
R5U42 0 NO_STUFF
SLOT2_D1_MINI 14
1
SLOT2_LED_Q
.
R5U46
5%
0 NO_STUFF R3B1 10K SLOT2_WP
Title
SLOT2_D2_MINI 14
SD / SDIO / MMC
3
5%
Q4B2 R5U47 0 SLOT2_D2_SDIO
7 SLOT2_DATA2
BSS138 5% R6B1 40.2K 1% SLOT0_CMD
R5U39 0 SLOT2_D3_SDIO .
7 SLOT2_LED 1 7 SLOT2_DATA3
5% R5B1 40.2K 1% SLOT1_CMD_R Size Document Number Rev
.
. R5U38 0 NO_STUFF
SLOT2_D3_MINI 14
.
A 1.5
2
5% R5F16 40.2K 1% SLOT2_CMD

. .

5 4 3 2 1
5 4 3 2 1
Boot Mode Programming Straps +V3.3A_KBC 27,30,40
P90-P92 needs to be at VCC for boot mode programming. They are
already pulled up in the design. MD0, MD1 needs to be at Vss.
System needs to supply +V3.3A to flash connector.
+V3.3A_KBC 27,30,40 +VREF_ADC 57 R8E9 R8E10 R8E11

240 240 240
LEDD1
LEDD2
LEDD3
Y8E1 C7D5
1 2 0.1uF
R8T5 R8E8 R8E12 10%
10MHZ 10K 10K 10K . GREEN GREEN GREEN
2
C8E1 C8E2 NOTE: Place C7T1
18PF 18PF C7T1 decoupling cap
D 0.1uF close to VCL pin 13 D
10% CR8E1 CR8E3 CR8E2
.
3LED_CAPS 1
LED_SCROLL 1
1
U8E1
1 VCC1 33
LED_NUM
PA7/KIN15#/PS2CD KBC_GP_DATA 30
J7E2 86 VCC3 34
PA6/KIN14/PS2CC KBC_GP_CLK 30
27 EC_RST# 1
2 VCL 13 38
VCL PA3/KIN11#/PS2AD KBC_MOUSE_DATA 30
EC RST# Jumper 3 36 39
VCC2 PA2/KIN10#/PS2AC KBC_MOUSE_CLK 30
J7E2 1-2 (Default) 77
J7E2 2-3 (H8 held in reset) CON3_HDR AVREF Q8T3
76 AVCC PA5/KIN13#/PS2BD 35 KBC_KB_DATA 30
2
37 BSS138
PA4/KIN12#/PS2BC KBC_KB_CLK 30
J8E2 J8E3 MD1 9 19 KBC_CAPSLOCK 1
MD1 P95/IRQ14#
3
MD0 10 20 KBC_SCROLLOCK
J8E2 1-2 J8E3 1-2 PH0/EXIRQ6#/TDPMCI2 P94/IRQ13# KBC_NUMLOCK Q8T2
. . 21 .
2
SYS_PWRGD P93/IRQ12# BSS138
(Default) (Default) 140 PH3
KBC_DIS# 141 78 KBC_SCANIN0 1
SMC_XTAL PH4 P60/KIN0#/FTCI/TMIX KBC_SCANIN1
143 XTAL P61/KIN1#/FTOA 79
3
SMC_EXTAL 144 80 KBC_SCANIN2 .
2
27,30,40 +V3.3A_KBC EXTAL P62/KIN2#/FTIA/TMIY KBC_SCANIN3 Q8T1
P63/KIN3#/FTIB 81
SMC_RES# 8 82 KBC_SCANIN4 BSS138
R8E18 KBC_DISABLE# SMC_STBY# RES# P64/KIN4#/FTIC KBC_SCANIN5
12 PH1/EXIRQ7#/TDPCKI2/TDPMCI2 P65/KIN5#/FTID 83 1
10K R8T6 100 NMI_R 11 84 KBC_SCANIN6
30 SMC_INITCLK NMI P66/IRQ6#/KIN6#/FTOB
2
85 KBC_SCANIN7 .
2
J8E5 1-X P67/IRQ7#/KIN7#/TMOX
. J8E5 H8_PIN15 15 P51/TMOY KBC_SCANIN[7:0] 30
(Default) H8_PIN16 16 96 KBC_SCANOUT15
P50/EXEXCL P27/PW15 KBC_SCANOUT14
. 27 SMB_BS_CLK 14 97
1
P52/EXIRQ6#/SCL0 P26/PW14 KBC_SCANOUT13

27 SMB_BS_DATA 17 P97/IRQ15#/SDA0 P25/PW13 98
18 99 KBC_SCANOUT12
8,14,15,28,49 SUS_CLK P96/0/EXCL P24/PW12
R7T10 R7T7 SMC_IRQ0 22 100 KBC_SCANOUT11
10K SMC_IRQ1 P92/IRQ0# P23/PW11 KBC_SCANOUT10
23 P91/IRQ1# P22/PW10 101
8.2K 24 102 KBC_SCANOUT9
44 SMC_ONOFF# P90/IRQ2#/ADTRG# P21/PW9
C . P20/PW8 103 KBC_SCANOUT8 C
R7R4 8.2K P70/EXIRQ0#/AN0 68 104 KBC_SCANOUT7
P70/EXIRQ0#/AN0 P17/PW7 KBC_SCANOUT6
57 VBRK_MON 69 P71/EXIRQ1#/AN1 P16/PW6 105
70 106 KBC_SCANOUT5
7,28 PM_SLPMODE P72/EXIRQ2#/AN2 P15/PW5
71 107 KBC_SCANOUT4
57 EC_BRK_CURRENT P73/EXIRQ3#/AN3 P14/PW4
72 108 KBC_SCANOUT3
44 ATX_DETECT# P74/EXIRQ4#/AN4 P13/PW3
TP_H8_AN5 73 109 KBC_SCANOUT2
TP_H8_AN6 P75/EXIRQ5#/AN5 P12/PW2 KBC_SCANOUT1
74 P76/AN6 P11/PW1 110
TP_H8_AN7 75 112 KBC_SCANOUT0
P77/AN7 P10/PW0 +V3.3A_KBC 27,30,40
27 EC_PA1 40 PA1/KIN9# KBC_SCANOUT[15:0] 30
8 CRB_DET# 41 PA0/KIN8# P30/LAD0 121 LPC_AD0 7,20,21,28,49
8,28 PM_PWRBTN# 136 P40/TMCI0/TXD2/DSERIRQ P31/LAD1 122 LPC_AD1 7,20,21,28,49
28,41 IMVP_VR_ON 137 P41/TMO0/RXD2/DCLKRUN# P32/LAD2 123 LPC_AD2 7,20,21,28,49
PM_THERM#_R 2 124
5,8 PM_THRM# P43/TMCI1 P33/LAD3 LPC_AD3 7,20,21,28,49
R8T13 . 0 3 125 R8R5
27,30 NMI_GATE P44/TMO1 P34/LFRAME# LPC_FRAME# 7,20,21,28,49
4 126 PLT_RST_R R8D9 100 10K
7,28,46 PM_RSMRST# P45/TMRI1 P35/LRESET# BUF_RST# 14,15,20,27,31,46
5,28 FAN_PWM 5 127 CLK_LPC_H8 7 .
R8T7 10K P46/PWX0 P36/LCLK
14,15 PMU_3 6 128 INT_SERIRQ 7,21,28
5% H8_PIN115 P47/PWX1 P37/SERIRQ
14 H8_PIN115 115 131 PM_CLKRUN# 7,21,28
NO_STUFF PB5/WUE5#/DLAD2 P82/CLKRUN# PM_SUS_STAT_R#
14,15 PMU_4 116 PB4/WUE4#/DLAD3 P83/LPCPD# 132 PM_SUS_STAT# 21
R7R5 0
117 134 NO_STUFF
14,27 EC_THRM_CLK PB3/WUE3#/DLFRAME# P85/IRQ4#/RXD1/IRRXD KBC_PROG_RX# 28,34
14,27 EC_THRM_DATA 118 PB2/WUE2# P86/IRQ5#/SCK1/SCL1 135 EMA_ALS_CLK 17,27
8,28 SMC_RUNTIME_SCI# 119 PB1/WUE1#/LSCI P42/EXIRQ7#/TMRI0/SCK2/SDA1 138 EMA_ALS_DATA 17,27
8,28 SMC_EXTSMI# 120 PB0/WUE0#/LSMI#
17,27 EMA_ALS_INTR# 129 P80/PME# VSS1 7
57 EC_CS_GAIN_SEL 130 P81/GA20 VSS2 42
VSS3 95
14 GPS_UART_RTS 113 PB7/WUE7#/DLAD0 VSS4 111 NOTE:GND_SYS_ISENSE tie to GND is on Page 53
14 GPS_UART_CTS 114 PB6/WUE6#/DLAD1 VSS5 139
67 GND_SYS_ISENSE
AVSS
133 P84/IRQ3#/TXD1/IRTXD
B 27,28,34 KBC_PROG_TX#
87 H8_87 R7R1 47 5% NO_STUFF
WWAN_RESET# 15
B
PC7/WUE15#/DLDRQ H8_88 R7R2 47 5% NO_STUFF
142 PH5 PC6/WUE14#/LDRQ 88 W_DISABLE# 14,15
14,15 PMU_2 H8_89 R7R3 47 5% NO_STUFF MODE TYPE MD0 MD1 MD2 NMI(P29)
PC5/WUE13# 89 PMU_1 14,15
28,40,46 PM_RSMRST_PWRGD 51 PG7/EXIRQ15#/EXSCLB PC4/WUE12# 90 SMC_LID 27
52 PG6/EXIRQ14#/EXSDAB PC3/WUE11# 91 VIRTUAL_BATTERY 27 Run Mode 0 0 1 0
14 GPS_nINTR
14 WIFI_RESET# 53 PG5/EXIRQ13#/EXSCLA PC2/WUE10# 92 EC_WIFI_PD# 14
27,28 H8_INIT# R8Y11 H8_PIN115 54 93 Program Boot Block 0 0 1 1
14 WIFI_HOST_WAKE PG4/EXIRQ12#/EXSDAA PC1/WUE9# SMC_SHUTDOWN 28,44
0 5% 55 94 TP_PC0/WUE8#
14 GPS_RESET# PG3/EXIRQ11#/EXTMIY PC0/WUE8# H8_CPU_PWRGD 6
NO_STUFF 56
14 WIFI_nINTR PG2/EXIRQ10#/EXTMIX NO_STUFF
14 GPS_ON 57 PG1/EXIRQ9#/EXTMCI1 PD7/TIOCB2/TCLKD 59 LPC_RST# 28
R8R4 58 60 TP_H8_60 R7E1 0 5%
0 5% PG0/EXIRQ8#/EXTMCI0 PD6/TIOCA2
PD5/TIOCB1/TCLKC 61 PM_SLP_S3#_J 27
. 43 62
28,44 PM_SYSRST# PF7/EXPW15 PD4/TIOCA1 PM_SLP_S4# 28,40,45,46
27,28 H8_A20M# 44 PF6/EXPW14 PD3/TIOCD0/TCLKB 63 PM_RSTWARN 8,28
15 WWAN_nINTR
27 REV_FAB_ID1 45 PF5/EXPW13 PD2/TIOCC0/TCLKA 64 RST# 8,16,21,22,27,49,50
46 65 +V3.3A_KBC 27,30,40
27 REV_FAB_ID0 PF4/EXPW12 PD1/TIOCB0 SCH_PWROK 7,28,46
27 FAN_ON 47 PF3/IRQ11#/EXTMOX PD0/TIOCA0 66 PM_SUS_STAT# 21 EC_MD2 27
Backup option in case of 2104 sub 28,40 PM_IMVP_PWRGD 48
49
PF2/IRQ10#
25 R8E14 4.7K
8,28 PM_RSTRDY# PF1/IRQ9# MD2
50 26 KBC_FWE R7T13 4.7K
7,28 PM_SLPRDY# PF0/IRQ8# PH2
R8T10 H8_PIN15 27
14 H8_SCIF_RXD ETRST# EC_ETRST# 27
0 5% 28
PE4/ETMS EC_ETMS 27
2
. 29 J8E4 1-X
PE3/ETDO EC_ETDO 27 (Default)
30 R7T17
R7T11 H8_PIN16 PE2/ETDI EC_ETDI 27 0 J8E4
14 H8_SCIF_TXD PE1/ETCK 31 EC_ETCK 27
0 5% 32 KBC_PE0 R7T14 NO_STUFF .
1
. PE0/LID3# 4.7K
H8S/2117 TFP144 +V3.3A_KBC 27,30,40 NOTE: Stuff R7T17 for
KBC_DISABLE# R8T12 KBC_DIS# D96714-001 write protect
2
0 5% R7T19
. Optional SPI Flash for testing only J8E1 0
R8T11 H8_PIN15 NO_STUFF
A 0 5% +V3.3 8,11,12,14,15,21..23,32,37,40,45,46 R9C4 PMU_4 H8 JTAG . Crown Beach A
1
R7T12
NO_STUFF
H8_PIN16 U9D1
0 5%
NO_STUFF J8E1 1-X
Intel Confidential
0 5% 8 VDD SI 5 SPI_DIN R9D2 H8_PIN115 (Default) Title
NO_STUFF 2 SPI_DOUT 0 5%
R9C2 SO
CE# 1 SPI_SELECT NO_STUFF Embedded Controller (1 of 2)
R8T8 SYS_PWRGD 3.3K 3 6 SPI_CLK R9D1 GPS_UART_RTS
0 5% WP# SCK 0 5%
.
. NO_STUFF
SPI_WP_HOLD 7 4 R9C3 GPS_UART_CTS
HOLD# VSS
28,40 PM_ALL_SYS_PWRGD
SST SPI FLASH
0 5%
NO_STUFF
A 1.5
NO_STUFF

5 4 3 2 1
5 4 3 2 1
+V3.3S 5..8,11,12,14..18,20..22,24,25,29,31,34,35,38,40,41,43..46,49..51,56..58
R8T3 1.40K 1%
EMA_ALS_CLK 17,26
R4R3 0 NO_STUFF
EC_THRM_DATA 14,26 +V3.3A 7,34,37,39,40,44..46,57
.
R8T4 1.40K 1%
EMA_ALS_DATA 17,26 +V3.3A_KBC 26,30,40
R4R2 0 .
5 ADI_THRM_DATA SMB_DATA 8,18,21,24,28,29,50
.
R7E2
+V3.3A_KBC 26,30,40
R4P7 0 . C7R1 C8T1 C7R2 C7T2
5 ADI_THRM_CLK SMB_CLK 8,18,21,24,28,29,50
0.01 1% C7E1 0.1uF 0.1uF 0.1uF 0.1uF
R7T8 1.40K 1% SMR0805 22uF 10% 10% 10% 10%
SMB_BS_DATA 26 . . . . .
D
. R4P8 0 NO_STUFF D
EC_THRM_CLK 14,26
R7T9 1.40K 1%
SMB_BS_CLK 26
.
R8T9 10K 5% +V3.3A_KBC 26,30,40
NMI_GATE 26,30
NO_STUFF
R7T6 10K 5% R9A1 SW9A1

EC_PA1 26
+V3.3A_KBC 26,30,40 10K 1
. 26 SMC_LID 2
R8E1 10K 5% . 3 LID JUMPER & SWITCH
KBC_PROG_TX# 26,28,34
2
NO_STUFF 4.7K 5% . R7T21
4.7K 5% . R7T18 J9A1 SPDT_SLIDE J9A1 1-X (Default)
R8R3 10K 5% 4.7K 5% . R7T15 R8U11 SW9A1 1-2 (Default)
EMA_ALS_INTR# 17,26 4.7K 5% . R7T16 SMC 10K .
1
. 4.7K 5% . R7T20 5%
5
.
28,30 SMC_RST# 1
U8U3 4 EC_RST# 26
2
J9F1
3
1 2 74AHC1G08 .
26 EC_ETCK
3 4 +V3.3A_KBC 26,30,40
26 EC_ETRST#
26 EC_ETDO 5 6
R8A1
7 8 10K VIRTUAL BATTERY JUMPER & SWITCH
SW8A1
26 VIRTUAL_BATTERY
9 10 . 1 J8A1 1-X (Default)
2
26 EC_ETMS SW8A1 1-2 (Default)
2
C +V3.3A_KBC 26,30,40 11 12 EC_MD2_R J8A1 3 SPDT_SLIDE C
26 EC_ETDI
R7E4 13 14 R8T14 .
1
0
5%
HEADER2X7 NO_STUFF
26 EC_MD2
8.2K J7E3
PM_SLP_S3#_PU 1
2 PM_SLP_S3# 8,28,40,45,46
26 PM_SLP_S3#_J 3
CON3_HDR
J7E3 2-3 (Default)
+V3.3A_KBC 26,30,40
FAB ID Strapping Table

+V3.3S 5..8,11,12,14..18,20..22,24,25,29,31,34,35,38,40,41,43..46,49..51,56..58
FAB REVISION
FAB_REV_ID BOARD FAB
1 0
R7T4 R7T2
C8D1 10K 10K 0 0 1
0.1uF Buffer to reduce 0 1 2
20% loading on RST# . . 1 0 3
. U8C1 1 1 4
5
1 R8D1
74AHC1G08 4 BUF_RST# 14,15,20,26,31,46
8,16,21,22,26,49,50 RST# 2 REV_FAB_ID1 26
100 5%
REV_FAB_ID0 26
R8C8
3
. 100K
B B
R7T3 R7T1
10K 10K
NO_STUFF NO_STUFF
+V3.3A_KBC 26,30,40
Thermal Monitoring R7R7 R7R8

R7R7 Enabled (Default) Stuffed Non-stuffed
. 100K
Disabled Non-stuffed Stuffed
FAN_ON 26
H_INIT# 3,6,20
R7R8
3 100K
J8D1
R8D5 NO_STUFF
2 1 1 Q8D1
26,30,40 +V3.3A_KBC 26,30,40 +V3.3A_KBC 1K 5% 2N3904
R8D3
. 100K 2
.
A H_A20M# 3 H_INIT# 3,6,20 A

R7T5 R7R6 R8T2 R8T1
Crown Beach
3
10K 10K 10K 10K

5%
NO_STUFF
5%
. Q7R2 .
5% 5%
. Q8R2 Intel Confidential
BSS138 BSS138
1 1 Title
Embedded Controller (2 of 2)
3
. .
2
Q7R1 Q8R1
BSS138 BSS138
26,28 H8_A20M# 1 26,28 H8_INIT# 1 Size Document Number Rev
. . A 1.5
2

5 4 3 2 1
5 4 3 2 1
D D
Note: Add-in card supplies this rail.

+V12_ATX 15,40,44,45
J7J3
B1 +V12_ATX_1 +V12_ATX_2 A1
B2 +V12_ATX_3 +V12_ATX_4 A2
B3 GND1 GND2 A3
B4 +V12_ATX_5 +V12_ATX_6 A4
B5 +V12_ATX_7 +V12_ATX_8 A5
8,14,15,26,49 SUS_CLK B6 SUS_CLK SCH_PWROK A6 SCH_PWROK 7,26,46
B7 GND3 GND4 A7
26,44 PM_SYSRST# B8 PSMI# PM_RSMRST# A8 PM_RSMRST# 7,26,46
B9 A20M# PM_RSMRST_PWRGD A9 PM_RSMRST_PWRGD 26,40,46
26,27 H8_A20M#
B10 GND5 GND6 A10
8,26 PM_RSTRDY# B11 RSTBTN# PM_SLPMODE A11 PM_SLPMODE 7,26
C 27,30 SMC_RST# B12 SMC_RST# PM_SLPRDY# A12 PM_SLPRDY# 7,26
C
B13 GND7 PM_RSTWARN A13 PM_RSTWARN 8,26
8,18,21,24,27,29,50 SMB_CLK B14 SMB_CLK PM_ALL_SYS_PWRGD A14 PM_ALL_SYS_PWRGD 26,40
8,18,21,24,27,29,50 SMB_DATA B15 SMB_DATA EXTSMI# A15 SMC_EXTSMI# 8,26
B16 PS_ON# IMVP_VR_ON A16 IMVP_VR_ON 26,41
26,44 SMC_SHUTDOWN
B17 PM_SUS_STAT# PM_IMVP_PWRGD A17 PM_IMVP_PWRGD 26,40
26,27 H8_INIT#
B18 GND8 GND9 A18
B19 PM_SLP_S3# FAN_PWR A19 FAN_PWM 5,26
8,27,40,45,46 PM_SLP_S3#
KEY
B20 PM_SLP_S4# SMC_RUNTIME_SCI# A20 SMC_RUNTIME_SCI# 8,26

26,40,45,46 PM_SLP_S4#
44 PS_ON# B21 SMC_ONOFF# INT_SERIRQ A21 INT_SERIRQ 7,21,26
7,20,21,26,49 LPC_FRAME# B22 LPC_FRAME# GND10 A22
B23 GND11 LPC_AD3 A23 LPC_AD3 7,20,21,26,49
7,20,21,26,49 LPC_AD2 B24 LPC_AD2 LPC_AD1 A24 LPC_AD1 7,20,21,26,49
7,20,21,26,49 LPC_AD0 B25 LPC_AD0 GND12 A25
B26 GND13 LPC_CLK A26 CLK_LPC_ALTEC 7
B27 LPC_RST# PM_CLKRUN# A27 PM_CLKRUN# 7,21,26
R8Y13 26 LPC_RST# KBC_PROG_TX_R# KBC_PROG_RX_R# R8J3
26,27,34 KBC_PROG_TX# B28 TX# RX# A28 KBC_PROG_RX# 26,34
B29 +V5SB_ATX_1 PM_PWRBTN# A29 PM_PWRBTN# 8,26
0 5% 40,44,45,56 +V5SB_ATX B30 A30 0 5%
+V5SB_ATX_2 PWR_SRC# PWR_SRC# 40,45
NO_STUFF NO_STUFF
60Pin_CardCon_H8_Bypass Rev 02
Note: Add-in card supplies this rail.
C77887-001
Note: Model has been changed from original.

Pin definition is different
B B
A Crown Beach A
Intel Confidential
Title
Embedded Controller Bypass

A 1.5

5 4 3 2 1
5 4 3 2 1
XDP
J1E3
1 GND0 GND1 2
3 XDP_BPM#5 3 OBSFN_A0 OBSFN_C0 4
D 3 XDP_BPM#4 5 OBSFN_A1 OBSFN_C1 6 D
7 GND2 GND3 8
3,48 XDP_BPM#3 9 OBSDATA_A0 OBSDATA_C0 10
3 XDP_BPM#2 11 OBSDATA_A1 OBSDATA_C1 12
13 14 +V1.05S_VTT_CPU 3,4,11,33,43,48,50
GND4 GND5
3 XDP_BPM#1 15 OBSDATA_A2 OBSDATA_C2 16
3,48 XDP_BPM#0 17 OBSDATA_A3 OBSDATA_C3 18
19 GND6 GND7 20
10,11,33,48,56 +V1.05S_SCH_VCORE R1E4 21 22 R1T3
OBSFN_B0 OBSFN_D0 1K
23 OBSFN_B1 OBSFN_D1 24 1%
25 26 NO_STUFF +V3.3S 5..8,11,12,14..18,20..22,24,25,27,31,34,35,38,40,41,43..46,49..51,56..58
C1E1 C1E2 56 5% GND8 GND9
27 OBSDATA_B0 OBSDATA_D0 28
0.01uF 0.01uF 29 30
10% 10% OBSDATA_B1 OBSDATA_D1 Layout note: R2U1 should
31 GND10 GND11 32
.402 .402 33 34 connect to H_CPURST# with C1T3 C1T1 C2T2 C1T2
OBSDATA_B2 OBSDATA_D2 no stub. 0.01uF 0.01uF 0.01uF 0.01uF
35 OBSDATA_B3 OBSDATA_D3 36
37 38 10% 10% 10% 10%
GND12 GND13 .402 .402 .402 .402
3 H_PWRGD_XDP 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40 CLK_XDP 24
6 H_TESTIN# 41 HOOK1 ITPCLK#/HOOK5 42 CLK_XDP# 24
43 VCC_OBS_AB VCC_OBS_CD 44
R1E3 . 1K 5% 45 46 RST_SNS1 R2E6 1K 1%
8,43 SLPIOVR# HOOK2 RESET#/HOOK6 H_CPURST# 3,6
47 48 R2T1 1K 5%
HOOK3 DBR#/HOOK7
49 GND14 GND15 50 .
XDP_DBRESET# 44
R1E2 0 NO_STUFF SMB_DATA_XDP 51 52 .
8,18,21,24,27,28,50 SMB_DATA SDA TDO XDP_TDO 8
R1E1 0 NO_STUFF SMB_CLK_XDP 53 54
8,18,21,24,27,28,50 SMB_CLK SCL TRSTN XDP_TRST# 3,8
55 TCK1 TDI 56 XDP_TDI 3
57 TCK0 TMS 58 XDP_TMS 3,8
8 XDP_TCK_1 59 GND16 GND17 60
R2E8
1
CONN60_ITP-XDP
J1D4 0 5%
. NO_STUFF
C LAYOUT NOTE: R1T1 C
2
56 J1D2
3 XDP_TCK_0
Place the XDP connector on the 5% R1T2 1
1
Default [1-X] primary side of the CRB and place 0 2
all components near the connector. 5% J1D3 XDP_TDO_CPU 3
3
NO_STUFF . Default [1-2]
1
CON3_HDR
2
J1F1 Default [1-2]
. XDP_TDI_SCH 8
TDE Option
2
Default [1-2]
B B
A Crown Beach A
Intel Confidential
Title
XDP

A 1.5

5 4 3 2 1
5 4 3 2 1
26,27,40 +V3.3A_KBC
14 14 14 14 R8R1
100K
J9D1
C8R1 R8E3 1M SMC_INIT_CLK1 1 2 SMC_INIT_CLK2 3 4 SMC_INIT_CLK3 5 6 11 10 SMC_INITCLK_J 1 2 SMC_INITCLK 26
0.1uF NO_STUFF
2
20% U8T1A U8T1B C8T2 U8T1C U8T1E NO_STUFF
3
U8R1 14 NO_STUFF 74HC04 74HC04 4.7uF 74HC04 74HC04 J8D4
Q9D1 7 NO_STUFF 7 NO_STUFF 10% 7 NO_STUFF 7 NO_STUFF
VCC
BSS138 NO_STUFF .
1
2 SMC_RST#_D R8D8 1K 9 8 SMC_RST 1 NO_STUFF SMC_INIT_CLK4 R8E4 SMC_INITCLK#
RST# 100K
GND
D U8T1D NO_STUFF D
3
74HC04 Boot Block
2
MAX809 7 NO_STUFF Q8E1 1Hz Clock J9D2 J8D4
Programming
1
BSS138 J9D2 Disable Shunt

1 NO_STUFF NORMAL 1-2 (DEFAULT)
SMC_RST# 27,28 26,27 NMI_GATE Enable No Shunt (Default)
NO_STUFF
1
Program 1-X
2
26,27,40 +V3.3A_KBC
Circuitry provides an interrupt to the SMC every 14
1s while in suspend (this allows the SMC to
complete housekeeping functions while R8R2 100 INVD2 13 12 TP_INVD2
suspended) NO_STUFF
U8T1F
74HC04
7 NO_STUFF
Spare gates
KBC_SCANOUT[15:0] 26
C C
J9D3
KBC_SCANOUT1 2 1 KBC_SCANOUT0
26,27,40 +V3.3A_KBC KBC_SCANOUT15 16 15 KBC_SCANOUT14 +V3.3A_KBC 26,27,40
18 17
20 19
22 21
+V5 8,12,14,15,21,23,32,36,37,44,45 KBC_SCANIN1 24 23 KBC_SCANIN0
KBC_SCANIN3 26 25 KBC_SCANIN2
2x15-SHD-HDR
.
Scan Matrix Key Board
2
KBC_SCANIN[7:0] 26
F1B1
3
1.1A
4
RP1N2C +V5 8,12,14,15,21,23,32,36,37,44,45

4.7K RP1N2D
PS2_PWR_L + 1
4.7K
CBTD has integrated
6
FB1N3 diode for 5V to 3.3V

5
KBD_CLK FB1N6 60ohm@100MHz 60ohm@100MHz voltage translation C1B5

1 KBD_DATA 0.1uF
CP1N1A 20%
B . B
47PF C1B3 U1B1
8 FB1B1 47pF
26 KBC_GP_DATA 3 1A1 VCC 24
31Ohm@100MHz 5% +V5 8,12,14,15,21,23,32,36,37,44,45 4
26 KBC_GP_CLK 1A2
7 2 GP_DATA
26 KBC_MOUSE_DATA 1A3 1B1
+V5 8,12,14,15,21,23,32,36,37,44,45 8 5 GP_CLK
26 KBC_MOUSE_CLK 1A4 1B2
3
11 6 MOUSE_DATA
26 KBC_KB_DATA 1A5 1B3
RP1N1C 9 MOUSE_CLK
1B4
L_KBD_DATA
L_PS2_PWR 4.7K 14 10 KBD_DATA

26 KBC_KB_CLK 2A1 1B5
17 2A2
4
FB1N1 18 15 KBD_CLK
L_KBD_CLK
RP1N1D 60ohm@100MHz 2A3 2B1

4 21 2A4 2B2 16
4.7K J1A2 GP_DATA 22 19
2A5 2B3
6 6 4 2 2 2B4 20
60ohm@100MHz C1B4 23
5
GP_CLK 47pF OE#_PS2 2B5

5 5 1 1 1 1OE#
13 2OE# GND 12
FB1N4 13 3 +V5 8,12,14,15,21,23,32,36,37,44,45
13 3 SN74CBTD3384
4 14 14
15 16 R1B2
15 16
2
CP1N1D 17 100
47PF 17 RP1N1B
10 10
5 4.7K
L_GP_CLK 12 8 L_GP_DATA
12 8
7
L_MOUSE_CLK 11 7 L_MOUSE_DATA MOUSE_DATA

11 7
9 3
+V5 8,12,14,15,21,23,32,36,37,44,45 60ohm@100MHz
DUAL_PS2 FB1N2 CP1N1C
9 47PF
1
6
RP1N1A
A 4.7K Crown Beach A
FB1N5
60ohm@100MHz
SPARE
+V5 8,12,14,15,21,23,32,36,37,44,45
Intel Confidential
8
MOUSE_CLK Title
2
2 RP1N2B RP1N2A PS/2

CP1N1B 4.7K 4.7K C1B1
C1B2 0.1uF
47PF 22uF 20%
7
7 .
A 1.5

5 4 3 2 1
5 4 3 2 1
5..8,11,12,14..18,20..22,24,25,27,29,34,35,38,40,41,43..46,49..51,56..58 +V3.3S
J4J3
IDE_D_PRST# 1 2
8 IDE_PDD[15:0] IDE_PDD[15:0] 8
IDE_PDD7 3 4 IDE_PDD8
5,12,17,33..35,40,41,44,45 +V5S IDE_PDD5 7 8 IDE_PDD10
R5J3 R5J4 IDE_PDD1 15 16 IDE_PDD14
8.2K 4.7K IDE_PDD0 IDE_PDD15
17 18
R4J5 19
D 10K +V5S 5,12,17,33..35,40,41,44,45 21 22 D
R4J6 5% 8 IDE_PDDREQ
. 8 IDE_PDIOW# 23 24
10K J4J2 25 26
5% 8 IDE_PDIOR#
. IDE_D_PRST#_J 1 2 27 28 IDE_PD_CSEL R5J5 470
8 IDE_PDIORDY
IDE_D_PRST
8 IDE_PDDACK# 29 30
6 . R5J2 31 32
220 8 INT_IRQ14 IDE_PATADET_CONN
8 IDE_PDA1 33 34
2 Q4J1B Preload Jumper 35 36
8 IDE_PDA0
3904 37 38 C5J2
8 IDE_PDCS1#
Default 1-2 IDE_PDACTIVE# R5J7 0.047uF
IDE_LED
. 39 40
1 15K 10%
20x2-RA-HDR 1% SMC0402
Preload 1-x NO_STUFF
3 R5J6 .
2
R4J7 10K
5% 8 IDE_PDCS3#
RST#_R_IDE 5 Q4J1A CR6J1 NO_STUFF
14,15,20,26,27,46 BUF_RST# 8 IDE_PDA2
3904 GREEN
10K 5%
. .
4 R4
1
IDE_PDACTIVE# 44 0
8 IDE_PATADET
5%
TP18 NO_STUFF
1 TESTPAD
OUTPUT ONLY
DO NOT PLUG ATX POWER SUPPLY HARD
C DRIVE POWER CONNECTORS INTO THIS CONNECTOR!!!!!!! C
5,16,17,33,35,45 +V12S
C3J5 J3J1
0.1uF C3J3
20% 10UF 1 12V
5,12,17,33..35,40,41,44,45 +V5S 2 GND1
R3J1 3 GND2
+V5S_PATA 4 5V
0.01_1%
SMR1206 4Pin_HD_PWR-CON
1
+ C3J1 C3J2 + C3J4
C4J1 0.1uF 0.1uF 15uF
100uF 20% 20% 20%
2
B B
A Crown Beach A
Intel Confidential
Title
PATA

A 1.5

5 4 3 2 1
5 4 3 2 1
8,11,12,14,15,21..23,26,37,40,45,46 +V3.3
8,12,14,15,21,23,30,36,37,44,45 +V5
USB_OC#4 8
3
RP2B1D RP2B1C
R3N1 10K 10K
0.01
1% U3N1 FB3N1
.
6
SMR0805 1 8 50OHM
+V5_USB_P3_P4 GND OC1# USBPWR_PORT4
2 IN OUT1 7
R3N3 1K 5%EN1_E 3 6 USBPWR_PORT3
C3N1 R3N2 1K 5%EN2_E EN1 OUT2
4 EN2 OC2# 5 USB_OC#3 8
0.1uF . FB2B1 + C2N2 + C3B4 Double USB
20% TPS2052B 50OHM C2A2 220uF C3B1 220uF
. 10% 470PF 10% Connector
D . 470PF D
. .
90@100MHz J3A1
+V5_USB_PORT4 1
USB_PORT4# VCC1 TOP
8 USB_PN4 2 3 2 P#0 PORT
USB_PORT4 3 9
P0 GND3
8 USB_PP4 1 4 4 GND1 GND4 10
GND5 11
L3B2 +V5_USB_PORT3 5 12
VCC2 BOTTOM GND6
1
USB_PORT3# 6
CR3B4 CR3B3 USB_PORT3 P#1 PORT
7 P1
8 GND2
Clamping-Diode Clamping-Diode
2
90@100MHz USB-PORTS
8 USB_PN3 2 3
8 USB_PP3 1 4
1
L3B1
CR3B2 CR3B1
2
J1A1
+V5_USB_CLIENT 1
L1M1 VBUS
1 4 USB_PORT2# 2
8 USB_PN2 USB-
2 3 USB_PORT2 3
8 USB_PP2 USB+
C C
1
90@100MHz 4 ID
1
5 GND
Clamping-Diode
2
USB,Mini-B
2
CR1M1 CR2M1
+V3.3 8,11,12,14,15,21..23,26,37,40,45,46
CR2M2 PORT 2 is designated for
client USB Validation.
8,11,12,14,15,21..23,26,37,40,45,46 +V3.3 RC Time Constant ~= 213 ms. R1A2

4.7K
R1A3
R6T12 8 SCH_GPIOSUS_3 100K
3
10K
Q1A1
. BSS138
USB_OC#2 8 1 USB_CLIENT_PWRDETECT# Table: USB Port Routing Locations
3
.
2
C1A1 Q2A1 USB Port Location
4.7uF BSS138
10% 1
. USB Port 0 Back of Chassis
.
USB Port 1 Back of Chassis
2
R1A1
100K USB Port 2 Back of Chassis
B B
USB Port 3 Back of Chassis
90@100MHz USB Port 4 Back of Chassis
2 3 USB Port 5 FPIO/Duckbay
15 USB_FP_PN0
USB Port 6 FPIO/Duckbay
1 4
15 USB_FP_PP0 USB Port 7 FPIO/Duckbay
1
L2B2
CR2B4 CR2B3 Double USB
Clamping-Diode Clamping-Diode Connector
2
90@100MHz J2A1
+V5_USB_PORT0 1
USB_PORT0# VCC1 TOP
8 USB_PN1 2 3 2 P#0 PORT
USB_PORT0 3 9
P0 GND3
8 USB_PP1 1 4 4 GND1 GND4 10
GND5 11
1
L2B1 +V5_USB_PORT1 5 12
CR2B2 CR2B1 USB_PORT1# VCC2 BOTTOM GND6
6 P#1 PORT
USB_PORT1 7
Clamping-Diode Clamping-Diode P1
8
2
GND2
USB-PORTS
8,11,12,14,15,21..23,26,37,40,45,46 +V3.3
+V5 8,12,14,15,21,23,30,36,37,44,45
2
A R2N1
0.01
RP2B1B RP2B1A Crown Beach A
1%
10K 10K Intel Confidential
.
SMR0805 U2N1 FB2N1 Title
7
1 8 USB_OC#0 8 50OHM
+V5_USB_P0_P1 2
GND
IN
OC1#
OUT1 7 USBPWR_PORT0 USB 2.0 (Back Panel)
R2N5 1K 5%EN1_P0P1 3 6 USBPWR_PORT1
C2N3 R2N6 1K 5%EN2_P0P1 EN1 OUT2
4 EN2 OC2# 5 USB_OC#1 8
0.1uF FB2B2
20%
.
TPS2052B 50OHM + C2B3 + C2N1
. 220uF 220uF
. C2B1
470PF 10%
C2A1
470PF 10% A 1.5
. .

5 4 3 2 1
5 4 3 2 1
5,16,17,31,35,45 +V12S +V12S 5,16,17,31,35,45
CR5G1
R5V9 BAT54A
0.01 V1.05A_BST_D 2 1 V1.05B_BST_D R5G1
1% 0.01
. 1%
SMR0805 .
3 SMR0805
V1.05A_INPUT +V5S 5,12,17,31,34,35,40,41,44,45
D V1.05B_INPUT D
1
C6F5 C6F7 C6F6 R6V7 C5G4 C5G5 C5G1
4.7uF 0.1uF 1000pF 1000pF 0.1uF 4.7uF
10% 10% 10% C5V7 10% 10% 10%
2
. . . 5 6 R6V8 C6V2 22 5% 1.0uF . . .
V1.05B_BST
C6V5 0 1.0uF . 20% C5V6
0.1uF 5%. 20% 402 0.1uF 6 5
10% .402 10%
V1.05A_BST
. R5V10 .
1
AGND_V1.05
Q6G1B EU6V1 . 0
4 R6V10 V1.05A_DH 17 5%
VCC
10 VDD .
8,11,12 +V1.05S_SCH FDS6994S R5G2 Q5G1B
5% FDS6994S
L6F1 . 23 BST1 BST2 13 4
10
Vout = 1.05V 3 V1.05A_PHASE_NODE V1.05B_DH 5% 11,24,34 +V1.05S_VTT
OCP = 4A
1 2 22 DH1 DH2 14 . L5F1 Vout = 1.05V
7 8
C6F4 C6F3 21 15 V1.05B_PHASE_NODE 3
1 2 OCP = 8A
330uF 0.1uF 2.2uH R6G1 LX1 LX2
20% 8 7
10% 22.6 2.2uH C5U9 C5F3
. 1% 330uF
. . 20 16 R5U50 0.1uF
R6U4 Q6G1A DL1 DL2 22.6 10% 20%
1% .
2.49K C6G1 2 R5U51 .
1% 1500pF FDS6994S Q5G1A . 4.75K
. 1%
10,11,29,48,56 +V1.05S_SCH_VCORE 10% MAX8717 2 FDS6994S C5U12 .
R6U3 . 1500pF +V1.05S_VTT_CPU 3,4,11,29,43,48,50
1 10% R5U49
2.49K 1% 29 .
GND 1
R6V2 C6U1 2K 1%
C6U2 1.82K . V1.05A_CSH 24
AGND_V1.05
1.0uF 1% 0.1uF 10% CSH1 . C5U10 R5V3 R5V6 C5V1

.
C 20% 25 CSL1 CSH2 12 V1.05B_CSH 1.82K
1%
1.82K
1%
1.0uF C
402 1V 0.1uF 10% NO_STUFF . 20%
. 48 V1.05S_SCH_VSET
NO_STUFF 26 11 402
FB1 CSL2 NO_STUFF
V1.05S_VTT_VSET 48 1V
C6V4 SCH_EN 6 10 .
C6V3 R6V6 1000pF ON1 FB2
1000pF 40.2K 10% VTT_EN 7 27 C5V5
1% . ON2 PGOOD1 PM_1.05S_SCH_PWRGD 40
10% . R5V2 1000pF R5V4 C5V4
. 5 9 10% 40.2K 1000pF
AGND_V1.05 FSEL PGOOD2 PM_1.05S_VTT_PWRGD 40 . 1%
0 5% . 10%
. 3 28 +V5S 5,12,17,31,34,35,40,41,44,45 .
AGND_V1.05 AGND_V1.05
R6V5 REF ILIM1 AGND_V1.05
R5U56 2 8
C6V1 SKIP1 ILIM2 AGND_V1.05 AGND_V1.05
0 5%
40 PM_1.05S_SCH_EN
PGND
AGND
0 5% . 4
. C5V3 0 5% SKIP2
0.1uF .R6V4 FSET= GND=200KHz
10% 0.1uF
REF f = 300KHz
18
19
NO_STUFF AGND_V1.05 . 10%
VCC f = 500KHz
AGND_V1.05
R5U55
R6G2
40 PM_1.05S_VTT_EN
0 5%
. C5V2 0 5%
0.1uF .
AGND_V1.05
10%
NO_STUFF
B B
A Crown Beach A
Intel Confidential
Title
Dual 1.05V VR

A 1.5

5 4 3 2 1
5 4 3 2 1
RS-232 TRANSCEIVER
+V3.3A 7,27,37,39,40,44..46,57
C6H5 C6H4
0.1uF 22UF
7,27,37,39,40,44..46,57 +V3.3A 20%
C5W4 U5H1 .
D 0.1uF C1+1 1
C1+ VCC 16
SERIAL PORT CONNECTOR D
.10% C5W5
C1-3 3 C1- 2 V_C_2 0.1uF
R5W1 C5W3 V+
.10%
10K 0.1uF C2+4 4 6 V_C_6 0.1uF
C2+ V-
.10% .10%
C2-5 5 C2- C5W2 2 7 FB6H1B SERPRT_RX_IN
12 13 RX_IN J6H1
26,28 KBC_PROG_RX# R1OUT R1IN
9 R2OUT R2IN 8 1 2
26..28 KBC_PROG_TX# 11 T1IN T1OUT 14 TX_OUT 1 8 FB6H1A SERPRT_TX_OUT 3 4
10 T2IN T2OUT 7 5 6
GND 15 7 8
9
MAX3232_RS232_TRNCVR
2X5-Header
3 6 FB6H1C .
4 5 FB6H1D
NOTE: USED FOR FACTORY PROGRAMMING OF EMBEDDED CONTROLLER 60OHM-100MHZ
VID COMPARATOR REFERENCE

C +V1.05S_VTT 11,24,33 C
SIO VID VOLTAGE TRANSLATION
R1B1
+V5S 5,12,17,31,33,35,40,41,44,45 +V5S 5,12,17,31,33,35,40,41,44,45 10K
1%
CAD NOTE: .
C2N4 Place C2N4 & C2P1 near C2P1
0.1uF 0.1uF VID_COMP
20% U2B1 & U2C1 20%
. .
3 3
U2B1A U2C1A R2B1
C2B2 10K
VID_COMP VID_COMP 0.1uF 1%
5 + 5 + .
2 SIO_VID0 2 SIO_VID4 20%
R2N4 VID_0_D 4 R2P2 VID_4_D 4 .
41 VR_VID0 - 41 VR_VID4 -
1K 1K
LM339 LM339
12 12
5..8,11,12,14..18,20..22,24,25,27,29,31,35,38,40,41,43..46,49..51,56..58 +V3.3S CPU VID LED

5,12,17,31,33,35,40,41,44,45 +V5S 5,12,17,31,33,35,40,41,44,45 +V5S
3 3 R1C1 R1C2 R1D1 R1D3 R1D4 R1D5 R1D6

U2B1B U2C1B 75 75 75 75 75 75 75
B VID_COMP 7 VID_COMP 7 B
LED_VID0
LED_VID1
LED_VID2
LED_VID3
LED_VID4
LED_VID5
LED_VID6
+ +
1 SIO_VID1 1 SIO_VID5
R2N3 VID_1_D 6 - R2P1 VID_5_D 6 -
41 VR_VID1 41 VR_VID5
1K 1K
LM339
LM339
12 12
2
5,12,17,31,33,35,40,41,44,45 +V5S
.
CR1C1 .
CR1C2 .
CR1D1 .
CR1D2 .
CR1D3 .
CR1D4 .
CR1D5
1
5,12,17,31,33,35,40,41,44,45 +V5S GREEN GREEN GREEN GREEN GREEN GREEN GREEN
3
3 U2C1C SIO_VID0
U2B1C
VID_COMP 9 + SIO_VID1
VID_COMP 9 + 14 SIO_VID6
14 SIO_VID2 R1N2 VID_6_D 8 - SIO_VID2
41 VR_VID6
R1N1 VID_2_D 8 - 1K
41 VR_VID2
1K SIO_VID3
LM339 LM339
12 SIO_VID4
12
SIO_VID5
5,12,17,31,33,35,40,41,44,45 +V5S SIO_VID6
5,12,17,31,33,35,40,41,44,45 +V5S LED Current = 16mA nominal
A 3 Crown Beach A
U2C1D Intel Confidential
3 Spare
U2B1D R2N9 10K U1B3D_SPARE 11 + Title
13 U1B3D_SPAREOUT
VID_COMP 11 + R2N10 10K U1B3D_SPARE# 10 -
Legacy Support
13 SIO_VID3
R2N2 VID_3_D 10 - R2N8
41 VR_VID3
1K LM339
12 10K Size Document Number Rev
12
LM339 NO_STUFF
A 1.5

5 4 3 2 1
5 4 3 2 1
5..8,11,12,14..18,20..22,24,25,27,29,31,34,38,40,41,43..46,49..51,56..58 +V3.3S
LAI fan support R1F3 R1F4 R1F1 R1F2

100K 75 100K 75
H_IERR#_LED CPU_MCERR#_LED
+V5S 5,12,17,31,33,34,40,41,44,45
D D
CPU_MCERR#_Q
2
2
J5H1 CR1F2 CR1F1
H_IERR#_Q
1 1 RED RED
2 2 . .
H_IERR#_LED_Q CPU_MCERR#_LED_Q
3 1
3 1
CONN2_HDR
.
Q1F3 Q1F1
BSS138 BSS138
1 1
R1F6 3 . R1F5 3 .
2
H_IERR#_D 1 Q1F4 CPU_MCERR#_D 1 Q1F2
3 H_IERR# 3 CPU_MCERR#
2N3904 2N3904
Chassis Fan Header +V12S 5,16,17,31,33,45 47K 2 47K 2
J3C3
1
2
3 CHASSIS_FAN_TACH
CON3,HDR,FAN C3C4
C74770-002 0.1uF
. 10%
SMC0402
.
C C
B B
A Crown Beach A
Intel Confidential
Title
LAI Fan Support - Debug LEDs

A 1.5

5 4 3 2 1
5 4 3 2 1
Discharge Selection Mode Selection

R5C5 R5C4 R5C15 R5C14, C5P5 & C5C5
Tracking Discharge (Default) STUFF NO_STUFF Current Mode NO_STUFF STUFF
Non-tracking Discharge NO_STUFF STUFF D_CAP Mode (default) STUFF NO_STUFF
+V12 45
DDR2 VREG R5C16
V12_1.8_INPUT
0.01 1%
SMR0805
.
C5C6 C6C5 C5P6
10uF 10uF 10uF R5C2
+V1.8 11,18,37 25V 25V 25V 0
.
AGND_DDR
D D
C5P2
R5C12 0 DDR_VBST_RC 0.1uF
+V0.9S 9,18,19 5% 16V .10% 6 5
.
R5R2
V0.9S_DDR2
0.01 1%
SMR0805
. Q5C1B NO_STUFF
DDR_DRVH_R R5C7 0 DDR_DRVH_RQ 4 FDS6994S TP6D1
C5C7 C5P4 C5C5 C5C3 5% +V1.8 11,18,37
10uF 10uF 10uF 1uF .
25V 25V 25V 20% L5P1 Vout = 1.8V
DDR_VBST_R
. DDR_LX2 3 Iout = 5.5A
1 2
8 7 1.0uH
C6P1 C6C4
Q5C1A 330uF 0.1uF
DDR_LDR2 R5C6 0 DDR_LDR2_RC 2 FDS6994S 20% .10%
5% 2.5V
. . 16V
+V5_FILT
1
24
23
22
21
20
19
R5C4 EU5C1
AGND_DDR
0 R5C15 DDR_CS_RC
VLDOIN
DRVH
LL
DRVL
VTT
VBST
0
NO_STUFF 1 18 +V5 8,12,14,15,21,23,30,32,37,44,45 C5P1 R5P1 +V5 8,12,14,15,21,23,30,32,37,44,45
VTTGND PGND 1000pF 8.25K
. 2 VTTSNS CS_GND 17
DDR_MODE_P2_HDR 3 16 5% 1%
GND CS .
4 MODE 15 .
C DDR_VTTREF 5 TPS51116 V5IN 14 C5C1 R5C3 C
11,18,37 +V1.8 DDR_COMP_RC VTTREF V5FILT 1uF 10
6 COMP PGOOD 13 5%
VDDQSNS
VDDQSET
R5C5 20% .
0 C5P3 . C5C2
0.033uF R5C14 1uF
NC1
NC2
. 5% 2.05K 25 20%
S3
S5
. 1% THRM .
NO_STUFF
+V5_FILT
7
8
9
10
11
12
AGND_DDR
DDR_COMP_RC2
AGND_DDR
C5P5 C5C4
PM_DDR_PWRGD 40
0.01uF 1000pF
10% 10%
NO_STUFF NO_STUFF PM_DDR_V1.8_EN 40
PM_DDR_VTT_EN 40
AGND_DDR 18,37 +V1.8_DIMM +V1.8 11,18,37

CAD NOTE: FEEDBACK NODE
R5P2
14K
1%
.
48 DDR_VSET 0.75V
R5P3
10K
1%
.
B B
A Crown Beach A
Intel Confidential
Title
DDR2 VR

A 1.5

5 4 3 2 1
5 4 3 2 1
NO STUFF BY DEFAULT (Spare circuit).

NO STUFF BY DEFAULT (Spare circuit for 1.05S PWR_GD monitor).
+V3.3 8,11,12,14,15,21..23,26,32,40,45,46
R8W3 100K 1%
40 PM_BYP_SUS_PWRGD
NO_STUFF
D 8,12,14,15,21,23,30,32,36,44,45 +V5 D
39,45,57 +V5A
12 +V1.05_SUS
R8V1 C8V1
14K 1.0uF R8V5 C8W1
1%
3
20% 0 0.1uF
NO_STUFF 8 5% U8W1A
402 Q8V1 10% +V3.3A 7,27,34,39,40,44..46,57
NO_STUFF 8
NO_STUFF 3 U8V1A BSS138 NO_STUFF LM393A
+ R8W9
1 1
2 NO_STUFF + 3 393_PIN3
-
1.05V 1.05V_SUS_REF 1 R8W6
2
LM358 +V1.05_SUS 12 2 6.81K 1% 15K
4 NO_STUFF - 1%
NO_STUFF
R7V8 8,11,12,14,15,21..23,26,32,40,45,46 +V3.3 NO_STUFF NO_STUFF
6.49K
1% 4 393_PIN2
NO_STUFF
1.05V_SUS_REF
C8V3 R8W1 C8W2
393_P2_DVIDR
0.1uF R8V2 R8W12 2.55K 0.1uF
1%
3
10% 1.40K 100K 1% 10%
NO_STUFF Q7V4 1% NO_STUFF NO_STUFF
R8V4 BSS138 NO_STUFF 39,45,57 +V5A NO_STUFF
14K 1 +V1.5_SUS 12
1% R8V9
NO_STUFF 0 U8W1B
NO_STUFF 8
2
5%
3
8 NO_STUFF LM393A R8V12
R8W13 3.24K
Q8V3 Q7V5 NO_STUFF
1.5V_SUS_REF U8V1B BSS138 BSS138 1%
5 + + 5
1.5V 7 1 1 1.5V_SUS_PWRGD 7 NO_STUFF
6 NO_STUFF - 6 6.81K 1%
-
C NO_STUFF NO_STUFF C
2
2
LM358 +V1.5_SUS 12
R8V3 4 NO_STUFF +V3.3A 7,27,34,39,40,44..46,57
11.5K 4
1%
NO_STUFF C8V4
0.1uF R8W7
10% 15K
NO_STUFF 1%
NO_STUFF
8,11,12,14,15,21..23,26,32,40,45,46 +V3.3
R8W11 C8W3
9.53K 0.1uF
1.5V_SUS_REF NO_STUFF 10%
R7G5 NO_STUFF
1K
5%
3
NO_STUFF
Q7V3 +V1.8_DIMM 18,36
BSS138
1 1.5V_SUS_EN#
8,12,14,15,21,23,30,32,36,44,45 +V5
3
NO_STUFF R7G2
2
1 V1.8_DIMM_SEQ
R7V6 1K 5%
0 2N3904 NO_STUFF
R6C8 5% 2
NO_STUFF Q7G1
10K NO_STUFF R7G3
2K
11,18,36 +V1.8 1%
10 NO_STUFF NO_STUFF
VDD+
B B
R6C10 2 U6C1A
10K -
1% TLV2463 VREF_DIMM1_MARG R6C2
1 M_VREF_SCH 9,48
5 OPAMP2_SHTDN# 0
3 NO_STUFF
48 M_VREF_SCH_IN +
R6C11
R6C4 C6C2 GND 10K
10K 0.1uF 4
1%
.10% .
Memory Reference Amplifiers

Pull down pin 5 (or pin 6) to disable
8,12,14,15,21,23,30,32,36,44,45 +V5 opamp channel. Output is Hi Z when
8,12,14,15,21,23,30,32,36,44,45 +V5 disabled.
C6C1
0.1uF R6C9 R6C3
10%
. 10K 0
11,18,36 +V1.8
10
VDD+ .
R6C12
A 10K
1%
8 - U6C1B
M_VREF_DIMM0 18,48 Crown Beach A
TLV2463 9
OPAMP1_SHTDN#
Intel Confidential
6
48 M_VREF_DIMM_A 7 + Title
C6C3 R6C7 PWRGD & DDR2 VREF
R6C5 0.1uF GND 10K
10K 4
1% .10%
NO_STUFF Size Document Number Rev
A 1.5

5 4 3 2 1
5 4 3 2 1
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,40,41,43..46,49..51,56..58 +V3.3S
D R5F18 D
V3.3S_1.5_INPUT
0.01 1%
1
SMR0805 R4F5
R4G6 0
. 10 C5G2
5% EU4F1 NO_STUFF
. 1.0uF 5%
20%
2
11 VCC VDD 4
C4G3 C4G5 402 . R4F6
1.0uF 470pF 18 0
20% 5% FBSEL1
.
402. . 10 17
COMP FBSEL0 5%
AGND_V1.5S
AGND_V1.5S 24 AGND_V1.5S
IN_1 C5F4 C5F5
7 PGOOD
40 PM_1.5S_PWRGD C5F6 10uF 10uF
IN_2 23
15 1.0uF 20% 20%
40 PM_1.5S_EN SHDN
2 20% . .
PGND_2
19 SKIP PGND_1 1
402 .
BST 20
MAX1515 C4F2 2.2uH +V1.5S 4..6,8,11,14,21,24
R4G5 L4F1
0.1uF
8 21 10% 1 2
TOFF LX_1 .
100K 5% 22 C5F1 + C5F2
LX_2 C4F1 10uF 220uF
. R4F1 1.0uF 20% 10%
C4G2 14 REFIN .
C 0 20% . C
13 NO_STUFF 402
REF2V 5% NO_STUFF
+V1.5S_SCH 10..12,56
1000pF
10% 3 9 C4G6
. IC FB 1.0uF
GND_BODY
16 20% R4G3
C5G3 MODE 15K
402
TP_SCH_VREF NO_STUFF 1%
6 5
GND
SS REFOUT AGND_V1.5S
.
AGND_V1.5S 0.01uF
25
12
10% 0.5V
.402 V1.5S_VSET 48
R4G7
AGND_V1.5S 40.2K
1%
.
R5F17
0 5% AGND_V1.5S
.
AGND_V1.5S
CAD NOTE: Place GND-AGND resistor on

secondary side near the controller
B B
A Crown Beach A
Intel Confidential
Title
1.5V VR

A 1.5

5 4 3 2 1
5 4 3 2 1
R3W12
AGND_51120
CAD NOTE: Place GND-AGND resistor on

secondary side near the controller
PM_5A_PWRGD 40
D R3W13 D
+V12A 44,45,57
VR_ALW_ENABLE 40,56
0 .
+V5A 37,45,57 VREF2
C3H9 R4W4
0.1uF V12A_5A_INPUT
10%
C3W4 NO_STUFF 0.01_1%
8 7
1
R3H8 C3H7 1000pF R3W15 C4W3 SMR1206
40.2K 1000pF 5% 0 0.1uF C4H6
1% 5% AGND_51120 10% 22uF
2
1V Q4W2A
AGND_51120 51120_DRVH1_R R4H4 51120_DRVH1_Q 2 FDS6994S
0
R3W10 R3H13 R3H11 +V5A 37,45,57
51120_EN1
10K +V5_LDO_FILT 0
1% 0 NO_STUFF 1 L4H1 R4H3 Icc-max=6A
51120_+V5A_MBL_Q 51120_+V5A_MBL_QL OCP=7A
51120_TONSEL
NO_STUFF 1 2
R3W14 6 5
0 3.3uH 0.002 1%
SMR2010
AGND_51120 AGND_51120 C3H8 .
1
51120_VBST1
51120_SKIPSEL 0.47uF C4H3 + C4W1 + C4H1
Q4W2B 0.1uF 220uF 220uF
51120_DRVL1_Q FDS6994S 10% 10% 10%
4 NO_STUFF
2
+V5_LDO_FILT R3H12
0
R3W9 3
NO_STUFF
0
32
31
30
29
28
27
26
25
EU3H1
C 33 C
DRVL1
SKIPSEL
TONSEL
PGOOD1
EN1
VBST1
DRVH1
LL1
AGND_51120 TH
+V12A 44,45,57
37,45,57 +V5A +V3_LDO 40
R3H7 C3H6 AGND_51120
9.76k_1% 470pF 1 24
NO_STUFF 5% VO1 PGND1 C4W4
NO_STUFF 51120_COMP1 2 23 51120_CS1_R R4W3 0.1uF
+V5_LDO_FILT_RC1 COMP1 CS1 14K 1% 10%
51120_VFB1 3 22
C3W3 VFB1 VIN
220PF VREF2 . +V5_LDO
NO_STUFF
4 VREF2 TPS51120 VREG5 21
5 20 +V5_LDO_FILT R4W2
GND V5FILT 49.9
R3H9 V3.3A_VSET C4W2 1% C4H5
6 VFB2 VREG3 19
AGND_51120 1.0uF 10uF
0 NO_STUFF 51120_COMP2 7 18 51120_CS2_R R4W1 C4H4 20% 20%
COMP2 CS2 12.4K 1% 10uF .402 .
R3H10 8 17 20%
VO2 PGND2 .
0 NO_STUFF PGOOD2 .
AGND_51120 +V12A 44,45,57
DRVH2
DRVL2
VBST2
R3H6 7,27,34,37,40,44..46,57 +V3.3A
EN5
EN3
EN2
LL2
0 R3W1
51120DRVH2_RQ
V12A_3.3A_INPUT
51120VBST2
9
10
11
12
13
14
15
16
1
C3W1 0.01_1%
C3H1 0.1uF SMR1206
51120VBST2_LR
5
6
7
8
22uF 10%
2
R3H4 C3W2 R3H3 R3G5 Q3W1
30.1K 100pF 51120DRVH2 4 IRF7811A
B 1% 40,56 VR_ALW_ENABLE B
NO_STUFF NO_STUFF 0 0 . +V3.3A 7,27,34,37,40,44..46,57
1
2
3
NO_STUFF C3H4
R4G14 Icc-max=7A
51120_VR_ALW_ENABLE
C3H5 0.47uF 51120VBST2_Q 1 2 OCP=8A

470pF L3G1
5% 40 PM_3A_PWRGD 3.3uH 0.002 1%
NO_STUFF SMR2010
5
6
7
8
1
. . C4G7 + C4V1 + C4G8
R3W8 Q4W1 CR3G1 0.1uF 330uF 330uF
100K 51120_DRVL2_Q IRF7822 10% 20% 20%
4 B320A
AGND_51120
.
1
2
3
2
R3W7
AGND_51120 1K
C3H2
0.1uF
48 V3.3A_VSET 10%
. V5 Output Mode Selection V3.3 Output Mode Selection
7,27,34,37,40,44..46,57 +V3.3A C3H6, R3H7 & R3W9 R3H9 C3H4, R3G8 & R3H1 R3H10
Fixed Output Mode NO_STUFF STUFF Fixed Output Mode NO_STUFF STUFF
AGND_51120 Adjustable Mode (default) STUFF NO_STUFF Adjustable Mode (default) STUFF NO_STUFF
Note: RC network for manually adjusting soft start delay
R3H2 C3H3 V5 Mode Selection V3.3 Mode Selection

23.7K 1000pF R3W9 R3H7, C3H6 & C3W3 R3H6 R3H4, C3W2 & C3H5
1% 5% Current Mode NO_STUFF STUFF Current Mode NO_STUFF STUFF
.
. D_CAP Mode (default) STUFF NO_STUFF D_CAP Mode (default) STUFF NO_STUFF
1V
A Crown Beach A
R3H1
10K
PROGRAMMING TABLE
PIN AGND VREF2 FLOAT +V5_LDO_FILT
Intel Confidential
1%
.
SKIPSEL
COMP
AUTO-SKIP
N/A
AUTO-SKIP FAULTS OFF
N/A
PWM FAULTS OFF
N/A
PWM
D-CAP MODE
Title
TONSEL(CH1/2) 380KHz/590KHz 290KHz/440KHz 220KHz/330KHz 180KHz/280KHz System Power VR
VFB1 N/A SHOULD NOT BE USED N/A 5V FIXED OUTPUT
VFB2 N/A SHOULD NOT BE USED N/A 3.3V FIXED OUTPUT
SWITCHER OFF SHOULD NOT BE USED N/A SWITCHER ON
AGND_51120 EN1,EN2
EN3,EN5 LDO OFF SHOULD NOT BE USED N/A LDO ON Size Document Number Rev
A 1.5

5 4 3 2 1
5 4 3 2 1
+V3.3_ATX 44,45
+V5SB_ATX 28,44,45,56
28,44,45,56 +V5SB_ATX
+V12_ATX 15,28,44,45
+V5_ATX 44
R1W2 R1W1 OP_PWR
3.0 3.0 C5J1
5% 5% R4J4 OP_PWR 0.1uF
. . 7.5K R4J3 .10%
1%
4
7.5K
. 8 1%
4
Q2V1 Q3V3 Q2V2 . 8
0.6_REF 3 U4J2A IRF1310NS IRF1310NS IRF1310NS Q1W1 Q2V3 Q2Y1 Q1V1 Q3W2
+
R1W3 R1V4 1 1 1 1 R4H5 Default [1-2] 0.75_REF 3 U4J1A IRF1310NS IRF1310NS IRF1310NS IRF1310NS IRF1310NS
10K +
3.0 3.0 2 . . . 1 1 1 1 1 1
- 5%
1
5% 5% C2V1 . 2 . . . . .
3
-
1
D D
. . Default [1-X] J4J1 R4J2 LM358 1.0uF C1W1
3
1K 4 10% L_5_G Q4H1 J5J2 R4J1 LM358 1.0uF L_12_G
. 1% . BSS138 1.33K 4 10%
. .
2
1% .
1 .
2
R1W4 R1V3 R2V8 R2Y1 R1V2 R3W11
3
3.0 3.0 OP_PWR R2V2 R3V4 R2V7 . 3.0 3.0 3.0 3.0
2
5% 5% 2.0 2.0 2.0 Q4H2 5% 5% 5% 5%
. . 8 5% 5% 5% BSS138 R1W5 . . . .
. . . 1 3.0
28,45 PWR_SRC#
5 U4J2B 5%
+
7 . .
2
R1W6 R1V1 6 -
3.0 3.0
5% 5% LM358
4
. .
OP_PWR
28,44,45,56 +V5SB_ATX 15,28,44,45 +V12_ATX TP5H1
4
CR4J1 8 NO_STUFF
2 1 Q5J1
5 U4J1B IRF1310NS
+
7,27,34,37,39,44..46,57 +V3.3A BAT54C 7 1 NO_STUFF
3 6 -
OP_PWR
3
LM358 R5J1
J5H4 4
0
R8V6 2 .
10K G1
5% S 1 5%
G3
G4
NO_STUFF 3 G2 SMA_SMT
R8V10 C51931-001
5
NO_STUFF R5H9 R5H8
37 PM_BYP_SUS_PWRGD
0 5% 51 1.0
8,11,12,14,15,21..23,26,32,37,45,46 +V3.3 NO_STUFF NO_STUFF 5%
NO_STUFF
C C
R8V11
100K
R8V8 5%
1K .
5%
.
R8V7 +V3.3A_KBC 26,27,30
36 PM_DDR_PWRGD PM_RSMRST_PWRGD 26,28,46
0 5%
.
39 +V3_LDO
R8W15
10K
5%
.
5,12,17,31,33..35,41,44,45 +V5S
R3W6
1K R8W14
5% 10K PM_IMVP_PWRGD 26,28
. 5%
3
.
R3W4 R8W4 Q8W5
1K BSS138
39 PM_5A_PWRGD 5%
0 5% . 1
39 +V3_LDO .
3
.
2
Q8W3
R3W2 BSS138
100K 1
5% 41,46 PM_DELAY_VR_PWRGD
R3W5 .
1K .
2
5%
NO_STUFF
R3W3
39 PM_3A_PWRGD PM_V5A3A_PWRGD 46
0 5%
. R5C8
B B
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,41,43..46,49..51,56..58
26,28,45,46 PM_SLP_S4# PM_DDR_V1.8_EN 36
0 5%
.
R5C10
R4G4 R5U52 0
1K
5% NO_STUFF
. 0 5%
. 5%
R4G2 R5C13
38 PM_1.5S_PWRGD 8,27,28,45,46 PM_SLP_S3# PM_DDR_VTT_EN 36
0 5% 0 5%
NO_STUFF .
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,41,43..46,49..51,56..58
R4G1
1K PM_1.5S_EN 38
C4G1
5% 0.1uF
.
R4V2 R5U53
1K 0 10%
5%
NO_STUFF NO_STUFF
R4V4 5% .
33 PM_1.05S_SCH_PWRGD PM_1.05S_SCH_EN 33
0 5%
.
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,41,43..46,49..51,56..58 R5U54
0
.
5%
R5V5
1K PM_1.05S_VTT_EN 33
5%
.
R5V7
A A
33 PM_1.05S_VTT_PWRGD
0 5%
PM_ALL_SYS_PWRGD 26,28
Crown Beach
.
Intel Confidential
R5V8
100K Title
5%
On Board ALWAYS VR Enable . ATX Power Supply Loads
R1J4
44 PM_ATX_PWROK VR_ALW_ENABLE 39,56
1K
A 1.5

5 4 3 2 1
5 4 3 2 1
Input Output S2 S1 S0
IMVP-6 CORE VR A C 1 1 0
B C 1 1 1
A D 1 1 1
B D 1 1 0
LAYOUT NOTE: PLACE Q2D1 AS CLOSE
Temperature Monitor TO PHASE FET AS POSSIBLE
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,43..46,49..51,56..58
D D
+V5S 5,12,17,31,33..35,40,44,45
Q2D1
1 GND1 TOVER# 5 H_PROCHOT# 3,8,48,50
2 GND2
3 4 R1P10 R1P8 R1P7 R1P5 R1P4 R1P2 R1P1 R1N3
HYST VCC C2D1 C2D2 100K 100K 100K 100K 100K 100K 100K 100K
MAX6501 2.2uF 0.1uF
10% 10% U1C1
. <NO_STUFF> 2 46 VR_VID0
50 IMVP-4STRAP_VID0 A0 C0
5 44 VR_VID1
8 41 VR_VID2
11 38 VR_VID3
13 36 VR_VID4
16 33 VR_VID5
18 31 VR_VID6
J1B1 21 A7 C7 28
23 A8 C8 26
R1P17 1K 5% 2 1
R1P32 . 1K 5% 4 3 3 45
4,50 H_VID0 B0 D0
R1P33 . 1K 5% 6 5 6 43
4,50 H_VID1 B1 D1
5,12,17,31,33..35,40,44,45 +V5S R1P34 . 1K 5% 8 7 9 40
4,50 H_VID2 B2 D2
R1P35 . 1K 5% 10 9 12 37
4,50 H_VID3 B3 D3
R1P36 . 1K 5% 12 11 14 35
4,50 H_VID4 B4 D4
R1P37 . 1K 5% 14 13 17 32
4,50 H_VID5 B5 D5
R1P38 . 1K 5% 16 15 19 30
4,50 H_VID6 B6 D6
R3C9 . 22 27
0.01 50 V3_S0 B7 D7 +V5S 5,12,17,31,33..35,40,44,45
1% 2X8_HDR 24 B8 D8 25
42 V12_CPU_PHASE . 5,12,17,31,33..35,40,44,45 +V5S
R2C2 SMR0805 J1B1 DEFAULT SHUNTS: V3_S0 1 7
8770_VCC V5S_IMVP_IN [1-2], [3-4], [5-6], [7-8], [9-10], [11-12], [13-14] R1P6 S0 VCC
C 48 S1 GND0 4 C
1% S2_S1 47 10
C2C2 10 1% C2C1 C3C3 J1B1 [15-16] : 10K S2 GND1 C1P1
140K 34 GND5 GND2 15
2.2uF 2.2uF 22uF Shorted for manual VID operation 5% 39 20 .01uF
R2B6 10% 10% 20% No Jumper for CPU driven VID operation (Default) GND6 GND3
. 42 GND7 GND4 29
4,5,42,43 +VCC_CORE EU2B1 SMC0805
. .
AGND_MAX
74CBT16209A
R2B7 71.5K
8770_BST1 42
C3B9 1%
470pF C3B10 8770_OSC
8770_DH1 42
5% 10% 1500pF 8770_TIME
NO_STUFF 8770_CCV
8770_LX1 42
8770_CCI
C3B8. 0.22uF 8770_REF
8770_DL1 42
10%
AGND_MAX
40,46 PM_DELAY_VR_PWRGD
34 VR_VID0
34 VR_VID1 Intel(R) CSP1 42
LX1_FBK 4,42
34 VR_VID2
34 VR_VID3
34 VR_VID4
VMP-6 TP_8770_DH2
+V5S 5,12,17,31,33..35,40,44,45
TP_8770_LX2
34 VR_VID5
34 VR_VID6
Controller
R3C8
0
26,28 IMVP_VR_ON 5%
TP_8770_DL2 .
7,21 PM_DPRSLPVR
TP_8770_BST2
B J2B1 3 PSI# B
8770_CSP2
3,6,21,50 H_DPRSTP#
1 2 CPU_PWR VCC_SNS_R
24 VR_PWRGD_CLKEN# 8770_VRHOT# 8770_GNDS
.
R2B10 R2B8
2.2K 10K 8770_FB C3N2
8770_THRM
1000pF
AGND_MAX
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,43..46,49..51,56..58 C3B12 10% Route to Die Sense Pins
+V3.3S 1000pF R3B9 R3B8 . as Differential Pair.
+V5S 5,12,17,31,33..35,40,44,45 10% 7.5K 3.74K
NO_STUFF 1% 1% AGND_MAX
R3N4 10
NO_STUFF . VSSSENSE 4
R2N7 8.25K 1% R3C11 0
. 5% 1%
8770_VCC J3C2
1
AGND_MAX
1 R3C10 VCC_SNS_R R3P1 10
C2N5 RT2N1 INTER# 1 Q3C1 1% VCCSENSE 4
2 INTER#_R
1000pF 100K 3 100K 5% BSS138
10% . NO_STUFF R3C1 27.4 1%
. CON3_HDR
2
2
NO_STUFF NO_STUFF
3
AGND_MAX
J3C1 Layout Note: use 27.4
Ohm routing for Vssense
C3B11 . and Vccsense
1
AGND_MAX
1000pF R3C2 27.4 1%
R3B10 0 10% NO_STUFF
Place R3B10 close to .
GND (Pin 18) Place near controller
AGND_MAX AGND_MAX
A A
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Intel Confidential
Title
IMVP-6 Controller

A 1.5

5 4 3 2 1
5 4 3 2 1
Cad Note:
D Needs Silk note next to each conn "VCORE PME". D
J3D2
1 3
2 4
2X2HDR
+V12S_CPU 6,43,45 .
J3C5
1 3
R2R8 .002 2 4
1W
SMR2512 C2C5 C3C8 C2C4 C2C6 C3C6 C3C7 C3C5 C3C10
0.01uF 0.01uF 0.01uF 0.01uF 47uF 47uF 47uF 4.7uF 2X2HDR
10% 10% 10% 10% 16V 16V 16V 20% .
V12_CPU_PHASE 41 .402 .402 .402 .402 NO_STUFF NO_STUFF
25V 25V 25V 25V
J3D1
R2C3
5
0 DH1_G D 1 3
41 8770_DH1
2 4
R2C1 G
0 8770_BST1_R 4 Q2C1 +VCC_CORE 4,5,41,43
41 8770_BST1 2X2HDR
HAT2168H
C2C3 S .
1
2
3
0.22uF
L2D1
10%
1 2 LX1_IND R3D2 .002 R3D1 .002
41 8770_LX1
0.88uH 1W 1W
D25752-001
9
D L2D2
LX1_FBK 4,41
8 1 2 R3R1
4 7 1.0uH 100 R3R2
41 8770_DL1 1%
CSP1_RT_R
G 6 NO_STUFF .
5 221 1%
nc .
RT3R1
S . FDS7088SN3 R3R3
1
2
3
EU2C1 1 2
221 1%
C3C1
1
C R3C5 CSP1_R
.
10K Place near
3
+ C3C9
330uF C
phase 1 20%
0 . 0.1uF 10% NO_STUFF .
2
. Inductor (L2D1)
41 CSP1
C3C2
4700PF
NO_STUFF
AGND_MAX
B B
A Crown Beach A
Intel Confidential
Title
IMVP-6 Core VR Phases

A 1.5

5 4 3 2 1
5 4 3 2 1
4,5,41,42 +VCC_CORE
Vcc Core Decoupling
Isolation resistor on the VR page

16 x 1uF (A36096-044) 0402
Place CPU Die Shadow - Secondary side
C3T20 C3T26 C3T28 C3T22 C3T31 C3T36 C3T40 C3T38 C3T21 C3T18 C3T41 C3T30 C3T42 C3T32 C3T27 C3T37
1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
.402 .402 .402 .402 .402 .402 .402 .402 .402 .402 .402 .402 .402 .402 .402 .402
D D
14 x 10uF (602433-075) 0603

Need to identify specific parts to meet ESR/ESL
Place between VR and CPU plane
C3T3 C3T11 C3T5 C3T6 C3T4 C3T2 C3T7 C3T15 C3T12 C3T8 C3T9 C3T10 C3T14 C3T13
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
<VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE> <VOLTAGE>
CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU
Place around the CPU socket
Three 330uF (C71589-001) Secondary Side

1
1
+ C3D1 + C3R1
3 330uF 3 330uF
20% 20%
. .
2
C C
Takasago Low ESL Capacitors
3,4,11,29,33,48,50 +V1.05S_VTT_CPU +VCCP1.05_CPU_C6_OFF 3,4
6,42,45 +V12S_CPU
C1E4
330uF
R2F11 2 20%
100K 2.5V 12 x 1uF (A36096-044) 0402
1% .
. Place CPU Die Shadow - Secondary side
B R2F3
B
3 C3T48 C3T52 C3T29 C3T47 C3T55 C3T39 C3T49 C3T35 C3T50 C3T53 C3T45 C3T25
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,44..46,49..51,56..58 +V3.3S 4 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF 1.0uF
R2F2 4
5
6
7
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6 1K . 5% 3 Q2F1 .402 402 .402 .402 402 .402 402 .402 402 402 .402 .402
R2F1
0 5% IRF6623 NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
1 .
0 5% Q2F3
1
2
NO_STUFF R2F5 IRF5851

3
100K C2F1
J2F1 1% Q2F2 0.1uF
. 8 x 0.1uF (A36096-043) 0402
IRLML2402 5 10%
1 Place CPU Die Shadow - Secondary side
2
8,29 SLPIOVR# 2 1 .
3
Default [1-2] C3T43 C3T33 C3T23 C3T34 C3T44 C3T46 C3T24 C3T54
2
Split Vtt Control CON3_HDR 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1-2 = GPIO controlled 10% 10% 10% 10% 10% 10% 10% 10%
2-3 = Force VCCP OFF R2F4 SMC0402
. SMC0402
. SMC0402
. SMC0402
. SMC0402
. SMC0402
. SMC0402
. SMC0402
Open = Force VCCP ON 1K NO_STUFF
5%
.
SLPIOVR# = 0(C6) => Switch OFF +VCCP1.05_CPU_C6_OFF = 0
SLPIOVR# = 1(Normal) => Switch ON +VCCP1.05_CPU_C6_OFF = +V1.05S_VTT_CPU
A Crown Beach A
Intel Confidential
Title
CPU Decoupling

A 1.5

5 4 3 2 1
5 4 3 2 1
Switch Control and On Board VR

Enable Circuitry
(see Notes for signal description)
28,40,45,56 +V5SB_ATX
28,40,45,56 +V5SB_ATX
D PS_ON# 28 D
R7W19
100K R8W5 R8W8
3
100K 100K
Q7W3 . .
BSS138
CR8V1
1 PS_ON_LATCH#
R7W20 3 1
R7H3 100K .
2
3
R7W17 0 . 5% NO_STUFF
BAT54
3
1K Q7W2
1 BSS138 . Q8W1 Q7W1
NO_STUFF 2 1 BSS138 BSS138
3 1 . 1 .
J7H4 2 . R7G9
51
2
5%
.
PWR_OPT
2
PS_ON_LATCH#
J7G1
NO_STUFF R7W8
3
C7W1 43K
1
Q8W6 1000pF .
BSS138 10%
1 . .
26,28 SMC_SHUTDOWN
2
28,40,45,56 +V5SB_ATX R7V7
100K
C . C
U8W2 C8W6
R8W18 1 GND VCC 4 . 0.01uF
100K 10%
POWER ON
and S5 PWR_BTN 2 3
IN OUT
ENTER/EXIT MAX6816
Button C8W5 1 R7H4
1uF R8W17 4.7K
20% CR8Y1 5%
.
NO_STUFF BAT54 0
System Reset Circuitry
3
4
NO_STUFF
SW3J1 SMC_ONOFF# 26 +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43,45,46,49..51,56..58
3 RESET
Push_Button R7H2 SW2J1
8.2K BUTTON
7,27,34,37,39,40,45,46,57 +V3.3A
1
2
PWR_BTN_FP# 5% R8Y8
. 1 3
2 4 10K
U8Y1 C8Y1 C8W7
Push_Button . 1 GND VCC 4 . 0.01uF 0.1uF
10% .10%
5
U8W3
2 3 MASTER_RESET#1
IN OUT
RSTBTNDB 4 PM_SYSRST# 26,28
1 MAX6816 2
CR8Y2 R8Y9 74AHC1G08
3
BAT54 100K
B B
ATX POWER 3 29 XDP_DBRESET#
ATX supply has ATX POWER +V5S 5,12,17,31,33..35,40,41,45

internal pull up
to 5V standby
40,45 +V3.3_ATX +V3.3_ATX 40,45 Front Panel Header +V5S 5,12,17,31,33..35,40,41,45
R7J1
330 +V5 8,12,14,15,21,23,30,32,36,37,45 R8J1
J3J2 +V5_ATX 40 330
J7J1
TP_-V12_ATX 13 1 +V5SB_ATX 28,40,45,56 FRONT1 FRONT2
14 2 1 2
15 3 31 IDE_PDACTIVE# 3 4
PS_ON# 5 6 C7J4
16 4 470pF
17 5 50 RST_PUSH#_D 7 8
+V12_ATX 15,28,40,45 +V12A 39,45,57 9 10
40 +V5_ATX 18 6
19 7 11 12
20 8 PM_ATX_PWROK 40 R1J3 13
TP_PS_LATCH# 15 16
21 9
22 10
23 11 .002 5% PWR_BTN_FP# 50
24 12 SMR2512
.
+V12_ATX 15,28,40,45 CON24_PWR C7J3 C7J5 C7J1
470pF 470pF 470pF C7J2
R2J1 470pF
ATX_DETECT# 26 ISENSE_POS 57
54.9 1%
J1J1
A 1 2 R7D6 R1J2 Crown Beach A
3 4 10K ISENSE_NEG 57 Intel Confidential
.
2X2HDR 54.9 1% Title
Start Up Sequence
C1J3 C1J4
470PF 470PF
A 1.5

5 4 3 2 1
5 4 3 2 1
7,27,34,37,39,40,44,46,57 +V3.3A +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43,44,46,49..51,56..58
S3 and S4 Rail Power 37,39,57 +V5A 5,12,17,31,33..35,40,41,44 +V5S
Switches 8 R4F4 8 R4G10

+V5 8,12,14,15,21,23,30,32,36,37,44
7 3 7 3
6 2 6 2 0.01_1%
5 1 0.002 1% 5 1 SMR1206 R4V7 5,12,17,31,33..35,40,41,44 +V5S +V12_SLOTS 21,22
+V12_ATX 15,28,40,44 Q4F1 SMR2010 97.6
IRF7811A . Q4G1 .SMR0805
R4G8
R4V1 .IRF7822
4
SLPS3#_CONTROL_R SLPS3#_CONTROL PS_S3BLEED
3
R4F2 R6B2 R7B1
3
R4V3 100K Q4V2 475 1% 10M 10M 10M
100K BSS138 R4V6 Q4V3
D 1 . C4G4 4.7K BSS138 D
5%
. 0.01UF NO_STUFF 1
PS_S3CNTRL . 10%
2
.
2
3
Q4V4
BSS138
8,27,28,40,46 PM_SLP_S3# 1
. +V3.3_SLOTS 22 +V12S 5,16,17,31,33,35 +V12 36

2
R4G13
100K
7,27,34,37,39,40,44,46,57 +V3.3A +V3.3 8,11,12,14,15,21..23,26,32,37,40,46
R8C1 R3C13 R1H4

+V5 8,12,14,15,21,23,30,32,36,37,44 10M 10M 10M
R4G9 R4G12
37,39,57 +V5A 0.01_1% 0.01_1%
SMR1206 SMR1206
8 8
7 3 7 3
6 2 6 2
5 1 5 1 R4V5
97.6
Q3G1 Q3G2 .SMR0805
+V12_ATX 15,28,40,44 IRF7811A IRF7822
R3G3
4
R3V2 PS_S4BLEED
SLPS4#_CONTROL_R SLPS4#_CONTROL
3
R3V1 100K 475 1%
3
C 100K R3V3 C
BSS138 . 4.7K Q3V2
PS_S4CNTRL Q3V1 C3G1 5% BSS138
1 NO_STUFF
0.1uF 1
3
. 10%
2
Q4V1 . .
2
BSS138
26,28,40,46 PM_SLP_S4# 1
.
2
R3G1
100K
+V12_ATX +V12_SLOTS 21,22
+V3.3_SLOTS
Q8W4
15,28,40,44 +V12_ATX 3 8 +V3.3_ATX 40,44 +V3.3_ATX 40,44

2 7
1 6
5 +V3.3_SLOTS 22 +V3.3_SLOTS 22
ATX vs. LPC card detect SI4425DY C9W1
0.33uF
4
+V5SB_ATX 28,40,44,56 0.33uF 100K Q8V2 Q8V4

PS_VBATSG
3 8 3 8
2 7 2 7
1 6 1 6
R9W2 5 C8V2 5 C9V1
4.7K C8W4 R8W16 SI4425DY 0.33uF SI4425DY 0.33uF
5% R8W10
.
4
100K
B 28,40 PWR_SRC#
B
1
PS_VBATSW
R8W2
100K
1%
. 2 3
Q8W2
BSS138
.
+V12S_CPU 6,42,43 +V12S 5,16,17,31,33,35

3
Q9V2
BSS138 R1H2 +V12A 39,44,57 +V12 36
8,27,28,40,46 PM_SLP_S3# 1
Q1H2 0.01_1% Q1H3
39,44,57
. +V12A 3 8 SMR1206 3 8
2
2 7 2 7
1 6 1 6
5 5
SI4425DY C1H2 SI4425DY C1J2
C1H3 R1H3 0.33uF C1H4 R1H5 0.33uF
4
0.33uF 100K 0.33uF 100K
C1H1 R1H1 C1J1 R1J1

A 0.1uF 0 0.1uF 0 Crown Beach A
10%
NO_STUFF
10%
NO_STUFF
Intel Confidential
. .
Title
3
Q1H1 Q1J1 Sleep Control

BSS138 BSS138
8,27,28,40,46 PM_SLP_S3# 1 26,28,40,46 PM_SLP_S4# 1 .
.
2
A 1.5

5 4 3 2 1
5 4 3 2 1
SYSTEM STATE LEDS
D D
7,27,34,37,39,40,44,45,57 +V3.3A
8,11,12,14,15,21..23,26,32,37,40,45 +V3.3
7,27,34,37,39,40,44,45,57 +V3.3A
2
Q8T4
2
1 SI2307DS
26,28,40,45 PM_SLP_S4#
Q7T2
1 SI2307DS .
8,27,28,40,45 PM_SLP_S3#
3
R8Y12 PP_S4LEDSW1
75 . 75 ohms chosen for R8E13
3
~16mA of LED current 75
R8E15
PP_SCH_RSMRSTLED 75
R7E3 PP_AlwaysPGLED
75
2 GREEN
2
PM_RSMRST CR8J2 PP_S4LED
2
Always_Powergood CR8E4
GREEN PP_S3CLED CR8E5
S4/S5
3 1
GREEN
2
S3
1
CR7E1
1
Q8Y1
BSS138 GREEN PP_AlwaysPGLEDSW
3
7,26,28 PM_RSMRST# 1
1
PP_S3ALED Q8T5
. BSS138
2
3
C 40 PM_V5A3A_PWRGD 1 C
Q7T1
BSS138 .
2
26,28,40,45 PM_SLP_S4# 1
2
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..45,49..51,56..58 +V3.3S
R8E16
75
7,27,34,37,39,40,44,45,57 +V3.3A
PP_PGLED
.
GREEN
2
Reset CR8E6
R8F27 R8J2 R8Y10 R8E17

75 75 75 75
1
3
PP_IMPVLED PP_SCHPWRGDLED PP_PMRSMRSTLED PP_S0LED
. . .
Q8T6 GREEN
2
GREEN GREEN GREEN BSS138
B B
2
2
PM_DELAY_VR_PWRGD 1 S0 CR8E7
14,15,20,26,27,31 BUF_RST#
CR8F1 SCH_PWROK CR8J3 PM_RSMRST_PWRGD CR8J1
.
3 1
PP_S0LEDSW
1
1
Q7T3
3
3
BSS138
Q8G1 Q8Y2 Q8Y3 1
8,27,28,40,45 PM_SLP_S3#
BSS138 BSS138 BSS138
40,41 PM_DELAY_VR_PWRGD 1 7,26,28 SCH_PWROK 1 26,28,40 PM_RSMRST_PWRGD 1 .
2
. . .
2
7,27,34,37,39,40,44,45,57 +V3.3A
ATX Mounting Holes J6A1

1 2 PP_S3ALED
PP_S0LEDSW
A 3
5
4
6 Crown Beach A
MT1B1 MT1J1 MT1G1 MT6A1 MT8A1 MT6G1 MT6J1 MT8G1
PP_S3CLED 7 8 PP_S4LEDSW1 Intel Confidential
1 1 1 1 1 1 1 1 8Pin HDR Title
2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 C77978-003
3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 ATX Mounting Holes - LEDs
4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8
5 9 5 9 5 9 5 9 5 9 5 9 5 9 5 9
MT_N156 MT_N156 MT_N156 MT_N156 MT_N156 MT_N156 MT_N156 MT_N156 Size Document Number Rev
NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF NO_STUFF
A 1.5

5 4 3 2 1
5 4 3 2 1
CROWN BEACH VV/CEB Power On Sequence v0.9 1) ATX supply plugged in (a). ATX
PS_ON# clamped low for always "on".
Power Supply Inserted PM_ATX_PWROK asserted once the power
power button latch power only rails are stable (b). PM_ATX_PWROK is
+V12_ATX 1a +V5SB_ATX enable for the TPS51120 to begin
+V3.3_ATX
2a PG 44 regulation of +V5A & +V3.3A (c). The
+V5_ATX H8 has it's own power good indicator
D SMC_ONOFF# from MAX809 (d). D
only 3 rails used PG 43

Min delay from 95% PS_ON# 2) Power Button pressed (a) which
Power-on jumper options: +V3.3A
voltage of rails is 100ms
max delay is 500ms PM_ATX_PWROK
1b 1) PS_ON# tied to GND so momentarily asserts SMC_ONOFF# (b).
when plugged in ATX
MAX-809 2b Battery charger
1c
supply is always on
1d 140ms delay and docking in S4/S5 for EC 3) H8 de-asserts PM_SLP_S4# (a) +V5 &
+V5A 2) PS_ON# tied to latch PG 30 +V3.3 pass (b) +V3.3 is used to
+V12A PG 37 generate +v1.05SUS and +V1.5SUS if the
ATX off until button press +V3.3A +V3.3_SCH
TPS +V3.3A 2nd button press powers on SCH/POULSBO 3c SCH internal VReg is broken and +V1.8
board. Pwr button press again RES# begins regulation (c). PM_RSMRST_PWRGD
51120 shuts off board and ATX supply SUS +V1.5_SUSBYP_SCH
+V1.05_SUSBYP_SCH
signifies that the 1.8V rail is "good".
PM_VR_ALW_EN
EN# PGD PM_V5A3A_PWRGD H8 SMC SCH_RSMRST# 4a Rails
(if needed)
PG 26
3b 4b SUS_CLK 4) H8 de-asserts SCH_RSMRST# after
SLP_S4# RST# 7c receiving PM_RSMRST_PWRGD (a). SCH
+V12A de-asserted +V12 5ms
DELAY
100us
DELAY PM_RSTWARN 7b begins driving SUS_CLK (b).
C PASS 3d C
+V5A +V5 20us 5) H8 de-asserts PM_SLP_S3# (a).
FETS PM_RSMRST_PWRGD 5ms DELAY
SCH_PWROK 7a 8 H_PWRGD
DELAY
PWROK +V0.9, +V5S, +V3.3S go active as
+V3.3 well as +V12_SLOTS and +V3.3_SLOTS
+V3.3A PG 45 2-20 BCLKS DELAY ; +V1.5S, +V1.05 (SCH & VTT) go
99ms DELAY
active (b). PM_ALL_SYS_PWRGD is
asserted to the SCH (c).
+V3.3 +V1.05_SUS 3a
PM_SLP_S4#
PM_SLP_S3# 5ms DELAY

5a
PM_ALL_SYS_PWRGD
LM358 +V1.5_SUS from CLKEN# to 6) H8 asserts IMVP_VR_ON (a).
Backup for Linear PWRGD Controller ramps to the 1.20V boot
SCH internal 6d PM_IMVP_PWRGD voltage (b). Controller asserts
VR 'broke' VR_PWRGD_CLKEN# ~60usec later (c).
Include option for
de-pop and still
3c IMVP_VR_ON Controller releases PM_IMVP_PWRGD (from
get correct PGD holding it low) 5msec later (d).
6a +VCC_CORE 6b
+V12 PG 36 +V1.8 3b 7) SCH_PWROK is asserted (a). H8 waits
B +V0.9 at least 20usec before asserting B
TPS CPU
51116 PM_RSTWARN to SCH (b) and then another
PM_DDR_V1.8_EN
EN1.8
5b System VR_PWRGD_CLKEN# Vreg 100usec from PM_RSTWARN assertion
PM_DDR_VTT_EN PGD Clock IMVP-VI before asserting RST# to the SCH (c).
EN0.9
5b 5c PG 24 PG 41-43
3c +V1.5S 6c
+V3.3S PG 38
8) SCH asserts H_PWRGD to the CPU.
SLP_S3# 5b MAX
1515
de-asserted +V12S PM_1.5S_EN PM_1.5S_PWRGD
+V12A EN# PGD
+V5A
PASS +V5S
FETS +V12S +V1.05S_SCH
+V3.3A PG 45 +V3.3S
O1 +V1.05S_VTT
MAX
O2
8717 5b
PM_1.05S_SCH_EN
EN1# PGD1 PM_1.05S_SCH_PWRGD
A
5b PM_1.05S_VTT_EN Crown Beach A
EN2# PGD2 PM_1.05S_VTT_PWRGD Intel Confidential
SLP_S3# Title
+V12_ATX de-asserted +V12_SLOTS PG 33
Power Sequencing Timing Block Diagram
PASS
+V3.3_ATX FETS +V3.3_SLOTS Size Document Number Rev
A 1.5
PG 45
5 4 3 2 1
5 4 3 2 1
J5C1 C51931-001 J6G1 C51931-001

2 R5C11 2 R6V3
G1 G1
S 1M_VREF_DIMM_A_VREFIN M_VREF_DIMM_A 37 S 1 +V1.05S_SCH_VREFIN
V1.05S_SCH_VSET 33
0 5% 4.7K 5%
G3
G4
G3
G4
3 G2 3 G2
SMA_SMT SMA_SMT
18,37 M_VREF_DIMM0 J6C3 10,11,29,33,56 +V1.05S_SCH_VCORE R6V1 J6F2
4
5
. 1 2 . +V1.05S_SCH_J 1 2
0 5%
D D
J6C1 C51931-001 . J4G1 C51931-001 .
2 R6C6 2 R4G11
G1 G1 .
S 1M_VREF_SCH_VREFIN M_VREF_SCH_IN 37 S 1 +V1.5S_SCH_VREFIN
V1.5S_VSET 38
0 5% 4.7K 5%
G3
G4
G3
G4
3 G2 3 G2
SMA_SMT SMA_SMT
9,37 M_VREF_SCH J6C2 7,10,11,56 +V1.5S_PCIE_SCH R6C1 J6C4
4
5
. 1 2 . +V1.5S_PCIE_SCH_J 1 2
0 5%
. J4C2 C51931-001 .
2 R5C9
G1 +V1.8_VREFIN .
S 1 DDR_VSET 36
20K 5%
G3
G4
3 G2 SMA_SMT .
10,11,56 +V1.8_SM_SCH R5C1 J5C2
5
+V1.8_SM_J 1 2
0 5%
J4F3 J3H1 C51931-001 .
C 2 R4T11 2 R3H5 C
G1 G1 .
S 1GTL_FSB_A_VREFIN H_GVREF 6 S 1 +V3.3A_VREFIN
V3.3A_VSET 39
0 5% 20K 5%
G3
G4
G3
G4
3 G2 3 G2
SMA_SMT SMA_SMT .
C51931-001 J4F2 10..12 +V3.3S_SCH R3G4 J3G2
4
5
. 1 2 +V3.3S_SCH_J_P1 1 2
0 5%
J4C3 . J5G1 C51931-001 .
2 R4T10 2 R5V1
G1 G1 .
S 1GTL_FSB_D_VREFIN H_CGVREF 6 S 1 +V1.05S_VTT_VREFIN
V1.05S_VTT_VSET 33
0 5% 4.7K 5%
G3
G4
G3
G4
3 G2 3 G2
SMA_SMT SMA_SMT
C51931-001 J3C4 3,4,11,29,33,43,50 +V1.05S_VTT_CPU R4F3 J4F4
4
5
. 1 2 . +V1.05S_VTT_J 1 2
0 5%
J1C3 . .
2 R1E10
G1 .
B S 1XDP_BPM#3_EV XDP_BPM#3 3,29 B
0 5%
G3
G4
3 G2 SMA_SMT
C51931-001
4
J1D1
2 R1T4
G1
S 1XDP_BPM#0_EV XDP_BPM#0 3,29
0 5% J2E2 R2E13 NO_STUFF
G3
G4
3 G2 SMA_SMT 1 2 H_SMI_R_HDR
H_SMI# 3,6,21
C51931-001 0 5%
4
. NO_STUFF
J1C2
2 R1D2
G1
S 1H_PROCHOT#_EV H_PROCHOT# 3,8,41,50
0 5%
G3
G4
3 G2
A SMA_SMT Crown Beach A
C51931-001 Intel Confidential
4
. Title
EV Voltage Margining - Validation Only
ALL 2 pin HEADERS on this page are for Size Document Number Rev
A 1.5
measurement only, do not shunt
5 4 3 2 1
5 4 3 2 1
PORT 80-83 DISPLAY High Nibble (CR7B2) Port 80/82 High Nibble (CR7B1) Port 81/83
Low Nibble (CR7B3) Port 80/82 Low Nibble (CR6B1) Port 81/83
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,50,51,56..58 +V3.3S
RP7N1D 4 5 150 LED_SEGDP
C7N1 Note: only one decoupling cap

D 0.1uF required since only one display D
5
3
8
5
3
8
5
3
8
5
3
8
20% is enabled at any given time CR7B2 CR7B3 CR7B1 CR6B1
.
DP
DP
DP
DP
CT
COM
CT
COM
CT
COM
CT
COM
G
G
C
D
C
D
C
D
C
D
A
B
A
B
A
B
A
B
E
F
37SEG_LED_CT3
37SEG_LED_CT1
37SEG_LED_CT4
37SEG_LED_CT2
7
6
4
2
1
9
10
7
6
4
2
1
9
10
7
6
4
2
1
9
10
7
6
4
2
1
9
10
RP7N2B 2 7 150 LED_SEGA
RP7N2A 1 8 150 LED_SEGB
RP7N1C 3 6 150 LED_SEGC
RP7N1B 2 7 150 LED_SEGD
RP7N1A 1 8 150 LED_SEGE Q8N4 Q7N1 Q8N1 Q8N2
RP7N2C 3 6 150 LED_SEGF BSS138 BSS138 BSS138 BSS138
RP7N2D 4 5 150 LED_SEGG 1 1 1 1
. . . .
2
LED_MUX_HI81
LED_MUX_HI80
C LED_MUX_LO81 C
LED_MUX_LO80
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,50,51,56..58 +V3.3S
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,50,51,56..58 +V3.3S
Port J8B1
LPC_FRAME# 7,20,21,26,28 Shunt
82 - 83
2
C8N2 C8N1 U8B1 R9N1
0.1uF 10uF J8B1 80 - 81 No Shunt (Default) C9N1 10K
9 VCC1 IO32 44
20% 20% 17 43 PORT82_EN# 0.1uF
. . VCC2 IO31 PLD_PD R8N2 20% 5%
29 42 . .
1
VCC3 IO30 10K . R8N1
41 VCC4 IO29 35 5%
3
34 10K
IO28 . 5%
33 J9B3 . Q8N3
IO27 LED_SEGA BSS138
TDO/IO26 32 1 2
31 LED_MUX_HI81 3 4 LED_SEGB 1
IO25 LED_MUX_LO81 LED_SEGC
IO24 30 6
37 28 LED_MUX_HI80 7 8 LED_SEGD .
7 CLK_LPC_PORT80
2
GCLK1 IO23 LED_MUX_LO80 LED_MUX_HI81 9 LED_SEGE
8,16,21,22,26,27,50 RST# 39 GCLR# IO22 27 10
26 LED_MUX_HI80 11 12 LED_SEGF
TCK/IO21 LED_MUX_LO81 13 LED_SEGG
IO20 25 14
OE#_PORT80 38 23 LED_MUX_LO80 15 16 LED_SEGDP
OE1 IO19
8,14,15,26,28 SUS_CLK 40 OE2/GCLK2 IO18 22
21 LED_SEGA 2X8_Header_K5
R8N3 IO17 LED_SEGB
IO16 20
100 19 LED_SEGC
IO15 LED_SEGD
IO14 18
. 15 LED_SEGE
B IO13 LED_SEGF B
IO12 14
13 LED_SEGG
IO11 LED_SEGDP
IO10 12
IO9 11
IO8 10
IO7 8
TMS/IO6 7 LPC_AD[3:0] 7,20,21,26,28
6 LPC_AD3
IO5 LPC_AD2
4 GND1 IO4 5
16 3 LPC_AD1
GND2 IO3 LPC_AD0
24 GND3 IO2 2
36 GND4 TDI/IO1 1
EPM7064AE
A88816-002
A Crown Beach A
Intel Confidential
Title
Port 80-83 - Validation Only

A 1.5

5 4 3 2 1
5 4 3 2 1
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58
J2C1 R2P3
H_STPCLK# 3,6
1 24 +V1.05S_VTT_CPU 3,4,11,29,33,43,48 4.7 5%
4,41 H_VID0 CPU_VID0 VCC3_3V
2 43 R2P10
4,41 H_VID1 CPU_VID1 VTT_FSB_1
4,41 H_VID2 3 CPU_VID2 VTT_FSB_2 44
4 100K 5% .
4,41 H_VID3 CPU_VID3
3
5 .
4,41 H_VID4 CPU_VID4
6 15 R2P9 Q2P2
4,41 H_VID5 CPU_VID5 P0_TEST1 ACLKPH 3 100K
8 17 BSS138
4,41 H_VID6 CPU_VID6 P0_TEST2 DCLKPH 3 5%
10 9 . H_STPCLK 1
CPU_VID7 P1_TEST1
P1_TEST2 11 3
14 R2P8 .
2
41 IMVP-4STRAP_VID0 VID_OVRD0 STPCLK_DRV# MAN_STPCLK_R#1 Q2P1
16 VID_OVRD1 SMB_SCL 28 SMB_CLK 8,18,21,24,27..29
41 IMVP-4STRAP_VID1 2N3904
18 VID_OVRD2 SMB_SDA 30 SMB_DATA 8,18,21,24,27..29
41 IMVP-4STRAP_VID2 . 1K 5%
20 VID_OVRD3
41 IMVP-4STRAP_VID3 2
D 41 IMVP-4STRAP_VID4
21 VID_OVRD4 P0_SST_LV# 34 D
22 VID_OVRD5
41 IMVP-4STRAP_VID5 H_STPCLK#_R R2P4 TP1C1
23 VID_OVRD6 STPCLK# 25 H_STPCLK# 3,6
41 IMVP-4STRAP_VID6 STPCLK_DRV# 0 5%
26 VID_OVRD7 STPCLK#_OVRD 27
33 H_PROCHOT#_R R2D1 . NO_STUFF +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58
P0_PROCHOT# H_PROCHOT# 3,8,41,48
12 35 PROCHOT_DRV# 0 5% R2E9
41 V3_S0 VID_SRC_SELECT P0_PROCHOT#_OVRD H_PROCHOT# 3,8,41,48
56 PM_THRMTRIP#_R R2D2 . 4.7 5%
P0_THERMTRIP# PM_THRMTRIP# 3,6
45 29 H_CPUSLP#_R R2D4 0 5% R2P7
3,24 CPU_BSEL0 CPU_BSEL0 SLP# H_CPUSLP# 3,6,21
47 31 CPU_SLP_DRV# 0 . 5%
3,24 CPU_BSEL1 CPU_BSEL1 SLP#_OVRD .
46 32 H_DPSLP#_R R2T4 . 100K 5%
3,24 CPU_BSEL2 CPU_BSEL2 DPSLP# H_DPSLP# 3,6,21
3
59 DPSLP_DRV# 0 5% .
BSEL_OVRD0 DPSLP#_OVRD H_DPRSTP#_R R2R4 . R2P6 Q2P4
38 BSEL_OVRD0 DPRSTP# 58 H_DPRSTP# 3,6,21,41
BSEL_OVRD1 40 57 DPRSTP_DRV# 0 5% 100K BSS138
BSEL_OVRD2 BSEL_OVRD1 DPRSTP#_OVRD H_PWRGD_R R2C5 . 5% H_PROC 1
42 BSEL_OVRD2 CPU_PWRGD 48 H_PWRGD 3,6,21 .
50 0 5% 3
ADC_DATA CPU_PWRON_ENA . R2P5
53 60 RST# 8,16,21,22,26,27,49 .
2
ADC_CLK VCORE_SDATA PLT_RST# PROCHOT_DRV# MAN_PROC_R# 1 Q2P3
51 VCORE_SCL
ADC_CS# 55 52 2N3904
VCORE_CS FP_PWR_BTN# PWR_BTN_FP# 44
54 . 1K 5%
FP_RST_BTN# RST_PUSH#_D 44 2
36 JA_OE
MANARA_PRSNT# 49 MANARA_PRSNT# BSEL_OVRD#
GND_1 7
CK_FSA_CLK_RMUX
GND_2 13
39 19 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 +V3.3S +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58
SPARE_PULL_DOWN GND_3 R2D3
41 NC GND_4 37 H_CPUSLP# 3,6,21
4.7 5%
16
1
U8U1A R2P13
R2C4 60 Pin_RCPTCL_Shrouded - MANARA BSEL_OVRD0 2
10K A .
A/B 4 R8U7 CK_FSA_CLK 100K 5%
5%
3
Y
NO_STUFF C21100-002 3 G 10K 5% .
51 CK_FSA_MUX B
. R2P12 Q2P7
SN74LV157AD R8U8 100K BSS138
8
15
5%
C +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 4.7K
5% . MAN_SLP 1 C
. 3
R2P11 .
2
BSEL_OVRD# CPU_SLP_DRV# MAN_CPUSLP_R#1 Q2P5
CK_FSB_CLK_RMUX
2N3904
R1P3 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 +V3.3S . 1K 5%
8.2K R1P9 2
NO_STUFF 100K
16
5%
1
J1C1 . U8U1B
BSEL_OVRD1 5 A
3 A/B 7 R8U9 +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58
Y CK_FSB_CLK 24
2 BSEL_OVRD# 6 G 10K 5% R2T3
51 CK_FSB_MUX B H_DPSLP# 3,6,21
1 . 4.7 5%
41 V3_S0
SN74LV157AD R8U14 R2R3
8
15
Note: 4.7K
2-3 Manara drives with VIDs 5% 100K 5% .
.
3
1-2 Manara always drives BSELs when present (Default) .
1-X Jumper / CPU always drives BSEL_OVRD# R2R2 Q2P8
100K BSS138
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 +V3.3S 5% MAN_DPSLP 1
.
3
R2R1
16
.
2
1
U8U1C DPSLP_DRV# MAN_DPSLP_R# 1 Q2P6
CK_FSC_CLK_RMUX 12
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 BSEL_OVRD2 11 2N3904
A
A/B 9 R8U16 . 1K 5%
Y CK_FSC_CLK 24 2
10 G 10K 5%
51 CK_FSC_MUX B
.
SN74LV157AD R8U18
8
15
4.7K
5% +V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58
.
R3B3 R3B5 R3B4 R2R5
10K 10K 10 H_DPRSTP# 3,6,21,41
BSEL_OVRD# 4.7 5%
B 5% 5% 5% R1R1 B
. . .
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58 +V3.3S
100K 5% .
3
.
16
1
C3B2 C3B3 U8U1D R2R6 Q2R1
100K
AD7453_VDD
0.1uF 10uF 14 BSS138

10%.
A
A/B
5% MAN_DPSLP 1
10% Y 12 .
. A_GND_LOCAL 13 G 3
B
R2R7 .
2
U3B1 R3C3 8 SN74LV157AD DPRSTP_DRV# MAN_DPSLP_R# 1 Q1R1
1 VDD GND 5 A_GND_LOCAL
VSSSENSE_R 4 15 2N3904
. 1K 5%
ADC_CLK AD7453_VIN_N 100 . 2
2 SCLK VIN_N 6
C3B7
ADC_DATA 3 7 AD7453_VIN_P 0.1uF
R3B6 SDATA VIN_P
.10%
ADC_CS# ADC_CD#_R 4 8 AD7453_VREF R3C4
150 5% CS* VREF
. AD7453B VCCSENSE_R 4
D25927-001 100 .
SOT23_8
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,51,56..58
R3B11
10 C3B14 U3B2 CAD Note: Route OUTS signal (AD7453_VREF) 10Mil wide
5% MAX6126_NR and attach close to AD7453 Controller.
. 1 NR OUTS 6
0.1uF 10% MAX6126_IN 2 7

. IN OUTF
3 5 C3B6 C3B5
A C3B13
4.7uF 4
GND NC5
8
0.01uF
10%
1uF
20%
A
10% GNDS NC8 .402 .
A_GND_LOCAL . MAX6126
Pins 5 & 8 Internally connected
Title
Do Not Use Signal Override 1 - Validation Only
A_GND_LOCAL D77513-001
A_GND_LOCAL SOI8_50IN_157X197
R3B7
0 .
A 1.5

5 4 3 2 1
5 4 3 2 1
BSEL COMPARATOR REFERENCE

+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,50,56..58
R7U2
40.2K
1%
.
D BSEL_COMP D
R7U3
C7U2 10K
0.1uF 1%
.
20%
.
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,50,56..58
C8U12 R8U13
0.1uF 10K
20% 5%
3 .
U8U2A .
R8U6
CK_FSA_R 5 +
24 CK_FSA
2 SIO_VID0
CK_FSA_MUX 50
1K . 5% BSEL_COMP 4 -
C LM339 C
12
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,50,56..58
3 R8U12
U8U2B 10K
R8U5 5%
.
CK_FSB_R 7 +
24 CK_FSB
1 SIO_VID1
CK_FSB_MUX 50
LM339
12
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,50,56..58
3 R7U7
U8U2C 10K
R7U4 5%
.
CK_FSC_R 9 +
24 CK_FSC
14 SIO_VID2
CK_FSC_MUX 50
B B
LM339
12
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49,50,56..58
3
U8U2D
R7U6 U500_SPARE 11 +
1K 5% 13 TP_U500_SPARE
R7U5 . U500_SPARE# 10 -
1K 5%
.
LM339
12
A Crown Beach A
Intel Confidential
Title
Signal Override 2 - Validation Only

A 1.5

5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK PAGE
B B
A Crown Beach A
Intel Confidential
Title
Blank Page

A 1.5

5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK PAGE
B B
A Crown Beach A
Intel Confidential
Title
Blank Page

A 1.5

5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK PAGE
B B
A Crown Beach A
Intel Confidential
Title
Blank Page

A 1.5

5 4 3 2 1
5 4 3 2 1
Rev 0.5 External BOM updates: Added four 0 ohms for stuffing option to UART.
R6T22, R5U36, R5U1 Added four nets to complete the 232 connections.
Initial Release Empty C5T1 Made connections match from UART option to H8
Empty R5H5
Emptying COMMs added parts for typical boards. Changed PCIe stuffing- Emptied R6E6,
Rev 1.0 External Empty R8F6 R6E7, R6D4, R6D2, R6E4 and R6E7.
Reversed stuffing son 2104 options Stuffed R6E5, R6E8, R6D3, R6D1, R6E3 and R6E2.
Added PWRGD switching circuit. R5V3/R5V6 reversal. Emptied C3T49, C3T50, C3T52, C3T53, C3T54 and C3T55
D D
Emptied C1H1 and C1J1. Changed all 3.3 loads to 3 ohms. for C6 adjustments.
Changed R1H1 and R1J1 from 100K to 0 ohm. Stuff R8Y13 and R8J3.
Added stuffing option on SDIO 1 bits 5-7. Added four pull-ups to SLT RSVD[3:0] SLT.
Empty U9D1 and Stuff R7E1.
More stuffing on SDIO PWR. Change R5U17 and R5U11 to 10ohms.
H8 connections for above SDIO options. Added ESD diode to client conn.
Stuff R5U8.
Added 10K pd on IDE_PDDREQ. Change the following 0ohms:
Added 0.047uF in parallel with R6J4 and emptied R. Emptied Q4C2 and stuffed R3C6 to bypass
R8F7, R8F9, R8F11, R8F12, R8F14, R8F16, R8F18, R8F17, R8F22, R8F20,
Inserted new pg for second PCIe MINI Card. R8F26, R8F24, R8F23, R8F25, R8F8, R8F10, R8F15, R8F13. Changed R3E13-16 from 1K to 0 Ohm
Add 10 up to INT_SERIRQ. Updated Poulsbo to incorporate B0 changes into model.
R7, R8, and R9 changed to 1K Stuffed. Changed jumper settings for J8G3 and J9G3 to 1-2
Updated H8 bypass conn model to pull out two gnds and and made that default.
change to TX and RX pins.
Added 0 ohm series to KBC_PROG_XX# and changed net
SMC_ONOFF# to PS_ON#.
Rev 1.5 External
Added CMOS_EN FET switch to CPU_CMREF. Emptied TP6B1, TP6B2 and TP6B3.
Added CMOS_EN circuit to H_CGVREF.
C Changed R9D2 to 1K. Changed R2E3 from 1K to 402. C
Reversed TX and RX on minicard conns. Changed R4R7 to 75K.
Reconnected pins 37, 39, 41 and 43 per new spec. Changed R2F3 to 10K and stuffed C2F1 with0.1uF
Pins 2 and 52 now connect to 3.3Aux, moved decoupling
to that rail. Changed R5V22 and R5V27 to 470 ohm.
Removed SLOT2_CLK_MINI and SLOT2CMD_MINI nets from conn Emptied C6N1, C4B2 and C4B1.
and renamed net to isolate from minicardA.
Changed Q8U2 to BSS138. Changed SMA footprints to 4 footed.
Emptied C8U8 and C9U7. Changed nets on U9J1 10,13 to xxx_TXD.
Added three pu's on the SLOTx_CD nets on the Poulsbo side Deleting R8U4 and Q8U1, to remove the inverter.
of the option resistor. Swap nets PMU_4 and H8_PIN115 on U9D1
Changed H8S/2104 BGA to H8S/2117 PQFP. Deleted MANARA_PRSNT# net and FET and changed VID over ride
Added 0ohm option on RSVD13-17 for USIM. pull-ups.
Added Pink and Green jacks, 4 3-pin hears for power options on Added 330uF to +V1.05S_VTT_CPU.
conn. Deleted two LEDs. Made MANARA_PRSNT# net local to this page only.
Added RS232 tranceiver and bypass option. Moved 8.2K pu here from pg 40 and emptied.
Added stuffing option on miniPCIe for SMBus (pins 30&32).
B B
Added stuffing option for 1.5v on pin 28 for STD miniPCIe. Added 0ohm in series from +V1.05S_VTT_CPU to J2E1 pin 1.
Change C7V11 to 10uF. Added empty 0 ohm from J2E1 pin 1 and +VCCP1.05_CPU_C6_OFF.
Add a series 0ohm resistor to pin 22 of J7H4. Added testpad on TP_GPIOSUS_0
Add THM test points on SLOT0_CD#, SLOT0_WP, SLOT0_LED. Added FSC option into 3 pin header selection for BSEL0.
Empty R5B1(R5B5), R5B2(R5B6), R5N3, R5N2, R7, R8, and R9. Added offpage on CK_FSC_CLK_RMUX
Empty R10, R11, R12.
Add series 1k res to pin 1 of Q9D2 (INIT# FET) and change Connected GPIOSUS_0 to pin 34 on IDE
FET Q9D2 to MMBT3904 (NPN). Connected GPIOSUS_0 to pin 34 via series 0 ohm.
Add three stuffed 0 ohm resistors connected between SD0PWR#
Updated SLT model to fix naming inconsistency.
and SLOT1-DATA5; SD1PWR# and SLOT1_DATA6; SD2PWR#
Change R5U17 and R5U11 to 22 ohm. Unstuff R5U8.
and SLOT1_DATA7.
Change R1 to 100 ohm, empty R5H1 and R5H4,
CAD note please place these resistors near J5B1.
Stuff R5H2 and R5H5
Empty R5U8, R5F4, R5F7, stuff R4, R5, R6 with 221ohm 0402.
Empty R7E1
Empty J9G3 and remove from table.
Empty R8J3 and R8Y13
Unstuffed R13.
Change R2F3 from 10K to 2K.
Added back in the two audio jacks.
A Added new net WWAN_nINTR to pin 44 of conn. Changed R2V2, R3V4 and R2V7 to 2.0ohms Crown Beach A
Connection made for above new net to pin 58. Intel Confidential
Added 1K pd on PSI. Stuffed U9J1, J9G6, C9J1, C9J2, C9J3, C9J4, C9J5 Title
C9J6, R9J4, R9J5, R9H4, R9H1, R9H6, R9J1. Revision History
Emptied R8Y11, R8T11 and R7T12.
Stuffed R8R4, R8T10, R7T11, R8T12 and R8T8. Size Document Number Rev
Emptied R4R3 and R4P8. A 1.5
Stuffed R4R2 and R4P7.
5 4 3 2 1
5 4 3 2 1
+V5SB_ATX 28,40,44,45
6,8,11 +V1.05S_VTT_SCH +V1.8_SM_SCH 10,11,48
10,11 +V1.5S_DLVDS_SCH +V1.5S_SDVO_SCH 10,11 SCH Part Detect

R9V3
7,10,11,48 +V1.5S_PCIE_SCH +V1.5S_SCH 10..12,38 100K
D D
.
10,11,29,33,48 +V1.05S_SCH_VCORE R9V2 R9W1
J7E1 100K
VR_ALW_ENABLE 39,40
3
1 2
3 4 Q9V1 0
5 6 BSS138
7 8 TP_J223_8 1 .
7 SCH_DETECT#
9 10
2
Note: Test Only .
2
. J8D3 R9V1
. 0
NO_STUFF
1
J8D3 default: Open
7,25 SLOT1_LED
C
Poulsbo strapping table C
7,25 SLOT1_CD#
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,57,58
7,25 SLOT1_WP
+V3.3S
7,25 SLOT1_CMD
CAD Note: Place resistors near J5B2 J5B2
R5B2 B12
7,25 SD2PWR# 0 . 5% D15
B10 D14
R5B3 A12
7,25 SD1PWR# 0 . 5% D13
A10 D12
R5B4 B9
7,25 SD0PWR# 0 . 5% D11 R5V15 R5V16
B7 D10 GND9 A2
A9 A5 10K 10K
D9 GND8 NO_STUFF
7,25 SLOT1_DATA[7:0] A7 D8 GND7 A8
SLOT1_DATA7 B6 A11 .
SLOT1_DATA6 D7 GND6
B4 D6 GND5 A14 SCH_GPIO_3 8,17
SLOT1_DATA5 A6 B2
D5 GND4 SCH_GPIO_0 8
SLOT1_DATA4 A4 B5
B
SLOT1_DATA3 D4 GND3 B
B3 D3 GND2 B8
SLOT1_DATA2 B1 B11
SLOT1_DATA1 D2 GND1 R5V12 R5V11
A3 D1
SLOT1_DATA0 A1 10K 10K
D0 NO_STUFF
A15 CLKN .
A13 CLKP
P6860 NO_STUFF CMC Base Address
SCH_GPIO_3 SCH_GPIO_0 Address
Note: Test Only 0 0 0xFFFB0000
0 1 0xFFFC0000
Do Not Populate SLOT1_CLK 7,25 1 0 0xFFFD0000 (Default)
1 1 0xFFFE0000
A Crown Beach A
Intel Confidential
Title
Validation Hooks 1

A 1.5

5 4 3 2 1
5 4 3 2 1
RS-232 TRANSCEIVER CORE WELL RS232 PORT MODE
+V3.3S 5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56,58
Setting Mode
Both 1-2 Data Communications Equipment
C6W2 U6H1 C5W6 (default) (Use a normal cable)
0.1uF SERBUFA_C1+ 1 16 0.1uF C5H2
10%
.
C1+ VCC C6W1 20% 22UF Both 2-3 Data Terminal Equipment
SERBUFA_C1- 3 2 SERBUFA_V+ 0.1uF . (Use a null modem cable)
C6W3 C1- V+
.10% J5H5
0.1uF SERBUFA_C2+ 4 6 SERBUFA_V- 0.1uF 1
C2+ V-
.10% .10% 2 SERPRT_TX_OUTA
SERBUFA_C2- 5 C6H6 3 J6H2
C2-
1 2
R5U4 0 NO_STUFF SCH_RXA CON3_HDR
D
7,25 SLOT2_DATA4
R5T8 0 NO_STUFF SCH_RXB
12
9
R1OUT R1IN 13
8
3
5
4
6
SCH POULSBO D
7,25 SLOT2_DATA6 R2OUT R2IN
7,25 SLOT2_DATA5
R5U5
R5U27
0
0
NO_STUFF
NO_STUFF
SCH_TXA
SCH_TXB
11
10
T1IN T1OUT 14
7
SCH_SOUTA
SCH_SOUTB 1
J6H3 7
9
8 SERIAL PORT
7,25 SLOT2_DATA7 T2IN T2OUT
GND 15 2 SERPRT_RX_INA
2X5-Header
CONNECTOR 1
3
DEBUG ONLY MAX3232_RS232_TRNCVR SCH_SINA .
CON3_HDR
SCH_SINB J5J1 J6J2
1 1 2
2 SERPRT_TX_OUTB 3 4 SCH POULSBO
3 5 6
CON3_HDR
7
9
8 SERIAL PORT
J6J1
2X5-Header
CONNECTOR 2
1
2 SERPRT_RX_INB .
3
CON3_HDR
Reserved - TEST ONLY
C C
System Current Sense Amp (6A Dynamic Range) +V5A 37,39,45

Embedded Controller ADC Reference
(Place close to VSB sense resistor) (Place close to the EC)
+V3.3A 7,27,34,37,39,40,44..46
+VREF_ADC 26 +V5A 37,39,45
U55_OUT_R
R7F8 C7G3
U7G1 22 0.1uF R7F1
NO_STUFF 475 3.3V ADC reference
1 SHDN# GSEL 8 8 16V 10% NO_STUFF
1%
R7F2
ISENSE_POS_R 2 7 0 +VREF_ADC 26
ISENSE_NEG_R RS- VCC U55_OUT U7F2A NO_STUFF .
3 RS+ OUT 6 3 +
4 5 U55_RFIN R7G1 1 EC_BRK_CURRENT 26
GND RFIN 20K_1% 2 -
MAX4072
C7G2 C7G1 NO_STUFF C7F6 C7F9
NO_STUFF
C7F7 AD8552
* *
CAD Note:
1uF 1uF 0.1uF 0.1uF C7F8 1uF 4 NO_STUFF Groud trace needs to be 20 mil
20% 20% 10% 10% 22UF 20% or larger going from the brick
NO_STUFF NO_STUFF 16V NO_STUFF NO_STUFF NO_STUFF to the EC and MAX4072 current
NO_STUFF sense amp.
1 The precision ADC and and 3.3 ADC reference
U7F1 optons are mutually exclusive. DO NOT STUFF
GND_SYS_ISENSE LM4040 BOTH AT THE SAME TIME OR THE PRECISION C7F3 C7F1
B 26 EC_CS_GAIN_SEL
NO_STUFF REFERENCE COULD BE DAMAGED. 22UF 0.1uF B
NO_STUFF 10%
R7F7 1K SH7F1 3.0V Precision ADC 2 NO_STUFF
ISENSE_NEG 44
NO_STUFF 1% Current Sense Range Reference circuit
R7G4 1K 0 - 3A: EN_CS_GAIN_SEL = 3.3V

ISENSE_POS 44
NO_STUFF 1% 0-6A EN_CS_GAIN_SEL = 0V GND_SYS_ISENSE
GND_SYS_ISENSE
System Voltage Monitor

(Place close to VSB sense resistor)
+V12A 39,44,45 +V5A 37,39,45
R7F6
24.3K
1%
8
NO_STUFF
5 U7F2B
+
7
6 VBRK_MON 26
R7F5 -
C7F5
4.02K 1uF AD8552
1% 4 NO_STUFF
20%
NO_STUFF NO_STUFF
A Crown Beach A
Intel Confidential
Title
GND_SYS_ISENSE
Validation Hooks 2

A 1.5

5 4 3 2 1
5 4 3 2 1
TEST COUPONS
5..8,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56,57 +V3.3S
2
J4F1 J4D2
G2
G1
G2
G1
S
S
250um 250um R6F2
NO_STUFF NO_STUFF 10K J7F1 1-X
1
D (Default) D
VNA_5
VNA_4 J7F1
8 SCH_GPIO_6 1 2
.
1
1
J5F1 J3D4 Reserved - TEST ONLY
G1
G2
G1
G2
S
S
250um 250um
NO_STUFF NO_STUFF
2
3
3
J3D3
G2
G1
S
250um
NO_STUFF
1
VNA_10
C C
1
J4E1
G1
G2
S
250um
NO_STUFF
2
B B
A A
Title
Validation Hooks 3

A 1.5

5 4 3 2 1

Rev 1 5

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Menlow Platform Crown Beach

Customer Enabling Board

2 Intel Confidential Schematics

x16 mechanically PCIE x1 PCIE SLOT 0 +V3.3S_SCH S0

SCN KB/ PS2 Title

Size Document Number Rev

Date: Wednesday, November 14, 2007 Sheet 1 of 64

CROWN BEACH VALIDATION VEHICLE

Mini WWAN 14 1-2 H_THERMDA 5

Default Jumper Settings For Stuffed Jumpers

Wake Events State Supported

Size Document Number Rev

Date: Friday, November 16, 2007 Sheet 2 of 64

6 H_INTR LINT0 D[20]# D[52]#

0 5% RSVD1 RSVD6 H_D#30 D[29]# D[61]# H_D#62

XDP_TDO_CPU 56 5% CPU 1% 1% NO_STUFF R2B9

CMVREF MARGIN header - TEST ONLY +V1.05S_VTT_CPU 4,11,29,33,43,48,50

3 G2 SMA_SMT 4,43 +VCCP1.05_CPU_C6_OFF R2E2 R2T2 R2E3 R2D6

XDP_BPM#4 56 5% 1% 1% 1% 1% Comp0,2 connect with Zo=27.4ohm, make

XDP_BPM#5 56 5% 10V CPU

Date: Tuesday, November 20, 2007 Sheet 3 of 64

Size Document Number Rev

Date: Tuesday, November 20, 2007 Sheet 4 of 64

CPU Thermal Sensors

C4P1 R4C4 R4P2

PM_ADI_THERM# CAD NOTE: PLACE TOP SIDE GND0 GND2

Fan Power Control PM_EXTTS# 7,18

Stuff for FAN Always ON R3C7 Q4C2

FAN_PWM needs to be driven NO_STUFF

the EC. 1uF R4C2 0 4 ADT_THERM_PWM

Date: Friday, November 16, 2007 Sheet 5 of 64

Size Document Number Rev

Date: Tuesday, November 20, 2007 Sheet 6 of 64

20,21,26,28,49 LPC_FRAME# K40 LPC_FRAME# R4H2

SLOT0_DATA6 47 5%SLOT0_R_DATA6 D16 AV48 SLPRDY# SLPMODE XBT5H1

25,56 SLOT1_WP . SD1_LED SDVOB_TVCLKIN SDVO_TVCLKIN 16

SLOT2_DATA6 R5T7 . 47 5%SLOT2_R_DATA6 SD2_DATA5

Size Document Number Rev

Date: Tuesday, November 27, 2007 Sheet 7 of 64

+V3.3S 5..7,11,12,14..18,20..22,24,25,27,29,31,34,35,38,40,41,43..46,49..51,56..58 J31

HDA_SYNC E13 HDA_SYNC 21

Date: Friday, November 16, 2007 Sheet 8 of 64

Size Document Number Rev

Date: Friday, November 16, 2007 Sheet 9 of 64

D76284-004 --> E11512-002

M30 VCC33_9 VCC_48 AB20

N21 VCC33_5 VCC_52 AM28

AA41 VCC5REFSUS VCC_70 Y20

Tuesday, November 20, 2007

All decoupling should be placed on the backside 10,29,33,48,56 +V1.05S_SCH_VCORE

4..6,8,14,21,24,38 +V1.5S 10,12,38,56 +V1.5S_SCH

10,12,38,56 +V1.5S_SCH +V1.5S_DLVDS_SCH 10,56

0.01 1% C5T55 C5T48

10,12,38,56 +V1.5S_SCH +V1.5S_SDVO_SCH 10,56

Size Document Number Rev

Date: Friday, November 16, 2007 Sheet 11 of 64

+V1.5S_DPLLB_SCH 10 NO_STUFF C5T83 C5T82 C5T89

120ohm@100MHz C5T2 C5T4 AHPLL AND DHPLL CONNECTED TOGETHER

+V5 8,14,15,21,23,30,32,36,37,44,45 5,17,31,33..35,40,41,44,45 +V5S

R5H1 R5H4 LPC_CLKOUT[0] Drive Strength

BH30 VSS_1 VSS_76 BB24

Size Document Number Rev

Date: Friday, November 16, 2007 Sheet 13 of 64