Digital Fundamentals (PDFDrive)

Digital
Fundamentals
Tenth Edition
Floyd
Chapters
4, 7, & 11
© 2009 Pearson Education,©Upper

2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Saddle River, NJ 07458. All Rights Reserved
ET285 Agenda - Weeks 7, 8, & 9
Exam:
• Chapters 12 & 14
Lecture:
• Chapter 7 (4, 7, & 11 ?)
Lab 5, Experiment #24:
Application of Shift Register Circuits
• Starts on Page 201 of your Lab Manual
• Your instructor must sign-off lab and you must
submit with Lab Questions answered.
Assignment:
• Review these topics!
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
ITT Technical Institute
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Programmable Array Logic
Chapters 4 & 7
Figures may not be in any order

SO
READ THESE CHAPTERS
Programmable Array Logic
Figure 11.1 Basic AND/OR structure

of a PAL.
PAL implementation of a sum-of-products expression.
PAL implementation of a sum-of-products expression.
Figure 4-47 (Example 4-35) Page 216
Figure x.x
General block diagram of a PAL or GAL.
Figure 4-49
Basic types of PAL/GAL macrocells for
combinational logic.
Figure x.x
Logic block diagram of a PAL16V8 and typical SPLD
package.
An I/O pin is
counted as both an
input and an output.
The GAL22V10
• The term GAL is defined as Generic Array Logic
• A GAL is an SPLD (Simple Programmable Logic

Device) with a reprogrammable AND array, a fixed
OR array and programmable output logic macrocells.
• The GAL 22V10 has 12 dedicated inputs and 10 I/O’s
Figure 7-1
GAL22V10 block diagram.
Figure 11.9
Block diagram of the GAL22V10 and typical
SPLD package.
GAL22V10 – Output Logic Macros
Output Logic Macrocells (OLMC) contain
programmable logic circuits that can be configured for
either combinational output/input or registered Output.
The OLMCs of the GAL22V10 are configured as follows:
• Two have eight product terms
(lines from the AND array to the OR gate)
• Two have ten product terms
• Two have twelve product terms
• Two have fourteen product terms
• Two have sixteen product terms
Each OLMC can be programmed for either active high or
active low output or as an input.
Figure 7--3
The GAL22V10 OLMC.
Figure 7--4
OLMC combinational mode.
The flip-flop is not

used in this mode.
Figure 7--5
Tristate output buffer operation.
Note: Output buffers are inverting buffers.
Figure 7--6
OLMC combinational output and input configurations.
Figure 7--7
Determine the output expression of the following OLMC
for the product terms from the AND array as shown.
The GAL22V10 Array
• The GAL22V10 programmable array is

organized as 22 input lines and complements
crossing 132 product lines.
Figure 7--8
GAL22V10 array diagram.
Figure 7--9
Organization of the programmable array showing one OLMC
portion.
The example OLMC below has 8 product terms that
can be used in a Sum Of Product function.
Notice: 8 AND gates going to OLMC.
Also, up to 10 separate SOP functions can be programmed.
Figure 7--10
See Example 7-2, page 370 in text
Programming a cell to the ON state simply connects
the input line to the product term line.
Below, X = ON
How many more product terms can be added to the
SOP example below?
Thomas L.
Floyd, Floyd Fundamentals,
Digital 10th ed © 2009 Pearson Education, Upper Saddle River, NJCopyright
07458.©2003
All Rights
by PearsonReserved
Education, Inc.
Digital Fundamentals, 8e Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 7--11
GAL16V8 block diagram and packaging.
Eight dedicated
inputs and eight
I/O’s
Thomas L.
07458.©2003
All Rights
by PearsonReserved
Education, Inc.
Figure 7--12
OLMC configurations in the simple mode.
One of three mode

of operation.
Thomas L.
07458.©2003
All Rights
by PearsonReserved
Education, Inc.
Figure 7--13
OLMC configurations in the complex mode.
Thomas L.
07458.©2003
All Rights
by PearsonReserved
Education, Inc.
GAL16V8 OLMC’s
• The OLMCs of the GAL16V8 can be configured

in Simple Combinatorial, Complex
Combinatorial, or Registered modes.
• In Complex Combinatorial mode only seven
product terms can be inputted to the OR gate of
the OLMC because the other AND output is used
for the tristate control.
• In register mode an input of the GAL must be
reserved for the clock pin.
GAL16V8 Example
• To implement a parallel in/serial out shift register
in a GAL16V8 you need to use the registers in the
OLMCs for the register function.
• Each input may go straight to the registers
without using any product terms or creating any
SOPs.
• The GAL16V8 has only 8 registers which limits
the size of the total shift register to the number of
OLMCs.
Figure 11.11
Basic block diagram of the Altera MAX 7000 series
CPLD.
Figure 11.12
Simplified diagram of a macrocell in a MAX 7000
series CPLD.
Figure 11.13
Example of how a shared expander can be used in a
macrocell to increase the number of product terms.
Figure 11.14
Simplified illustration of
using a shared
expander term from
another macrocell to
increase an SOP
expression. The red
Xs and lines represent
the connections
produced in the
hardware by the
software compiler
running the
programmed design.
Figure 11.15
Basic concept of the parallel expander.
Figure 11.16
Simplified
illustration of using
parallel expander
terms from another
macrocell to
increase an SOP
expression.
Figure 11.18
MAX II CPLDs have LUT logic. Classic CPLDs
have AND/OR arrays.
Figure 11.20
Comparison of a basic PLA to a basic PAL.
Figure 11.24
Commonly used symbol for a multiplexer.
It can have any number of inputs.
Figure 11.25
A macrocell in the Altera MAX 7000 family of
CPLDs.
Figure 11.26
A macrocell configured for generation of an
SOP logic function.
Red indicates data path.
Figure 11.27
A macrocell configured for generation of a
registered logic function.
Figure 11.29
A macrocell configured for generation of an
SOP logic function.
Figure 11.30
A macrocell configured for generation of a
registered logic function.
Figure 11.31
Basic structure of an FPGA.
CLB is configurable logic block.
Figure 11.32
Basic configurable logic blocks (CLBs) within the
global row/column programmable interconnects.
Figure 11.33
Basic block diagram of a logic module in an
FPGA.
Figure 11.34
The basic concept of an LUT programmed for a
particular SOP output.
Figure 11.39
Simplified diagram of a Stratix II adaptive logic
module (ALM).
Figure 11.41
Expansion of an ALM to produce a 7-variable
SOP function in the extended LUT mode.
Figure 11.42
Figure 11.45
Example of using cascade chains for expansion
of an SOP function.
Figure 11.46
Implementation of a 16-input AND gate to
produce a product term with sixteen variables.
Weeks 8 Agenda
Exam:
• Chapters 12 & 14
Lecture:
• Chapter 7 (4, 7, & 11 ?)
Assignment:
• Review these topics!
• PROJECTS!
th
Floyd, Digital Fundamentals, 10 ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
To Be Continued
Next Week
Weeks 9 Agenda
Lecture:
• Chapter 11 ?
Assignment:
• Obtain Assignment sheet from your instructor.
• PROJECTS DUE!
Programmable Logic Arrays
Programming with ABEL
Digital Fundamentals, Chapters 4 and 7
ABEL
Advanced Boolean Expression Language
• Allows logic designs to be implemented in programmable
logic devices
• Can be used to program any type of SPLD (device-
independent).
• Run on a computer connected to a language-independent
device programmer to which the SPLD is inserted.
• Logic entry can be in the form of equations, truth tables,
and state diagrams.
• A design can be simulated using test vectors to make sure
there are no errors.
• Logic Synthesis is the means of converting the logic entry
to a standard JEDEC file format required to actually
implement the design in©an
th
Floyd, Digital Fundamentals, 10 ed
SPLD.
2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
ABEL
There are three parts to an input file:

• Declaration,
• Logic Descriptions,
• Test Vectors
Boolean Operations used for Logic
Expressions
To write a boolean expression in ABEL special
characters must be used as follows:
Logic Operation ABEL Symbol Example

NOT ! !A
AND & A&B
OR # A#B
XOR $ A$B
Upper case and Lower case are two different variables.

All equations must end in a semicolon. X=A$B#!A;
ABEL
Advanced logic expressions include the following
commands:
• GOTO
Can be used for state diagrams to tell the complier the
compiler which input expression to use. See page 596.
• IF-THEN-ELSE
Describes what to do next based on current conditions.
All equations can be implemented in upper or lower case.
Figure 11.50
Essential elements for programming an SPLD,
CPLD, or FPGA.
Figure 11.51
Examples of text and schematic entry screens.
Figure 11.57
Example of logic optimization during
synthesis.
Figure 11.60
Downloading a design to the target device.
ET285 Agenda - Weeks 7, 8, & 9
Lecture:
• Chapter 11 ?
Assignment:
• Obtain Assignment sheet from your instructor.
• PROJECTS DUE!

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© 2009 Pearson Education,©Upper

Figures may not be in any order

Figure 11.1 Basic AND/OR structure

• The term GAL is defined as Generic Array Logic

• A GAL is an SPLD (Simple Programmable Logic

• The GAL 22V10 has 12 dedicated inputs and 10 I/O’s

The flip-flop is not

Note: Output buffers are inverting buffers.

• The GAL22V10 programmable array is

One of three mode

• The OLMCs of the GAL16V8 can be configured

It can have any number of inputs.

Red indicates data path.

Red indicates data path.

Red indicates data path.

Red indicates data path.

Digital Fundamentals, Chapters 4 and 7

There are three parts to an input file:

Logic Operation ABEL Symbol Example

Upper case and Lower case are two different variables.

All equations can be implemented in upper or lower case.

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