A project Report on

FPGA Implementation of Boolean Functions

Using Multiplexer
Submitted in partial fulfillment of the requirements for the award of the
degree of

Bachelor of Technology
in
ELECTRONICS & COMMUNICATION ENGINEERING
By

VANGAVOLU DINESH
20MH1A04C5

Under the Esteemed Guidance of

Mrs. K. Vijaya Kumari, M.Tech.

Assistant Professor

Department of Electronics & Communication Engineering

ADITYA COLLEGE OF ENGINEERING(A)

(Approved by AICTE, New Delhi & affiliated to JNTU, Kakinada)

Aditya Nagar, ADB road, Surampalem, E.G.Dt, A.P-533437

2020-2024
 ADITYA COLLEGE OF ENGINEERING

DEPARTMENT OF ELECTRONICS AND

COMMUNICATIONENGINEERING

BONAFIDE CERTIFICATE
This is to certify that the Project Report entitled

FPGA Implementation of Boolean Functions Using

Multiplexer
being submitted by

VANGAVOLU DINESH 20MH1A04C5

In partial fulfillment of the requirements for the award of the Degree of Bachelor of
Technology in Electronics and Communication Engineering, at Aditya College of
Engineering is a bonafide work carried out by them under my guidance and super vision. The
result embodied in this report has not been submitted to any other University or Institution for
the award of any degree or diploma.

Project Guide Head of the Department

Mrs. K. Vijaya Kumari, M.Tech. Ms. CH. Janaki Devi , M.Tech,

(Ph.D)
Assistant Professor, Associate Professor,
Department of ECE Department of ECE
Aditya College of Engineering(A) Aditya College of Engineering(A)
2020 – 2024
 DECLARATION

I hereby declare that the entire project work embodied in this dissertation entitled “FPGA
Implementation of Boolean Functions Using Multiplexer” has been independently carried
out by us. As per my knowledge, no part of this work has submitted for any degree in any
institution, university and organization previously. I here by boldly state that to the best of my
knowledge my work is free from plagiarism.

Yours sincerely,

V.DINESH

20MH1A04C5
 ACKNOWLEDGEMENT

We express our sincere gratitude and heartful thanks to the under stated person for
thesuccessful completion of our final project on “FPGA Implementation of Boolean
Functions Using Multiplexer”.

First and foremost we wish to thank our beloved guide Asst.Prof Mrs. K. Vijaya Kumari for
her kind guidance, valuable advices and utmost care at every stage of our final project.

We would like to thank Assoc.Prof Ms.CH.Janaki Devi, head of the department of E.C.E,
who have provided vital information, which was necessary for success of the project.

The credit in successful completion of our final project goes to highly esteemed Prof
Dr.A.RAMESH sir, principal of ADITYA COLLEGE OF ENGINEERING (A) for his kind
guidance, commendable and noteworthy advices and even memorable encouragement to the
same.

Yours sincerely,

V.DINESH

20MH1A04C5
 ABSTRACT

FPGA implementation of Boolean functions with multiplexers using a laboratory board, based on
Spartan-6 devices, is presented in the paper. It will be used in the training of electrical engineers in the
courses “Digital Circuits” and “Pulse and Digital Devices” introducing students of electrical specialties
to the main topics in digital electronics. One of the topics is “Implementation of Boolean functions
using multiplexers” and using the laboratory board makes the topic more attractive and easier for
assimilation by the students.
 INDEX

CONTENTS Page No.

CHAPTER 1: INTRODUCTION 1

1.1 Multiplexers 1

1.2 Applications 6

1.3 Advantages 7

1.3.1 Disadvantages 9

CHAPTER 2: SOFTWARE DESIGN AND SIMULATION 12

2.1 Simulation software – Xilinx 13

CHAPTER 3: CONCLUSION 16

3.1 Conclusions 16

CHAPTER 4: REFERENCES 17

4.1 References 18
 CHAPTER-1

INTRODUCTION

1.1 Multiplexer :

Multiplexers (MUX) are versatile digital circuits that play a crucial role in FPGA design. They act
as data selectors, choosing one of several input signals to be routed to the output based on a control
signal. This ability makes them ideal for implementing various logic functions and data routing tasks
in FPGAs.

A basic multiplexer consists of the following components:

 Data Inputs (D): These are the input signals from which the output will be selected.

 Select Lines (S): These are the control signals that determine which data input is routed to the output.

 Output (Y): This is the single output signal that receives the selected data input.

The number of data inputs and select lines determines the size of the multiplexer.

The functionality of a multiplexer is straightforward. The select lines determine which data input is
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 routed to the output. When a specific select line is asserted (logic 1), the corresponding data input is
connected to the output. All other data inputs are disconnected from the output.

The main objectives of FPGA implementation of Boolean functions using multiplexer project are:

 To gain a comprehensive understanding of Boolean functions and their implementation using logic
gates.

 To familiarize with the concept of multiplexers and their operation.

 To design and implement various Boolean functions using multiplexers on an FPGA.

 To analyze the hardware utilization, performance, and resource consumption of the implemented
designs.

 To compare the efficiency of multiplexer implementation with traditional combinational circuits.

Multiplexers (MUX) are versatile digital circuits that play a crucial role in FPGA design. They act as
data selectors, choosing one of several input signals to be routed to the output based on a control signal.
This ability makes them fundamental for implementing various logic functions and data routing tasks in
Xilinx FPGAs.

1. Multiplexer Implementation using Boolean Functions:

Instead of using pre-built MUX components within Xilinx tools, it's possible to implement them using
fundamental logic gates and Boolean functions. This approach offers a deeper understanding of MUX
functionality and provides greater flexibility in design.

2. Cascading for Larger Multiplexers:

For larger multiplexers with more data inputs (e.g., 4x1, 8x1), you can implement them by cascading
multiple 2x1 MUX stages. This involves using the output of one MUX stage as an input for the next
stage, controlled by additional select lines.

3. Xilinx Implementation:

The actual implementation of the Boolean function for a MUX in Xilinx tools depends on the specific
tool and version you are using. However, the general steps involve:
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 Define the logic gates: Use the logic gates available in the Xilinx library (e.g., AND, OR, NOT) to
represent the Boolean function.

 Connect the inputs and outputs: Connect the data inputs, select lines, and output of the logic gates
according to the desired functionality.

 Compile and simulate the design: Use the Xilinx tools to compile and simulate the design to verify its
functionality.

4. Benefits of Custom MUX Implementation:

Although Xilinx provides pre-built MUX components, implementing them using Boolean functions
offers certain advantages:

 Deeper understanding: It provides a deeper understanding of MUX functionality and how they can be
implemented using logic gates.

 Flexibility: You can customize the design to your specific needs and requirements.

 Resource optimization: In some cases, custom implementation can lead to more efficient use of FPGA
resources.

We have different types of multiplexers ,such as 2x1 Mux , 4x1 Mux , 8x1 Mux, 16x1 Mux etc,…

1. 2x1 MUX:

This is the simplest MUX with two data inputs (D0 and D1) and one select line (S). The Boolean
function for this MUX is:

Y = S * D1 + (S1) * D0

where:

 Y: Output of the MUX

 S: Select line

 D1: Data input 1

 D0: Data input 0

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 This function states that the output (Y) equals the selected data input (D1 or D0) based on the value of
the select line (S). When S is 1, D1 is routed to the output, and vice versa.

2. 4x1 MUX:

This MUX has four data inputs (D0, D1, D2, D3) and two select lines (S1 and S0). The Boolean
function for this MUX can be expressed using the following sub-functions:

Then, the output function becomes:

Y = M1 * D3 + M2 * D2 + M3 * D1 + M4 * D0

where:

 Y: Output of the MUX

 Si: Select line i (i=0,1)

 Di: Data input i (i=0,1,2,3)

 Mi: Boolean function for selecting input i

3. 8x1 MUX:

This MUX has eight data inputs (D0 to D7) and three select lines (S2, S1, and S0). The
implementation follows a similar approach to the 4x1 MUX, with additional sub-functions and
combinations for selecting each data input.

4. MUX with Inverting Output:

You can implement an inverting MUX by adding an inverter to the output of the MUX circuit. This
negates the selected data input, effectively providing the opposite value.

5. MUX with Enable Signal:

You can add an enable signal (EN) to the MUX design. When EN is low, the output remains at a
specific value (e.g., 0) regardless of the data inputs and select lines. This allows for additional control
over the MUX functionality.

6. Implementing AND, OR, NOT functions with MUX:

4
 By using specific combinations of data inputs and select lines, you can implement basic logic
functions like AND, OR, and NOT using a MUX. This demonstrates the versatility of MUX circuits in
digital design.

7. MUX with Decoding Logic:

For designs requiring complex data routing or selection based on multiple variables, you can
combine MUX circuits with decoding logic. This involves using decoders to generate control signals for
the MUX based on specific input conditions.

These are just a few examples of implementing MUX using Boolean functions. The specific
implementation details and complexity will depend on the desired functionality and number of data
inputs/select lines

5
 1.2 Applications :

Implementing Boolean functions using multiplexers (MUX) on FPGAs offers several advantages
and opens doors to various applications.:

1. Data Selection and Routing:

 MUX serves as a central element for routing data between different parts of an FPGA. This is crucial in
communication interfaces, data acquisition systems, and multi-channel processing circuits.

 Its ability to select specific data based on control signals allows for dynamic and flexible routing
configurations within the FPGA.

2. Implementing Complex Logic Functions:

 MUX can efficiently implement complex Boolean functions with fewer logic gates compared to
traditional combinational circuits. This leads to smaller, faster, and more power-efficient FPGA designs.

 Applications include ALU (arithmetic logic unit) implementation, error correction circuits, and custom
logic operations specific to the project.

3. Dynamic Reconfiguration:

 MUX allows for dynamic reconfiguration of FPGA circuits by changing the control signals. This enables
adaptability and flexibility in real-time applications.

 Examples include on-the-fly modification of processing algorithms, adjusting filtering parameters, and
adapting to changing environmental conditions.

4. Bit Manipulation and Decoding:

 MUX can manipulate individual bits of data by selecting specific inputs based on control signals. This
facilitates bit-level operations like masking, clearing, and setting bits.

 Applications include data encryption/decryption, error correction codes, and protocol decoding for
communication interfaces.
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 5. Code Compression and Optimization:

 Implementing logic functions using MUX can lead to code compression, minimizing the amount of HDL
code required for a specific functionality. This can be advantageous for large and complex designs.

 Additionally, MUX implementation can optimize resource utilization by reducing the number of logic
gates required compared to traditional approaches.

Beyond these core applications:

 MUX plays a crucial role in various FPGA-based systems, including:

o Image and video processing circuits

o Digital signal processing (DSP) applications

o High-performance computing systems

o Embedded systems and controllers

o Medical diagnostic equipment

o Robotics and automation systems

Choosing MUX Implementation:

The decision to use MUX for implementing Boolean functions depends on various factors:

 Complexity of the function: For simple functions, traditional logic gates may be more efficient.

 Performance requirements: MUX can offer faster performance for some functions.

 Resource utilization: MUX may require fewer logic gates but may use more routing resources.

 Design flexibility: MUX allows for dynamic reconfiguration and code compression.

In conclusion, the FPGA implementation of Boolean functions using MUX offers a powerful and
versatile approach for various digital design applications. Understanding its advantages and limitations

allows for optimal design choices and efficient utilization of FPGA resources.

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1.2 Advantages :

Simplicity: Using a multiplexer simplifies the circuit design compared to building a complex
combination of logic gates. It provides a compact and elegant solution.

Reduced Gate Count: Multiplexers inherently reduce the number of gates required to implement a
Boolean function, which can result in a more efficient and faster circuit.

Flexibility: Multiplexers are versatile and can be used to implement a wide range of Boolean
functions. This flexibility makes them suitable for various applications.

Ease of Expansion: If the Boolean function needs to be expanded or modified, it's relatively easy to
do so with a multiplexer by adding more input lines and adjusting the select lines accordingly.

Reduced Wiring Complexity: Multiplexers help reduce the complexity of wiring by consolidating
multiple inputs into a single component. This simplifies the physical layout of the circuit and
minimizes potential errors.

Speed: Multiplexers are often faster than equivalent combinational logic circuits, which can be
advantageous in applications where speed is crucial.

Resource Efficiency: In terms of hardware resources, using a multiplexer can be more efficient than
other methods, especially for larger Boolean functions.

In summary, implementing Boolean functions using multiplexers offers simplicity, reduced gate
count, flexibility, ease of expansion, reduced wiring complexity, speed, and resource efficiency.
These advantages make multiplexers a valuable component in digital circuit design.

1.3 Disadvantages :

Limited Complexity: Multiplexers are generally used for relatively simple Boolean functions. If the
function becomes too complex, the number of inputs and control signals for the multiplexer may
increase significantly, making it less practical. In such cases, other dedicated logic elements like
lookup tables (LUTs) might be more suitable.

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Resource Utilization: FPGA resources are finite, and using multiplexers extensively may lead to
inefficient resource utilization. Multiplexers can consume a considerable amount of logic resources,
limiting the overall complexity of the design that can be implemented on the FPGA.

Propagation Delay: The implementation of Boolean functions using multiplexers may introduce
additional propagation delay compared to other dedicated logic elements. This can impact the overall
performance of the circuit, especially in high-speed applications.

Power Consumption: Multiplexers can contribute to higher power consumption in FPGA designs.
The dynamic power consumption is influenced by factors such as the switching activity of the
multiplexer and the capacitance of the connected nodes. In certain low-power applications, this may
be a significant concern.

Routing Challenges: Routing signals through multiplexers can introduce challenges in FPGA
designs. As the complexity of the design increases, the routing resources on the FPGA may become a
bottleneck, leading to longer design times and potentially compromising performance.

Limited Flexibility: Multiplexers are dedicated to specific functions, and once configured, they may
lack the flexibility to adapt to changes in the design. This can be a limitation when compared to more
general-purpose elements like lookup tables in FPGAs.

Complexity in Debugging: Implementing complex Boolean functions using multiplexers can make
the design more difficult to debug and maintain. Understanding the relationship between the input
signals, control signals, and the resulting output can be challenging as the design grows in
complexity.

Area Efficiency: In some cases, using a combination of different logic elements like AND, OR, and
XOR gates might result in a more area-efficient implementation compared to relying solely on
multiplexers.

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 CHAPTER 2

SOFTWARE DESIGN AND SIMULATION

1. Design Considerations:

A. Choosing the MUX size:

 The required MUX size depends on the number of input variables (n) in the Boolean function.

 A 2x1 MUX is sufficient for n=1, while larger MUXs (e.g., 4x1, 8x1) are needed for n>1.

B. Implementing complex logic:

 For complex functions with numerous input variables, use cascaded MUX stages.

 The output of one MUX stage serves as an input for the next stage, controlled by additional select lines.

C. Selecting an HDL:

 Xilinx offers Verilog and VHDL as HDL options. Choose the one you're comfortable with.

2. Software Design Flow:

A. Functional Design:

1. Define the Boolean function: Specify the input variables and desired output function.

2. Create the truth table: Show the output value for all possible input combinations.

3. Derive the Boolean expression: Use Karnaugh maps or other techniques to minimize the expression.

4. Map to MUX logic: Identify select lines and data inputs based on the simplified expression.

5. Design cascaded MUX stages: If needed, plan the structure and logic for each stage.

B. Xilinx HDL Implementation:

1. Open Xilinx ISE Design Suite or Vivado Design Suite: These are the primary software tools for Xilinx
FPGA design.

10
2. Create a new project: Specify the target FPGA device and HDL language (Verilog or VHDL).

3. Define modules: Create separate modules for the MUX circuit and any additional logic elements.

4. Implement logic: Use the chosen HDL syntax to define the MUX logic, including
gates, connections, and select lines.

5. Add test bench: Design a test bench module to simulate the circuit's functionality.

3. Simulation and Analysis:

1. Compile code: Use Xilinx software to compile the HDL code into a format suitable for the FPGA
device.

2. Run simulation: Use Xilinx simulation tools like ModelSim to test the MUX circuit against the expected
outputs.

3. Analyze results: Verify output waveforms against the truth table for all input combinations.

4. Debug and refine: If discrepancies exist, analyze the results and refine the code to correct errors.

In electronics, a multiplexer (also called a data selector) is a device that selects between several
analog or digital input lines (signals) and forwards it to a single output line. A multiplexer of 2n inputs
(information) has n select lines (control, address inputs), used to select which input line to be sent to the
output. Multiplexers are mainly used to increase the amount of data that can be sent over the
communication network within a certain amount of time and bandwidth. An electronic multiplexer
makes it possible for several signals to share one device or resource, instead of having one device per
input signal. Multiplexers can also be used to implement Boolean functions of multiple variables. By
means of a multiplexer with n address inputs ( 2n information inputs), each Boolean function of n + 1
arguments can be realized. The most significant n arguments are connected to the address inputs of the
multiplexer, and its information inputs are given the Boolean functions of the least significant argument
(so-called remaining variable). These are the basic functions of an argument – constant 0, variable x,
inversion ( x) and constant 1 [1, 2, 3, 4, 5, 6].

The connection of information inputs can be determined in two ways:

- Tabular.

11
 - Using Karnaugh map.

The column “Remaining variable” is filled in according to the value of the function for each pair of
input combinations, differing only by the value of the least significant argument.

Using Karnaugh map. Pairs of input combinations, which differ only in the least significant
argument, are considered. For them, the function depends only on it. The common arguments of each
pair specify the address, and the value of the function – the basic function, fed to the corresponding
information input of the multiplexer.

Example 1: Build a circuit that implements the following Boolean function f ( x1, x2, x3, x4 ) = v ( 0,3,
4,5,9,10,12,13 ) using an eight-input multiplexer [1,2,3,4,5,6]

The solution of this example is illustrated in fig 1.

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 x3x4 00 01 11 10
x1x2
00 1 0
01 1 0
11 1 1 0 0
10 0 1 0 1

b c

Fig 1. Solution of Example 1 : a) Tabular ; b) Karnaugh map ; c) Circuit of the implementation of the
function

This is the so-called “traditional solution” (trivial), in which the address inputs are submitted to the
most significant three arguments. Based on the output function of the multiplexer, the location of the
information inputs in the Karnaugh map can be justified (Fig. 2).

Fig2. Justification of the location of the information inputs in the Karnaugh map in the “traditional”
solution

13
 It is possible, however, to submit three other arguments to the address inputs. In this case, one must
determine where the information inputs in the Karnaugh map are located, again based on the output
function of the multiplexer. This case is not considered in the paper [1, 4, 5, 6].

If the number of information inputs of the multiplexer is insufficient to implement the logic
function, cascaded (stepwise) multiplexer connection or additional logic gates are used to implement the
functions submitted to the information inputs.

Example 2: Build a circuit that implements the following function f ( x1, x2, x3 ) = v (0,1,3,6) using
a) a four-input multiplexer; b)cascade of 2-input multiplexers [1, 2, 4].

The Solution of this example is illustrated in Fig 3.

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 b

Fig. 3. Solution of Example 2: a) a four-input multiplexer;

b) a cascade of two-input multiplexers

FPGA IMPLEMENTATION

At present, the work with the laboratory board has not been used in the learning process on the
topic of implementing Boolean functions by multiplexers. It is expected to be included in the educational
process in the next academic year for the courses mentioned above. Below the problem that students will
have to solve during the classes is formulated.

Problem: Fill in the truth tables of the devices after programming the FPGA with the file
Mx_8_4_WG_xx.bit (xx = 01 ... 60). The devices implement: a) a function of four variables using 8-
input multiplexers (Example 1); b) a function of four variables with 4-input multiplexer and additional

logic gates (not considered in the paper); c) a function of three variables with a 4-input multiplexer
(Example 2); d) a function of three variables by a cascade of two-input multiplexers (not considered in
the paper). After filling in the truth tables of the devices after testing them with the laboratory board,
build the circuits of the devices that were used to create the bit file in ISE Project Navigator. If there is
free time during the classes, create your own bit file in ISE Project Navigator [4, 9].

Note: The generated bit file allows to examine the four devices by appropriately multiplexing the
outputs. After programming the FPGA with the specified bit file, only one student can work on one of
the four problems related to the multiplexers. The realization of these four functions on the laboratory
board is done by multiplexing the outputs, with input signals x7 and x6 being used to select one of the
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four functions (x7 = 0 and x6 = 0 for Problem 1, x7 = 0 and x6 = 1 for Problem 2, x7 = 1 and x6 = 0 for
Problem 3 and x7 = 1 and x6 = 1 for Problem 4). The enabling inputs of all multiplexers are connected
to a high level (logical 1). The match between the lab signals and the inputs and outputs of the devices
are given in the truth tables.

The implementation of the four examples is shown in Fig. 4. The implementation is based on their
schematic presentation in ISE Project Navigator. When creating the bit file, the student should draw the
circuit of only one of the four functions in ISE Project Navigator (Fig. 4, Block 1, the individual
problems are separated by a dash) and can use the input block for communication of the basic PCB with
the input module of the laboratory board (Fig. 4, Block 2). When combining the four functions into a
single bit file, it is also necessary to realize the multiplexing of the outputs (Fig. 4, Block 3). To avoid
this, the student can draw the circuit for each problem into a separate bit file. In order to properly
generate the bit files, corrections should also be made to the XC6T.ucf file, which specifies which of the
inputs and output signals will be used by the bit files.

Fig. 4. Implementation of functions using multiplexers – different schematic solutions based on their
schematic representation in ISE Project Navigator

Solution:

Problem 1: x7 = 0 and x6 = 0
16
a) implementing a function of 4 variables using an 8-input multiplexer

1. Filling in the truth table (by testing with the laboratory board – only the cells in color), Fig. 5:

2. Building the structural circuit (Fig. 1 c).

Problem 2: x7 = 0 and x6 = 1

b) implementing a function of 4 variables with 4-input multiplexer and additional logic gates.

Additional logic means any of the logic gates studied in the courses: repeater (x), NOT ( x ), OR (x +
y),AND(xy), NOR(x+y), NAND(xy), Prohibititon (xy), implication (x + y) , sum modulo 2 (known as
exclusive OR , XOR , x+y = xy+xy),equivalence ( EQU x = y = x.y + x.y = x + y). It may be necessary
to provide a constant 0 or a constant 1 at one of the information inputs.

Note: Each of the functions provided to the information inputs of the multiplexer must be implemented
with only one logic gate.

1.Filling in the truth table (by testing with the laboratory board – only the cells in color), Fig. 6:

In this case, the functions I0...I3 are determined in the type of sums of products and are
simplified by applying the Redundancy law. For their determination, Karnaugh maps for four variables
(Fig. 7) can also be used, describing the functions I0...I3 only with respect to the two non-addressing
variables.

2. Building the structural circuit (Fig. 8).

17
Fig. 5. Filling in the truth table, Problem 1, x7 = 0 and x6 = 0

Fig. 7. Justification of the location of the information inputs I 0…I3 in the Karnaugh map and
determining the functions I0…I3

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 Fig. 8. Implementation of a function of 4 variables using a 4-input multiplexer and additional logic
gates

. Fig .Testing with the laboratory board.

Output waveform :

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 Fig . Timing Diagram of 8:1 MUX

Fig . Schematic of 8:1 MUX

CHAPTER -3
CONCLUSION
A laboratory board based on Spartan-6 FPGA Family, developed at the University of Ruse, is
presented in the paper. The board is intended for teaching the courses “Pulse and Digital Devices” and
“Digital Circuits” for the students of the specialties “Electronics” and “Computer Systems and
Technologies”. The logic blocks in FPGAs can be configured to perform combinational functions. In
the courses different functional units of combinational type are studied. One of the topics is
“Implementation of Boolean functions using multiplexers” and using the laboratory board when
explaining the topic makes it more attractive and easier for assimilation by the students in the
University of Ruse. FPGA Implementation of Boolean functions with multiplexers using a laboratory
board is presented in the paper. It will be used in the training of electrical engineers in the courses
“Digital Circuits” and “Pulse and Digital Devices” introducing students of electrical specialties to the
main topics in digital electronics.
20
 CHAPTER 4
REFERENCES
[1] S. Todorova and Y. Ruseva, “Synthesis and Analysis of Logic Circuits”, University of Ruse
“Angel Kanchev”, Ruse, 2008 (in Bulgarian).
[2] V. Tzonev, “Pulse and Digital Devices”, Lectures, University of Ruse “Angel Kanchev”, Ruse,
2003 (in Bulgarian).
[3] V. Tzonev, N. Bencheva, Y. Ruseva, S. Todorova, “Pulse and Digital Devices”, Exercises,
University of Ruse “Angel Kanchev”, Ruse, 2003 (in Bulgarian).

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[4] A. Borodzhieva. “Pulse and Digital Circuits. Laboratory Practice with Modern Circuit Solutions -
FPGA (part 1). Ruse, Academic Publishing House “University of Ruse”, 2019, 100 pages, ISBN
978-954-712-783-8. (in Bulgarian) (in press).
[5] D. Grigorova, V. Mollov. “Analysis and Synthesis of Logic Circuits”. Technical University –
Sofia, 2009.
[6] S. Ivanov, Y. Petkova. “Analysis and Synthesis of Logic Circuits”. Technical University – Varna,
1998.
[7] I. Stoev, A. Borodzhieva, V. Mutkov. FPGA-Modelling and Simulation of Code Converters
Applied in the Educational Process. 11th Annual International Conference of Education, Research
and Innovation, Seville (Spain), 12-14 November 2018, Proceedings, pp. 10337-10346.
[8] https://teachingcommons.stanford.edu/resources/learning- resources/promoting-active-learning.
[9] Xilinx documentation, https://www.xilinx.com/content/
xilinx/en/downloadNav/design-tools/v2012_4---14_7.html.

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