2020 International Conference on Electrical and Electronics Engineering (ICE3-2020)

Implementation of 4X4 Fast Vedic Multiplier using GDI

Method
Rishu Yadav, Manish Kumar
rishu.yadav2408@gmail.com,
mkece@mmmut.ac.in
Department of Electronics and
communication Engineering
Madan Mohan Malaviya University of
Technology, Gorakhpur.

Abstract— Multipliers are used in the building blocks of
several processors. Conventional multiplication is time
consuming and lengthy process; to overcome these drawbacks
the circuit designers must develop speedy multipliers. Vedic
multipliers can be utilized for high speed multiplication
process. In Designing of CMOS circuits an issue of area is
always there, to reduce this Gate Diffusion input (GDI)
technique can be used. The GDI concept assist in reduction of
Transistor Count (TC), due to this power dissipation is
minimized. In this study the design of fast speed 4x4 Vedic
Multiplier has been presented using GDI technique. The power
dissipation of proposed multiplier is reduced as compared to
conventional CMOS multiplier.
Step 2: It states that, two binary bits are multiplied
crosswise; the product result is added with the earlier
generated carry. LSB bit will be used as the outcome in the
output bit and the residual bits is forward to the next step.
Step 3: MSB bits are multiplied vertically, where previous
generated carry and result is added to use output as a result
[1].
A1 A0 A1 A0 A1 A0

Keywords— And, Half Adder, Full Adder, Vedic Mathematics,

B1 B0 B1 B0 B1 B0
GDI. Fig 1: 2x2 Vedic Multiplications
I. INTRODUCTION
The Vedic multiplier is designed using Vedic mathematics. It The 2x2 Vedic multiplier is designed with the help of four
is named as an early mathematics; it was discovered by Shri AND gates and two half adders circuit, 4 bit output occurs.
Bhartiya Krishna Tirtha Maharaja. Vedic mathematics has 16 The diagram is shown in figure 2.
Sutras which helps in solving mathematical operation,
algebra and geometry [1]. For the multiplication, Urdhva
Tiryagbhyam method is used. In Urdhva Tiryagbhyam Sutra A1 B1 A0 B1 A1 B0 A0 B0
multiplication is done in vertical and cross wise operation. It
is based on an idea where the productions of all partial
products are completed by the simultaneous addition of AND AND AND AND
partial product. To reduce the power, Vedic multiplier
technique is used [2, 3].
A 4x4 multiplier is implemented by the amalgamation
of Vedic multiplier and GDI logic. Implementation of HALF ADDER
multiplier is done by using CMOS technique as well as GDI
technique and these are compared with each other, the result
of GDI technique leads to less delay. While designing a 4-bit
multiplier, the half adders as well as full adders are the main HALF ADDER
basic blocks in multiplier.
S1 S0
S3 S2
II. Vedic Multiplier For 2x2 bit
The Urdhva Tiryagbhyam method denotes that the
multiplication is completed vertically and crosswise process. Fig 2: 2-bit Vedic multiplier [5]
The 2x2 Vedic multiplication processes is performed using
following steps [6]:
Step 1: The initial LSB of two binary numbers is to be III. GDI TECHNIQUE
multiplied up as well as down, and then numbers are added GDI is a process in which less-power circuit is integrated, by
by previous carry, the previous carry will be zero in this case. reducing power dissipation, as well as propagation delay.
As a result, LSB bit is used in the output bits and bits which The complexity of the circuit reduces. By comparing the
are remaining is promoted to next step. conventional CMOS circuit and GDI circuit, the result of
GDI is better as compared to CMOS.

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 2020 International Conference on Electrical and Electronics Engineering (ICE3-2020)
The essential GDI cell has two transistors. It consists of three
inputs, which are G, P and N. The drain terminal of both the
transistor gives the output, and source terminal of a p-type
metal oxide semiconductor (pMOS) is single input and the
source of the n-type metal oxide semiconductor (nMOS) is
an additional input.
The variation in the method of CMOS and GDI is that in
case of GDI N, P, and G terminal can be set as a supply of
‘VDD’ or ‘GND’, or input signals are supplied with it by
depending on the design of the circuit.

IV. TOOLS AND TECHNIQUE

The main aim of this work is to calculate the power
dissipation and propagation delay for 4x4 Vedic multiplier.
Circuit simulation is done by Mentor graphics tools for
180nm technology.
Half adder and full adder are used to
implement the circuit. On the basis of GDI and CMOS
technology, the circuit diagram of half adder and full adder
is compared. The result of GDI is having less power
dissipation and then these basic blocks are used in designing
of 4 bit Vedic multiplier.

V. 4x4 VEDIC MULTIPLIER IMPLEMENTATION Fig 4: Full Adder Using GDI

In proposed work we have implemented 4x4 Vedic
multiplier by using GDI technique in all basic blocks used in
this multiplier, so firstly we implement the half adder and A A A
full adder using GDI circuit, these are the main blocks used
in implementation of multiplier.
A B CIN B CIN B CIN B B A

F.A.4 F.A.3 F.A.2 F.A.1 H.A.1

A B

H.A.3 H.A.2

F.A.8 F.A.7 F.A.6 F.A.5 H.A.4

Fig 3: Half Adder using GDI S6 S5 S4 S3 S2 S1

Half Adder using GDI is designed by pmos and nmos, the

output is in the form of sum and carry.
S0

Fig 5: Proposed 4x4 Vedic Multiplier

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 2020 International Conference on Electrical and Electronics Engineering (ICE3-2020)
The basic blocks of half adder and Full adders are used VII. CONCLUSION
inside the proposed model of 4x4 Vedic Multiplier. The
power delay product of the proposed multiplier has been Circuit complexity reduces, with the concept of GDI and
calculated with the help of concerned power dissipation and Vedic mathematics.The high -speed adders are designed
propagation delay. using GDI technique, which are used to reduce power
dissipation with increased speed. It is achieved due to
VI. RESULT AND ANALYSIS decrease in transistor counts.The 4x4 Vedic multiplier is
used to multiply four binary numbers and this multiplier
The result of CMOS and GDI circuits of full adder and half produce a lesser amount of power.
adder are compared and the power delay product is
calculated.
VIII. REFERENCES
Table 1: Comparison of basic blocks
[1] A. Garg and G. Joshi, “Gate diffusion input based 4-bit
BLOCK POWER DELAY POWER Vedic multiplier design,” IET Journals, vol. 12 Iss. 6, pp.
DISSIPATION DELAY 764-770, 2018.
PRODUCT [2] Z. Ariafar and M. Mosleh, “Effective Designs of
Conventional 906.43uW 50.01ns 0.0453nJ Reversible Vedic Multiplier,” International Journals of
Theoretical Physics, Springer, 2018.
Half Adder
[3] E. Prabhu, H. Mangalam and P. R. Gokul, “A Delay
Half Adder 189.07pW 12.51ns 0.236fJ Efficient Vedic Multiplier,” Springer, 2018.
using GDI [4] M. Shoba and R. Nakkeeran, “Energy and Area Efficient
logic Hierarachy Multiplier Architecture Based on Vedic
Conventional 211.45pW 59.87ns 0.0126fJ Mathematics and GDI logic,” Elsevier, 2016.
Full Adder [5] I. Khan and S. K. Dilshad, “Design of 2x2 Vedic
Full Adder 76.71pW 40.26ns 0.003fJ Multiplier using GDI Technique,” IEEE Conference,
2017.
Using GDI
[6] G. Ganesh Kumar and V. Charishma, “Design of High
Logic Speed Vedic Multiplier using Vedic Mathematics
Techniques,” International Journal of Scientific and
Research Publications, March, 2012.
The power dissipation of half adder using GDI is reduced to [7] M. Shams, M. Haghparast, K. Navi, “Novel reversible
189.07pW, and so as in full adder using GDI the reduction multiplier circuit in nanotechnology,” World Appl. Sci.
is 76.71pW. The delay is also reduced as compared to J. vol. 3 (5), pp. 806–810, 2008.
CMOS circuits.
Table 2 presents the power dissipation and propagation
delay of 4x4 Vedic multiplier using Conventional CMOS
and GDI circuits.

Table 2: Comparison of 4x4 Vedic Multiplier

BLOCK POWER DELAY POWER

DISSIPATION DELAY
PRODUCT
4x4 Vedic 13.0574uw 0.93ns 12.14fJ
Multiplier
using
Conventional
CMOS
4X4 Vedic 39.109pW 0.929ns 0.036zJ
Multiplier
using GDI
Technique

The power dissipation of 4x4 Vedic multiplier using GDI

logic is reduced as compared to conventional CMOS. The
area is reduced in the GDI, as less number of transistors is
used for designing of the circuit in case of GDI logic.

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