28 International Symposium on

th

VLSI Design and Test

(VDAt 2024)
Theme: EmergingstTechnologies for VLSI Design Ecosystem
rd 1 - 3 September 2024
Vellore Institute
1 -3
st rd

of Technology, Vellore September 2024

General Chairs
Sivanantham S, VIT Vellore
Venkata Rangam Totakura, Infineon Technologies
Organizing Chairs
Jagannadha Naidu K, VIT Vellore
Ananiah Durai S, VIT, Chennai
Technical Program Chairs
Kumaravel. S, VIT Vellore
Rahul H Iyer, Samsung, India
Shanti Rangaswamy, Intel, India
Tutorial Chairs
Renold Sam Vethamuthu, Microchip Technologies, India
Venkat Sunkara, Chip Edge, India
N.B.Balamurugan, TCE, Madurai
Sponsorship Chairs
Mehala Balasundaram, Synopsys, India
Karthikeyan B, VIT Vellore
Design Contest Chairs
Sivasankaran K, VIT Vellore
Padmanabhan, Intel, India
Noor Mohammed SK, IIIT Kancheepuram
Fellowship Chairs
Kala S, IIIT Kottayam
Philaman Daniel, NIT Silchar
Satheesh Kumar S, VIT Vellore
Anita Angeline A, VIT, Chennai
CALL FOR PAPERS
The VLSI Design & Test Symposium (VDAT) was organized as a workshop in 1998.
The growing number of researchers and practitioners in the VLSI sector has led to
VDAT's recognition as a symposium since 2005. The purpose of the Symposium is to
foster the sharing of new ideas, and industry knowledge among researchers, and
professionals in the many fields of VLSI Design and Testing. The Vellore Institute of
Technology (VIT) Vellore, Tamil Nadu will host the 2024 VLSI Design & Test
Symposium (VDAT-2024), a unique convergence of design and technology, on
September 1st to 3rd 2024. VDAT-2024 is Co-organized by the VLSI Society of India,
with support and sponsorship from leading institutes and the industry.
For More Information: VDAT 2024 Website
TRACKS
Emerging Devices and Material Technologies
PAPER SUBMISSION
VLSI Circuit and System Design
CAD for VLSI
Testing and Verification
Embedded Systems Design
Emerging Processors for System Design

Registration Chairs
Prayline Rajabai C, VIT Vellore
Aarthy M, VIT Vellore
TIMELI E N
th
Full Paper Submission 15 May 2024
Publication Chair
Arunachalam V, VIT Vellore Notification of Acceptance 15
th
July 2024

IEEE Madras Section EXCOM

Dr. K. Porkumaran, Chairman Camera Ready Paper 15
th
August 2024
Dr .P. Sakthivel, Vice Chairman – Academics

S MISSIO G IDELI ES
Dr. S. Joseph Gladwin Vice Chairman – Industry
Dr. R. Hariprakash, Secretary UB N U N
Dr. S. Radha, Treasurer

Publicity Chairs VDAT 2024 invites original, unpublished research articles on the above topics but not
Abirami R, Cadence, India limited to. Please submit your papers in PDF format (Portable Document Format)as
Harpreet Vohra, Thapar University, Patiala per the IEEE Conference paper format. Papers should not exceed six A4 size pages
Usha Mehta, Nirma University, Ahmedabad
Umakanta Nanda, VIT- AP and be uploaded via Microsoft CMT. All submitted papers will undergo double blind
Shubhajit Roy Chowdhury, IIT, Mandi review process. On acceptance notification, at least one of the authors should register
Shelja, VIT, Vellore and present in the conference to publish in the conference proceedings.
Website and Outreach Chairs
Prachi Sharma, VIT Vellore
Sridevi S, VIT Vellore
Advisory Committee
Navin Bishnoi, Marvell, India
Veeresh Shetty, Siemens, India
Srikanth B Settikere, Microchip Technologies, India
Santosh Kumar Vishvakarma, IIT Indore
Raja Subramaniam, Synopsys, India
Satya Gupta, President, VLSI Society of India
Chitra Hariharan, Secretary, VLSI Society of India
Vipin Madangarli, Global Foundries, India
Ganesan Narayanasamy, Stealth Mode, USA
98944 32359

Contact Us: vdat.chair@vit.ac.in

99430 62343