SIR C R REDDY COLLEGE OF ENGINEERING, ELURU

DEPARTMEMT OF ELECTRONICS AND

COMMUNACTIONS ENGINEERING

UNIT-I
8086 LOGIC PIN OUT

By
A.M. Vamsee Krishna
Assistant Professor
Dept .of ECE
Dept.of ECE, Sir.C.R.R.C.O.E, Eluru
 Signal Description of 8086

❖ INTEL 8086 is a 16-bit N-channel HMOS Microprocessor

❖ 8086 has 20- address lines and 16- data lines

❖ With 20-address lines 8086 can access upto 1MB (220) memory

❖ 8086 is a 40-pin DIP (Dual-In-Line ) packaged IC

❖ Requires a single +5V Power supply

❖ 8086 operates with a 5MHz clock frequency

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru
 Signal Description of 8086

❖ Other versions of 8086 processor are

❖ 8086-1 10 MHz clock frequency

❖ 8086-2 8 MHz clock frequency
❖ 8086-4 4 MHz clock frequency

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Limitations of 8086 IC

❖ INTEL 8086 has the following limitations

1. 8086 has multiplexed address, data and status signals

therefore these signal lines are to be Demultiplexed

2. Appropriate control signals need to be generated for

interfacing memory and I/O devices to 8086 processor

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

Logic Pin out of 8086:

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Logic Pin out of 8086

❖ All the signals of 8086 are can be defined into three groups :

1. Common signals

2. Minimum mode signals

3. Maximum mode signals

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

AD0 – AD15:

❖ These lines constitute time – multiplexed Address/Data bus

❖ During T1- clock cycle of the bus cycle they carry low-order 16-
bits of address

❖ During T2,T3,T4 - clock cycle they carry 16-bit data

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

A16/S3 – A19/S5:

❖ These are time – multiplexed lines

❖ During T1- clock cycle of the bus cycle they carry high-order 4-
bits of address

❖ During T2,T3,T4 - clock cycle they carry status signal

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

A16/S3 – A19/S5:
A16/S3-A17/S4:

❖ These lines carry the address

bits A16, A17 during T1 clock
cycle

❖ During T2,T3,T4 - clock cycle

these lines carry status signals
S3 and S4

❖ S3 and S4 signals are used to

identify memory segments
Dept.of ECE, Sir.C.R.R.C.O.E, Eluru
 Signal Description of 8086

A16/S3 – A19/S5:

A18/S5:

❖ The status signal S5 is multiplexed with the address line A18

❖ During T1- clock cycle eighteenth bit (A18) of address is

transferred over this line

❖ During T2,T3,T4 - clock cycle S5 status is transmitted

❖ S5 is interrupt enable status : Gives status of Interrupt Flag (IF)

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

A16/S3 – A19/S6:

A19/S6:

❖ The status signal S6 is multiplexed with the address line A19

❖ During T1- clock cycle nineteenth bit (A19) of address is

transferred over this line

❖ During T2,T3,T4 - clock cycle it remains low (S6 Low)

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

BHE’ / S7:
❖ Bus High Enable (BHE’) remains
low during T1 clock cycle

❖ BHE’ is used to enable data of

high order data line D8 - D15

❖ BHE’ signal in conjunction with

A0 address line to determine
whether a byte or word will be
accessing from memory

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

RD’ : (Active Low)

❖ This is Read control signal

❖ Read signal indicates that the selected I/O or memory device is

to be read

❖ Places data on data bus

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

READY: (Active High)

❖ An acknowledgement received from Peripheral device

❖ If this signal is LOW, Processor enters into wait state

❖ When this signal is high, indicates that peripheral device is

ready to transfer data

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

RESET: (Active High)

❖ System reset

❖ When this signal is LOW, Processor goes into reset state

❖ It clears DS, ES, SS and IP registers and code segment (CS) is

initialized with FFFF

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

NMI : (Active High)

❖ Non maskable interrupt request

INTR: (Active High)

❖ General purpose interrupt request signal

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

TEST’ : (Active Low)

❖ This signal is used to test the status of math co-processor 8087

❖ When TEST’ signal low , the 8086 goes to the next instruction
and continues execution of the program

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

MN/MX’ : signal indicates the operating mode of 8086 processor

❖ If MN/MX’ = 1 : processor operates in Minimum mode

MN/MX’ = 0 : processor operates in Maximum mode

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

CLK: clock input

❖ Connected to the clock generator 8284

Vcc : Power supply

❖ single +5V power supply is Connected

GND : Ground

❖ Connected to ground
Dept.of ECE, Sir.C.R.R.C.O.E, Eluru
 Minimum Mode signals of 8086

Minimum mode signals are:

INTA’ : Interrupt Acknowledge HOLD : Hold request

WR’ : Write control HLDA : Hold acknowledge

ALE : Address Latch Enable

DEN’ : Data Enable

DT/R’ : Data Transmit Receive

M/IO’ : Memory or I/O

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Minimum Mode signals :

INTA’ : (Active Low)- Interrupt Ackmowledge

❖ On receiving interrupt signal the processor issues an interrupt

acknowledge through this line

WR’ : (Active Low)

❖ This is write control signal

❖ Write signal indicates that the data on data bus are to be

written into selected I/O or memory device
Dept.of ECE, Sir.C.R.R.C.O.E, Eluru
 Signal Description of 8086

Minimum Mode signals :

ALE : Address Latch Enable

❖ This is a positive going pulse generated every time the

microprocessor begins an operation

❖ Generated during T1 – state of bus cycle

❖ It indicates that the bits on AD0 – AD15 are address bits (A0-
A15)

❖ This signal is used to latch low order 16-bit address from

multiplexed bus
Dept.of ECE, Sir.C.R.R.C.O.E, Eluru
 Signal Description of 8086

Minimum Mode signals :

DEN’ : (Active Low)- Data Enable

❖ In the minimum mode of operation processor used this signal to

enable 8286/8287 bus transceiver

DT/R’ : Data Transmit/ Receiver

❖ When minimum mode system incorporates the 8286/8287 octal
bus transceiver, This signal is used for data flow control

❖ If DT/R’ = 1 : data are sent

DT/R’ = 0 : data are received

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Minimum Mode signals :

HOLD : (Active High)

❖ When HOLD signal is activated by an external device, the

processor relinquishes control of address and data buses to I/O
device to use them

HLDA : (Active Low)

❖ On receiving HOLD signal the processor acknowledges through

this line

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Minimum Mode signals :

M/IO’ : This is a status signal used to differentiate between

memory and I/O operations

❖ If M/IO’ = 1 : indicates Memory operations

M/IO’ = 0 : indicates I/O operations

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Maximum Mode signals of 8086

Maximum mode signals are:

QS1, QS0 : Queue status

S’0 , S’1, S’2 : status signals

LOCK’ : lock prefix

RQ’/GT’0 , RQ’/GT’1 : Bus Request/ Bus Grant

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Maximum Mode signals :

QS1, QS0 : Queue status

❖ In the maximum mode,

QS1, QS0 signals are
used to indicate status
of Queue

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Maximum Mode signals :

S’0 , S’1, S’2 : status signals

❖ These signals are required by

8288 bus controller to generate
memory and I/O signals

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Maximum Mode signals :

LOCK’ : (Active Low)

❖ This signal is activated by LOCK prefix instruction

❖ Remains active until the completion of instruction prefixed by

LOCK

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

 Signal Description of 8086

Maximum Mode signals :

RQ’/GT’0 , RQ’/GT’1 : Bus Request/ Bus Grant (Active Low)

❖ These signal lines are bidirectional

❖ These requests are used by the other local bus maters to force
the processor to release local bus at the end of processor’s
current bus cycle

❖ RQ’/GT’0 has higher priority than RQ’/GT’1

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

Minimum Mode system:

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru

Maximum Mode system:

Dept.of ECE, Sir.C.R.R.C.O.E, Eluru