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Performance of Different Topologies for Three Level Inverter Based on Space

Vector Pulse Width Modulation Technique

Conference Paper · November 2014

DOI: 10.1049/cp.2014.1490

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 Performance of Different Topologies for Three Level Inverter
Based on Space Vector Pulse Width Modulation Technique
Zulkifilie Bin Ibrahim, Md. Liton Hossain, Syamim Binti Sanusi, Nik Munaji Bin Nik Mahadi, Ahmad Shukri Abu Hasim
Department of Power Electronics and Drive,
Faculty of Electrical Engineering,
Universiti Teknikal Malaysia Melaka,
Melaka, Malaysia
Email: drzulkifilie@utem.edu.my, mlhossaineee@yahoo.com, syamimsanusi@yahoo.com, nik.munaji@gmail.com,
asyuk31@yahoo.com

Keywords: DCLI; CCLI; CHBI; SVPWM; THD.
Abstract
Multilevel inverters are progressively being used in high-
power medium voltage energy control industrial drive
applications due to their superior performance compared to
conventional two-level inverters. There are a number of
topologies applied in recent years. The most widely applied
topologies are Diode Clamped Inverter (DCLI), Capacitor
Clamped Inverter (CCLI) and Cascaded H-Bridge Inverter
(CHBI). Three level DCLI requires additional 6 clamping
diodes and CCLI requires 3 clamping capacitors that make
the system bulky and quite difficult to implement while
increasing the number of level. CHBI requires no additional
diodes or capacitors and it is easy to implement. But it
requires 2 DC sources that increases the system cost. In this
paper, these three topologies for three level inverter using
space vector pulse width modulation (SVPWM) technique
has been modelled and simulated using
MATLAB/SIMULINK and Origin 6.1 for a passive R-L load.
From the simulation results, CHBI with separate DC source
(CHBISEDCS) shows the better performance to the others in
terms of THD. CHBI using single DC (CHBISDC) source is
also presented and compared with CHBISEDC. CHBISDC
shows better performance without significant increase of
THD compared to CHBISEDC. Hence CHBISDC minimizes
the system cost and provides better performance.
inverter topologies to increase the power delivered to the load
and to improve the quality of the voltage [2]. The most
common topologies are diode clamped, capacitor clamped
and cascaded h-bridge inverter. In this paper, these three
topologies has been modelled, simulated and analysed based
on space vector pulse width modulation (SVPWM) technique.
The on-time calculation is based on two level SVPWM
algorithm that is simple and the equations of on-time
calculation do not change with the position of reference
vector like the conventional algorithm. In the space vector
diagram of an m-level inverter, the triangle where the
reference vector is positioned is identified as integer ∆n. Any
switching sequence can be generated with respect to triangle
∆n, leading to an easiness and flexibility of optimizing the
switching sequence. Three level space vector diagram is
divided into six sector each containing four triangles shown in
figure 1. Shantanu Chatterjee used 7 switching states for
triangle 1, 4 switching states for triangle 2 and 4 and 5
switching states for triangle 3 that needed more memory
space, more computation time and more lookup table [3]. In
this control technique, there have been proposed only four
active switching states in each triangle shown in table 1 that
required less number of lookup table and computations. This
technique can be used for any m-level inverter without any
significant increase in computations.

1 Introduction
Multilevel inverters has brought attractive interest in high-
power medium voltage industrial drive applications due to
their superior performance compared to conventional two-
level inverters. Harmonic distortion is high for conventional
inverter that reduces the machine’s life time and create
synchronization problem with grid voltage. Due to the
reduction of harmonic distortion of conventional inverter, a
large size of filter is needed that makes the system very bulky.
Hence, a new family of multilevel inverters has developed as
the solution for working with higher voltage levels and lower
harmonic distortion [1]. Harmonic distortion can be reduced
significantly by using suitable topology and control
technique. Rodríguez and Lai discussed several multi-level Figure 1: Space vector diagram for three level inverter

1
 Sector Triangle No. Sequence of Active Vectors
0 111-211-221-222
1 100-200-210-211
1 operation, int and rem are standard math function of integer
2 100-110-210-211
3 110-210-220-221
0 111-121-221-222
1 110-120-220-221
2
2 110-120-121-221
3 010-020-120-121
0 111-121-122-222
1 010-020-021-121
3
2 010-011-021-121
3 011-021-022-122
0 111-112-122-222
1 011-012-022-122
4
2 011-012-112-122
3 001-002-012-112
0 111-112-212-222
1 001-002-102-112
5
2 001-101-102-112
3 101-102-202-212
0 111-211-212-222
1 101-201-202-212
6
2 101-201-211-212
3 100-200-201-211
Table 1: Switching Sequence of Active Vectors for Three
Level Inverter
2 SVPWM algorithm
SVPWM compensates the required volt-seconds using
discrete switching states and on-times. The classical two-level
space vector pulse width modulation technique can be used
for on-time calculation. The space vector diagram is a
hexagon consisting of six sectors. Every sector consists of
equilateral triangle of unity side and h (=√3/2) is the height of
a sector [4]. The on-time calculation is same for all sectors.
The calculation of ON times,
= − (1)
= (2)
= − − (3)
Where Ts = 1/2fs, fs is the switching frequency. For any given
reference vector, the sector of operation and its angle within
the sector is determined by using Equn. (4) and equn. (5),
respectively.
= +1 (4)
! = "#$ (5)
2
In eqn. (4) and eqn. (5), %(0 ≤ % ≤ 360) is the angle of the
reference vector with respect to x-axis, !(0 ≤ ! ≤ 60) is the
angle within the sector and (1 ≤ ≤ 6) is its sector
and reminder.
Triangle can be divided into two types for each sector. Type 1
triangle has its base side at the bottom and type 2 triangle has
its base side at the top. The triangle number ∆. can be
determined in terms of two integer variables P1 and P2, that
are dependent on the position of reference vector( , 0 ).
12 = + (6)
√4
1 =
(7)
Eqn. (6) signifies the part of the sector between the lines
5 + √3 = √312 and √36 = √3(12 + 1) . This forms one
region and Eqn. (7) signifies the part of the sector between the
lines 5 = ℎ. 12 and 5 = ℎ. (12 + 1)[5]. This forms another
region. Let ( , 0 ) be the coordinates of the reference
vector with respect to the origin of the rhombus.
= − 12 +. 51 (8)
0 = 0 −1 ℎ (9)
In eqn. (8) and eqn. (9), ( / 0 ) is the slope of the line
between the origin of the rhombus and the reference vector
and it is compared with slope of the diagonal of the rhombus
which is √3 [5].
The slope evaluation is done by comparing inequality
( 0 ≤ √3 ) and to determine the small vector VZ and the
triangle number ∆. . If ( 0 ≤ √3 ) which indicates
triangle of type 1 and these triangles are similar to sector 1 of
two-level inverter. The triangle number ∆. is obtained from
eqn. (10).
∆. = 12 + 21 (10)
If ( 0 > √3 ) which indicates triangle of type 2 and these
triangles are similar to sector 2 of two-level inverter. The
triangle number ∆. is obtained from eqn. (11).
∆. = 12 + 21 + 1 (11)
In eqn. (10) and eqn. (11), ∆ indicates the triangle and n is the
triangle number. Hence, ∆. is an integer and signifies nth
triangle in the sector. Using eqn. (10) and eqn. (11), to
identify triangle in a sector and the on times are calculated
using eqns. (1)–(3). The ∆. is formulated to provide a simple
way of arranging the triangle, leading to ease of identification
and extension to any level. The switching sequences are
shown in table 2 for DCLI and CHBI and table 3 for CCLI.
 Switching States for Phase A
Terminal
Voltage
Sa1 Sa2 Sa3 Sa4

1 1 0 0 Vdc

0 1 1 0 Vdc/2

0 0 1 1 0

Table 2: Switching Sequence of Phase A for DCLI and CHBI

Figure 3.1 Three level diode clamped inverter

Switching States for Phase A
Terminal
Voltage
Sa1 Sa2 Sa3 Sa4

1 1 0 0 Vdc

0 1 1 0 Vdc/2

0 0 1 1 0

Table 3: Switching Sequence of Phase A for CCLI

3 Three different topologies Figure 3.2 Three level capacitor clamped inverter
The concept of multilevel converters has been presented since
1975 [6]. Since Nabea A. proposed the three-level inverter
during the IAS annual conference in 1980, the multilevel
converter has advanced rapidly and has been a hotspot for
high-power applications as a new breed of power converter
option. From previous research, it was shown that the
multilevel converter has better performance than conventional
converters in terms of harmonic distortion [7]. Different
multilevel converter topologies have been proposed during
the last two decades for this purpose [1]. The most three
common topologies for multilevel inverter are capacitor
clamped; diode clamped and cascaded half bridge topologies.
There are 6 (m-2) numbers of diodes required for m level
diode clamped inverter. Three level diode clamped inverter is
shown in figure 3.1. There are 3(m-2) capacitors required for
m level capacitor clamped inverter. Three level capacitor Figure 3.3 Three level cascaded h-bridge inverter
clamped inverter is shown in figure 3.2. With the increase of
level, more number of diode or capacitor are required that
make the system bulky and quite difficult to implement. This
problem is solved by cascaded half bridge multilevel inverter
topology that is free from clamping diodes or capacitors.
Three level cascaded h-bridge inverter is shown in figure 3.3.
But each half bridge requires separate DC source that increase
the system cost. This problem can be solved by using
conventional capacitor paralleled to single DC source. Three
level cascaded h-bridge inverter using single DC source based
on SVPWM is shown in figure 3.4. Hence, cascaded h-bridge
topology using single dc source minimizes the system cost,
make the system easy to implement without significant
reduction of the inverter output performance.
 2

C urrent ( A )
1
0
-1
-2
0 2000 4000 6000 8000 10000
Time (ms)
Figure 3.4 Complete simulation block diagram for three Figure 4.3: Measurement of three phase current for
level cascaded h-bridge inverter based on SVPWM CHBISEDCS

4 Result and discussion 2

C urrent ( A )
Simulations are performed for these three topologies based on 1
SVPWM by using MATLAB/Simulink and Origin 6.1. The
measurements of current THD are 3.96%, 2.89% and 2.69% 0
for DCLI, CCLI and CHBI respectively. CHBI shows the best
performance to the others in terms of current HD shown in -1
figure 4.1. Fundamental harmonic distortion is always 100%
that has been skipped due to simplicity of graphical -2
presentation. The measurements of voltage THD are 28.11%,
27.97% and 27.57% for DCLI, CCLI and CHBI respectively. 0 2000 4000 6000 8000 10000
Time (ms)
Figure 4.4: Measurement of three phase current for
1.0 CHBISDC
DCLI
0.8 CCLI
CHBI
HD( %)

0.6

0.4

0.2

0.0
2 4 6 8 10 12 14 16 18 20
Harmonic Order
Figure 4.1: Measurement of current HD for three topologies

Figure 4.5: Measurement of current THD for CHBISEDCS

1.5
DCLI
CCLI
1.0 CHBI
HD( %)

0.5

0.0

2 4 6 8 10 12 14 16 18 20
Harmonic Order

Figure 4.2: Measurement of voltage HD for three topologies Figure 4.6: Measurement of current THD for CHBISDC
 200 70

No. of Com pone nt s

60 DCLI
V o lta g e ( V )

100 CCLI
50
CHBI
40
0
30
-100 20
10
-200
0
0 2000 4000 6000 8000 10000 2 3 4 5 6 7
Time (ms) Number of Level
Figure 4.7: Measurement of voltage for CHBISEDCS Figure 4.11: Required no. of components with level of
inverter for three topologies
200 CHBI shows enhance performance to the others shown in
figure 4.2. Three phase output current are shown in figure 4.3
V o lta g e ( V )

100 and 4.4 for CHBISEDCS and CHBISDC respectively. Their

HDs are shown in figure 4.5 and 4.6 respectively. Though
0 CHBISEDCS shows better performance than CHBISDC, both
satisfied the IEEE519 standard on harmonics level. Output
-100 line-line voltages are shown in figure 4.7 and 4.8 respectively.
They show consistent performance in terms of THD shown in
figure 4.9 and 4.10 respectively. Required number of
-200 components with levels is compared for these three topologies
0 2000 4000 6000 8000 10000 in figure 4.11. CHBI requires lesser number of components
Time (ms) (no. of (IGBT + diode + capacitor)) that reduces the system
Figure 4.8: Measurement of voltage for CHBISDC cost.

5 Conclusion
Three different topologies are presented and analyzed based
on SVPWM in this technical paper. CCLI shows better
performance than DCLI and CHBI shows better performance
than CCLI in terms of THD and required no. of components.
CHBISDC shows better performance without significant
reduction of THD compared to CHBISEDC. Hence,
CHBISDC requires lesser no. of components i.e minimizes
the cost and provides the better output performance to the
others.

Acknowledgements
Figure 4.9: Measurement of voltage THD for CHBISEDCS
This work has been supported by Malaysian Technical
Universities Network (MTUN) grant. All the research
students of the Research Laboratory of Electric Vehicle and
Drive in UTeM are thanked for contributing to solve many
critical problems.

References
[1] Jose Rodriguez, Steffen Bernet, Peter K. Steimer, Ignacio
E. Lizama, “A Survey on Neutral-Point-Clamped
Inverters”, IEEE Transactions on Industrial Electronics,
Vol. 57, No. 7, Jul, 2010.
[2] José Rodríguez, Jih-Sheng Lai, Fang Zheng Peng,
Figure 4.10: Measurement of voltage THD for CHBISDC “Multilevel Inverters: A Survey of Topologies, Controls,

5
 and Applications”, IEEE Transactions on Industrial
Electronics, Vol. 49, No. 4, Aug, 2002.
[3] Shantanu Chatterjee, “A Multilevel Inverter Based on
SVPWM Technique for Photovoltaic Application”,
International Journal of Power Electronics and Drive
System, Vol. 3, No. 1, March 2013.
[4] Amit Kumar Gupta, Ashwin M. Khambadkone, “A
Space Vector PWM Scheme for Multilevel Inverters
Based on Two-Level Space Vector PWM”, IEEE
Transactions on Industrial Electronics, Vol. 53, No. 5,
Oct, 2006.
[5] M. Valan Rajkumar, P.S. Manoharan, “FPGA based
multilevel cascaded inverters with SVPWM algorithm
for photovoltaic system”, ScienceDirect, Vol. 87, 229–
245, 2013.
[6] N. Mohan Teja, R S Ravi Sankar, Talath Anjum,
P.Sanjay, “Waveform Analysis of New Diode Clamped
and Cascaded H-Bridge Multilevel Inverters with PWM
Technique”, International Journal of Innovative
Technology and Exploring Engineering, Vol. 3, Issue. 10
March 2014.
[7] XU Xiang-lian, ZOU Yun-ping, DING Kai, WANG
Cheng-zhi, JIN Hong-yuan, “Research on cascaded
multilevel inverter and its application in STATCOM”,
Front. Electr. Electron. Eng. China, Vol. 4, Pages:
390−395, 2006.

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