PERFORMANCE EVALUATION OF

MULTILEVEL INVERTER FED INDUCTION

MOTOR DRIVE

A DISSERTATION
Submitted in partial fulfillment of the
requirements for the award of the degree
Of
MASTER OF TECHNOLOGY
in
ELECTRICAL ENGINEERING
(With Specialization in Electric Drives and Power Electronics)

By
B.RAJENDER

(* (~ at t o i 9i,
.........._......,
Date !'....

DEPARTMENT OF ELECTRICAL ENGINEERING

INDIAN INSTITUTE OF TECHNOLOGY ROORKEE
ROORKEE•247.667 (INDIA)
JUNE, 2011
 CANDIDATE'S DECLARATION

I hereby declare that the work, which is being presented in the dissertation entitled
Performance evaluation of Multilevel Inverter fed Induction Motor Drive" in the partial fulfillment
f the requirements for the award of degree of M. Tech. in the Electric Drives & Power Electronics
Decialization, submitted in the Department of Electrical Engineering, IIT Roorkee, is an authentic record
f my own work carried out under the guidance of Dr. M. K. Pathak, Assistant Professor and Dr. G.K.
,ingh, Professor, Electrical Engineering Department, IIT Roorkee.

The matter embodied in this dissertation has not been submitted by me for the award of any
►
ther degree or diploma of this institute or any other university/institute.
0

B.RAJENDER
En. No. 09527005
Date: 30-06-2011 M.Tech. (EDPE)
Place: Roorkee IIT Roorkee

CERTIFICATE

This is to certify that the above statement made by the candidate is correct to the best of our
knowledge and belief.
ad!~lnT
(Dr. G.K. Sumgnj (Dr. M.KPathak)
Professor, Assistant Professor,
Electrical Engg. Dept. Electrical Engg.Dept.
lIT Roorkee. IIT Roorkee.
 ACKNOWLEDGEMENTS
I take this opportunity to express my sincere gratitude to Dr. M.K.Pathak, Assistant Professor
and Dr. G.K. Singh, Professor, Electrical Engineering Department, IIT Roorkee, for encouraging me to
undertake this dissertation work as well as providing me all the necessary guidance and inspirational
support throughout this work, without which this work would not have been in its present shape.

Special sincere heartfelt gratitude to my parents whose sincere prayer, best wishes, concern,
support, unflinching encouragement and thoughtfulness has been a constant source of strength to me
during the entire work.

I thank all the members of Electrical Engineering Department for their help and encouragement
at the hour of need.

My special thanks to all my friends for their valuable suggestion and discussions.

Last, but not the least, I thank to Almighty God whose Divine Light provided me guidance,
inspiration and strength to complete this work.

(B.RAJENDER)
 ABSTRACT
Multilevel inverters are increasingly being used in high-power medium voltage applications due to
their superior performance compared to two-level inverters, such as lower common-mode voltage,
lower dv/dt, lower harmonics in output voltage and current, and reduced voltage on the power
switches. Especially for use in high power applications, some medium voltage motor drives and
utility applications require medium voltage and megawatt power level. For a medium voltage grid,
it is troublesome to connect only one power semiconductor switch directly. As a result, a
multilevel power converter structure has been introduced as an alternative in high power and
medium voltage situations. All the matters are that minimize the THD in conventional two level
voltage source inverter (VSI) is towards various PWM techniques. However , this trend invited
problems, like the increase of switching frequency increased the switching loses, generating a
common mode voltage which becomes significant at high power levels. Multi level power
converters have gained much attention in recent years due to the proven mitigation of various
problems sited above. The general structure of the multi level inverter is such as to synthesize a
sinusoidal voltage from several levels of DC voltage. Increasing the number of levels produces a
fine staircase wave form approaching close to a sinusoidal wave with minimum harmonic
distortion.
In this simulation of various inverters Two level and Three Level NPC Inverter is carried
out and the performance of these Inverters with different Modulation Control Schemes and under
various operating conditions by changing the load and output frequencies are Investigated. The
work mainly focuses on the improvement in THD of both voltage and current wave forms from
normal VSI PWM inverter to Three Level Neutral Point Clamped inverter. Space Vector
Modulation Scheme for both Two and NPC Inverter have been implemented, from this observed
that as THD Values are reduces to very desired values, and the performance is highly superior to
other Modulation Schemes, inverters in reduced harmonic distortion, lower EMI (Electro Magnetic
Interference) and higher dc link voltages The performance of scalar v/f control of the 3-phase
induction motor drive fed from both conventional three phase inverter and neutral point clamped
inverter is investigated in closed loop.
 Table of Contents

Candidate's declaration i
Acknowledgement ii

Abstract iii

List of Figures vii

List of Tables xi

Chapter 1: Introduction and Literature Review 1

1.1. Introduction 1

1.2 Technical Requirements and Challenges to MV Drives 3

1.2.1 Line-Side Requirements 4
1.2.2 Motor-Side Challenges 4
1.2.3 Switching Device Constraints 5
1.2.4 Drive System Requirements 6
1.3 VSI fed induction motor drive 6
1.4. Multi level Inverter Fed Induction Motor Drive 8
1.5 MV industrial drives based on three level NPC inverter 9
1.6. Three-Phase Induction Motor 11

1.6.1 Introduction 11

1.6.2 Speed control of Induction Motor 12

1.7 Literature Review 17

1.8 Conclusion 19

1.9 Organization Of This Thesis - — 20

Chapter 2: Multilevel Inverter Topologies 21

2.1 Multilevel power conversion concept and Voltage level notation 21

2.2 Multilevel Power Converter Topologies 25

iv
 2.2.1 Neutral Point Clamped(NPC) Multilevel Converters 25

2.2.2 Flying-Capacitor Multilevel Converters 35

2.2.3 Cascaded H-Bridge Multilevel Converters 36

2.3 Application of Multilevel Inverters 38

2.4 Conclusion 40

Chapter 3: Control Strategies of Multi level Inverter 41

3.1. Introduction 41

3.2 Multilevel Converter PWM Strategies 42

3.3 Selective Harmonic Elimination PWM 43

3.4 Sinusoidal Pulse Width Modulation 44

3.5 Third Harmonic Injection PWM 46

3.6 Space Vector Control 47

3.7 Direct Torque Control 48

3.8 Space vector Pulse Width modulation 49

3.9 SVM for Three Level Inverter 55

3.10 Neutral Point Voltage Control 65

3.11 Conclusion 65

Chapter: 4 Performance evaluation of Multilevel Inverter Fed Induction Motor Drive 66

4.1 Two Level Inverter Fed Induction Motor Drive 66

4.1.1 Sinusoidal Pulse Width Modulation 66

4.1.2 Third Harmonic Injection PWM 74

4.1.3 Space Vector Pulse Width Modulation 79

4.2 Three Level NPC Inverter fed Induction Motor Drive 85

V
 4.2.1 Level Shift Multicarrier PWM

4.2.2 Third harmonic injection Multicarrier PWM 91

4.2.3 Space Vector Pulse Width Modulation for Three Level NPC Inverter 96

4.3 THD Variation with Frequency 102

4.4 Conclusion 103

Chapter: 5 Conclusion and Future Scope 104

5.1 Conclusion 104

5.2 Scope for Future Work 105

References 106

Appendix 110

vi
 LIST OF FIGURES

Fig.No Description Pg.No

1.1 Voltage and Power Rating of MV Drive 2
1.2 Voltage Source Inverter fed Induction Motor 7
1.3 Line to Line Voltage of VSI 7
1.4 NPC Inverter fed Induction Motor 8
1.5 Line to Line Voltage of NPC Inverter 9
1.6 GCT-based three-level NPC inverter-fed MV drive 10
1.7 IGBT-based three-level NPC inverter-fed MV drive 10
1.8 Torque Vs speed for different voltage levels 13
1.9 Open-Loop V/f Control & variation of voltage with frequency 14
1.10 Voltage boost at lower speeds 15
1.11 Torque-Speed variation showing effect of frequency variation, load torque 15
and supply voltage
1.12 Closed-Loop speed control of induction machine using V/f principle 16
2.1 Multi Level Inverter System 22
2.2 Output Voltage for various Level 23
2.3 Nine Level Inverter Voltage Wave Form 23
2.4 Classification of Multi level Converters 25
2.5 Three level NPC Inverter 27
2.6 Switching State, Gate Signal and Inverter Terminal Voltage V,z 28
2.7 Inverter terminal and Line to Line voltage Waveforms 29
2.8 Gate Signal Commutation During switching transition 29
2.9 Commutation with iA>0 30
2.10 Commutation with iA< 0 31
2.11 line voltage waveforms of the 5-level diode clamped converter 32
2.12 Waveforms showing capacitor charging profile 33
2.13 One Phase Leg of Three Level Flying Capacitor Inverter 35
2.14 Cascaded H-bridge topology with two cells. 36
2.15 Switching states of the H-bridge cell. 37
3.1 Classification of PWM Multi level Converter Modulation Strategies 42
3.2 Generalized stepped-voltage waveform. 43
vii
3.3 Sinusoidal pulse-width modulation (SPWM). 44
3.4 Inverter cell voltages 45
3.5 Total voltage of three cells in series connection for different phase 46
Displacement in the carriers.
3.6 Modulating wave VmAwith third harmonic injection. 47
3.7 Load voltage space vectors generated by an 11-level inverter 47
3.8 Voltages generated by an 11-level inverter with SVC 48
3.9 Three phase two level inverter 49
3.10 Three-phase Two-Level Inverter Switching States 50
3.11 Space vector diagram for the two-level inverter 52
3.12 53
Vref zed by V ,V2 ,Vo
synthesized
3.13 Seven Segment Switching Sequence for Vref in sector 1 54
3.14 Space vector diagram of the NPC inverter. 57
3.15 Division of sectors and regions. 57
3.16 Voltage vectors and their dwell times. 59
3.17 61
The relationship between the locations of Vref and dwell times.

3.18 Effect of Switching States on Neutral point voltage deviation 63

3.19 Seven-segment switching sequence for Vref in sector I-4. 64
4.1 Simulink block for all two level inverter fed induction motor drive 67
4.2 SPWM Control Scheme for 2-level PWM Inverter 67
4.3 Sinusoidal Pulse width Modulation 68
4.4 Line to Line Voltage (volt) 68
4.5 Stator current on No load 69
4.6 Performances of Speed(Rpm), Torque(N-m). 69
4.7 Performances of Stator currents(amp). 70
4.8 Performance of Speed(Rpm), Torque(N-m) with load 70
4.9 Line to Line voltage and Harmonic Spectrum 71
4.10 Line currents (amp) and Harmonic Spectrum 71
4.11 Stator current Ia (amp) 72
4.12 Performance of Speed(Rpm), Torque(N-m) with 40 Hz 72
4.13 Stator Currents (amp) with Change in Load 73

viii
4.14 Performance of Speed(Rpm), Torque(N-m) with change in load 73
4.15 Control Scheme Block for Third Harmonic Injection SPWM 74
4.16 Block for Third Harmonic Injection 74
4.17 Response of Stator Current Ia 75
4.18 Performance of Speed(Rpm), Torque(N-m) with load 75
4.19 Line Voltage(Volt) and Harmonic Spectrum 76
4.20 Current Wave form and Its Harmonic Spectrum 76
4.21 Performance of Speed and torque with 40Hz supply 77
4.22 Variation of Speed(Rpm), Torque(N-m) and Flux(Wb) during Step Change 78
in load
4.23 Response in Stator Currents during step change in load 78
4.24 Simulink Block of SVM Control Scheme 79
4.25 Line to Line Voltages 80
4.26 Stator Currents of Inverter with load 80
4.27 Performances of Speed (Rpm),Torque(N-m) and Flux with 10(N-m) load 81
4.28 Performances of Speed and Torque with Supply Frequency 40Hz 81
4.29 Response of Speed and Torque During Step Change in Speed .7 Sec 82
4.30 Line voltages and Harmonic Spectrum 82
4.31 Line Currents and Harmonic Spectrum 83
4.32 Generalized simulink block for Three Level NPC Inverter 85
4.33 Two carrier signal with level shifted, with sinusoidal modulating wave 85
4.34 Control Scheme for Level Shift PWM 86
4.35 Variation of Speed and Torque with no load 86
4.36 Stator Currents with Load 87
4.37 Performance of Speed(Rpm), Torque(N-m) 87
4.38 Line voltages and its harmonic spectrum 88
4.39 Line Currents and Harmonic Spectrum 88
4.40 Stator Currents Ia, lb and Ic(Amp) 89
4.41 Response of Torque(N-m) and Speed(Rpm) with 40Hz 89
4.42 Performance of speed and torque with change in speed at 0.3 sec 90
4.43 Performance of Speed(Rpm) and Torque(N-m) During Step Change in Load 90
4.44 Simulink Model for Control Scheme 91
4.45 Third Harmonic injection in Modulating Wave 91
ix
4.46 Line to Line Voltages 92
4.47 Performance of Speed and Torque on No Load 92
4.48 Stator Currents with No Load 92
4.49 Performance of Speed and torque on Full Load 93
4.50 Stator Currents with full Load 93
4.51 Line Voltages and Harmonic Spectrum 94
4.52 Line Current and Harmonic Spectrum 94
4.53 Stator Currents(Amp) changing when load Change after .3 Sec 95
4.54 Variations in Torque(N-m) and Flux(Wb) with Load 95
4.55 Generalized block diagram of Three level NPC Inverter 96
4.56 Phase Voltages Vaz, Vbz,Vcz of NPC Inverter 97
4.57 Line to Line Voltages Vab, Vbc, Vca(volts) 97
4.58 Line Current(amp) and Hormonic Spectrum 98
4.59 Line Voltage and Harmonic Spectrum 98
4.60 Variations in Speed Torque and Current With No load 99
4.61 Performance variation in speed and torque 99
4.62 Voltage THD variations vs Increasing in Levels with different 101
modulationschemes
4.63 Current THD variations vs Increasing in Levels with different modulation 101
schemes
4.64 THD Variation with frequency for different modulation schemes 102
4.65 THD Variation with frequency for different modulation schemes 103

x
 List of Tables
'able No Description Pg No.

.l Definition of Switching State 27

!.2 Component Count of diode clamped multi level inverters 34

3.1 Definition of Switching State 51

3.2 Space Vectors, Switching States and On State Switches 51

3.3 Representation of Switching Sequence 55

3.4 Voltage Vectors and switching States 58

3.5 Dwell Time Calculations 60

4.1 Line Current THD% for two level 84

4.2 Line Voltages THD% for two level 84

4.3 Line Current THD% for three level 100

4.4 Line Voltages THD% for three level 101

xi
 CHAPTER 1
INTRODUCTION AND LITERATURE REVIEW

This Chapter focuses on Introduction to Multi Level Inverter fed Medium Voltage Drives
system, Technical Challenges to Medium Voltage Drives and what is the necessity of Multi
Level Inverters and comparison with Voltage source Inverter, Introduction to Induction Motor,
scalar V/f Control and Literature Review of multi Level Inverters and organization of this Thesis
work.
1.1 Introduction
Multilevel converter technologies are receiving increased attention recently, especially
for use in high power applications, some medium voltage motor drives and utility applications
require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome
to connect only one power semiconductor switch directly. As a result, a multilevel power
converter structure has been introduced as an alternative in high power and medium voltage
situations. A multilevel converter not only achieves high power ratings, but also enables the use
of renewable energy sources. The concept of multilevel converters has been introduced since
1975. The term multilevel began with the three-level converter. The general structure of the
multilevel converter is to synthesize a sinusoidal voltage from several levels of voltages,
typically obtained from capacitor voltage sources.
However, the elementary concept of a multilevel converter to achieve higher power is
to use a series of power semiconductor switches with several lower voltage do sources to
perform the power conversion by synthesizing a staircase voltage waveform. The commutation
of the power switches aggregate these multiple dc sources in order to achieve high voltage at the
output; however, the rated voltage of the power semiconductor switches depends only upon the
rating of the dc voltage sources to which they are connected.
Multilevel power conversion was first introduced 20 years ago [1]. The general concept
involves utilizing a higher number of active semiconductor switches to perform the power
conversion in small voltage steps. There are several advantages to this approach when compared
with traditional (two-level) power conversion. The smaller voltage steps lead to the production of
higher power quality waveforms and also reduce the dv/dt stresses on the load and reduce the

1
electromagnetic compatibility (EMC) concerns. Another important feature of multilevel
converters is that the semiconductors are wired in a series-type connection, which allows
operation at higher voltages. However, the series connection is typically made with clamping
diodes, which eliminates overvoltage concerns. Furthermore, since the switches are not truly
series connected, their switching can be staggered, which reduces the switching frequency and
thus the switching losses.
The development of high-power converters and medium-voltage (MV) drives started in
the mid-1980s when 4500-V gate turn off (GTO) thyristors became commercially available [2].
The GTO was the standard for the MV drive until the advent of high-power insulated gate
bipolar transistors (IGBTs) and gate commutated thyristors (GCTs) in the late 1990s [3, 4].
These switching devices have rapidly progressed into the main areas of high-power electronics
due to their superior switching characteristics, reduced power losses, ease of gate control, and
snubberless operation. The MV drives cover power ratings from 0.4 MW to 40 MW at the
medium voltage level of 2.3 kV to 13.8 kV. The power rating can be extended to 100 MW where
synchronous motor drives with load commutated inverters are often used [5]. However, the
majority of the installed MV drives are in the 1- to 4-MW range with voltage ratings from 3.3 kV
to 6.6 kV as illustrated in Fig. 1.

0.4MW ~, 1 MW 2MW 4MW / 10MW 40 MW

2.3 kV \,~3.3 kV 4.16 kV 6.6 kV ~.' it kV 13.8 kV

Fig. 1.1 Voltage and Power Rating of MV Drive

The high-power MV drives have found widespread applications in industry.They are used
for pipeline pumps in the petrochemical industry [6], fans in the cement industry [7], pumps in
water pumping stations [8], traction applications in the transportation industry [8], steel rolling
mills in the metals industry [10], and other applications [11,12]. In recent years, there has been a
substantial increase in interest in multilevel power conversion. This is evident by the fact that
some Institute of Electrical and Electronic Engineers (IEEE) conferences are now holding entire
2
sessions on multilevel converters. Recent research has involved the introduction of novel
converter topologies and unique modulation strategies. Some applications for these new
converters include industrial drives [13-15], flexible AC transmission systems (FACTS) [16-
18], and vehicle propulsion [19, 20]. One area where multilevel converters are particularly
suitable is that of medium-voltage drives [21].
Among various modulation techniques [22] for a multilevel inverter, space vector
modulation (SVM) is an attractive control strategy due to the following merits. It directly uses
the control variable given by the control system and identifies each switching vector as a point.in
complex (a, (3) space. It is suitable for digital signal processor (DSP) implementation. It can
optimize switching sequences. The lower order harmonics are eliminated by driving a three-
phase induction motor from a three level inverter. Since three level inverter can generate five
level line-to-line staircase waveform, the generated voltage and current waveforms are nearly
sinusoidal even at fundamental switching frequency. The magnitude of the lower order
harmonics is very low so there is no need of a large filter circuit, which makes the inverter
cheaper, lighter, more compact, output line voltage THD is very much less and can be controlled
compared to higher levels. For a given dc bus voltage the maximum inverter line-to-line voltage
generated by the SVM scheme is 15.5% higher than that by the SPWM scheme
In this a new and computationally very efficient SVM algorithm for general two and
three level converters is developed using simulink block sets of MATLAB and this algorithm is
used to generate gating pulses for two and three level inverters and also the performance of the
three phase induction motor is studied based on the developed algorithm The harmonic analysis
in terms of THD is also studied for inverter line voltages of three level inverter fed three phase
induction motor. Simulation studies are carried out using 3-Phase, 50HP, 400V, 50Hz, and
1500RPM induction machine.
1.2 Technical Requirements and Challenges to MV Drives
The technical requirements and challenges for the MV drive differ in many aspects from
those for the low-voltage (< 600 V) ac drives. Some of them that must be addressed in the MV
drive may not even be an issue for the low-voltage drives. These requirements and challenges
can be generally divided into four groups: the requirements related to the power quality of line-
side converters, the challenges associated with the design of motor-side converters, the
constraints of the switching devices, and the drive system requirements.

3
1.2.1 Line-Side Requirements
(a) Line Current Distortion. The rectifier normally draws distorted line current from the utility
supply, and it also causes notches in voltage waveforms. The distorted current and voltage
waveforms can cause numerous problems such as nuisance tripping of computer-controlled
industrial processes, overheating of transformers, equipment failure, computer data loss, and
malfunction of communications equipment. Nuisance tripping of industrial assembly lines often
leads•to expensive downtime and ruined product.
(b) Input Power Factor. High input power factor is a general requirement for all electric
equipment. Most of the electric utility companies require their customers to have a power factor
of 0.9 or above to avoid penalties. This requirement is especially important for the MV drive due
to its high power rating.
(c) LC Resonance Suppression. For the MV drives using line-side capacitors for current THD
reduction or power factor compensation, the capacitors form LC resonant circuits with the line
inductance of the system. The LC resonant modes may be excited by the harmonic voltages in
the utility supply or harmonic currents produced by the rectifier. Since the utility supply at the
medium voltage level normally has very low line resistance, the lightly damped LC resonances
may cause severe oscillations or over voltages that may destroy the switching devices and other
components in the rectifier circuits. The LC resonance issue should be addressed when the drive
system is designed.
1.2.2 Motor-Side Challenges
(a) dv/dt and Wave Reflections. Fast switching speed of the semiconductor devices results in
high dv/dt at the rising and falling edges of the inverter output voltage waveform. Depending on
the magnitude of the inverter dc bus voltage and speed of the switching device, the dv/dt can
well exceed 10,000 V/ s. The high dv/dt in the inverter output voltage can cause premature
failure of the motor winding insulation due to partial discharges. It induces rotor shaft voltages
through stray capacitances between the stator and rotor. The shaft voltage produces a current
flowing into the shaft bearing, leading to early bearing failure. The high dv/dt also causes
electromagnetic emission in the cables connecting the motor to the inverter, affecting the
operation of nearby sensitive electronic equipment.

4
(b) Common-Mode Voltage Stress. The switching action of the rectifier and inverter normally
generates common-mode voltages. The common-mode voltages are essentially zero-sequence
voltages superimposed with switching noise. If not mitigated, they will appear on the neutral of
the stator winding with respect to ground, which should be zero when the motor is powered by a
three-phase balanced utility supply. Furthermore, the motor line-to-ground voltage, which should
be equal to the motor line-to-neutral (phase) voltage, can be substantially increased
due to the common-mode voltages, leading to the premature failure of the motor winding
insulation system. As a consequence, the motor life expectancy is shortened.
(c) Motor Derating. High-power inverters may generate a large amount of current and voltage
harmonics. These harmonics cause additional power losses in the motor winding and magnetic
core. As a consequence, the motor is derated and cannot. operate at its full capacity.
(d) LC Resonances. For the MV drives with a motor-side filter capacitor, the capacitor forms an
LC resonant circuit with the motor inductances. The resonant mode of the LC circuit may be
excited by the harmonic voltages or currents produced by the inverter. Although the motor
winding resistances may provide some damping, this problem should be addressed at the design
stage of the drive.
(e) Torsional Vibration. Torsional vibrations may occur in the MV drive due to the large
inertias of the motor and its mechanical load. The drive system may vary from a simple two-
inertia system consisting of only the motor and the load inertias to very complex systems such as
a steel rolling-mill drive with more than 20 inertias. The torsional vibrations may be excited
when the natural frequency of the mechanical system is coincident with the frequency of torque
pulsations caused by distorted motor currents. Excessive torsional vibrations can result in broken
shafts and couplings, and also cause damages to the other mechanical components in the system.
1.2.3 Switching Device Constraints
(a) Device Switching Frequency. The device switching loss accounts for a significant amount
of the total power loss in the MV drive. The switching loss minimization can lead to a reduction
in the operating cost when the drive is commissioned. The physical size and manufacturing cost
of the drive can also be reduced due to the reduced cooling requirements for the switching
devices. The other reason for limiting the switching frequency is related to the device thermal
resistance that may prevent efficient heat transfer from the device to its heat sink. In practice, the
device switching frequency is normally around 200 Hz for GTOs and500 Hz for IGBTs and

5
GCTs. The reduction of switching frequency generally causes an increase in harmonic distortion
of the line- and motor-side waveforms of the drive. Efforts should be made to minimize the
waveform distortion with limited switching frequencies.
(b) Series Connection. Switching devices in the MV drive are often connected in series for
medium-voltage operation. Since the series connected devices and their gate drivers may do not
have identical static and dynamic characteristics, they may not equally share the total voltage in
the blocking mode or during switching transients. A reliable voltage equalization scheme should
be implemented to protect the switching devices and enhance the system reliability.
1.2.4 Drive System Requirements
The general requirements for the MV drive system include high efficiency, low
manufacturing cost, small physical size, high reliability, effective fault protection, easy
installation, self-commissioning, and minimum downtime for repairs. Some of the application-
specific requirements include high dynamic performance, regenerative braking capability, and
four-quadrant operation.
1.3VSI Fed Induction Motor Drive
The Voltage source inverter (VSI) creates a relatively well defined switched voltage
wave form at terminal of the motor. This requires stiff DC bus Voltage, It is sub divided into two
types called the six step inverter and pulse width modulated inverter. The six step inverter has six
steps in the output liner to neutral voltage and the order of harmonics in the wave form (6n+1).
The Fourier analysis of this waveform reveals a" squre wave" type of geometric progression of
the harmonics. That is the line to line and line to neutral waveform contains 1/5`h of 5`h
harmonic,l/7t' harmonic of 7th harmonic, so on. That the 20% 5'h harmonic, 14.28% 7`I'
harmonics son on which are quite high. The PWM inverter combines both the voltage and
frequency control within the inverter itself. Various PWM techniques have been implemented
with sinusoidal PWM, it is found that the one of techniques o synthesize the motor currents are
near to sinusoidal as possible.
The lower order voltage harmonics can greatly attenuated in this technique, PWM
Inverter fed motor tends to rotate much more smoothly at low speed. Torque pulsation and
harmonics can be greatly reduces as compared to 6-inverter fed Drive. But the problem with this
type of drive, is high dv/dt caused duet o high switching frequency between highest DC Voltage
level to zero. This produces common mode voltages across the motor winding that drives current

0
through the motor bearings resulting in its failure, high rate of change voltage causes corona
losses in winding layers. The Switching losses are high , further more voltage and switching
frequency ratings of devices are required to be high ay high power and high voltage applications

Fig: 1.2 Voltage Source Inverter fed Induction Motor

V
+Vc

-Vc

Fig : 1.3 Line to Line Voltage of VSI

Undesirable effects of VSI fed IM Drives are:
➢ Generates output voltage with high distortion and dv/dt.
➢ More torque pulsation
> It produces Lower order harmonics, these are undesirable it causes heating.
> Failure of motor winding and bearings.
➢ Corona losses
➢ High Switching Losses
These undesirable affects are over come with Multi level inverter.

7
1.4 Multi Level Inverter fed IM Drive
Multilevel power conversion was first introduced 20 years ago [1]. The general concept
involves utilizing a higher number of active semiconductor switches to perform the power
conversion in small voltage steps. There are several advantages to this approach when compared
with traditional (VSI) power conversion. The smaller voltage steps lead to the production of
higher power quality waveforms and also reduce the dv/dt stresses on the load and reduce the
electromagnetic compatibility (EMC) concerns. Another important feature of multilevel
converters is that the semiconductors are wired in a series-type connection, which allows
operation at higher voltages. However, the series connection is typically made with clamping
diodes, which eliminates overvoltage concerns. Furthermore, since the switches are not truly
series connected, their switching can be staggered, which reduces the switching frequency and
thus the switching losses. Three different topologies have been proposed for multilevel inverters:
diode-clamped (neutral-clamped) [1]; capacitor-clamped (flying capacitors) [23], [24], [25]; and
cascaded multicell with separate do sources [23], [26]—[27]. In addition, several modulation and
control strategies have been developed or adopted for multilevel inverters including the
following: multilevel sinusoidal pulse width modulation (PWM), multilevel selective harmonic
elimination, and space-vector modulation (SVM).

Fig: 1.4 NPC Inverter fed Induction Motor

8
 4.
Voltal
+2V,
+V

-V
-2VI

Fig: 1.5 Line to Line Voltage of NPC Inverter

The most attractive features of multilevel inverters over two level VSI are as fol lows.

> They can generate output voltages with extremely low distortion and lower dv/dt.
> They draw input current with very low distortion.
> They generate smaller common-mode (CM) voltage, thus reducing the stress in the motor
bearings. In addition, using sophisticated modulation methods, CM voltages can be
eliminated [8].
➢ They can operate with a lower switching frequency.

1.5 MV Industrial Drives Based On Three Level NPC Inverter

A number of MV drive products are available on the market today. These drives come
with different designs using various power converter topologies and control schemes. Each
design offers some unique features but also has some limitations. The diversified offering
promotes the advancement in the drive technology and the market competition as well. A few
examples of the MV industrial drives are as follows. Figure 1.6 illustrates the picture of an MV
drive rated at 4.16 kV and 1.2 MW. The drive is composed of a 12-pulse diode rectifier as a front
end and a three-level NPC inverter using OCT devices. The drive's digital controller is installed
in the left cabinet. The cabinet in the center houses the diode rectifier and air-cooling system of
the drive. The inverter and its output filters are mounted in the right cabinet. The phase-shifting
transformer for the rectifier is normally installed outside the drive cabinets.
Figure 1.7 shows an MV drive using an IGBT-based three-level NPC inverter. The IGBT
heat sink assemblies in the central cabinet are constructed in a modular fashion for easy
assembly and replacement. The front. end converter is a standard 12-pulse diode rectifier for line

7
current harmonic reduction. The phase-shifting transformer for the rectifier is not included in the
drive cabinet.

Figure 1.6 GCT-based three-level NPC inverter-fed MV drive. Courtesy of ABB

(ACS1000).

Figure 1.7 IGBT-based three-level NPC inverter-fed MV drive. Courtesy of Siemens

(SIMOVERT MV).
10
1.6. Three-Phase Induction Motor
1.6.1. Introduction
The ac induction motors are the most common motors particularly squirrel cage motors
used in industrial motion control systems, as well as in main powered appliances. Simple and
rugged design, low cost and low maintenance are some of the main advantages of 3-phase ac
induction motors. Various types of induction motors are available in the market.
However, mechanical energy is more than often required at variable speeds, where the
speed control system is not a trivial matter. The only effective way of producing a variable
induction motor speed drive is to supply the induction motor with three phase voltages of
variable frequency and variable amplitude. A variable frequency is required because the rotor
speed depends on the speed of the rotating magnetic field provided by the stator. A variable
voltage is required because the motor impedance reduces at low frequencies and consequently
the current has to be limited by means of reducing the supply voltages.

Speed of an Induction motor:The magnetic field created in the stator rotates at a synchronous
speed (N a ).

NS =120*f

Where:N5 = the synchronous speed of the stator magnetic field in rpm

P = the number of poles on the stator
f = the supply frequency in Hertz
The magnetic field produced in the rotor because of the induced voltage is alternating in
nature. To reduce the relative speed, with respect to the stator, the rotor starts running in the
same direction as that of the stator flux and tries to catch up with the rotating flux. However, in

11
practice, the rotor never succeeds in "catching up" to the stator field. The rotor runs slower than
the speed of the stator field. This speed is called the Base speed(Nb ). The difference between
Ns and Nb is called the slip. The slip varies with the load. An increase in load will cause the rotor
to slow down or increase slip. A decrease in load will cause the rotor to speed up or decrease
slip.The slip is expressed as a percentage and can be determined with following formula:

%slip = N SN Nb * 100 (1.2)

Where NS = the synchronous speed in rpm

Nb = the base speed in rpm
1.6.2. Speed Control of Induction Motor
Speed control means speed variation under open loop (feed forward) or close loop
conditions. For cage-rotor induction motors, all speed control methods have to act on the stator
windings as only they are available.
From Eq. 1.2, Speed of induction motor is given by,

N = Ns(1— s) (1.3)

This can be rewritten as N = p_ (1 — s); [from Eq. 1.11 (1.4)

Equation (1.4) suggests that the speed may be modified through:

• Slip `s' variation: through voltage reduction
• Pole `p' variation: through pole changing windings
• Frequency `f control: through frequency converters
Here voltage reduction method and frequency controls are only discussed for the dissertation
work.
Voltage reduction method:
When reducing the stator phase (line) voltage through an autotransformer or an AC
voltage controller as inferred to torque equation of induction motor, the critical slip Sk remains
constant but breakdown (peak) torque varies with voltage VS squared.
Te = f (s).V52 (1.5)
The speed may be varied downward until the critical slip speed Nk is reached.

Nk = f (1— sk) 1.6)

Pi

12
Variable frequency control:
When changing frequency f, the ideal no-load speed N =120* (17p)changes and so does
the motor speed for given slip. As seen from the speed-torque characteristics, the induction
motor draws the rated current and delivers the rated torque at the base speed. When the load is
increased (over-rated load), while running at base speed, the speed drops and the slip increases.
Generally, the motor can take up to 2.5 times the rated torque with around 20% drop in the
speed. Any further increase of load on the shaft can stall the motor. The torque developed by the
motor is directly proportional to the magnetic field produced by the stator. So, the voltage
applied to the stator is directly proportional to the product of stator flux and angular velocity.
This makes the flux produced by the stator proportional to the ratio of applied voltage and
frequency of supply. By varying the frequency, the speed of the motor can be varied. Therefore,
by varying the voltage and frequency by the same ratio, flux and hence, the torque can be kept
constant throughout the speed range.
Open-Loop v/f Control:
This is very simple method of speed control of Induction Machine, whereas at low
speeds, voltage drop across stator impedance is significant compared to airgap voltage. So it has
poor torque capability at low speeds. So some voltage has to boost up at low frequencies. i.e.
increasing the ratio of v/f for lower speeds. At low speeds to maintain Elf ratio constant we need
to boost voltage to maintain 1,,,.(0r flux) constant.

Fig 1.9 Open-Loop V/f Control & variation of voltage with frequency

14
 V+
i
V "-

V +
c♦y
Li vv, F22V n 0# v+
LiVo bba j2Visin(e,- ) Vb investor
w~ ~+ va 4 t;sin (8, + 2) vo
41
1

Motor

Fig 1.10 Voltage boost at lower speeds

While examine the variation of speed with a fan or pump type load torque TL=KWW r2, as
the frequency is increased the speed increases almost proportionally and along the load torque
curve from points 1->2->3 ... etc. moving smoothly through the different operating modes of the
induction motor.

Fig 1.11 Torque-Speed variation showing effect of frequency variation, load torque and supply
voltage

When the effects of dynamic variations in load torque and line voltage observed Suppose
the load torque are changed from TL to TL' for the same frequency command, the speed will drop
slightly from c to w1-'. This type of speed variation can easily be tolerated by a fan or pump.

15
Now suppose the operating point is `a' and the line voltage drops so that the operating point
moves to W. Again the speed is tolerable for some applications.

Closed-Loop V/f Control:

DC sup ply voltage

slip compensator Pole pair Pxv.

p12 KVt 2
ø, PT roatrr ilex
Pt'IV3 3—ph
w~ Ox,I PWMP11
1 ~ 4 inverter
J

V i f profile

speed J
sensor !i

Fig 1.12. Closed-Loop speed control of induction machine using V/f principle

The problem associated with open-loop control is, it has poor speed regulation. At higher
load torques the speed will be decreased. So, machine has to operate in Closed-Loop to
compensate the change in speed (Slip Compensation). At no-load torque, the slip is very small
and the speed is nearly the synchronous speed. Thus, the simple open-loop Vs/f system cannot
precisely control the speed with presence of load torque. The slip compensation can be simply
added in the system with the speed measurement (Fig 1.12).
In this process the speed loop error generates a slip command cost« via a proportional-
integral controller and limiter. This slip command is added to the feedback speed signal (or to get
the frequency command tne* which, in turn, generates the voltage command through a volts/Hz
function generator. Since slip is proportional to torque at constant flux, this approach may be
considered as open loop torque control within a speed control loop. To do this analysis an
inverter which is capable of giving voltage at required frequency and magnitude is required.
PWM pulses for Inverter can be generated in different ways, of which SPWM (Sine triangle
Pulse Width Modulation) & SVM (Space Vector Modulation) are two techniques.

16
1.7 Literature Review
The results of a patent search show that multilevel inverter circuits have been around for
more than 25 years. An early traceable patent appeared in 1975 [28], in which the cascade
inverter was first defined with a format that connects separately dc-sourced full-bridge cells in
series to synthesize a staircase ac output voltage. Through manipulation of the cascade inverter,
with diodes blocking the sources, the diode-clamped multilevel inverter was then derived [29].
The diode-clamped inverter was also called the neutral-point clamped (NPC) inverter when it
was first used in a three-level inverter in which the mid voltage level was defined as the neutral
point. Because the NPC inverter effectively doubles the device voltage level without requiring
precise voltage matching, the circuit topology prevailed in the 1980s. The application of the NPC
inverter and its extension to multilevel converter was found.
Although the cascade inverter was invented earlier, its applications did not prevail until
the mid-1990s. Two major patents [30], [31] were filed to indicate the superiority of cascade
inverters for motor drive and utility applications. Due to the great demand of medium-voltage
high-power inverters, the cascade inverter has drawn tremendous interest ever since. Several
patents were found for the use of cascade inverters in regenerative-type motor drive applications
[32]—[34]. The last entry for U.S. multilevel inverter patents, which were defined as the
capacitor-clamped multilevel inverters, came in the 1990s [35]. Today, multilevel inverters are
extensively used in high-power applications with medium voltage levels. The field applications
include use in laminators, mills, conveyors, pumps, fans, blowers, compressors, and so on.
Harmonic distortion was one of the most important factors in the evolution of the
multilevel inverters. Akira Nabae et. Al. [1] in their publication titled, "A New Neutral-Point-
Clamped PWM Inverter", has made a clear distinction between the conventional and the
multilevel inverters vis-a-vis the harmonic spectra. The multilevel technique was introduced here
in combination with the already existing PWM technique.
Jih-Sheng Lai and Fang Zheng Peng in their publication [22] titles, "Multilevel
Converters — A New Breed of Power Converters", bring out clearly the working of each of the
three basic types of multilevel inverters. The potential applications like reactive power
compensation, back-to-back intertie and adjustable speed drives has been presented.

17
 Jose Rodriguez, Jih-Shing Lai and Fang Zheng in their publication [23] titles "Multilevel
Inverters: A survey of Topologies, Controls and Applications" presents the most important
topologies like diode-clamped inverter (neutral-point clamped), capacitor clamped (Flying
Capacitor) and cascaded multicell with separate dc sources. Emerging topologies like diode
asymmetric hybrid cells and soft switched multilevel inverters are also discussed. This paper also
presents the most relevant control and modulation methods developed for this family of
converters: multilevel sinusoidal pulse width modulation, multilevel selective harmonic
elimination and space vector modulation.
Texas instruments application note no. SPRA248a [42] titles "AC Induction Motor
Control Using Constant V/HZ Principle and Space Vector PWM Technique with TMS320C240"
presents digital implementation of space vector modulation using d-q model and principles of
constant V/HZ control for AC induction motor. Two different implementations are presented.
Implementation issues such as command voltage generation, switching pattern determination,
speed measurement and scaling are discussed.
Hyo L. Liu, Nam S. Choi and Gyu H. Cho in their publication [41] titled "DSP based
Space Vector PWM for Three Level Inverter with DC-Link voltage balancing", presented a new
PWM method for three-level inverter considering DC-link capacitor balancing problem using
Motorola DSP 56000. In this paper each voltage vector on space vector plane is classified to
charging discharging action of DC capacitors.
Masato Koyama, Toshiyuki Fuzzi, Ryohei Uchida, Takao Kawabata in their publication
[36] titled, "Space Voltage Vector-Based New PWM Method for Large Capacity Three-Level
GTO Inverter". presented new PWN method for three- level. inverter based on the space voltage
vectors. This PWM method can minimize the harmonic components of the output voltage under
the minimum pulse width limitation of GTS's and also suppress the fluctuation of the neutral-
point voltage.
Yo-Lan Lee, Bum-Seok, Dong-Seok Hyun in their publication [40] titles "A Novel PWM
Scheme for a Three-Level Voltage Inverter with GTO Thyristors" presents a new PWM method
for a three level GTO inverters based on the space voltage vectors and with this method the
harmonic components of the output voltage by avoiding minimum pulse with limitation problem
of GTO Thyristors and keeping the voltage balancing of the dc-link capacitors.

18
 Annette von Jouanne, Shaoan Dai, Haoran Zhang in their publication [37] titles "A
Multilevel Inverter Approach Providing DC —Link Balancing, Ride — Through Enhancement,
and Common-Mode Voltage Elimination" presents a simple control method for balancing the dc-
link voltage of three-level neutral-point-clamped inverters, while providing enhanced ride-
through and common mode voltage (CMV) elimination.
Sun-Kyoung Lim, Jun-Ha Lim and Kwanghee Nam in their publication [38] tilted " A
DC-Link Voltage Balancing Algorithm for 3-Level Converter Using the Zero Sequence Current"
have given a method of balancing DC link voltage by using the zero-sequence current flowing in
the link made between the neutral point the source transformer on the AC side and the midpoint
of DC- Link for the 3-level case.
Amit Kumar Gupta, Student Member, IEEE, and Ashwin M. Khambadkone, Senior
Member, IEEE [39] "A Space Vector PWM Scheme for Multilevel Inverters Based on Two-
Level Space Vector PWM" have given that Multilevel inverters are increasingly being used in
high-power medium voltage applications due to their superior performance compared to two-
level inverters. Among various modulation techniques for a multilevel inverter, the space vector
pulse width modulation (SVPWM) is widely used. However, the implementation of the SVPWM
for a multilevel inverter is complicated. The complexity is due to the difficulty in determining
the location of the reference vector, the calculation of on-times, and the determination and
selection of switching states.

1.8 Conclusion
This chapter provides an overview of high-power converters and medium-voltage (MV)
and an overview of two level and multilevel power conversion. The technical requirements and
challenges for the MV drive are also summarized. What is the need to go multi level inverter
topologies and advantages and disadvantages are compared with voltage source inverter fed
induction motor Drives. It is conclude that to get better performance of PWM inverter fed
induction motor drive we should opt to Multi Level Inverter Topologies.

F0]
1.9 Organization of This Thesis
Chapter: 2 In this Chapter the design, operation and classification of multilevel Inverters and
obtaining of multi level wave forms, which includes some of recently developed circuit
topologies the salient features of all these topologies have been presented and comparison also
been made, application , advantages , feature and disadvantages are discussed.

Chapter: 3 In this chapter presents various PWM techniques available for Multilevel Inverters
and their implementation. The Main Objective of this chapter is implementation of Sinusoidal
Pulse width Modulation, Third Harmonic Injection SPWM, Multi carrier PWM and Space
Vector Pulse Width Modulation (SVPWM) Techniques for both Two level and Three level
Neutral Point Clamped Inverter.
Chapter: 4 In this chapter the performance of two level PWM inverter and Three Level
Neutral Point Clamped Inverter fed Induction Motor Drive with Sinusoidal PWM, Third
Harmonic Injection and Space Vector Modulation are evaluated. The steady state and dynamic
performance of drive was discussed under different condition of speed, frequency and load. The
THD variation with frequency was also evaluated and the performance comparison of the
various inverters fed induction motor drives was also presented.
Chapter: 5 Conclusions and Future Scope

20
 CHAPTER 2
MULTILEVEL INVERTER TOPOLOGIES

This Chapter focuses on the design, operation and classification of multilevel Inverters
and obtaining of multi-level wave forms, which includes some of recently developed circuit
topologies the salient features of all these topologies have been presented and comparison also
been made, application , advantages, feature and disadvantages are discussed.
2.1 Multilevel Power Conversion Concept and Voltage Level Notation
This section introduces the general multilevel power converter as well as the advantages
of using an increasing number of voltage levels. A motor drive which will be used to exemplify
general multilevel concepts is shown in Figure 2. Although an inverter is used as the basis for
this discussion, the multilevel converter can be used in active rectifier and flexible AC
transmission systems (FACTS) applications, etc. [16,17]. From a system point of view, the
multilevel inverter has been inserted in place of a standard inverter.
Herein, n is used to represent the number of voltage levels and can be set to two in order
to represent standard inverter. An output L-C-R filter has been placed in-between the inverter
and motor load in order to meet harmonic requirements at the motor terminals. Herein, switching
states Sa, Sb, and S, will be defined for the a, b, and c phases respectively. Each switching state
has a range from 0 to (n —1) in order to represent the complete number of switching levels.
Assuming proper operation, the inverter output line-to-ground voltages (defined from the phase
nodes a, b, and c to the negative rail of the dc bus) follow the switching states as

Vbg Sb (2.1.1)
n-1
Vag =LS~

From Figure 2.1, it can be seen that the modulator determines the switching states;
thereby depicting the inverter output voltages. This system is somewhat idealized since, in
practice, the output of the modulator is the transistor signals. Furthermore, the line-to-ground
voltages may vary a bit from (21.1)-(2.1.3) since the voltage levels are typically made up from a
series capacitor bank.

21
 Motor
a ice, Load

f
Multi-. b ib ,
S - -
level
converter -~ ,

L' lei
.r

Transistor
signals
Multilevel ,' L.,
pulse-width !S} A~} (4
modulation
(PWM)

Fig: 2.1 Multi Level Inverter System

However, these issues will be more formally addressed in the following section relating
to the specific multi-level hardware. Figure 2.2 shows inverter line-to-ground voltages for
several values of n. According to the modulation process, the output is an ideal sine-wave with
switching harmonics. It is fairly obvious that increasing the inverter levels results in an inverter
output voltage that more closely tracks the ideal sinusoidal output. As a fmal note, various
voltage definitions will be described for clarity. The line-to-neutral voltages may be determined
directly from the line-to-ground voltages by
Van 2 —1 —1 Vag
Vb„ _ —1 2 —1 Vbg (2.1.2)
Van —1 —1 2 Vcg

Inverter line-to-line voltages are related to the line-to-ground voltages by

VQb 1 —1 0 Vag
Vb, = 0 1 —1 Vbg (2.1.3)
V'Q —1 0 1 V'g

Figure 2.3 shows the switching state, line-to-ground voltage, line-to-neutral voltage, and
line-to line voltage for the case where n =9. Therein, the line-tog round voltage contains a third
harmonic component which is added in order to maximize the inverter output voltage [27].

22
Therein, it can be seen that the line-to neutral and line-to-line voltages do not contain the third
harmonic. Also, it is interesting to note that these voltages contain more levels than the original
line-to ground voltages. It is easily understood that there are 2n —1 line-to-line voltage levels
consisting of n positive levels, n negative levels, and zero. In Figure 2.2,these seventeen voltage
levels can be clearly seen in Vab. As it turns out, there are(4n —3) line-to-neutral voltage levels,
which work out to thirty-three for nine level inverter. However, the switching between the levels
is not perfectly even since all three phases are involved.

0
xY

7J-~?
t3

f\
0
/*\4/'
irr F~3

Fig. 2.2Output Voltage for various Level

vM (kV)
-6
0

i
"-U
5 ms.
V. (kV) 0
-4

Fig.2.3 Nine Level Inverter Voltage Wave Form

One good method of gaining insight into the operation of multilevel inverters is to view
the voltages in the q-d stationary reference frame. The resulting vector plot contains information

23
from all three phases and displays redundant switching states. The plot is particularly useful for
comprehending the higher number of switching states as compared to the two-level inverter. In
addition, some mathematical relationships and derivations can be readily obtained from the
vector plot. The vector diagram has also been used to formulate multilevel modulation. However,
it will be shown later that this is more readily accomplished in the time domain.
The inverter voltages can be expressed in the arbitrary q-d reference frame by [27]

Vdn COS B COS(e — 2 ) cos(O + 2 ) Van

3 3 II I

V9n = sin B sin(8 — 23 ) sin(O +1

3 ) Vbn (2.1.4)

11 1
VOn 2 2 2 Y cn

Considering (2.1.1), (2.1.2), and that the angle is 0=0 for the stationary reference frame,
the q-d stationary voltages can be expressed in terms of the switching states by

VS = Vd, (2sa - sb - s c)
qn 3(n —1)

_ ( ~r ~r
V S dn J (nc_ 1) l'Jc b)

24
2.2 Multilevel Power Converter Topologies
Below figure shows one way to classify multilevel converters, similar to the classification
by Lai and Peng. [221

r,• ACC No.................

te

Date.....................

&j. ROO

Fig.2.4 Classification of Multi-level converters

2.2.1 Neutral-Point-Clamped (NPC) Multilevel Inverter

The neutral point converter proposed by Nabae, Takahashi, and Akagi in [1] 1981 was
essentially a three-level diode-clamped inverter. These Plentiful multilevel converter topologies
have been proposed during the last two decades In the 1990s, several researchers published
articles that have reported experimental results for four-, five-, and six-level diode-clamped
converters for uses such as static var compensation, variable speed motor drives, and high-
voltage system interconnections.
The diode-clamp method can be applied to higher level converters. As the number of
levels increases, the synthesized output waveform adds more steps, producing a staircase wave
which approaches the sinusoidal wave with minimum harmonic distortion. Ultimately, a zero
harmonic distortion of the output wave can be obtained by an infinite number of levels. More
levels also mean higher voltages can be spanned by series devices without device voltage sharing

25
problems. Unfortunately, the number of the achievable voltage levels is quite limited not only
due to voltage unbalance problems but also due to voltage clamping requirement, circuit layout,
and packaging constraints.
An m-level NPC inverter consists of (m-1) capacitors on the DC bus, 2(m-1) switching
devices per phase and 2(m-2) clamping diodes per phase. Fig. 2.5 shows the simplified circuit
diagram of Three level NPC Inverter. The DC bus voltage is split into 3 levels by using 2 DC
capacitors, Cdl and Cd2, Providing a neutral point. Each capacitor has Vd/2 (Here E) volts and
each voltage stress will be limited to one capacitor level through clamping diodes. The diodes
connected to the neutral point, Dzi and DZ2, are the clamping diodes. When switches S2 and S3
are turned on, the inverter output terminal A is connected to the neutral point through one of the
clamping diodes. The voltage across each of the dc capacitors is E, which is normally equal to
half of the total dc voltage Vd. With a finite value for Cdl and Cu, the capacitors can be charged
or discharged by neutral current iZ, causing neutral-point voltage deviation.
The number of levels can be extended to a higher level by additional switching devices
and with these additions, the inverter will be able to achieve higher AC voltage, producing more
voltage steps that will be approaching sinusoidal with minimum harmonics distortion. During
inverter operations, the switches near the centre tap are switched on for a longer period compared
to the switches further away from the centre tap as given in the switching states in Table 1. As
the switch is further away from the centre tap the switching time is shorter. Another difference
between the conventional 2-level and multilevel NPC is the clamping diode.
In case of 3-level NPC inverter, clamping diode, DZI and DZ2 clamped the DC bus
voltage into three voltage level, +E, 0 and -E. Diode, D,2 balances out the voltage sharing
between S4in and S4out, with S4in blocking the voltage across Cdl and S4out blocking the
voltage across C.
The operating status of the switches in the NPC inverter can be represented by switching
states shown in Table 2.1. Switching state `P' denotes that the upper two switches in leg A are on
and the inverter terminal voltage V,z, which is the voltage at terminal A with respect to the
neutral point Z, is +E, whereas `N' indicates that the lower two switches conduct, leading to
VAZ= —E. Switching state `0' signifies that the inner two switches S2 and S3 are on and VAZ is
clamped to zero through the clamping diodes.
 Vd

Leg a Leg b Leg c

Fig 2.5 Three level NPC Inverter

Switching Device Switching Status (Leg A) Inverter Terminal

State Voltage(Van)
SI S2 S3 S4

P ON ON OFF OFF +E

0 OFF ON OFF ON 0

N OFF OFF ON ON -E

Table 2.1 Definition of Switching State

Depending on the direction of load current iA, one of the two clamping diodes is turned
on. For instance, a positive load current (iA> 0) forces Dzi to turn on, and the terminal A is
connected to the neutral point Z through the conduction of DZ1 and S2.

27
 It can be observed from Table 2.1 that switches SI and S3 operate in a complementary
manner. With one switched on, the other must be off. Similarly, S2 and S4are a complementary
pair as well. Figure 2.6 shows an example of switching state and gate signal arrangements, where
vgl to vg4 are the gate signals for Si to S4, respectively. The gate signals can be generated by
carrier-based modulation, space vector modulation, or selective harmonic elimination schemes.
The waveform for V,z phase three voltage levels, +E, 0, and —E, based on which the inverter is
referred to as a three-level inverter.

I I I I I I I 1 I ii
v l
l# 11 I 1 I 1 III

I I 1 I I I I I 1 1 1
i
1 I 1 I I I i at I I 1
V 1 0 I 11 ( V .
g4
1 i! t ar ! it 1€
-+L
4 t It I i
l I I i I 1
a I I 1 6 I

0 ' I I I .1 1 12,r
... E w-►U I_— ICJ
Fig:2.6 Switching State, Gate Signal and Inverter Terminal Voltage VAz

Figure 2.7 shows how the line-to-line voltage waveform is obtained. The inverter
terminal voltages VAZ, VBZ, and VIZ are three-phase balanced with a phase shift of 120° between
each other. The line-to-line voltage Vp can be found from VB=V,z - VBZ, which contains five
voltage levels (+2E, +E, 0, —E, and —2E).

f:3
 I I

V All 3 1—Y

1 I !
V 48 —V AZ —VA

Fig: 2.7 Inverter terminal and Line to Line voltage Waveforms

The commutation of switching devices in the NPC inverter, consider a transition from
switching state [0] to [P] by turning S3 off and turning Si on. Figure 2.8 shows the gate signals
Vgl to Vg4 for switches Si to S4, respectively, a blanking time of S is required for the
complementary switch pair Si and S3.

V l
Col [P]
i 1
Vg2

L i ?
i t

vg3
# ?
Y I i
Vg4

Fig 2.8 Gate Signal Commutation During switching transition

Figures 2.9 and 2.10 show the circuit diagram of the inverter leg A during commutation,
where each of the active switches has a parallel resistor for static voltage sharing. According to
the direction of the phase A load current iA, the following two cases are investigated.
Case 1: Commutation With iA> 0. The commutation process is illustrated in Fig.2.9. It is
assumed that (a) the load current iA is constant during the commutation due to the inductive load,
(b) the do bus capacitors Cd, and Cd2 are sufficiently large such that the voltage across each

29
capacitor is kept at E, and c) all the switches are ideal. In switching state [0], switches S1 and S4
are switched off while S2 and S3conduct. The clamping diode DZ1 is turned on by the positive
load current (iA> 0).The voltages across the on-state switches S2 and S3 are given by V52 = Vs3
0, while the voltage on each of the off-state switches S1 and S4 is equal to E.
During the S interval, S3 is being turned off. The paths of iA remain unchanged. When S3
is completely switched off, the voltages across S3 and S4 become V53 = Vsa= E/2 due to the static
voltage sharing resistors R3 and R4.In switching state [P], the top switch St is gated on (Vs, = 0).
The clamping diodeDzl is reverse biased and thus turned off. The load current iA is commutated
fromDZ1 to S1. Since both S3 and S4 have already been in the off-state, the voltage across these
two switches is equally divided by R3 and R4, leading to V53 = V54 = E.

S)A R, E sal ~~, + 0v

E
-rC~ai 152 ..
Its 01f is
-r 1~,~ ,S
R2 OF L± 0v

+j fJZ2 S3 FT + -F1 UZ21 53

R3$.E12 E
-T
E
L
" Cd2
LU_i-

0- 0_I
Switching State [0] 6 interval Switching State [P]
Fig: 2.9 Commutation with iA>0
Case 2: Commutation With iA< 0. The commutation process with iA< 0 is illustrated in Fig.2.10.
In switching state [0], S2 and S3 conduct, and the clamping diode Dz2 is turned on by the
negative load current A. The voltage across the off state switches Si and S4 is Vsi = Vs4 = E.
During the S interval, S3 is being turned off. Since the inductive load current iA cannot change its
direction instantly, it forces diodes D1 and D2 to turn on, resulting in Vs1 = V52 = 0. The load
current is commutated from S3 to the diodes. During the Saturn-off transient, the voltage across
S4 will not be higher than E due to the clamping diode DZ2, and it will also not be lower than E
since the equivalent resistance ofS3 during turn-off is always lower than the off-state resistance

30
of S4. Therefore, VS3increases from zero to E while VS4 is kept at E. In switching state [P], the
turn-on of S1 does not affect the operation of the circuit. Although S1 and S2 are switched on,
they do not carry the load current due to the conduction of D1 and D2 .

E 01' S
D~ +01

:_0V
D71 S2

xa
rA Z

+ DZ2 ,S3 1 ; +
01' PW E-
1- I Z R3 E
:E. E
S ~ t R-0 -E

Switching State [0] 8 interval Switching State [P]

Fig.2. 10 Commutation with iA< 0
It can be concluded that all the switching devices in the NPC inverter withstand only half
of the dc bus voltage during the commutation from switching state [0] to[P]. Similarly, the same
conclusion can be drawn for the commutation from [P] to[O], [N] to [O], or vice versa.
Therefore, the switches in the NPC inverter do no thave dynamic voltage sharing problem.
It should be pointed out that the switching between [P] and [N] is prohibited for two reasons: (a)
It involves all four switches in an inverter leg, two being turned on and the other two being
commutated off, during which the dynamic voltage on each switch may not be kept same; and
(b) the switching loss is doubled. It is worth noting that the static voltage sharing resistors may
be omitted if the leakage current of the top and bottom switches (Si and S4) in each inverter leg
is selected to be lower than that of the inner two switches (S2 and S3). In doing so, the voltages
across the top and bottom switches, which tend to be higher than those of the inner switches, are
clamped to E by the clamping diodes in steady state. As a result, the voltage on each of the inner
two switches is also equal to E, and the static voltage equalization is achieved.
The three-level NPC inverter offers the following features:
> No dynamic voltage sharing problem. Each of the switches in the NPC inverter
withstands only half of the total do voltage during commutation.

31
 ➢ Static voltage equalization without using additional components. The static voltage
equalization can be achieved when the leakage current of the top and bottom switches in
an inverter leg is selected to be lower than that of the inner switches.
Low THD and dv/dt. The waveform of the line-to-line voltages is composed of five
voltage levels, which leads to lower THD and dv/dt in comparison to the two-level
inverter operating at the same voltage rating and device switching frequency.
Fig. 2.11 shows line voltage waveforms of the example 5-level converter. The line voltage
consists of a positive phase-leg a voltage and a negative phase-leg b voltage. Each phase voltage
tracks one-half of the sinusoidal wave. The resulting line voltage is a 9-level staircase wave. This
implies that an m-level converter has an m-level output phase voltage and a (2m - 1) Level
output line voltage.
'p

Fig.2.11 he voltage waveforms of the 5-level diode clamped converter

Features
1. High-Voltage Rating Required for Blocking Diodes: Although each active switching
device is only required to block a voltage level of Vdc/(m - 1), the clamping diodes need
to have different voltage ratings for reverse voltage blocking. Assuming that each
blocking diode voltage rating is the same as the active device voltage rating, the number
of diodes required for each phase will be (m - 1) x (m - 2). This number represents a
quadratic increase in m. When m is sufficiently high, the number of diodes required will
make the system impractical to implement.
2. Capacitor Voltage Unbalance: In most applications, a power converter needs to transfer
real power from ac to dc (rectifier operation) or dc to ac (inverter operation). When
operating at unity power factor, the charging time for rectifier operation (or discharging
time for inverter operation) for each capacitor is different, as shown in Fig. 2.12(a). Such

32
 a capacitor charging profile repeats every half cycle, and the result is unbalanced
capacitor voltages between different levels. The voltage unbalance problem in a
multilevel converter can be solved by several approaches, such as replacing capacitors by
a controlled constant dc voltage source such as pulse-width modulation (PWM) voltage
regulators or batteries.

~r {.,Y ~ YJ dtydsalY~a}

(a) (b)
Fig: 2.12 Waveforms showing capacitor charging profile. (a)Voltage and current in phase.
(b)Voltage and current are 900 out of phase.

The use of a controlled do voltage will result in system complexity and cost penalties.
With the high power nature of utility power systems, the converter switching frequency must be
kept to a minimum to avoid switching losses and electromagnetic interference (EMI) problems.
When operating at zero power factor, however, the capacitor voltages can be balanced by equal
charge and discharge in one-half cycle, as shown in Fig. 2.12(b). This indicates that the converter
can transfer pure reactive power without the voltage unbalance problem.

Table 2.2 lists the component count for the multi level diode clamped inverters
.Assuming that all the active switches and clamping diodes have the same voltage rating; the
rated inverter output voltage is proportional to the number of active switches This suggest that if
the number of switches is doubled, the maximum inverter output voltage increases two fold, and
so does its output power. However ,the number of clamping diodes increases dramatically with
the voltage level ,For example the three-level inverter requires only six clamping diodes while
the five level inverter needs 36 clamping diodes This is ,in fact one of the main reason why the
four- and five-level inverters are seldom found in industrial applications.

33
 Voltage Active Clamping Dc
level switches diodes capacitors

m 6(m-1) 3(m-1)(m-2) (m-1)

3 12 6 2

4 18 18 3

5 24 36 4

6 30 60 5

Table 2.2 Component count of diode clamped multi level inverters

Applications:
➢ One application of the multilevel diode-clamped inverter is an interface between a
high-voltage dc transmission line and an ac transmission line.
➢ Another application would be as a variable speed drive for high-power medium-
voltage (2.4-13.8 kV) motors.
➢ Static var compensation is an additional function which several authors have
proposed for the diode-clamped converter.
Advantages:
➢ Also for practical uses such as a high-voltage back-to-back inter-connection or an
adjustable speed drive.
➢ The capacitors can be pre-charged as a group.
➢ Efficiency is high for fundamental. All of the phases share a common dc bus, which
minimizes the capacitance requirements of the converter. For this reason, a back-to-
back topology is not only possible but frequency switching.
Disadvantages:
> Real power flow is difficult for a single inverter because the intermediate dc levels
will tend to overcharge or discharge without precise monitoring and control.

➢ The number of clamping diodes required is quadratically related to the number of

levels, which can be cumbersome for units with a high number of levels.

34
2.2.2 Flying-Capacitor Multilevel Converters
Figure 2.13shows one phase of a three-level flying-capacitor multilevel converter. The
general concept behind this converter is that the added capacitor is charged to one half of the
DC-link voltage and maybe inserted in series with the DC-link voltage to form an additional
voltage level. As can be seen, switching states involve gating on the two lower and upper
transistors as was done with the diode-clamped structure. The capacitor voltage may be either
added to the converter ground or subtracted from the DC link voltage.

Vdc a

Fig 2.13 One Phase Leg of Three Level Flying Capacitor Inverter
In essence, there is switching redundancy within the phase leg. Since the direction of the
current through the capacitor changes depending on which redundant state is selected, the
capacitor voltage may be maintained at one half the DC-link voltage through the redundant state
selection with in the phase.
Application:
One application proposed in the literature for the multilevel flying capacitor is static var
generation.
Advantages:
Phase redundancies are available for balancing the voltage levels of the capacitors.
➢ Real and reactive power flow can be controlled.

35
 The large number of capacitors enables the inverter to ride through short duration
outages and deep voltage sags.
Disadvantages:
Control is complicated to track the voltage levels for all of the capacitors. Also,
precharging all of the capacitors to the same voltage level and startup are complex.
Switching utilization and efficiency are poor for real power transmission.
The large numbers of capacitors are both more expensive and bulky than clamping diodes
in multilevel diode clamped converters. Packaging is also more difficult in inverters with
a high number of levels.

2.2.3 Cascaded H-Bridge Multilevel Converters

Cascaded H-bridge converters consist of a number of H-bridge power conversion cells,
each supplied by an isolated source on the DC side and series-connected on the AC. side [31-33].
Figure 2.14shows the a-phase of a cascaded H-bridge converter, where two H-bridge cells are
utilized. It should be pointed out that, unlike the diode-clamped and flying-capacitor topologies,
isolated sources are required for each cell in each phase. In some systems these sources may be
available through batteries or photovoltaic cells [32], but in most drive systems
transformer/rectifier sources are used. Figure 2.15illustrates the switching state detail for one H-
bridge cell.

Fig.2.14 Cascaded H-bridge topology with two cells.

As can be seen, three unique output voltages are possible. In accordance with the
convention used here, the lowest switching state will be labeled state 0. When these cells are

36
combined in series, an effective switching state can be related to the switching states of the
individual cells. By defining switching states in this way, the modulation scheme of the previous
section may be applied to this converter as well. The output voltage of the inverter may be
determined from the switching states of the individual cells by
n
Vag = ( Sai — 1 )Vdci
i=0
Where p is the number of series H-bridge cells.
If the DC voltage applied to each cell is set to the same value, then the effective number
of voltage levels may be related to the number of cells by
n = 3+2(p-1)

Figure.2.15 Switching states of the H-bridge cell.

Features
For real power conversions, (ac to dc and dc to ac), the cascaded-inverter needs separate
dc sources. The structure of separate dc sources is well suited for various renewable energy
sources such as fuel cell, photovoltaic, and biomass, etc. Connecting separated do sources
between two converters in a back-to-back fashion is not possible because a short circuit will be
introduced when two back-to-back converters are not switching synchronously.
Applications:
. The inverter could be controlled to either regulate the power factor of the current drawn
from the source or the bus voltage of the electrical system where the inverter was
connected.
➢ Peng and Joos have also shown that a cascade inverter can be directly connected in series
with the electrical system for static var compensation.

37
 Cascaded inverters are ideal for connecting renewable energy sources with an ac grid,
because of the need for separate dc sources, which is the case in applications such as
photovoltaic or fuel cells.
l' This use as the main traction drive in electric vehicles, where several batteries or ultra-
capacitors are well suited to serve as SDCSs.
The cascaded inverter could also serve as a rectifier/charger for the batteries of an electric
vehicle while the vehicle was connected to an ac supply. Additionally, the cascade
inverter can act as a rectifier in a vehicle that uses regenerative braking.
Advantages:
The number of possible output voltage levels is more than twice the number of dc sources
(m=2s+1).
The series of H-bridges makes for modularized layout and packaging. This will enable
the manufacturing process to be done more quickly and cheaply.
Disadvantages:
Separate dc sources are required for each of the H-bridges. This will limit its application
to products that already have multiple SDCSs readily available.

2.3 Applications of multilevel inverters

Multilevel inverters are fmding increased application in industrial environment with
greater demand for high voltage high power processing techniques with improved efficiency.
The essential advantage of multilevel inverters is the improvement in the output voltage signal
quality using devices of low voltage rating with lesser switching frequency, thereby increasing
the overall efficiency of the system. The schemes such as single and 3-phase NPC( neutral point
clamped), FC ( Flying Capacitor), and cascaded H-bridge( CHB) are well established in medium
voltage drives and power system applications such as active filter and reactive power
compensators.
Increasing the number of levels in a multilevel inverter provides better output voltage
profile, but at the cost of larger number of switches and greater complexity in control. Recently,
many alternative schemes have been reported in literature to achieve multilevel voltage profile,
particularly suitable for induction motor drive applications, by use of conventional 2-level
inverters and open-end winding structure for the motor.

38
 Many interesting multilevel topologies have also been reported with reduction in the
number of active DC link power sources by effective control of the DC link capacitor voltages,
along with elimination of common mode voltage variations, without increasing the complexity of
the power circuit. Some of the applications of the multilevel inverters are described below.

1.Multi Level Inverter For Large Automotive Drive: for high-power and/or high-
voltage electric motor drives, Multilevel inverter can generate near sinusoidal voltages with only
fundamental frequency switching, have almost no electromagnetic interference or common-mode
Voltage and are suitable for large volt ampere-rated motor drives and high voltages.

Large electrical vehicles will require advanced power electronic inverter to meet the high
power demands(> 1 MW) require of them. The traditional high frequency PWM inverter for
motor drives have several problems associated with their high switching which produces high
voltage change(dv/dt) rates. Multi-level inverter solves this problems because their devices
switch at the fundamental frequency. Two different multilevel converter topologies are ideal for
use as electric drives. The cascaded inverter with separate dc sources closely fits the needs of
electric vehicles because it can use the onboard batteries or fuel cells to synthesize a sinusoidal
voltage waveform to drive the main vehicle traction motor. Where generated ac voltage is
available, a back-to-back diode clamped converter can be used to output variable frequency ac
voltage for the main traction motor.

2.Renewable Energy Interface: Multilevel converters can be used to interface with

renewable energy or distributed energy resources because several batteries, fuel cells, solar cells,
wind turbines, and micro turbines can be connected through a multilevel converter to supply a
load or the ac grid without voltage balancing problems.

3.Multilevel Inverter Technology For High Power Supply: Multilevel inverter

technology has emerged recently as a very important alternative in area of high power medium
voltage control, power inverter modules fed with separate dc voltage sources of voltage ratio
15v/30v/120v are connected to form a cascade multilevel inverter

4. Multilevel Inverter for Power System Applications: Highlighting Asymmetric

Design Effects From a Supply Network Point of View. The poor quality of current and voltage
waveforms of a power system fed by a classical two level inverter overcome by multi-level

39
inverter techniques are widely used in the power engineering community (for HVDC link, active
filtering, static var compensators, medium voltage variable speed drives.

A summary of Applications of MV Drives

Industry Application Examples

Petrochemical Pipeline pumps, gas compressors, brine pumps, mixers/extruders,

electrical submersible pumps, induced draft fans, boiler feed water
pumps, water injection pumps.

Cement Kiln-induced draft fans, forced draft fans, bag house fans, preheat tower
fans, raw mill induced draft fans, kiln gas fans, cooler exhaust fans,
separator fans.

Mining and Metals Slurry pumps, ventilation fans, de-scaling pumps, tandem belt
conveyors, bag house fans, cyclone feed pumps, crushers, oiling mills,
hoists, coilers, winders.

Water/Wastewater Raw sewage pumps, bio-roughing tower pumps, treatment pumps,

freshwater pumps, storm water pumps.

Transportation Propulsion for naval vessels, shuttle tankers, icebreakers, cruisers.

Traction drives for locomotives, light-track trains.

Electric Power Feed water pumps, induced draft fans, forced draft fans, effluent pumps,
compressors.

Forest Products Induced draft fans, boiler-feed water pumps, pulpers, refiners, kiln
&Miscellaneous drives, line shafts. Wind tunnels, agitators, test stands, rubber mixers.
2.4 Conclusion
The elementary concept of a multilevel converter to achieve higher power is to use a series of
power semiconductor switches with several lower voltage dc sources to perform the power
conversion by synthesizing a staircase voltage waveform has been discussed. The commutation
of the power switches aggregate these multiple dc sources in order to achieve high voltage at the
output. There are several advantages to this approach when compared with traditional (two-level)
power conversion. The smaller voltage steps lead to the production of higher power quality
waveforms and also reduce the dvldt stresses on the load and reduce the electromagnetic
compatibility (EMC) concerns. The advantages, features and applications have been discussed.

40
 CHAPTER 3
MODULATION AND CONTROL STRATEGIES

This chapter focuses on various PWM techniques available for Multilevel Inverters and
their implementation. The Main Objective of this chapter is implementation of Sinusoidal Pulse
width Modulation, Third Harmonic Injection SPWM, Multi carrier PWM and Space Vector
Pulse Width Modulation (SVPWM) Techniques for both Two level and Three level Neutral
Point Clamped Inverter.

3.1 Introduction
Since Bhagavat and Stefanovic introduced the concept of the multilevel pulse width
modulation (PWM) converter, because an inverter contains electronics switches, it is possible to
control output voltage as well as optimize the harmonics by performing multiple switching
within the inverter with the constant dc input voltage. Basic working of PWM shown below,
various modulation strategies have been developed. Moreover, abundant modulation techniques
and control paradigms have been developed for multilevel converters such as sinusoidal pulse
width modulation (SPWM), selective harmonic elimination (SHE-PWM), space vector
modulation (SVM), and others. Among these strategies, space-vector modulation (SVM) stands
out because it offers significant flexibility to optimize switching waveforms, and because it is
well suited for implementation on a digital computer. However, regardless of its advantages,
SVM for more than three-level converters is still mostly unexplored. This is largely the
consequence of increasing computational difficulties for converters with a higher number of
levels. In addition, many multilevel converter applications focus on industrial medium-voltage
motor drives, utility interface for renewable energy systems, flexible ac transmission system
(FACTS), and traction drive systems.
The availability of SCR s in high power ratings, having turn-off times in the range of a
few microseconds, has increased the feasibility of achieving a practically sinusoidal output by
employing sophisticated switching patterns in inverter circuits. The derivation of optimal
switching patterns to obtain a harmonic-free sinusoidal output is now possible.

41
3.2 Multilevel Converter PWM Strategies
The pulse width modulated inverters make use of different modulation schemes such as
Classification of PWM multilevel converter modulation strategies as shown below

Fig.3.1 Classification of PWM multilevel converter modulation strategies

The following are some major concerns when comparing different PWM techniques:
➢ Good utilization of DC power supply i.e. to deliver a higher output voltage with the
same DC supply
Good linearity in voltage and or current control.
➢ Low harmonics contents in the output voltages especially in the low-frequency
region.
➢ Low switching losses.
The advantage of PWM based switching power converter over linear power amplifier is:

➢ Easy to implement and control

42
 ➢ No temperature variation and aging-caused drifting or degradation in linearity.
➢ Compatible with today's digital micro-processors
➢ Lower power dissipation.

3.3 Selective Harmonic Elimination Pulse Width Modulation (SHE PWM)

Selective harmonic elimination PWM technique is introduced by Patel. The SHE
technique can be applied to three-phase VSIs. In this case, the power valves of each leg of the
inverter are switched so as to eliminate a given number of harmonics and to control the
fundamental phase voltage amplitude. The idea of such a method is that the basic square-wave
output is "chopped" a number of times, which are obtained by proper off-line calculations. Fig.
3.2 shows a generalized quarter-wave symmetric stepped voltage waveform synthesized by a
(2m+1)-level inverter,

v.
V2
v,
t

Fig.3.2 Generalized stepped-voltage waveform.

where m is the number of switching angles. By applying Fourier series analysis, the amplitude of
any odd harmonic of the stepped waveform can be expressed as 3.1, whereas the amplitudes of
all even harmonics are zero
N
H„ = 4E (-1)
N(1+21(--1)k cos(nak ) (3.1)
nor k=1

Where N is no. of switching angles, n odd harmonic order, ak is kth switching angle, According
to fig 3.2 a, to am must satisfy al< a2<.......< am <n/2.

To minimize harmonic distortion and to achieve adjustable amplitude of the fundamental

component, up to M-1 harmonic contents can be removed from the voltage waveform. In
general, the most significant low-frequency harmonics are chosen for elimination by properly

43
selecting angles among different level inverters, and high-frequency harmonic components can
be readily removed by using additional filter circuits.

3.4 SINUSOIDAL Pulse Width Modulation (SPWM)

The principle of the sinusoidal PWM scheme for the two-level inverter is illustrated in
Fig. 3.3, where VmA, V, and Vmc are the three-phase sinusoidal modulating waves and Vcr is
the triangular carrier wave. The fundamental-frequency component in the inverter output voltage
can be controlled by amplitude modulation index

m —V'"
a -
V~r

., ., „ _ ..
V

0 fit

V AN

ON

V?N

0 tot

V AR

0 a)'

Figure 3.3 Sinusoidal pulse-width modulation (SPWM).

where Vm and Vcr are the peak values of the modulating and carrier waves, respectively. The
amplitude modulation index ma is usually adjusted by varying Vm while keeping Vcr fixed. The
frequency modulation index is defined by

f fm
where fm and f are the frequencies of the modulating and carrier waves, respectively.

44
 Several multicarrier techniques have been developed to reduce the distortion in multilevel
inverters, based on the classical SPWM with triangular carriers. Some methods use carrier
disposition and others use phase shifting of multiple carrier signals. Fig. 3.4(a) shows the typical
voltage generated by one cell for the inverter shown in Fig. 3.5 by comparing a sinusoidal
reference with a triangular carrier signal. A number of Nc—cascaded cells in one phase with their
carriers shifted by 0 c =360/Ne and using the same control voltage produce a load voltage with
the smallest distortion. The effect of this carrier phase-shifting technique can be clearly observed
in Fig3.5 This result has been obtained for the multi-cell inverter in a seven-level configuration,
which uses three series-connected cells in each phase. The smallest distortion is obtained when
the carriers are shifted by an angle of 0 c =360/3=120. A very common practice in industrial
applications for the multilevel inverter is the injection of a third harmonic in each cell, as shown
in Fig. 3.4(b), to increase the output voltage.
Another advantageous feature of multilevel SPWM is that the effective switching
frequency of the load voltage is times the switching frequency of each cell, as determined by its
carrier signal. This property allows a reduction in the switching frequency of each cell, thus
reducing the switching' losses.

O Tm 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

Time (s)

fl1Jff[UL 111111
(& 1

bi HTFTIfliL
O 0.00S 0.01 0.016 0.02 0,025 0.03 0.035 0.04

Time (s)
Fig. 3.4 Inverter cell voltages. (a) Output voltage and reference with SPWM.
(b) Output voltage and reference with injection of sinusoidal third harmonic.

45
 ltlftllUJUffi
v
v 0c00
an THD=75.94%
•
soo
0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065 0.07

^V~ p r U f / E?IV
THD=44.54%
-500
0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065 0.07
500

Va, 0
THD=29.75%
.500
0.02 0.025 0,03 0 035 0.04 0.045 0.05 0.055 0.06 0.065 (107

500
[v~
Van Q
THD=24.65°k

0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.0555 0.06 0.065 0.07
Time [Sec.]

Fig:3.5 Total voltage of three cells in series connection for different phase
Displacement in the carriers.
3.5 Third Harmonic Injection PWM
The inverter fundamental voltage VAB can also be increased by adding a third harmonic
component to the three-phase sinusoidal modulating wave without causing over modulation. This
modulation technique is known as third harmonic injection PWM. Figure 3.6 illustrates the
principle of this PWM scheme, where the modulating wave VmA is composed of a fundamental
component Vml and a third harmonic component Vm3, making VmA somewhat flattened on the
top. As a result, the peak fundamental component Vml can be higher than the peak triangular
carrier wave Vcr, which boosts the fundamental voltage vABI. In the meantime the peak
modulating wave VmA can be kept lower than Vcr, avoiding the problems caused by
overmodulation. The maximum amount of VAB1 that can be increased by this scheme is 15.5%
[22, 23].

46
 i.—
V

0 «t

Figure 3.6 Modulating wave VmA with third harmonic injection.

3.6 Space Vector Control

A conceptually different control method for multilevel inverters, based on the space-
vector theory, has been introduced . This control strategy, called SVC, works with low switching
frequencies and does not generate the mean value of the desired load voltage in every switching
interval, as is the principle of SVM. Fig. 3.7 shows the 311 different space vectors generated by

an 11-level inverter. The reference load voltage vector V,pf is also included in this figure. The

main idea in SVC is to deliver to the, load a voltage vector that minimizes the space error or dis-
tance to the reference vector . The high density of vectors produced by the 11-level inverter (see

Fig. 3.7.) will generate only small errors in relation to the reference vector V,~f ; it is, therefore, "

unnecessary to use a more complex modulation scheme involving the three vectors adjacent to
the reference..
i a•..aw ,-:ao e. I•o•r.e , .a ♦ .e-.-r.s r. or r.. ..~:.

:.r. j~ y..~,; n y. `a ~.1~• k_ y .gyp •

r V

:•~rsif. •:-:.:. -i3LSi - -:•4 •'r.. i ;•~s ii►d•~i -

a..i ...t».iaz a..t...w ♦ :~. t± srM.

-#r,t. .M.~-' •.•:w ix l.4 t d.~.♦ t

T t..` M'i'l e'o. : .:.:. 4.. # -Eti av•'

} ;-:-.:. .:i 4:4.4.: i4: A-:^+-,"M
liti 4
:! ;• a .•
•

Fig. 3.7. Load voltage space vectors generated by an 11-level inverter.

47
 The shaded hexagon of Fig. 3.7 shows the boundary of highest proximity, which means
that when the reference voltage is located in this area, vector V, must be selected, because it has
the greatest proximity to the reference. Fig. 3.8 (a) presents the voltage generated by one cell in
an eleven-level multicell inverter with five cells per phase and an output frequency of 50 Hz. The
load voltage of the inverter for the same frequency and modulation index 0.99 is shown in Fig.
3.8(b).

0
flfl

0 0.005 0.01 0.015 002

Tone (s)

(a)
400

200

•200

-400
0 0.01 0..02 0.03 0.04 0.05
rat (s)

(b)
Fig. 3.8 Voltages generated by an 11-level inverter with SVC. (a) One-cell
voltage. (b) Resulting load voltage.
This method is simple and attractive for high number of levels. As the number of levels
decreases, the error in terms of the generated vectors with respect to the reference will be higher;
this will increase the load current ripple.

3.7 Direct Torque Control (DTC)

The DTC technique has been developed for low-voltage two level inverters as an
alternative to the field oriented method to effectively control torque and flux in ac drives. DTC
and hysteresis current control techniques have also been applied in multilevel inverters. It must
be noticed that one major manufacturer has been selling medium-voltage three-level diode-
clamped inverters controlled with DTC.

48
3.8 Space Vector Pulse Width Modulation
Among various modulation techniques for a multilevel inverter, space vector pulse width
modulation (SVPWM) is an attractive candidate due to the following merits. It directly uses the
control variable given by the control system and identifies each switching vector as a point in
complex (a, Q) space. It is suitable for digital signal processor (DSP) implementation. It can
optimize switching sequences. The space-vector PWM method is an advanced, computation-
intensive PWM method and is possibly the best among all the PWM techniques because for a
three phase inverter makes it possible to adapt the switching behavior to different situations such
as: half load, full load, linear load, non-linear load, static load, pulsating load, etc and the
following are the advantages. Very low values can be reached for the output voltage THD, robust
dynamic response, the efficiency of the inverter can be optimized for each load condition and
SVM enables more efficient use of the DC voltage (15% more than conventional PWM
techniques, so the inverter will accept a 15% lower DC voltage making full use of the available
battery energy). Space vector modulation (SVPWM) is one of the preferred real-time modulation
techniques, for variable-frequency drive applications. Because of its superior performance
characteristics, and is widely used for the digital control of Voltage source inverters. It is an
advanced, computation intensive PWM and possibly the best among all the PWM techniques for
variable frequency drive applications.

Consider a three phase two-level inverter, Switching states represent the operating status
of switches in the two-level inverter the switching sequence of an inverter is in the order of 1-2-
3, 2-3-4, 3-4-5, 4-5-6, 5-6-1,6-1-2 and so an each switch conducts over 180 in a period and
inverter in 180 mode of conduction.

1 3 S

V'c
a s 2

Fig 3.9 Three phase two level inverter

49
Switching states of the inverter:

Switching from one sequence to another takes place at every 60 degrees.

There are two more possible sequences that produce no voltage are 1-3-5 and 4-6-2. So
that there are 6 active states and 2 inactive states.
Positive group switches : 1,3,5
Negative group switches: 4,6,2
Switching vector a, b, c for the three legs represented by 1's and 0's.
1 indicates positive group switches are on
0 indicates negative group switches are on
The eight permissible switching states of the inverter are as shown below:

vn — V1 = [i 0 n)
-i

[O 1 07
F-1 P-i ii
= F-1
V4(0 s 13

.....
.i j1
..... ._. . _
hh
V6 z [I 0 1] v, =[111
I
Figure 3.10 Three-phase Two-Level Inverter Switching States

The operating status of the switches in the two-level inverter in Fig. 3.9 can be
represented by switching states. As indicated in Table 3.1, switching state `P' denotes that the
upper switch in an inverter leg is on and the inverter terminal voltage is positive (+Vd) while `0'
indicates that the inverter terminal voltage is zero due to the conduction of the lower switch.
There are eight possible combinations of switching states in the two-level inverter as listed in
Table 3.2 The switching state [P00], for example, corresponds to the conduction of S 1, S6, and
S2 in the inverter legs A, B, and C, respectively.

50
 Switching Leg A Leg B Leg C
State

Si S2 Van S3 S6 Vbn S5 S6 Vcn

P On Off Vd On Off Vd On Off Vd

0 Off On 0 Off On 0 Off On 0

Table: 3.1 Definition of Switching States

Space Vector Switching State On State Switch Vector Definition

V [000] 135
0 V0 -
—0

V [POO] 162
=2
V -
V,d 3 V ej0
V [PPO] 132

V [OPO] 432
3 3 = 3 d

V [OPP] 435
4 —2
V4 = 3 Vd e'3 /

[OOP] 465
V5s 5 = 3 d

V [POP] 165
6 6 3 d

V [PPP] 462 0V
Table:3.2 Space Vectors, Switching States and On state Switches

The active and zero switching states can be represented by active and' zero space vectors,
respectively. A typical space vector diagram for the two-level inverter is shown in Fig.3.10,

where the six active vectors V, to V6 form a regular hexagon with six equal sectors (I to VI). The

zero vector TO lies on the center of the hexagon. Assuming that the operation of the inverter is
three-phase balanced, we have
VAQ(t)+VBO(t)+Vco(t) = 0 (3.8.1)

Where, vAo, VBO, and vco are the instantaneous load phase voltages.

51
 v3 j3 Yz

% SECTOR
SECTOR III IL w SECTOR 1

OPP\ j Poo

SECTOR M►' SECTOR VI

A
C4
POP
VS Va

Figure: 3.11 Space vector diagram for the two-level inverter.

From mathematical point of view, one of the phase voltages is redundant since given any
two phase voltages, the third one can be readily calculated. Therefore, it is possible to transform
the three-phase variables to equivalent two-phase variables [5].

2 1. — 2 — VAO (t)
[Va]=
Veo (t) (3.8.2)

Vfl 3 0
2
—
2
Vco (t)

The coefficient 2/3 is somewhat arbitrarily chosen. The commonly used value is 2/3. The
main advantage of using 2/3 is that the magnitude of the two-phase voltages will be equal to that
of the three-phase voltages after the transformation. A space vector can be generally expressed in
terms of the two-phase voltages in the a-[i plane

V(t)=va(t)+ jvfl (0 (3.8.3)

Substituting (3.8.2) into (3.8.3), we have

+VBO (t )e j2A13 +Vco (t )e'an~s

V (t) = 3 [VAO(t)ej° (3.8.4)

all six active vectors can be derived by

ar
2 j(k -1)
Vk = 3Vae 1 ,k =1,2,.....6

The zero vector V° has two switching states [PPP] and-[000], these redundant switching

state can be utilized to minimize the switching frequency of the inverter or perform other useful

functions. For a given magnitude (length) and position, V,,f can be synthesized by three nearby

52
stationary vectors, based on which the switching states of the inverter can be selected and gate

signals for the active switches can be generated. When V j passes through sectors one by one,

different sets of switches will be turned on or off. As a result, when V,,j rotates one revolution

in space, the inverter output voltage varies one cycle over time. The inverter output frequency

corresponds to the rotating speed of , while its output voltage can be adjusted by the

magnitude of VJ .

Dwell Time Calculation

The dwell time for the stationary vectors essentially represents the duty-cycle time (on-state or
off-state time) of the chosen switches during a sampling period Ts of the modulation scheme.
The dwell time calculation is based on `volt-second balancing' principle, that is, the product of

the reference voltage V,pj and sampling period Ts equals the sum of the voltage multiplied by

the time interval of chosen space vectors.

U T. r~i
T;

Fig.3.12 V,ej synthesized by V, ,V2, Vo

The volt-second balancing equation is

Vrejl =VITQ +VZTb +VVTO (3.8.5)

TS =T,,+Tb +To

Where, Ta, Tb, and To are the dwell times for the vectors V, , V2 and V,, respectively.

53
 TQ =Tma sin1 3 —B

Tb =Tsma sin(6) for0<_0 <,r/3

Where mais modulation index ma = [3Vref

Vd

1/ ~
~1 i i V2 t V,
000 POO PPO i PPP PPO i POO bo
E 4 i i
V1

I
E l
~

3 E rA I

E 3 1 1y i

0'
E E 9 E !

L
To T Try Tc, Tn 7'

Fig: 3.13 Seven Segment Switching Sequence for V,ef in sector 1

With the space vectors selected and their dwell times calculated, the next step is to

arrange switching sequence. In general, the switching sequence design for a given Vref is not

unique, but it should satisfy the following two requirements for the minimization of the device
switching frequency, The transition from one switching state to the next involves only two
switches in the same inverter leg, one being switched on and the other switched off. The

transition for V,,f moving from one sector in the space vector diagram to the next requires no or

minimum number of switching's. In SVM 90.7 percentage of the fundamental at the squre wave

54
is available in region compared to 78.55 percent in the sinusoidal PWM.In order to minimize the
number of switching's in the inverter, the following switching pattern is selected
Sector STATE STATE
(on sequence) T., (off sequence) Ts

Sector-1 Vo-V1-V2-V7. V7-V2-V1-V0.

Sector-2 Vo-V3-V2-V7. V7-V2-V3-V0.
Sector-3 V0- V3-V4-V7. V7-V4- V3-Vo.
Sector-4 Vo-V5-V4-V7. V7-V4-V5-V0.
Sector-5 Vo-V5-V6-V7. V7-V6-V5-V0.
Sector-6 Vo-V1-V6-V7. V7-V6-V1-V0.
Sector-7 Vo-V1-V2-V7. V7-V2-V1-Vo.
Table 3.3. Representation of switching sequence

However, the implementation of the SVPWM for a multilevel inverter is becomes

complicated, as level is increases. The complexity is due to the difficulty in determining the
location of the reference vector, the calculation of on-times, and the determination and selection
of switching states. To overcome, above so many SVPWM techniques have been proposed.

3.9 SVM for Three Level Inverter

Among various modulation techniques for a multilevel inverter, space vector modulation
(SVM) is an attractive control strategy due to the following merits. It directly uses the control
variable given by the control system and identifies each switching vector as a point in complex
(a, (3) space. It is suitable for digital signal processor (DSP) implementation. It can optimize
switching sequences. The space vector diagram of any three-phase n-level inverter consists of six
sectors. Each sector consists of (n — 1)2 triangles. The tip of the reference vector can be located
within any triangle. Each vertex of any triangle represents a switching vector. A switching vector
represents one or more switching states depending on its location. There are n3 switching states
in the space vector diagram of an n-level inverter. The SVM is performed by suitably selecting
and executing the switching states of the triangle for the respective on-times. The performance of
the inverter significantly depends on the selection of these switching states.
The space vector diagram of a three-level inverter is shown in Fig. 3.14 There are six
sectors (S1—S6), four triangles in each sector, and a total of 27 switching states in this space

55
vector diagram. As level n increases, the increased number of triangles, switching states, and
calculation of on-times adds to the complexity of SVM for multilevel inverters. There are two
common approaches to obtain the on-times. The first approach is to determine the triangle, and
then solve three simultaneous equations for this triangle to obtain the on times. Whereas, the
second approach is to determine the triangle, and then use the particular on-time equations stored
in the lookup for this triangle, as in. However, as the number of level increases, both of these
approaches become computationally intensive.
The studies in and proposed a general method to obtain on-times for the SVM of
multilevel inverter in linear modulation range. A Euclidean vector system based SVM algorithm
is presented by Celanovic and Boroyevich, which is quite involved due to the use of several
matrix transformations. Furthermore, does not provide a systematic approach for determining the
switching states nor does it provide a real-time implementation. Wei et al. propose an algorithm
which is a different representation of the scheme in this scheme uses 600 coordinate system to
calculate on-times and determine switching states. Since most control schemes provide a voltage
reference in a—[i coordinates, the 60° transformation adds to complexity.

Space Vectors
As indicated earlier, the operation of each inverter phase leg can be represented by three
switching states [P], [0], and [N]. Taking all three phases into account, the inverter has a total
of 27 possible combinations of switching states. As listed in Table 3.4, these three-phase
switching states are represented by three letters in square brackets for the inverter phases A, B,
and -C.
To find the relationship between the switching states and their corresponding space
voltage vectors, the 27 switching states listed in the table 3.4 correspond to 19 voltage vectors
whose space vector diagram is given in Fig. 3.14. Based on their magnitude (length), the voltage
vectors can be divided into four groups:

Zero vector ( V4 ) representing three switching states, [PPP], [000], and [NNN]. The

magnitude of iyo is zero.

Small vectors (V, to V6 ), all having a magnitude of Vd/3. Each small vector has two

switching states, one containing [P] and the other containing [N], and therefore can be further
classified into a P- or N-type small vector.

62
Medium vectors (V7 to VZ ), whose magnitude is 3Vd/3.

Large vectors (V13 to V,8 ), all having a magnitude of 2Vd/3.

ii k rr 2

V1fi

4!t7 YI t 1'18

Figure:3.14 Space vector diagram of the NPC inverter.

Dwell time calculation

The dwell time calculation, the space vector diagram of Fig. 3.14 can be divided into six
triangular sectors (I to VI), each of which can be further divided into four triangular regions (1 to
4) as illustrated in Fig. 3.15 The space vector modulation for the NPC inverter is also based on
"volt-second balancing" principle, that is the product of the reference voltage Vref and sampling
period TS equals the sum of the voltage multiplied by the time interval of chosen space vectors.
SECTOR [I
Ais Pt OPN vta
NPN PPN
SECTOR ITT -. ti , ° .° SECTOR I
Ort) N
N'N) TiON' OON ION
2
1 3
• OPP \4 PPP ~j e
NPI' N \ NNN ~y (X)o ONN PN3d
3 2 1

Iio 001' • P01' . •

NOP NCO IFS lINt)

4
SECTOR IV --" • SECTOR VI
NNP rNI'
II. P, ONP 0
SECTOR V

57
 Figure 3.15 Division of sectors and regions.
Space Vector Switching State Vector Vector
Classificati Magnitude
on
[PPP][000][NNN] Zero 0
Vector
Ptype Ntype
V -~ [P00]
VIP
[ONO]
V, N
-, -- [PPO]
VZ V zP
-+ [OON]
V2N
[OPO]
V3 V 3P Small 3 Vd
-i [NON] Vector
V3N
[OPP]
V4 V4P
- [NO0]
V4N
[OOP]
V5 V5N

[NNO]
V5P
-+ [POP]
V7 V6N
-+ [ONO]
V6P
[PON]
V77
-► [OPN]
Vs
{NPO] 3 a
V9
[NOP] Medium
V10 Vector
- [ONP]
V,1
[PNO]
V12

V 13 [P] 3Vd
[PPN] Large
- 14
V
[NPN] Vector
V15
--4 [NPP]
V16
-► [NNP]
[NNP]
V17

V18

58
 Table 3.4 Voltage Vectors and Switching States
In the NPC inverter, the reference vector Vref can be synthesized by three nearest

stationary vectors. For instance, when Vfef falls into region 2 of sector I as shown in

Fig.3.16, the three nearest vectors are V, , VZ , and V, , from which

ii, +V, Tb +V', =VYefTs (3.9.1)

TQ +Tb +T, =Ts

Where Ta, Tb, and T. are the dwell times for y , V, , and V2 respectively. Note that VYef can also

be Synthesized by other space vectors instead of the "nearest three."However, it will cause
higher harmonic distortion in the inverter output voltage, which is undesirable in most case
1 4 PPN

4
S~C7'OR I

p2 PPU
~~iQN
o0N

1 2 3

T '
~6 B I'M T, PNN
ONN
3

Figure 3.16 Voltage vectors and their dwell times.

The voltage vectors VVZ ,V and V,, can be expressed as

V — +V, V2 — 3 Vde15/ , V = $ Vaei/ and Vref = V,efe )o (3.9.2)

Substituting 1 into 2 yields

3 VdTa +4 Vaei'1Tb + 3 VdeiT, = V,fei°Ts

1VdT. + - Vd (cos -+ j sin Z )Tb +1Vd (cos Ir + j sin ! )Tc = V1ef (cos 9 + j sin B)TS
3 3 6 6 3 3 3
We have real and imaginary parts

Re: T +- Tb +2T, =3 (cos9)T (3.9.3)

Im: +',+4i = 3 - (sin 9)Ts

59
Solve (3) together with Ta +Tb +TT = T, for dwell time
T,, =Ts 2m0 sin0

Tb =T,[2-2ma sin(3 + 0)]

T, = T,[2me sin(-3 3 — 0)]

Where ma is the modulation index, given by

The maximum length of the reference vector V.,f corresponds to the radius of the largest
circle that can be inscribed within the hexagon of Fig. 3.14, which happens to be the length of
the medium voltage vector

V~I,max = F3Vd / 3

Substituting Vrefmax, it yields the maximum modulation index

m _ E Yr ef ,max _1
a,max y , V
d

from which the range of ma is 0 <_ mw <_ I

Table 3.5 gives the equations for the calculation of dwell times for V,ef in sector I.
Ta Tb TC

V TS [2ma sin( — 0)] V TS [1— 2ma sin( + 8)] Vi TS [2ma sin B]

3 3

y TS [1-2ma sin B] Y, T5[2ma sin(3 +0)-1] V2 T5[1-2ma sin(3 —9)]

TS[2masin0] V,3 Ts[2ma sin(3 —0)-1]

V T5[2-2ma sin(3 +0)]

V14 TS[ 2ma sin 0-1] V7 Ts[2ma sin(3 —0)] VZ Ts[2-2ma sin(3 + 0 )]

Table 3.5 Dwell Time Calculation for Vef in sector 1

60
 The equations in Table 3.5 can also be used to calculate the dwell times when Vref is in
other sectors (II to VI) provided that a multiple of 2t13 is subtracted from the actual angular
displacement 0 such that the modified angle falls into the range between zero and n/3 for use in
the equations.
Relationship Between Vref Location and Dwell Times
To demonstrate the relationship between the V location and dwell times, consider an

example shown in Fig. 3.17 Assuming that the head of V,. j points to the center Q of region 4,

the dwell times for the nearest three vectors V2, VV, and V14 should be identical since the distance

from Q to these vectors is the same. This can be verified by substituting ma = 0.882 and 0 =
49.10 into the equations in Table 3.5, from which the calculated dwell times are Ta = Tb = Tc =

0.333Ts. With V,,f moving toward V2 from Q along the dashed line, the influence of V2on Vref

becomes stronger, which translates into a longer dwell time for V2. When V,p1 is identical to V2,
the dwell time Te for V2 reaches its maximum value (Tc = Ts) while Ta and Tb for V14 and V7
diminish to zero.

pia PPN

4~Q SECTOR I

\
PO

ut, =0,882

P
P00 PNN
ONN
V0 E13

Figure 3.17 An example to demonstrate the relationship between the location of

V,.,f and dwell times.

Switching Sequence Design

The neutral point voltage VZ which is defined as the voltage between the neutral point

61
 Z and the negative dc bus, normally varies with the switching state of the NPC inverter. When
designing the switching sequence, we should minimize the effect of the switching state on
neutral point voltage deviation. Taking into account the two requirements presented in Chapter
6 for the two-level inverter, the overall requirements for switching sequence design in the NPC
inverter are as follows:
➢ The transition from one switching state to the next involves only two switch- es in the same
inverter leg, one being switched on and the other switched off.

➢ The transition for V,,f moving from one sector (or region) to the next requires no or

minimum number of switching's.

➢ The effect of switching state on the neutral-point voltage deviation is minimized.
Effect of Switching States on Neutral-Point Voltage Deviation.
The effect of switching states on neutral voltage deviation is illustrated in Fig. 3.18
When the inverter operates with switching state [PPP] of zero vector Vo, the upper two
switches in each of the three inverter legs are turned on, connecting the inverter terminals A, B,
and C to the positive dc bus as shown in Fig. 3.18(a). Since the neutral point Z is left
unconnected, this switching state does not affect Vz. Similarly, the other two zero switching

states, [000] and [NNN], do not cause Vz to shift either.

Figure 3.18(b) shows the inverter operation with P-type switching state [POO] of small vector V i .
Since the three-phase load is connected between the positive do bus and neutral point Z, the
neutral current iZ flows into Z, causing VZ to increase. On the contrary, the N-type switching state
[ONN] of V1 makes Vz to decrease as shown in Fig. 3.18(c).

The medium-voltage vectors also affect the neutral-point voltage. For medium vector V7 with
switching state [PON] in Fig. 3.18(d), load terminals A, B, and C are connected to the positive
bus, the neutral point, and the negative bus, respectively.
Depending on the inverter operating conditions, the neutral-point voltage VZ may rise or drop.

Considering a large vector V13 with switching state [PNN] shown in Fig. 3.18(e), the load
terminals are connected between the positive and negative dc buses. The neutral point Z is left
unconnected, and thus the neutral voltage is not affected.
It can be summarized that
. ➢ Zero vector Vo does not affect the neutral point voltage Vz.

62
➢ Small vectors V1 to V6 have a dominant influence on Vz. A P-type small vector makes
Vz rise, while an N-type small vector causes Vz to decline.
> Medium vectors V7 to V12 also affect Vz, but the direction of voltage deviation is
undefined.
➢ The large vectors V13 to V18 do not play a role in neutral-point voltageeviation

+ /_
1'•Z3:
,/
TT" __ii
0d
ll
I ç4.
~~ ~
\~
# rZ
44
BO
1 A
D

l y1 V

[PPP] Vz not affected [POO] Vz

(a) Zero Voltage Vector (b) P- Type Small Vector

Cal L
I I J.._
L
d~
. I
1/~. f A ,~ + A
D

T 2 DC
_1'jC(I2

[CNN] >> Vz J. [PON] Vz not defined

(c)N-Type small vector (d) medium vector

Cat L
4A
r7 1° 1
1A1

V~ d-
0 "

[PNN] Vz not affected

(e)Large Vector
Fig 3.18 Effect of Switching States on Neutral point voltage deviation

63
Switching Sequence with Minimal Neutral-Point Voltage Deviation.
As mentioned earlier, a P-type small vector causes the neutral-point voltage Vz to rise
while an N-type small vector makes Vz fall. To minimize the neutral point voltage deviation,
the dwell time of a given small vector can be equally distributed between the P- and N-type
switching states over a sampling period. According to the triangular region that the reference

vector V,ef lies in, the following case is investigated.

One Small Vector Among Three Selected Vectors.

When the reference vector Vf is in region 3 or 4 of sector I shown in Fig. 3.16, only

one of the three selected vectors is the small vector. Assuming that V falls into region 4, it

can be synthesized by V2, V7, and V14. The small vector V2 has two switching states [PPO]

and [OON]. To minimize the neutral voltage deviation, the dwell time for V2 should be equally

distributed between the P- and N-type states. Figure 3.19 shows a typical seven-segment
switching sequence for the NPC inverter, from which we can observe that
➢ The dwell times for the seven segments add up to the sampling period of the PWM
pattern (TS = Ta + Tb + Tc ).

64
 -- `-------------r—.-.._. '------r------
i
~2h 3 V7 r11 i 1/211 : i4 i V7 Y2'v
!,00N PON PPN ''O i P9'N PON 'OON'

0•

V/vt
0.

Vr.x

I i ~
vfrN< +L i.
4 1 P € i
Te I Th s T, I C t f T1,
4i 2 i 2 i 2 i 2 i 2 i4
o. .., ......,_— .,..,_. — ............ ............._...,M._..... _,., .._,.__....,.3.14...,,.,,.,.m.... — ,_,,,..,..................ti

__

Figure 3.19 Seven-segment switching sequence for

V,ef in sector I-4.
> Design requirement (a) is satisfied. For instance, the transition from [OON] to [PON] is
accomplished by turning Si on and switching S3 off, which involves only two switches.
➢ The dwell time Tc for V2 is equally divided between the P- and N-type switching states,
which satisfies design requirement (c).
➢ Among the four switching devices in an inverter leg, only two are tuned onand off once

per sampling period. Assuming that the transition for Vrej moving from one sector (or
region) to the next does not involve any switching's, the device switching frequency
fsw,dev is equal to half of the sampling frequency fsp, that is,
fsw,dev = fsp/2 =1/(2Ts)
3.10 NEUTRAL-POINT VOLTAGE CONTROL
As indicated earlier, the neutral-point voltage VZ varies with the operating condition of
the NPC inverter. If the neutral-point voltage deviates too far, an uneven voltage distribution
takes place, which may lead to premature failure of the switching devices and cause an increase
in the THD of the inverter output voltage.
Causes of Neutral-Point Voltage Deviation
In addition to the influence of small- and medium-voltage vectors, the neutral-point
65
voltage may also be affected by a number of other factors, including
> Unbalanced dc capacitors due to manufacturing tolerances
> Inconsistency in switching device characteristics
> Unbalanced three-phase operation
To minimize the neutral-point voltage shift, a feedback control scheme can be
implemented, where the neutral-point voltage is detected and then controlled.

3.11 Conclusion
In this chapter the implementation of Sinusoidal Pulse width Modulation, Third Harmonic
Injection SPWM, Multi carrier PWM and Space Vector Pulse Width Modulation (SVPWM)
Techniques have been discussed. It is possible to control output voltage as well as optimize the
harmonics by performing multiple switching within the inverter with the constant dc input
voltage among all the PWM techniques because it possible to adapt the switching behavior to
different situations. Very low values can be reached for the output voltage THD, SVM enables
more efficient use of the DC voltage 15% more than conventional PWM techniques.

65
 CHAPTER-4
PERFORMANCE EVALUATION OF MULTILEVEL
INVERTER FED INDUCTION MOTOR DRIVE

In this chapter the performance of two level PWM inverter and Three Level Neutral Point
Clamped Inverter fed Induction Motor Drive with Sinusoidal PWM, Third Harmonic Injection
and Space Vector Modulation are evaluated. The steady state and dynamic performance of drive
was discussed under different condition of speed, frequency and load. The TI-ID variation with
frequency was also evaluated and the performance comparison of the various inverters fed
induction motor drives was also presented.
The rating of 3-Phase Induction Motor:
Power . 20HP
Voltage : 400 Volts
Frequency : 50 Hz
Speed . 1460 rpm
Poles : 4
4.1 Two Level Inverter Fed Induction Motor Drive
4.1.1 Sinusoidal Pulse Width Modulation
The generalized simulink block of Two Level PWM Inverter fed Induction Motor Drive
for all two level schemes shown in Fig.4.1 and Fig 4.2 shows the switching control block of
Sinusoidal Pulse Width Modulation for the 2 level inverter fed induction motor drive. In the
switching control block, from the reference speed obtained after processing the speed error
through PI controller and limiter and adding it to measured speed, the frequency was calculated
and converted to radians(w). from this the three sinusoidal modulating signals for the SPWM
were obtained by multiplying `w' with time `t' as follows.
Sin(w * t)
2~c
Sin(w*t— 3 )

Sin(W * t +7
2 )

66
 By multiplying the frequency obtained with constant v/f ratio and adding boost voltage to
it. The required voltage was obtained. Then by dividing it with rated voltage, the modulating
index was obtained. Now the three sinusoidal modulating signals with variable frequency and
voltage were ready for the SPWM and the rest of the part of generating control signals.

Fig: 4.1 Simulink block for all two level inverter fed induction motor drive

Fig: 4.2 SPWM Control Scheme for 2-level PWM Inverter

67
 12

Fig 4.3 Sinusoidal Pulse width Modulation

The steady state performance of the 2-level inverter fed induction motor drive for different speed
and load conditions was shown below Figs
Response for Starting with No Load
Here the motor was started without any load and the reference speed was set to 1500
RPM. When the speed error reaches nearly zero rpm, the winding current also reduces to no load
value and the developed torque equals to zero. Fig 4.4 shows line to line voltage of two level
inverter.

7 GA 0.z 0.3 0.d as 16 a7 os U9 1

Time

1 0.1 02 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Time

T.

Fig: 4.4 Line to Line Voltages (volt)

68
 40

90

20

05 O
".i5
-10

30

-40
2
'rk

Fig: 4.5 Stator current (amp) on No load condition.

woo

15.,

-: 1000
0
ca

-500 7
0.05 0i 0.15 0.2 0.25 0.3 0.35 O. 4
Time
200

150

100
m,
50
r`
.a
0

-50

.-1(0
0:1 0.16 0.2 0.25 0.3 035 O.4
Time
Fig:4.6 Performances of Speed (Rpm), Torque (N-m).
Response for starting with Full Load:
In this case the motor was started with load 95 Nm and the reference speed was set to
1500RPM. When the speed reaches to steady state value, the winding current and the developed
torque equals to the set value of load. The performance of Induction Motor drive is shown in
following Figures.4.7-4.8.The figs 4.9-4.10 show the harmonic spectrum of line voltages and line
currents.
200

7 5(]

„SCI

Fig: 4.7 Performances of Stator currents(amp).

f ,;r

3 1.05 0.1 0:15 0.2 0.25 0.3 0.35 O4

Time

35~

CO

200

so

OD

4
Time

Fig: 4.8 Performance of Speed (Rpm), Torque (N-m) with load.

70
 FFTwindow: 5 of 39.94 cycles of selected signal

___ __ H LJ Li
-500
0.4 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49
Time (s)

Fundamental (50.1 Hz) = 436.5 , THD= 30.07%

0 4
t~..
0 3
C2
7

0 2 4 6 8 10 12 14 16 18
Harmonic order

Fig: 4.9 Line to Line voltage and Harmonic Spectrum

ialyze
Mlected s€gnaO fos Display FFT window
FFT window 5 of 50 cycles of selected signal

20 ,r~^

0.4 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49

is
Fundamental (50Hz) = 23.15 THD=18.99%

4
C
E 3
C
C
_
L4"
0
C'

0
0 2 4 6 8 10 12 14 16 18 20
Harmonic order

Fig: 4.10 Line currents (amp) and Harmonic Spectrum.

71
Response for Frequency 40 Hz
Under this case the motor was started with load 95 Nm and the reference speed was set to
1250 RPM. When the speed reaches to steady state value, the winding current and the developed
torque equals to the set value of load. The performance during this case the torque and speed
oscillates and it will take more time to reaches steady state. The performance of Induction Motor
during Loading Condition is shown in following Figs 4.11-4.12

Fig: 4.11 Stator current Ia (amp)

1400
1200
1000
Soo
600
400

200
O
200

'31117
_a0
ten]

54
fri7

01 0.1ti n. . - o.: p...:i u.:3s u.

Fig: 4.12 Performance of Speed(Rpm), Torque(N-m) with 40 Hz

72
Response for step change in load
Motor is first started o no load with reference speed of 1500RPM. Starting torque will be
developed to accelerate the machine. Once the speed reaches to reference speed torque
developed also set to zero, at 0.3 sec a load torque of 95 N-m is applied. Sudden application of
load on the rotor causes an instantaneous fall in the speed of motor. In response to this drop in
speed value, the output of the controller responds by increasing the reference speed value. So
developed torque increases and motor speed settles at steady value again, and winding current
will increase. The performance of Motor during this case shown in below Figs: 4.13-4.14.

Fig:4.13 Stator Currents (amp) with Change in Load

1500

E 1000 ./
500

-500 ._____..._.__._......__—....__—._...._._._._—.....__ . ~.._._..r.__

Q 005 0.1 0-15 (12 0.25 (13 0.35 Cl
Time

250
200
950

100
50

0
-50

.108
05. 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Tim®

Fig: 4.14 Performance of Speed(Rpm), Torque(N-m) with change in load

73
4.1.2 Third Harmonic Injection PWM
The inverter Line-to-Line voltage VAB can also be increased by adding a third harmonic
component to the three-phase sinusoidal modulating wave without causing over modulation.
Where the modulating wave is composed of a fundamental component and a third harmonic
component, making modulating wave somewhat flattened on the top.

Adds

Fig: 4.16 Control Scheme Block for Third Harmonic Injection SPWM

0.8

0.6

0.4

0.2

-0.2

.0.4

40.6

-0.8

Time

Fig:4.17 Third Harmonic Injection

74
 400

3w

sao

c
0
a

i00

200

300

a~0 0.1 02 0.3 0.4 0 5 0

Time

Fig: 4.17 Response of Stator Current Ia

In this case the motor was started with load 95 Nm and the reference speed was set to
1500RPM. When the speed reaches to steady state value, the winding current and the developed
torque equals to the set value of load. The performance of Induction Motor drive is shown in
below Figure 4.18 and fig 4.19, 4.20 shows the harmonic spectrum of line voltages and line
currents.

Time

0.2 0.3 0.4 0,5 0.6 02

Time

Fig: 4.18 Performance of Speed (Rpm), Torque (N-m) with load 95 N-rn

75
 :1 I i U
500 .li `;

i~ Y

-500

0.4
r'

0.41 0.42
`►,

0.43 0,44
F 0.45 0.46
Il 0.47 0.48 0.49
Time (s)
sis

Fundamental (50.1Hz) = 577.8 , THD= 26.09%

10

(U

E
1° 6
LL
V_
o Q

~ 2

1
U 5 10 15 20 25 30 35
Harmonic order

Fig: 4.20 Line Voltage (Volt) and Harmonic Spectrum

FFTwindow. 2 of 25 cycles of selected signal

0
-20
0.2 0.205 0.21 0.215 0.22 0.225 0.23 0.235
lime (s)

Fundamental (50Hz) = 23.92 , THD=16.55%

0 5 10 15 20 25 30 35 40
Harmonic order

Fig: 4.21 Current Wave form and Its Harmonic Spectrum

76
Performance with 40Hz Frequency
Performance Under this case the motor was started with load 95 Nm and the reference
speed was set to 1250 RPM. When the speed reaches to steady state value, the winding current
and the developed torque equals to the set value of load. The performance during this case the
torque and speed oscillates and it will take more time to reaches steady state. The performance
of Induction Motor during Loading Condition is shown in following Figs.
1400

1200

1000

E am
0 600

400

200

0 0.05 0.1 0.15 0.2 0,25 0.3 0.35 0.4

Time

300

200

E 100

r°- 0

-100

.200
0.05 0,1 0.15 0.2 0.25 0.3 0.35 0.4
Time

Fig: 4.22 Performance of Speed and torque with 40Hz supply

Step Change in Load

Motor is first started o no load with reference speed of 1500RPM. Starting torque will be
developed to accelerate the machine. Once the speed reaches to reference speed torque
developed also set to zero, at 0.3sec a load torque of 95 N-m is applied. Sudden application of
load on the rotor causes an instantaneous fall in the speed of motor. In response to this drop in
speed value, the output of the controller responds by increasing the reference speed value. So
developed torque increases and motor speed settles at steady value again, and winding current
will increase.

77
 2000

0 0.05 0.1 0.15 02 0.25 0.3 0.35 0.4

Time

U
100

.1

0.05
I 0.1 0.15 0,2
Time
0.25 0.3
I
0.35 0.4

Fig: 4.23 Variation of Speed (Rpm), Torque (N-rn) during Step Change in load

150

100

60

-.50

=1m

-150
Time

Fig: 4.24 Response in Stator Currents during step change in load

 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
lime
500

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0,05
time

] 0 am 0.01 0.015 0.02 0.025 0.03 0.035 0.04 OOmm 111

time

Fig: 4.26 Line to Line Voltages (Volts)

i I I I I I I I
1 0.05 0.1 0.15 0.2 0.25 0.3 0,35 0.4 0.45
Time

Fig: 4.27 Stator Currents (Amp) with load

W
1800.5

1600

1499.5

1499
0,2 04 0.6 0.8 1 1.2 1.4 1.6
15M

1000

800

.500 I I I
02 12.4 0.6 ((B 1 I 1) 11
200 I I

100

-100 I I
02 0,4 06 0.8 1
0,8
I I

0.6

0.4

0.2 014 ((0 00 1 11 11 0

Fig: 4.27 Performances of Speed (Rpm), Torque (N-m) and Flux with 1 0(N-m) load

1400 I I

1200

1000'

SW

600

0.2 03 0.4 0.5 0B 07 08 0.9

time

20

15

-5

Time

ig: 4.28 Performances of Speed and Torque with Supply Frequency 40Hz

81
 1500

1400

1300

1200

1100

1000
0.2 0.4 0.6 0.8 1 1.2 1.4 U
2000

1000

-1000
0 0.2 0.4 0.6 0.8 1 1.2 1,4 1.E

7 0.2 0.4 06 08 1 1.2 to t

7 0.2 0.4 0.6 0.8 1 i2 1 ti

Fig: 4.30 Response of Speed and Torque during Step Change in Speed .7 Sec

400
200
0
•200
•400
0.4 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0,48 0.49
Time-Est
sis
Fundamental (50.2Hz) = 368.6 , THD= 15.27%

rn 4

0 . !IIHIhI
2 4 6 a 10
Harmonic order
12 14 16 1B 20

Fig: 4.31 Line voltages and Harmonic Spectrum

82
 FFT window: 5 of 50.1 cycles of selected signal

-5

0.4 0.41 0.42 0.43 0.44 0.46 0.46 0.47 0.48 0.49
Time (s)

Fundamental (50.1 Hz) = 6.779 , THU= 4.06%

10

0
0 2 4 6 8 10 12 14 16 18
Harmonic order

Fig: 4.32 Line Currents and Harmonic Spectrum

Performance Comparison of Two Level Inverter fed IM Drive

The performance of two level inverter fed induction motor drive has been studied under different
modulation schemes and under different load and speed conditions. The Line Currents and Line
voltages Harmonic Spectrum is evaluated, by the comparison following conclusion have been
found by observing the steady state and dynamic characteristics.
A With different modulation technique the THD values are varies,
> Better harmonic spectrum has found in space vector modulation scheme the THD values
are very less as compared with sinusoidal pulse width modulation scheme.
➢ Lower order harmonics are almost absent in space vector modulation
> As Frequency is reduces it will take time to reach steady state value.
> The magnitude of ripple content in dynamic characteristic are reduces with desired THD
> Over all better dynamic and steady state performance are improved with space vector
modulation scheme

83
 ➢ Space vector modulation provides a more efficient use of the dc bus as well as smaller
torque ripple, lower switching loss and lower total harmonic distortion in an ac motor
drive application.
The THD% of Line Current and Line Voltages with different control schemes are shown below
table 4.1 and 4.2:

Line Current(A) SVM SPWM Third Harmonic Injection

Ia 4.06 18.99 16.55
Ib 4.10 18.86 16.42
Ic 3.98 19.07 16.61
Table: 4.1 Lines Current THD% for two level

Line Voltage(V) SVM SPWM Third Harmonic Injection

Vab 15.27 30.07 26.09

Vbc 15.21 30.12 25.96

Vca 15.16 30.23 26.14

Table: 4.2 Line Voltages THD% for two level

84
4.2 Three Level NPC Inverter fed Induction Motor Drive
4.2.1 Level Shift Multicarrier PWM
The generalized simulink block diagram three level NPC Inverter fed induction motor Drive is
shown in Fig 4.33 and control based of carrier based SPWM is Shown Fig 4.35, In control
Scheme carrier signals are Two In this case Unlike two level SPWM is shown in Fig 4.37.

Fig: 4.33 Generalized simulink block for Three Level NPC Inverter

,.5

0.5

-0.5

Time

Fig: 4.34 Two carrier signal with level shifted, with sinusoidal modulating wave

85
 rR,

Fig: 4.34 Control Scheme for Level Shift PWM

0.4

SOJ

XU

1W

0 ~'~,+,;~M" ~,Mnr.~w~,rnwvwwJ.~tirn+w.^'N+wvwwN+.+r+wNVr

700 .0......___._..._.__ W. 3.
0.A5 A.f 0.15 02 0.75 0.9 0.35. 0.4 .1345 0.

Fig: 4.35 Variation of Speed and Torque with no load

86
Performance with Load
In this case the motor was started with load 90 Nm and the reference speed was set to
1500RPM. When the speed reaches to steady state value, the winding current and the developed
torque equals to the set value of load.

59

5
im8

Fig: 4.36 Stator Currents with Load

e~. ruu

1500

1000

to
500

1 0.1 . 0.2 0.3 ' 0.4 0.5 0.5 0.7 0.8- 0.9 1
Time
300

250

200

150

100

6$
1 012 -t).3 0.4 0,5 0.6 0.7 0.6. 073 t
Time

Fig: 4.37 Performance of Speed (Rpm), Torque (N-m)

87
 400

100
L
C-)

100

..90

-300

Time

Fig: 4.40 Stator Currents Ia, Ib and Ic(Amp)

1400

1200

dr 000

c a 400

n.

000
X 400
:?t30

I 0.2 0.3 0.4 O.5 0.0 0.7 0.0 0.3

T.rn .

Fig: 4.41 Response of Torque(N-m) and Speed(Rpm) with 40Hz

Performance with Step change in Speed

Performance of drive during this case the motor was started with load 1000rpm and
When the speed reaches to steady state value, at 0.3 sec speed changes to 1500 rpm the winding
current and the developed torque equals to the set value of load. The performance during this
case the torque and speed oscillates and it will take more time to reaches steady state. The
performance of Induction Motor during Loading Condition is shown in following Fig 4.42

89
 I 000

000

` 100

~.. v.z 00 0.4 0 0B 0.7 0,0

Time

Fig: 4.42 Performance of speed and torque with change in speed at 0.3 sec

Step Change in Load

Motor is first started o no load with reference speed of 1500RPM. Starting torque will be
developed to accelerate the machine. Once the speed reaches to reference speed torque
developed also set to zero, at 0.3 sec a load torque of 90 N-m is applied. Sudden application of
load on the rotor causes an instantaneous fall in the speed of motor. In response to this drop in
speed value, the output of the controller responds by increasing the reference speed value. So
developed torque increases and motor speed settles at steady value again, and winding current
will increase.

-..:::_. _—...._ ...................................__..-_._.. -_..._..........

1ff /
F-
o~-
011
0 005 0.15 0.2 O.X 0.3 0m 0.a
Time
_.

400 A

0 0.05 "WW
0.1 0.75 0.3 025 0.3 0.35 0,4 0.45 0.5

Fig: 4.43 Performance of Speed (Rpm) and Torque (N-m) During Step Change in Load
 MMMMMMWW
1000

T--T-

Time

AAAAAAAAA'AAAAAI AAAAAAAAAAAAAAAAAAAAAAAA'd

u.i U.2 0.3 0.4 0.5 0.6 0.7 0.5 0.9

Time

Fig:,4.46 Line to Line Voltages (Volt)

2t013
. I

. ..--------.-..- .... -.... -

/
/1
(1

I I I I
8 005 0.1 815: 02 0.25 0.3 030 24 0.45 05

I I

0 005 (II 1110 02 ((2 030 94 0.45 cs

Tlim

Fig: 4.47 Performances of Speed and Torque on No Load condition

40

20

&b
-20

20 0 200 0 30 4) .300 4) 37 0.275 0 25 0 255 0.20 0 3 4) 3

Fig: 4. 48 Stator Currents with No Load

92
Performance of drive on full load
The performance in this case the motor was started with load 95 Nm and the reference speed
was set to 1500RPM. When the speed reaches to steady state value, the winding current and the
developed torque equals to the set value of load. The performance of Induction Motor drive is
shown in following Figures 4.49 and 4.50.

I I I I
0 A00 01 015 02 F, 133 0..313 Oa. 040 q,
101,4
!Q3 I
=

20A

too

t 0.G5 0.1 -0.15 0.2 11.20 0.9 0.36 0.4 0.45 0.6
lime.

Fig: 4.49 Performance of Speed and torque on Full Load

so
40

30

20

10

-10

-30

-40

F+g
.non

Fig: 4.50 Stator Currents with full Load

93
Step Change in Load
Motor is first started o no load with reference speed of 1500RPM. Starting torque will be
developed to accelerate the machine. Once the speed reaches to reference speed torque
developed also set to zero, at 0.5sec a load torque of 50N-m is applied. Sudden application of
load on the rotor causes an instantaneous fall in the speed of motor. In response to this drop in
speed value, the output of the controller responds by increasing the reference speed value. So
developed torque increases and motor speed settles at steady value again, and winding current
will increase.

Fig: 4.53 Stator Currents (Amp) changing when load Change after .3 Sec

0:2 0.9 7.4 0.5 0.0 07

TIm1

1 1
O.A C3.5 RF O

Fig: 4.54 Variations in Torque(N-m) and Flux(Wb) with Load

95
4.2.3 Space Vector Pulse Width Modulation for Three Level NPC Inverter
The space vector diagram of any three-phase n-level inverter consists of six sectors. Each
sector consists of (n — 1)2 triangles. The tip of the reference vector can be located within any
triangle. Each vertex of any triangle represents a switching vector. A switching vector represents
one or more switching states depending on its location. There are n3 switching states in the space
vector diagram of an n-level inverter. The SVM is performed by suitably selecting and executing
the switching states of the triangle for the respective on-times. The performance of the inverter
significantly depends on the selection of these switching states. The generalized Block Diagram
of three level NPC Inverter is Shown in Fig 4.55.

Fig 4.55 Generalized block diagram of Three level NPC Inverter

The following Algorithm is uses to generating switching control of Space Vector Modulation.
1. 3- sinusoidal voltage references are taken
2. Three phase A,B,C quantities transformed in to 2-phase equivalent quantities on
stationary reference frame.
3. The a-f3 quantities are converted to amplitude and angle form.
4. Based on 6 the sectors are chosen in hexagon.

96
 FFT window 15 of 50 cycles of selected signal

0.4 0.46 0.5 0.55 0.6 0.65

Time (s)
318

Fundamental (50Hz) = 7.124 , THL 3.77%

20

15
ro
a
U- 10

m 5

• 0 2 4 6 6 10 12 14 16 18 20
Harmonic order

Fig: 4.58 Line Current(amp) and HormonicSpectrum

FFT window: 15 of 50 cycles of selected signal
400
200
0
-200

0.4 0.45 0.5 0.55 0.6 0.65

Time (s)
is

Fundamental (50Hz) = 361,8 THD=10.92%

20

ro
15
ro
C
10

m 5
ro

0 L I 1 I } 1 1 1 1 1 1. i I. t L
0 4 6 8 10 12 14 16 18 20
Harmonic order

Fig:4.59 Line Voltage and Harmonic Spectrum

98
 Speed

__________
0.3 0.4 0.5 Os
Tr.uc:

EEI
I( I I

Ii 01 (1.2 03 0.4 05 06

ib
1001

1O) I I

0 01 0.2 03 OA C5 OAS

Fig: 4.60 Variations in Speed Torque and Current With No load

Performance with Load

In this case the motor was started with load and the reference speed was set to 1500RPM.
When the speed reaches to steady state value, the winding current and the developed torque
equals to the set value of load the variation of torque speed and currents shown in fig 4.61
Speed

0.1 0.2 0.3 0,4 0. 0.6

Torque

JIT
_02 03 "I 3
It

h CA 02 03 . H
ib
10

WV w
-10

H
n

WW
1 0.1 0.2 03 0.4 0.5 0,
Fig: 4.61 performance variation in speed and torque

99
Performance Comparison of Three Level NPC Inverter fed IM Drive
The performance of three level NPC inverter fed induction motor drive has been studied
under different modulation schemes and under different load and speed conditions. The Line
Currents and Line voltages Harmonic Spectrum is evaluated, by the comparison following
conclusion have been found by observing the steady state and dynamic characteristics.
➢ Comparison with conventional two level inverter, the line to line voltage level is
Increases by two steps thus it approaches to near sinusoidal wave.
➢ Line current is almost sinusoidal with very less in ripples.
➢ THD harmonic spectrum has found in space vector modulation scheme the THD values
are very less as compared with sinusoidal pulse width modulation scheme.
Lower order harmonics are almost absent in space vector modulation
➢ As Frequency is reduces it will take time to reach steady state value.
> The magnitude of ripple content in dynamic characteristic are reduces with desired THD
➢ Over all better dynamic and steady state performance are improved with space vector
modulation scheme
➢ Space vector modulation provides a more efficient use of the do bus as well as smaller
torque ripple, lower switching loss and lower total harmonic distortion in an ac motor
drive application.
➢ As number of levels is increases the synthesized output wave form adds a staircase
voltage levels which approaches a sinusoidal wave form with minimum harmonic
distortion.
> Ultimately Zero harmonic distortion of output wave form can be obtained by Infinite
number of levels.
The THD% of Line Current and Line Voltages with different control schemes are shown below
table 4.3 and 4.4:

Line Current(A) SVM SPWM Third Harmonic Injection

Ia 3.77 8.74 8.16

lb 3.68 8.56 8.24

Ic 3.61 8.68 8.19

Table: 4.3 Line Current THD%

100
 Line Voltage(V) SVM SPWM Third Harmonic Injection
Vab 10.92 18.72 16.59
Vbc 10.65 18.86 16.64
Vca 10.84 18.52 16.56
Table: 4.2 Line Voltage THD%

Voltage THDs
35
30
25
20
15 —svm
10 --spwm
5 —third har
0
2 3

levels

Fig: 4.62 Voltage THD variations vs Increasing in Levels with different modulation schemes

Current THDs
20
1s
16
14
12
v 10 —svm
P 8
6 —spwm
4 —third har
2
0
2 3

Levels

Fig: 4.63 Current THD variations vs. increasing in Levels with different modulation scheme

101
4.3 THD Variation with Frequency
The line Currents THD Variation with Frequency for two level and three level fed
induction motor drive are observed. The frequency varied over a range (30Hz to 60Hz) and as
frequency increases the THD values are get reduces , and finally we get Very low THD value
and drive performances are optimized. The Line Current Waveform and its harmonic Spectrum
Shown in Fig 4.64, 4.65 for SPWM, Third Harmonic Injection and SVM respectively. The
change in harmonic spectrum and THD was observed for frequency variation in range (30Hz to
60Hz) and the THD variation with frequency for 2-Level inverter fed Induction motor was
plotted, it shown below, observation the line current THD variation with frequency for two and
three level inverter fed IM drive was compared, and it is observed that THD variation of line
current is decreasing with frequency, it is significantly three level offers better results, which
means the lower frequency operation of drive is going to be very lossy and noisy as compared to
higher frequency operation, it means for lower frequency operation filters should be employed to
reduce the distortion. The improvement in the THD, from the lowest to highest frequency is high
in case of two level inverter as compared to Three Level NPC Inverter.

3-level
16
14
12
10
o 8
- Svm
6
4 —spwm
2 --third bar
0.
30 40 50 60

Frequency (Hz)

Fig: 4.64 THD Variation with frequency for different modulation schemes

102
 2-level
30

25

20

p 15 svm
10 spwm

5 third har

0
30 40 50 60

Frequency (Hz)

Fig: 4.65 THD Variation with frequency for different modulation schemes

4.4 Conclusion
In this chapter the steady state and dynamic performance of two level and three level NPC
inverter fed induction motor drive was observed under conditions of load torque, speed and
frequency. Line voltage and line current THD variation with different control schemes was
observed and their performance comparison has been made. Line current THD variation with
frequency curve has been plotted and it was observed that the frequency goes decreases then the
performance of motor drive becomes poor. The level of inverter increases the line current THD
decrease and the drive performance will be improved.
 CHAPTER 5
CONCLUSION and FUTURE SCOPE

The "multilevel converter" has drawn tremendous interest in the power industry to
overcome the problem associated with conventional two level PWM inverters The general
structure of the multilevel converter is to synthesize a sinusoidal voltage from several levels
of voltages, typically obtained from capacitor voltage sources. The so called "multilevel" starts
from three levels. The diode-clamp method can be applied to higher level converters. As the
number of levels increases, the synthesized output waveform adds more steps, producing a
staircase wave which approaches the sinusoidal wave with minimum harmonic distortion.
Ultimately, a zero harmonic distortion of the output wave can be obtained by an infinite
number of levels.
5.1 Conclusion
The performance of two level and three level NPC inverter was evaluated using sinusioda pulse
width modulation (SPWM) Technique, third harmonic injection Pulse Width Modulation, Space
Vector Pulse width modulation(SVPWM) technique. The effect of harmonic spectra and THD
has been evaluated for induction motor drive. It was observed that as the number of level
increases there is decrease in THD values in Line current and Line voltages. The pros and cons
iin going two levels to multilevel were illustratily presented. It is observed that the smaller
voltage steps lead to the production of higher power quality waveforms and also reduce the dv/dt
stresses on the load and reduce the electromagnetic compatibility (EMC) concerns and another
important feature of multilevel converters is that the semiconductors are wired in a series-type
connection, which allows operation at higher voltages. It is therefore concluded that with careful
designing of modules, the number of levels can be increased beyond three levels for a better
quality of output waveform.
The performance of multilevel inverters fed induction motor drive evaluated, the inverter
consider were two level inverter and three level NPC inverters. The steady state and dynamic
performance of the drive under different condition of load and speed has been compared. It was
observed that the steady state and dynamic response of three level NPC inverter has better
'performance over to two level inverter, also observed that level increases the performance of
drive increases . The THD variation with frequency was evaluated and it was found that there

104
was a large decrease in Current THD from the low to high frequency operation, which means the
low frequency drive operation is lossy and noisy compared to the high frequency operation. It
was observed the space-vector PWM method is an computation-intensive PWM method and is
possibly the best among all the PWM techniques because for a three phase inverter makes it
possible to adapt the switching behavior to different situations such as: half load, full load, linear
load, non-linear load, static load, pulsating load, etc and very low values can be reached for the
output voltage THD, robust dynamic response, the efficiency of the inverter can be optimized for
each load condition and SVM enables more efficient use of the DC voltage 15% more than
conventional PWM techniques.
5.2 Scope for Future Work
In this dissertat}on work performance is evaluated up to three level only, the work can be
extended to higher number of levels for future improvement in drive performance. In this work
scalar control technique was evaluate the performance of the induction motor drive. Though the
scalar control is simple to implement, it is gives poor drive performance. Hence superior control
technique like ector control, direct torque control can be used to improve the multilevel inverter
fed induction drive performances. The hardware implementation can be done up to certain level
of inverter keeping in mind the circuit and control complexities with increased level of inverter.

105
 REFERENCES

1. Nabe, A., Takahashi, I., and Akagi, H., A new neutral-point clamped PWM inverter,
IEEE Trans. Ind. App!., 17, 518, 1981.
2. S. Rizzo and N. Zargari, Medium Voltage Drives: What Does the Future Hold? The 4'"
International Power Electronics and Motional Control Conference (IPEMC), pp. 82-89,
2004.
3. H. Brunner, M. Hieholzer, et al., Progress in Development of the 3.5 kV High Voltage
IGBT/Diode Chipset and 1200A Module Applications, IEEE International Symposium
on Power Semiconductor Devices and IC's, pp. 225-228, 1997.
4. P. K. Steimer, H. E. Gruning, et al., IGCT—A New Emerging Technology for High
Power Low Cost Inverters, IEEE Industry Application Magazine, pp. 12-18, 1999.
5. R. Bhatia, H. U. Krattiger, A. Bonanini, et al_, Adjustable Speed Drive with a Single 100-
MW Synchronous Motor, ABB Review, No. 6, pp. 14-20, 1998.
6. W. C. Rossmann and R. G. Ellis, Retrofit of 22 Pipeline Pumping Stations with 3000-hp
Motors and Variable-Frequency Drives, IEEE Transactions on Industry Applications,
Vol. 34, Issue: 1, pp. 178-186, 1998.
7. R. Menz and F. Opprecht, Replacement of a Wound Rotor Motor with an Adjustable
Speed Drive for a 1400 kW Kiln Exhaust Gas Fan, The 44th IEEE IAS Cement Industry
Technical Conference, pp. 85-93, 2002.
8. B. P. Schmitt and R. Sommer, Retrofit of Fixed Speed Induction Motors with Medium
Voltage Drive Converters Using NPC Three-Level Inverter High-Voltage IGBT Based
Topology, IEEE International Symposium on Industrial Electronics, pp. 746-751, 2001.
9. S. Bernert, Recent Development of High Power Converters for Industry and Traction
Applications, IEEE Transactions on Power Electronics, Vol. 15, No. 6, pp. 1102-
1117,2000.
10. H. Okayama, M. Koyama, et al., Large Capacity High Performance 3-level GTO Inverter
System for Steel Main Rolling Mill Drives, IEEE Industry Application Society (IAS)
Conference, pp. 174-179, 1996.
11. N. Akagi, Large Static Converters for Industry and Utility Applications, IEEE Proceed-
ings, Vol. 89, No. 6, pp. 976-983, 2001.

106
12.R. A. Hanna and S. Randall, Medium Voltage Adjustable Speed Drive Retrofit of an Ex
isting Eddy Current Clutch Extruder Application, IEEE Transaction on Industry
Applications, Vol. 33, No. 6, pp. 1750-1755.
13.Tenconi, S. M., Carpita, M., Bacigalupo, C., and Cali, R., Multilevel voltage source
converter for medium voltage adjustable speed drives, in Proc. ISLE, IEEE, Athens, 1995,
91.
14.Osman, R. H., A medium-voltage drive utilizing series-cell multilevel topology for
outstanding power quality, in Proc. MS, IEEE, Phoenix, 1999, 2662.
15.Mahfouz, A., Holtz, J., and El-Tobshy, A., Development of an integrated high-voltage 3-
level converter inverter system with sinusoidal input-output for feeding 3-phase induction
motors, in Proc. 5th European Conference on Power Electronics and Applications,
Brighton, U.K., 1993, 134.
16.Seki, N. and Uchino, H., Converter configurations and switching frequency for a GTO
reactive power compensator, IEEE Trans. Ind. Appl., 33, 1011, 1997.
17.Chen, Y., Mwinyiwiwa, B., Wolanski, Z., and Ooi, B. T., Regulating and equalizing DC
capacitive voltages in multilevel statcom, IEEE Trans. Power Delivery, 12, 901, 1997.
18.Hatziadoniu, C. J. and Chalkiadakis, F. E., A 12-pulse static synchronous compensator
for the distribution system employing the 3-level GTO-inverter, IEEE Trans. Power
Delivery, 12, 1830, 1997.
19.Nakata, K., Nakamura, K., and Ito, S., A three-level traction inverter with IGBTS for
EMU, in Proc. IAS, IEEE, Denver, 1994, 667.
20. Willkinson, R. H., Horn, A., and Enslin, J. H. R., Control options for a bi-directional
multilevel traction chopper, in Proc. PESO IEEE, Maggiore, 1996, 1395.
21. Lyons, J. P., Vlatkovic, V., Espelage, P. M., Boettner, F. H., and Larsen, E., Innovation
IGCT main drives, in Proc. LIS, IEEE, Phoenix, 1999, 2655.
22. J. Rodriguez, J. S. Lai, and F. Z. Peng, "Multilevel inverters: A survey of topologies,
controls, and applications," IEEE Trans. Ind Electron vol. 49, no. 4, pp. 724-738, Aug.
2002.
23. J. S. Lai and F. Z. Peng, "Multilevel converters—A new breed of power converters," IEEE
Trans. Ind. Applicat., vol. 32, pp. 509-517,May/June 1996.

107
24. T. A. Meynard and H. Foch, "Multi-level choppers for high voltage applications," Eur.
Power Electron. Drives J., vol. 2, no. 1, P. 41, Mar.1992.
25. C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, "Comparison of multilevel inverters
for static var compensation," in Conf. Rec. IEEE-L4SAnnu. Meeting, Oct. 1994, pp. 921-
928.
26. P. Hammond, "A new approach to enhance power quality for medium voltage ac drives,"
IEEE Trans. Ind. Applicat., vol. 33, pp. 202-208, Jan./Feb. 1997.
27. E. Cengelci, S. U. Sulistijo, B. O. Woom, P. Enjeti, R. Teodorescu, and F. Blaabjerge, "A
new medium voltage PWM inverter topology for adjustable speed drives," in Conf. Rec.
IEEE-L4SAnnu.Meeting, St. Louis, MO, Oct. 1998, pp. 1416-1423.
28. R. H. Baker and L. H. Bannister, "Electric power converter," U.S. Patent3 867 643, Feb.
1975.
29. R. H. Baker, "Switching circuit," U.S. Patent 4 210 826, July 1980.
30. P.W.Hammond, "Mediumvoltage PWMdrive andmethod,"U.S. Patent 5 625 545, Apr.
1997.
31. F. Z. Peng and J. S. Lai, "Multilevel cascade voltage-source inverter with separate DC
sources," U.S. Patent 5 642 275, June 24, 1997.
32. P.W.Hammond, "Four-quadrant AC-AC drive andmethod," U.S. Patent 6 166 513, Dec.
2000.
33. M. F. Aiello, P. W. Hammond, and M. Rastogi, "Modular multi-level adjustable supply
with series connected active inputs," U.S. Patent 6 236 580, May 2001.
34. J. P. Lavieville, P. Carrere, and T. Meynard, "Electronic circuit for converting electrical
energy and a power supply installation making use thereof," U.S. Patent 5 668 711, Sept.
1997.
35. T. Meynard, J.-P. Lavieville, P. Carrere, J. Gonzalez, and O. Bethoux, "Electronic circuit
for converting electrical energy," U.S. Patent 5 706 188, Jan. 1998.
36. Masato Koyama, Toshiyuki Fuzzi, Ryohei Uchida, Takao Kawabata, "Space Voltage
Vector-Based New PWM Method for Large Capacity Three-Level GTO Inverter" ," in
Conf. Rec. IEEE-L4SAnnu.Meeting, St. Louis, MO, Oct. 1998, pp.
37. Annette von Jouanne, Shaoan Dai, Haoran Zhang "A Multilevel Inverter Approach
Providing DC —Link Balancing, Ride — Through Enhancement, and Common-Mode
Voltage Elimination" ,IEEE Trans. Ind. App!., 25, 1011, 1997.
38. Sun-Kyoung Lim, Jun-Ha Lim and Kwanghee Nam " A DC-Link Voltage Balancing
Algorithm for 3-Level Converter Using the Zero Sequence Current", in Proc. L4S, IEEE,

108
 Phoenix, 1999, 4695. IEEE transactions on industrial electronics, vol. 53, no. 5, october
2006
39. Amit Kumar Gupta, Student Member, IEEE, and Ashwin M. Khambadkone, Senior
Member, IEEE "A Space Vector PWM Scheme for Multilevel Inverters Based on Two-
Level Space Vector PWM" IEEE transactions on industrial electronics, vol. 53, no. 5,
october 2006.
40. Yo-Lan Lee, Bum-Seok, Dong-Seok Hyun in their publication [7] titles "A Novel PWM
Scheme for a Three-Level Voltage Inverter with GTO Thyristors" IEEE Trans. Ind.
Appl., 85, 6511, 1990
41. Hyo L. Liu, Nam S. Choi and Gyu H. Cho in their publication [5] titled "DSP based
Space Vector PWM for Three Level Inverter with DC-Link voltage balancing", IEEE
Trans. Ind Applicat., vol. 33, pp. 202-208, Jan./Feb. 2001.
42. Texas instruments application note no. SPRA248a [4] titles "AC Induction Motor Control
Using Constant V/HZ Principle and Space Vector PWM Technique with TMS320C240"

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 APPENDIX
Specifications of Three Phase Squirrel Cage Induction Motor

Rated Voltage 400 V

Rated Frequency 50 Hz

Power Output 15 KW

Rated Speed 1460 RPM

No. of Poles 4

Stator resistance per phase 0.2147 ohm

Rotor resistance per phase 0.2205 ohm

(stator referred)
Stator leakage inductance per phase 0.000991 Henry

Rotor leakage inductance per phase 0.000991 Henry

(stator referred)
Mutual inductance per phase 0.06419Henry

Moment of Inertia, J 0.102 Kg.m2

110