Vietnamese-German University (VGU)

Design Project
ECE Module 61ECE114: Engineering Design
Winter Semester 2023/24 Lecturer: Udo Klein
Date: 7th January 2024 Signature:
Place: homework
Deadline: 15th January 2024
No. of design problems: 1
No. of points: 100

Declaration
I hereby declare that I have read and understood the examination rules on the reverse
page and I have done the design project myself using permitted tools only. I am aware
that failure to observe the examination rules is considered as cheating and will result in a
“failed” exam. I understand that the design report needs to be submitted to the examiner
before the deadline of the design project.

Family Name:

Middle Name:

Given Name:

VGU Student ID:

I have read and understood the “Declaration” above.

Date:

Turn the page please.

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 Vietnamese-German University (VGU)

Please read the following design project examination rules carefully!

• This design project is one part of four design projects for the Engineering Design
module.

• This is an open-book assignment. You are allowed to use textbooks, tutorials, and
any other resources.

• You are not allowed to submit any simulation results and/or printouts that
were created by somebody other than you. To pass off somebody else’s work as
your own is considered plagiarism and is not tolerated.

• All simulations that you need to perform for the Spice design project should be done
by using the LTSpice XVII simulation software.

• The deliverable for your design project is a design report in a single pdf file. The
first section of your report needs to show the circuit schematics as you created it in
LTSpice. The following chapters need to provide the circuit analysis and simulation
results as requested in the parts (and subparts) of the problem statement of the
design problem(s).

• Both the circuit schematics and the simulation graphs are to be created either by
printing the corresponding LTSpice window to pdf output files or by taking suitable
high-quality and appropriately cropped screenshots. Please use a white background
colour and appropriate font sizes and line thicknesses. All these parameters can be
configured in the Control Menu under Tools. Examples of good layouts are shown
in the Appendix.

• The Spice design project will be evaluated on

(a) technical content (80%)

(b) report quality (20%).

• Please remember to add the filled-in cover sheet as the first page of your re-
port in pdf format. You can directly fill in the pdf form with any pdf viewer that
supports form elements and document level JavaScript, such as Acrobat Reader. Al-
ternatively, you can either annotate the cover page or fill in the information manually
and scan in the page.
Free tools such as PDFtk can be used to extract pages, join and manipulate pdf
files.

• Please submit your design report to the examiner via the VGU Moodle course
web site at https://moodle.vgu.edu.vn/ no later than 6:00pm on the day of
the deadline. No late submissions of the design report will be accepted.
The file name of your uploaded design report needs to be as follows:

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 Vietnamese-German University (VGU)

<DPSpice_##### (family name, middle name(s), given name).pdf>, where

##### is to be replaced by your student ID number.
Example for design report file name: DPSpice_12345 (Nguyen Dung Tien).pdf

Turn the page please.

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Engineering Design Design Project WS 2023/24

Design Problem 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 points

Astable multivibrators, also known as oscillators, are electronic circuits designed to
continuously produce a square wave or rectangular waveform without the need for an
external triggering signal. These circuits are characterized by their ability to oscillate
between high and low states indefinitely, creating a pulsating output signal.
The astable multivibrator is a type of relaxation oscillator, relying on the charging
and discharging of capacitors through resistors to generate the oscillatory behaviour.
Unlike monostable and bistable multivibrators, astable circuits have no stable states;
instead, they continually switch between two quasi-stable states.
Key components in an astable multivibrator include resistors, capacitors, and tran-
sistors. The interaction between these components determines the frequency and
duty cycle of the output waveform. Astable multivibrators find widespread applic-
ation in generating clock signals, timekeeping circuits, and various pulsating signal
sources within electronic systems. Their simplicity and versatility make them valuable
building blocks in electronic design and circuitry.

470 Ω R3 47 kΩ R1 R2 47 kΩ R4 470 Ω
VCC +
− 9V

LED1 C2 C1 LED2
out
10 µF 10 µF

BC547B BC547B
Q1 Q2

Use LTSpice to analyze the astable multivibrator circuit provided above and write
a design report with your numerical and graphical results, addressing the following
questions:
(a) Create the LTSpice Schematic of the astable multivibrator circuit. 15 pts.
• Use the default built-in transistor model for the BC547B bipolar transistor.
• Provide a power supply of 9 V to the circuit.
Show your LTSpice schematic of the astable multivibrator circuit.
(b) Amplitude of Output Waveform 15 pts.
• Conduct transient analysis to observe the circuit’s output waveform and
measure its peak-to-peak amplitude.
• Utilize the .MEASURE directive to reliably identify maxima and minima of the
waveform.

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Engineering Design Design Project WS 2023/24

• Plot a trace of the output waveform over a time duration of 3 s.

• Discuss the relationship between the output signal and the LEDs in the
circuit. Plot the LED currents to investigate the ON/OFF states of the
LED.
(c) Frequency of Oscillation 20 pts.
• Determine the period and the frequency of the output waveform. Use the
.MEASURE directive to analyze the output waveform.
Note: In a real circuit, the start of the oscillation occurs randomly. Use
appropriate parameters for the “Time to start saving data:” and the
“Start external DC supply voltages at 0V:” parameters in your sim-
ulation command. Furthermore, consider neglecting the first cycle(s) of the
output waveform to avoid nonperiodic behaviour during startup.
• Simulate the multivibrator circuit with different capacitor values for C1 and
C2 . What are the frequencies of the oscillations with both capacitors being
4.7 µF and 20 µF, respectively?
• Simulate the multivibrator circuit with different resistor values for R1 and
R2 . What are the frequencies of the oscillations with both resistors R1 and
R2 being 22 kΩ and 100 kΩ, respectively?
• Discuss the relationship between frequency, resistance, and capacitance.
(d) Duty Cycle 20 pts.
• Simulate the multivibrator circuit and measure the duty cycle of the output
waveform. Use the .MEASURE directive to determine the duty cycle.
Note: The duty cycle of a square wave is the ratio of the duration the
waveform is in the high state (ON) to the total period of one cycle, expressed
as a percentage.
• Vary the component value of C2 and observe the effect on the duty cycle.
What are the duty cycles and the frequencies of the oscillations with C2
being 4.7 µF and 15 µF, respectively (keeping the value of C1 = 10 µF)?
• Discuss how to achieve a desired duty cycle and the trade-offs involved.
(e) Rise- and Fall-Time Analysis 20 pts.
• Analyze the rise- and fall-time of the circuit’s output waveform.
Note: The rise-and fall-time of a square wave refers to the time it takes for
the signal to transition between the 10 % and 90 % amplitude points during
the rising and falling edges, respectively.
• Simulate the multivibrator circuit with different resistor values for R3 and
R4 . What are the rise- and fall-times of the square wave with both resistors
R3 and R4 being 220 Ω, 470 Ω, 2.2 kΩ, and 4.7 kΩ, respectively?
• Discuss your observations regarding rise- and fall-times of the multivibrator
circuit.
(f) Design 10 pts.
• Design a multivibrator circuit with an oscillation frequency of 2.0 Hz (±10 %),
a duty cycle between 20 % and 25 %, and a rise-time of less than 10 ms.

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Engineering Design Design Project WS 2023/24

Keep component values of the given circuit as much as possible unchanged.

Only use component values of the E12 series (EIA-96 standard). Plot a
trace of the output waveform over a time duration of 3 s.

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Engineering Design Design Project WS 2023/24

Appendix - Examples of LTSpice Output

R10 K1 L1 L2 1
D1
48k OUT1
Q2 L1 L2 2µH 1N5817 C4 R5
2N2222 50µH
D2 5
10µ

BZX84C8V2L C5

Vcc
IN

10µ
V1
C1 R1
24
Vin
100p 51k
Run/SS SW
U1
G
Iprg Gate R9
Q1 16k
C2 R3 LTC3872 Si3460DV
Ith FB
4700p 6.81K GND R6
100m

.tran 2m startup

--- D:\WorkingDirectories\Spice\examples\LTC3872_flyback_converter.asc ---

Circuit schematics of flyback converter.

V(out1)
5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

1.5V

1.0V

0.5V

0.0V

-0.5V
0.0ms 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
--- D:\WorkingDirectories\Spice\examples\LTC3872_flyback_converter.raw ---

Transient of output voltage vout (t) after start up.

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