Chap - 4

Micro-programmed control
 Looping
Outline
• Control Memory
• Address Sequencing
• Micro-instruction Code Format
• General Register Organization
• Stack Organization
• Instruction format
• Addressing Modes
• Data transfer and manipulation
• Program Control
• Reduced Instruction Set Computer (RISC)
• Complex Instruction Set Computer (CISC)
Section - 1
Control Memory

1 CONTROL MEMORY
Hardwire Control vs. Microprogrammed Control :
• The function of the control unit in a digital computer is to initiate sequences
of microoperations, The number of different types of microoperations that are
available in a given system is finite. The complexity of the digital system is
derived from the number of sequences of microoperations that are performed.
• When the control signals are generated by hardware using conventional logic
design techniques, the control unit is said to be hardwired.
• Microprogramming is a second alternative for designing the control unit of a
digital computer. The principle of microprogramming is an elegant and
systematic method for controlling the microoperation sequences in a digital
computer.
Control Memory

• Hardwired
Memory Instruction code

Combinational . Control
Sequence Counter
Logic Circuits . signals

• Microprogrammed
CAR: Control Address Register
Memory Instruction code CDR: Control Data Register

Next Address . Control

Control CDR Decoding
Generator CAR .
Memory Circuit signals
(sequencer)
Control Memory

Microprogrammed Control :
• The control unit initiates a series of sequential steps of microoperations. During any given
time, certain microoperations are to be initiated, while others remain idle. The control
variables at any given time can be represented by a string of l's and 0’s called a control
word. As such, control words can be programmed to perform various operations on the
components of the system.
• A control unit whose binary control variables are stored in memory is called a
microprogrammed control unit.
• Each word in control memory contains within it a microinstruction.
• The microinstruction specifies one or more microoperations for the system.
• A sequence of microinstructions constitutes a microprogram. Since alterations of the
microprogram are not needed once the control unit is in operation, the control memory can
be a read-only memory (ROM).
Control Memory

Advantages of Microprogrammed Control :

• The main advantage of the microprogrammed control is the fact that once the
hardware configuration is established, there should be no need for further hardware
or wiring changes.

• If we want to establish a different control sequence for the system, all we need
to do is specify a different set of microinstructions for control memory.

• The hardware configuration should not be changed for different operations; the only
thing that must be changed is the microprogram residing in control memory.
Control Memory

Hardwire Control :
• It should be mentioned that most computers based on the reduced instruction set
computer (RISC) architecture concept use hardwired control rather than a
control memory with a microprogram.
Control Memory
 A computer that employs a microprogrammed control unit will have two separate memories: a
main memory and a control memory.

 The control memory holds a fixed microprogram that can not be altered by the occasional user.

 The microprogram consists of microinstructions that specify various internal control signals
for execution of register microoperation.

 Microinstructions generates the microoperations to fetch instruction from main memory; to

evaluate the effective address, to execute the operation specified by the instruction, and to
return control to the fetch of next instruction.
Microprogrammed Control Organization

External Control
input word
Next-
Control Control Control
address
address memory data
generator
register (ROM) register
(Sequencer)

Next-address information
Control Memory

Control Memory :
• The content of the words in ROM are fixed and cannot be altered by simple
programming since no writing capability is available in the ROM. ROM words are
made permanent during the hardware production of the unit. The use of a
microprogram involves placing all control variables in words of ROM for use by the
control unit through successive read operations. The content of the word in ROM at
a given address specifies a microinstruction.
• A more advanced development known as dynamic microprogramming permits a
microprogram to be loaded initially from an auxiliary memory such as a magnetic
disk. Control units that use dynamic microprogramming employ a writable control
memory. This type of memory can be used for writing (to change the microprogram)
but is used mostly for reading. A memory that is part of a control unit is referred
to as a control memory.
Control Memory

Main Memory vs. Control Memory :

• A computer that employs a microprogrammed control unit will have two separate
memories: a main memory and a control memory. The main memory is available
to the user for storing the programs. The contents of main memory may alter
when the data are manipulated and every time that the program is changed. The
user's program in main memory consists of machine instructions and data.
• In contrast, the control memory holds a fixed microprogram that cannot be altered
by the occasional user. The microprogram consists of microinstructions that specify
various internal control signals for execution of register microoperations. Each
machine instruction initiates a series of microinstructions in control memory. These
microinstructions generate the microoperations to fetch the instruction from main
memory; to evaluate the effective address, to execute the operation specified by the
instruction, and to return control to the fetch phase in order to repeat the cycle for the
next instruction.
Control Memory
Control Address Register :
• Control memory address register specifies the address of the microinstruction, and the
control data register holds the microinstruction read from memory. The
microinstruction contains a control word that specifies one or more microoperations for
the data processor. Once these operations are executed, the control must determine the
next address. The location of the next microinstruction may be the one next in
sequence, or it may be located somewhere else in the control memory.
• For this reason it is necessary to use some bits of the present microinstruction to control
the generation of the address of the next microinstruction. The next address may also be
a function of external input conditions. While the microoperations are being
executed, the next address is computed in the next address generator circuit and then
transferred into the control address register to read the next microinstruction. Thus a
microinstruction contains bits for initiating microoperations in the data processor
part and bits that determine the address sequence for the control memory.
Control Memory

Sequencer :
• The next address generator is sometimes called a microprogram sequencer, as it
determines the address sequence that is read from control memory. The address
of the next microinstruction can be specified in several ways, depending on the
sequencer inputs.

• Typical functions of a microprogram sequencer are incrementing the control address

register by one, loading into the control address register an address from control
memory, transferring an external address, or loading an initial address to start the
control operations.
Control Memory

Pipeline Register :

• The control data register holds the present microinstruction while the next address
is computed and read from memory. The data register is sometimes called a
pipeline register.

• It allows the execution of the microoperations specified by the control word

simultaneously with the generation of the next microinstruction.

• This configuration requires a two-phase clock, with one clock applied to the address
register and the other to the data register.
Control Memory
Non-pipeline Microprogrammed Control :
• The system can operate without the control data register by applying a single-
phase clock to the address register.
• The control word and next-address information are taken directly from the control
memory. It must be realized that a ROM operates as a combinational circuit, with the
address value as the input and the corresponding word as the output.
• The content of the specified word in ROM remains in the output wires as long as its
address value remains in the address register. No read signal is needed as in a random-
access memory. Each dock pulse will execute the microoperations specified by the
control word and also transfer a new address to the control address register. In the
example that follows we assume a single-phase clock and therefore we do not use a
control data register.
• In this way the address register is the only component in the control system that
receives dock pulses. The other two components: the sequencer and the control
memory are combinational circuits and do not need a dock.
Section - 2
Address Sequencing
 Microinstructions are stored in control memory in groups, with each group specifying a routine.
 The transformation from the instruction code bits to an address in control memory where the
routine is located is referred to as a mapping process.
 The address sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.
Address Sequencing
Instruction code

Mapping
logic

Status Branch Mux

bits Multiplexer
logic select
Subroutine
register
(SBR)
Clock
Control address register
(CAR)
Incrementer

Control memory

Select a status bit

Branch address
Microoperations
Address Sequencing
 Routine : Microinstructions are stored in control memory in groups, with each group
specifying a routine.
 Boot Computer : An initial address is loaded into the control address register when
power is turned on in the computer.
 Mapping : The transformation from the instruction code bits to an address in control
memory where the routine is located is referred to as a mapping process.
 Special Bits : The branch logic provides decision-making capabilities in the control
unit. The status conditions are special bits in the system that provide parameter
information such as the carry-out of an adder, the sign bit of a number, the mode bits of
an instruction, and input or output status conditions.
 Branch Logic : The branch logic hardware may be implemented in a variety of
ways. The simplest way is to test the specified condition and branch to the
indicated address if the condition is met; otherwise, the address register is incremented.
Address Sequencing
 Branch Logic : Unconditional Branch:- An unconditional branch microinstruction
can be implemented by loading the branch address from control memory into the
control address register.
 Mapping Logic : A special type of branch exists when a microinstruction specifies
a branch to the first word in control memory where a microprogram routine for an
instruction is located.
 Mapping Example :
Address Sequencing
 Mapping ROM : The contents of the mapping ROM give the bits for the control
address register. In this way the microprogram routine that executes the instruction can
be placed in any desired location in control memory.
 Mapping ROM Implementation : The mapping function is sometimes implemented
by means of an integrated circuit called programmable logic device or PLD. A PLD is
similar to ROM in concept except that it uses AND and OR gates with internal
electronic fuses. The interconnection between inputs, AND gates, OR gates, and
outputs can be programmed as in ROM. A mapping function that can be expressed in
terms of Boolean expressions can be implemented conveniently with a PLD.
 Subroutines : Subroutines are programs that are used by other routines to accomplish
a particular task. A subroutine can be called from any point within the main body of the
microprogram.
 Subroutine Register : Microprograms that use subroutines must have a provision for
storing the return address during a subroutine call and restoring the address during a
subroutine return.
Section - 3
Section - 3
Micro-instruction Code Format

3 3 3 2 2 7
F1 F2 F3 CD BR AD

 F1, F2, F3: Microoperation fields

 CD: Condition for branching
 BR: Branch field
 AD: Address field
Symbols & Binary Code for Microinstruction Fields

F1 Microoperation Symbol F2 Microoperation Symbol

000 None NOP 000 None NOP
001 AC AC + DR ADD 001 AC AC - DR SUB
010 AC 0 CLRAC 010 AC AC DR OR
011 AC AC + 1 INCAC 011 AC AC DR AND
100 AC DR DRTAC 100 DR M[AR] READ
101 AR DR(0-10) DRTAR 101 DR AC ACTDR
110 AR PC PCTAR 110 DR DR + 1 INCDR
111 M[AR] DR WRITE 111 DR(0-10) PC PCTDR
Symbols & Binary Code for Microinstruction Fields
F3 Microoperation Symbol
000 None NOP
001 AC AC + DR XOR CD Symbol Comments
010 AC AC’ COM 00 U-1 Unconditional branch
011 AC shl AC SHL 01 I - DR(15) Indirect address bit
100 AC shr AC SHR 10 S - AC(15) Sign bit of AC
101 PC PC + 1 INCPC 11 Z - AC = 0 Zero value in AC
110 PC AR ARTPC
111 Reserved

BR Symbol Function
00 JMP CAR AD if condition = 1, CAR CAR+1 if condition = 0
01 CALL CAR AD, SBR CAR+1 if condition=1, CAR CAR+1 if condition=0
10 RET CAR SBR (Return from subroutine)
11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0
Section - 4
 Clock Input

R1
R2
R3
R4
R5
R6
R7

Load
(7 lines) SEL A MUX - A MUX - B SEL B

3x8 A - bus B - bus

decoder

Arithmetic Logic Unit

OPR
SEL D (ALU)

Output
General Register Organization
 Example: R1 R2 + R3
 To perform the above operation, the control must provide binary selection variables to the
following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output bus into R1.

 Control Word:

SELA SELB SELD OPR

General Register Organization
OPR Select Operation Symbol
00000 Transfer A TSFA
Binary
SELA SELB SELD 00001 Increment A INCA
Code
000 Input Input None 00010 A+B ADD
001 R1 R1 R1 00101 A–B SUB
010 R2 R2 R2 00110 Decrement A DECA
011 R3 R3 R3 01000 A and B AND
100 R4 R4 R4 01010 A or B OR
101 R5 R5 R5 01100 A xor B XOR
110 R6 R6 R6 01110 Complement A COMA
111 R7 R7 R7 10000 Shift right A SHRA
11000 Shift left A SHLA
Encoding of Register Selection Fields
Encoding of ALU Operations
Section - 5
Stack Organization
 A stack is a storage device that stores information in such a manner that the item stored last is
the first item retrieved (LIFO).
 The register that holds the address for the stack is called a stack pointer (SP) because its
value always points at the top item in the stack.
 The physical registers of a stack are always available for reading or writing. It is the content of
the word that is inserted or deleted.
 There are two types of stack organization
1. Register stack – built using registers
2. Memory stack – logical part of memory allocated as stack
Register Stack
 PUSH Operation Address

63
SP ← SP + 1
FULL EMTY
M[SP] ← DR
IF (SP= 0) then (FULL ← 1)
EMTY ← 0

 POP Operation 4
SP C 3
DR ← M[SP] 2
B
SP ← SP - 1 A 1
0
IF (SP= 0) then (EMTY ← 1)
FULL ← 0 DR
Register Stack
 A stack can be placed in a portion of a large memory or it can be organized as a collection of a
finite number of memory words or registers. Figure shows the organization of a 64-word
register stack.
 The stack pointer register SP contains a binary number whose value is equal to the address of
the word that is currently on top of the stack.
 In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
 Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary).
 The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is set
to 1 when the stack is empty of items.
 DR is the data register that holds the binary data to be written into or read out of the stack.
Memory Stack
Address
 PUSH Operation
PC Program 1000
SP ← SP - 1 (instructions)
AR Data 2000
M[SP] ← DR (operands)
3000
 POP Operation Stack

3997
DR ← M[SP]
SP 3998
SP ← SP + 1
3999
4000
4001

DR
Memory Stack
 The implementation of a stack in the CPU is done by assigning a portion of memory to a stack
operation and using a processor register as a stack pointer.
 Figure shows a portion of computer memory partitioned into three segments: program, data,
and stack.
 The program counter PC points at the address of the next instruction in the program which is
used during the fetch phase to read an instruction.
 The address registers AR points at an array of data which is used during the execute phase to
read an operand.
 The stack pointer SP points at the top of the stack which is used to push or pop items into or
from the stack.
 We assume that the items in the stack communicate with a data register DR.
Reverse Polish Notation
 The common mathematical method of writing arithmetic expressions imposes difficulties when
evaluated by a computer.
 The Polish mathematician Lukasiewicz showed that arithmetic expressions can be represented
in prefix notation as well as postfix notation.

Infix Prefix or Polish Postfix or Reverse

Polish
A+B + AB AB +

A*B+C*D AB * CD * +
Reverse Polish
Evaluation of Arithmetic Expression

(3 * 4) + (5 * 6) 34*56*+ 42

4 5 5 30

3 3 12 12 12 12 42

3 4 * 5 6 * +
Section - 6
Instruction Formats
 Instructions are categorized into different formats with respect to the operand fields in the
instructions.
1. Three Address Instructions
2. Two Address Instruction
3. One Address Instruction
4. Zero Address Instruction
5. RISC Instructions
Three Address Instruction
 Computers with three-address instruction formats can use each address field to specify either
a processor register or a memory operand.
 The program in assembly language that evaluates X = (A + B) * (C + D) is shown below.
ADD R1, A, B R1← M[A]+ M[B]
ADD R2, C, D R2← M[C]+ M[D]
MUL X, R1, R2 M[X]← R1 * R2
 The advantage of three-address format is that it results in short programs when evaluating
arithmetic expressions.
 The disadvantage is that the binary-coded instructions require too many bits to specify three
addresses.
Two Address Instruction
 Two address instructions are the most common in commercial computers. Here again each
address field can specify either a processor register or a memory word.
 The program to evaluate X = (A + B) * (C + D) is as follows:

MOV R1, A R1← M[A]

ADD R1, B R1← R1+ M[B]
MOV R2, C R2← M[C]
ADD R2, D R2← R2+ M[D]
MUL R1, R2 R1← R1 * R2
MOV X, R1 M[X]← R1
One Address Instruction
 One address instructions use an implied accumulator (AC) register for all data manipulation.
 For multiplication and division these is a need for a second register.
 However, here we will neglect the second register and assume that the AC contains the result
of all operations.
 The program to evaluate X = (A + B) * (C + D) is

LOAD A AC← M[A]

ADD B AC← AC+M[B]
STORE T M[T]←AC
LOAD C AC← M[C]
ADD D AC← AC+M[D]
MUL T AC← AC*M[T]
STORE X M[X]←AC
Zero Address Instruction
 A stack-organized computer does not use an address field for the instructions ADD and MUL.
 The PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack.
 The program to evaluate X = (A + B) * (C + D) will be written for a stack-organized computer.
 To evaluate arithmetic expressions in a stack computer, it is necessary to convert the
expression into reverse polish notation.
PUSH A TOS← M[A]
PUSH B TOS← M[B]
ADD TOS←(A+B)
PUSH C TOS← M[C]
PUSH D TOS← M[D]
ADD TOS←(C+D)
MUL TOS←(C+D)*(A+B)
POP X M[X] ← TOS
RISC Instruction
 The instruction set of a typical RISC processor is restricted to the use of load and store
instructions when communicating between memory and CPU.
 All other instructions are executed within the registers of the CPU without referring to memory.
 A program for a RISC type CPU consists of LOAD and STORE instructions that have one memory
and one register address, and computational-type instructions that have three addresses with
all three specifying processor registers.
 The following is a program to evaluate X = (A + B) * (C + D)
LOAD R1, A R1← M[A]
LOAD R2, B R2← M[B]
LOAD R3, C R3← M[C]
LOAD R4, D R4← M[D]
ADD R1, R1, R2 R1← R1+R2
ADD R3, R3, R4 R3← R3+R4
MUL R1, R1, R3 R1← R1*R3
STORE X, R1 M[X] ← R1
Section - 7
Addressing Modes
 The addressing mode specifies a rule for 1. Implied Mode
interpreting or modifying the address field of 2. Immediate Mode
the instruction before the operand is actually 3. Register Mode
referenced. 4. Register Indirect Mode
 Computers use addressing mode techniques 5. Autoincrement or Autodecrement Mode
for the purpose of accommodating one or 6. Direct Address Mode
both of the following provisions: 7. Indirect Address Mode
1. To give programming versatility to the user by
providing such facilities as pointers to memory,
8. Relative Address Mode
counters for loop control, indexing of data, and 9. Indexed Addressing Mode
program relocation. 10. Base Register Addressing Mode
2. To reduce the number of bits in the addressing
field of the instruction.
 There are basic 10 addressing modes
supported by the computer.
1. Implied Mode & 2. Immediate Mode
1. Implied Mode
 Operands are specified implicitly in the
definition of the instruction.
 For example, the instruction “complement
accumulator (CMA)” is an implied-mode
instruction because the operand in the
accumulator register is implied in the
definition of the instruction.
 In fact, all register reference instructions
that use an accumulator and zero address
instructions are implied mode instructions.
2. Immediate Mode
 Operand is specified in the instruction
itself.
 In other words, an immediate-mode
instruction has an operand field rather than
an address field.
 The operand field contains the actual
operand to be used in conjunction with the
operation specified in the instruction.
 Immediate mode of instructions is useful for
initializing register to constant value.
 E.g. MOV R1, 05H
instruction copies immediate number 05H
to R1 register.
3. Register Mode & 4. Register Indirect Mode
3. Register Mode
 Operands are in registers that reside within
the CPU.
 The particular register is selected from a
register field in the instruction.
 E.g. MOV AX, BX
move value from BX to AX register
4. Register Indirect Mode
 In this mode the instruction specifies a register
in the CPU whose contents give the address of
the operand in memory.
 Before using a register indirect mode
instruction, the programmer must ensure that
the memory address of the operand is placed in
the processor register with a previous
instruction.
 The advantage of this mode is that address field
of the instruction uses fewer bits to select a
register than would have been required to
specify a memory address directly.
 E.g. MOV [R1], R2
value of R2 is moved to the memory location
specified in R1.
 5. Autoincrement or Autodecrement Mode & 6. Direct Address Mode
5. Autoincrement or Autodecrement Mode 6. Direct Address Mode
 This is similar to the register indirect mode  In this mode the effective address is equal
expect that the register is incremented or to the address part of the instruction.
decremented after (or before) its value is  The operand resides in memory and its
used to access memory. address is given directly by the address
 When the address stored in the register field of the instruction.
refers to a table of data in memory, it is  E.g. ADD 457
necessary to increment or decrement the
register after every access to the table. This
can be achieved by using the increment or
decrement instruction.
7. Indirect Address Mode & 8. Relative Address Mode
7. Indirect Address Mode
 In this mode the address field of the
instruction gives the address where the
effective address is stored in memory.
 Control fetches the instruction from
memory and uses its address part to access
memory again to read the effective address.
 The effective address in this mode is
obtained from the following computational:
Effective address = address part of instruction
+ content of CPU register
8. Relative Address Mode
 In this mode the content of the program
counter is added to the address part of the
instruction in order to obtain the effective
address.
 The address part of the instruction is
usually a signed number which can be either
positive or negative.
Effective address = address part of instruction
+ content of PC
9. Indexed Addressing Mode & 10. Base Register Addressing Mode
9. Indexed Addressing Mode
 In this mode the content of an index register
is added to the address part of the
instruction to obtain the effective address.
 The indexed register is a special CPU
register that contain an index value.
 The address field of the instruction defines
the beginning address of a data array in
memory.
 Each operand in the array is stored in
memory relative to the begging address.
Effective address = address part of instruction
+ content of index register
10. Base Register Addressing Mode
 In this mode the content of a base register
is added to the address part of the
instruction to obtain the effective address.
 A base register is assumed to hold a base
address and the address field of the
instruction gives a displacement relative to
this base address.
 The base register addressing mode is used
in computers to facilitate the relocation of
programs in memory.
Effective address = address part of instruction
+ content of base register
Addressing Modes (Example)
Address Memory
200 Load to AC Mode
PC = 200
201 Address = 500
202 Next instruction
R1 = 400

XR = 100 399 450

400 700

AC
500 800

600 900

702 325

800 300
Section - 8
Data transfer and manipulation

The most computer instructions can be classified into three

categories:
1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
Data transfer instructions
 Data transfer instructions move data from one place in the computer to another without
changing the data content.
 The most common transfers are between memory and processor registers, between processor
registers and input or output, and between the processor registers themselves.

Name Mnemonic The data manipulation instructions in a typical

Load LD computer are usually divided into three basic
Store ST types:
Move MOV 1. Arithmetic instructions
Exchange XCH 2. Logical and bit manipulation instructions
Input IN 3. Shift instructions
Output OUT
Push PUSH
Pop POP
Data manipulation instructions

The data manipulation instructions in a typical computer are usually divided into three
basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
Data manipulation instructions
Logical & Bit
Arithmetic Instructions Manipulation Instructions Shift Instructions
Name Mnemonic Name Mnemonic Name Mnemonic
Increment INC Clear CLR Logical shift right SHR
Decrement DEC Complement COM Logical shift left SHL
Add ADD AND AND Arithmetic shift right SHRA
Subtract SUB OR OR Arithmetic shift left SHLA
Multiply MUL Exclusive-OR XOR Rotate right ROR
Divide DIV Clear carry CLRC Rotate left ROL
Add with carry ADDC Set carry SETC Rotate right through carry RORC
Subtract with borrow SUBB Complement carry COMC Rotate left through carry ROLC
Negate (2’s complement) NEG Enable interrupt EI
Disable interrupt DI
Section - 9
Program Control
 A program control type of instruction, when executed, may change the address value in the
program counter and cause the flow of control to be altered.
 The change in value of the program counter as a result of the execution of a program control
instruction causes a break in the sequence of instruction execution.

Name Mnemonic
Branch BUN
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST
Status Bit Conditions
A B  Bit C (carry) is set to 1 if the end
8 8
carry C8 is 1. It is cleared to 0 if the
𝐶7 carry is 0.
8-bit ALU
𝐶8  Bit S (sign) is set to 1 if the highest-
V Z S C order bit F7 is 1. It is set to 0 if the
𝐹7 − 𝐹0 bit is 0.
 Bit Z (zero) is set to 1 if the output is
𝐹7 zero and Z = 0 if the output is not
zero.
 Bit V (overflow) is set to 1 if the
exclusive-OR of the last two carries
Check for zero output
is equal to 1, and cleared to 0
otherwise. This is the condition for
8
an overflow when negative numbers
are in 2’s complement.
Output F
Conditional Branch Instructions
Mnemonic Branch Condition Tested Mnemonic Branch Condition Tested
Condition Condition
BZ Branch if zero Z=1 BLO Branch if lower A<B
BNZ Branch if not zero Z=0 BLOE Branch if lower or equal A≤B
BC Branch if carry C=1 BE Branch if equal A=B
BNC Branch if no carry C=0 BNE Branch if not equal A≠B
BP Branch if plus S=0 Signed compare conditions (A – B)
BM Branch if minus S=1 BGT Branch if greater than A>B
BV Branch if overflow V=1 BGE Branch if greater or equal A ≥ B
BNV Branch if no overflow V=0 BLT Branch if less than A<B
Unsigned compare conditions (A – B) BLE Branch if less or equal A≤B
BHI Branch if higher A>B BE Branch if equal A=B
BHE Branch if higher or equal A ≥ B BNE Branch if not equal A≠B
Program Interrupt
 The interrupt procedure is, in principle, quite similar to a subroutine call except for three
variations:
1. The interrupt is usually initiated by an internal or external signal rather than from the execution of an
instruction
2. The address of the interrupt service program is determined by the hardware rather than from the address
field of an instruction
3. An interrupt procedure usually stores all the information necessary to define the state of the CPU rather than
storing only the program counter.
 After a program has been interrupted and the service routine has been executed, the CPU
must return to exactly the same state that it was when the interrupt occurred. Only if this
happens will the interrupted program be able to resume exactly as if nothing had happened.
 The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is
determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions
Types of interrupts
 There are three major types of interrupts that cause a break in the normal execution of a
program. They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
1. External Interrupt
 External interrupts come from
 Input-output (I/O) devices
 Timing device
 Circuit monitoring the power supply
 Any other external source
 Examples that cause external interrupts are
 I/O device requesting transfer of data
 I/O device finished transfer of data
 Elapsed time of an event
 Power failure
 External interrupts are asynchronous.
 External interrupts depend on external conditions that are independent of the program being
executed at the time.
2. Internal interrupts (Traps)
 Internal interrupts arise from
 Illegal or erroneous use of an instruction or data.
 Examples of interrupts caused by internal error conditions like
 Register overflow
 Attempt to divide by zero
 invalid operation code
 stack overflow
 protection violation.
 These error conditions usually occur as a result of a premature termination of the instruction
execution.
 Internal interrupts are synchronous with the program. If the program is rerun, the internal
interrupts will occur in the same place each time.
3. Software interrupts
 A software interrupt is a special call instruction that behaves like an interrupt rather than a
subroutine call.
 The most common use of software interrupt is associated with a supervisor call instruction.
This instruction provides means for switching from a CPU user mode to the supervisor mode.
 When an input or output transfer is required, the supervisor mode is requested by means of a
supervisor call instruction. This instruction causes a software interrupt that stores the old CPU
state and brings in a new PSW that belongs to the supervisor mode.
 The calling program must pass information to the operating system in order to specify the
particular task requested.
Section - 10
Reduced Instruction Set Computer (RISC)
 Characteristics of RISC are as follows:
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instructions
 All operations done within the registers of the CPU
 Fixed-length, easily decoded instruction format
 Single-cycle instruction execution
 Hardwired rather than microprogrammed control
 A relatively large number of registers in the processor unit
 Use of overlapped register windows to speed-up procedure call and return
 Efficient instruction pipeline
 Compiler support for efficient translation of high-level language programs into machine language programs
Overlapped Register Window
R15
Common to D and A
 A characteristic of some
R10 RISC processors is their
R73
Local to D use of overlapped
R64 register windows to
R63
Common to C and D provide the passing of
R58
Proc D R57 parameters and avoid
Local to C the need for saving and
R48
R47
Common to B and C
restoring register
Window size = L + 2C + G R42 values.
Proc C R41
Register file = (L + C) W + G Local to B  Each procedure call
R32
R31 results in the allocation
Common to A and B
R26 of a new window
R9
Common to all Proc B R25
Local to A
consisting of a set of
procedures R16 registers from the
R0 R15
Global
Common to A and D register file for use by
R10 the new procedure.
register Proc A
s
Overlapped Register Window
 Windows for adjacent procedures have overlapping registers that are shared to provide the
passing of parameters and results.
 Suppose that procedure A calls procedure B.
 Registers R26 through R31 are common to both procedures, and therefore procedure A stores
the parameters for procedure B in these registers.
 Procedure B uses local registers R32 through R41 for local variable storage.
 If procedure B calls procedure C, it will pass the parameters through registers R42 through
R47.
 When procedure B is ready to return at the end of its computation, the program stores results
of the computation in registers R26 through R31 and transfers back to the register window of
procedure A.
 Note that registers R10 through R15 are common to procedures A and D because the four
windows have a circular organization with A being adjacent to D.
Overlapped Register Window

 The organization of register windows has the relationship as

• Number of global registers = g
• Number of local registers present in each window = l
• Number of registers common to two adjacent windows = c
• Number of windows = w
 Then the number of registers available for each window is calculated by
• Window size = L+2C+G
 The total number of registers required in the processor is
• Register file = (L + C)W+ G
Section - 11
Complex Instruction Set Computer (CISC)
 Characteristics of CISC are as follows:
 A larger number of instructions – typically from 100 to 250 instructions
 Some instructions that perform specialized tasks and are used infrequently
 A large variety of addressing modes – typically from 5 to 20 different modes
 Variable-length instruction formats
 Instructions that manipulate operands in memory