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Ultra low power frequency divider for 2.45 GHz ZigBee frequency synthesizer

Article in Analog Integrated Circuits and Signal Processing · January 2011

DOI: 10.1007/s10470-012-9935-3

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Ultra low power frequency divider for
2.45 GHz ZigBee frequency synthesizer

Ali Sahafi, Jafar Sobhi, Mahdi Sahafi,

Omid Farhanieh & Ziaddin Daie
Koozehkanani

Analog Integrated Circuits and Signal

Processing
An International Journal

ISSN 0925-1030
Volume 74
Number 1

Analog Integr Circ Sig Process (2013)

74:97-103
DOI 10.1007/s10470-012-9935-3

1 23
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 Author's personal copy
Analog Integr Circ Sig Process (2013) 74:97–103
DOI 10.1007/s10470-012-9935-3
Ultra low power frequency divider for 2.45 GHz ZigBee
frequency synthesizer
Ali Sahafi • Jafar Sobhi • Mahdi Sahafi •
Omid Farhanieh • Ziaddin Daie Koozehkanani
Received: 14 January 2012 / Revised: 14 July 2012 / Accepted: 19 July 2012 / Published online: 3 August 2012
Ó Springer Science+Business Media, LLC 2012
Abstract An ultra low power CMOS frequency divider
whose modulus can be varied from 481 to 496 is presented.
It has been customized to be used in 2.45 GHz Integer-N
PLL frequency synthesizers utilized in ZigBee standard. Its
based on swallow divider that replaces the swallow counter
by a simple digital circuit in order to reduce power con-
sumption and design complexity. Also a low power and
high speed divide-by-7/8 is presented. Post layout simula-
tion results exhibit 420 lW power consumption for 4 bit
frequency divider in 2.45 GHz ISM frequency band that
proves 40 % reduction compared to same previous works.
All of the circuits have been designed in 0.18 lm TSMC
CMOS technology with a single 1.8 V DC voltage supply.
Keywords Swallow divider  Frequency divider 
Frequency synthesizer  PLL  Dual modulus prescaler 
ZigBee
1 Introduction
ZigBee is a recently developed wireless technology used in
many commercial and research applications. Based on the
IEEE 802.15.4 specication [1], it has become a very
attractive wireless connectivity solution due to its open
standard, low cost and low power characteristics [2]. Zig-
Bee is suitable for low data-rate and low power consump-
tion applications [3] in comparison with other wireless
A. Sahafi (&)  J. Sobhi  M. Sahafi  O. Farhanieh 
Z. D. Koozehkanani
Faculty of Electrical and Computer Engineering,
University of Tabriz, Tabriz, Iran
e-mail: a.sahafi@tabrizu.ac.ir
technologies such as Bluetooth and WiFi. Applications
include home and building automation, industrial control,
building management systems, environmental monitoring,
etc. Operational frequency of this standard is 860, 920 and
2450 MHz.
Majority of networks based on ZigBee protocol are
powered by battery. Power consumption reduction of net-
work nodes is one of the salient challenges for designers. A
critical RF function in the nodes is the frequency synthe-
sizer, more particularly the programmable frequency divi-
der. The frequency divider consists of logic gates which
operate at (or close to) the highest RF frequency. Due to
the divider’s complexity, high operation frequency nor-
mally leads to high power dissipation.
In [4] a new structure for frequency divider has been
introduced that operates up to 5 GHz with power efficiency
of 1.79 GHz/mW. A common method to implement a low
power and high frequency divider in high frequency Inte-
ger-N PLLs is based on pulse swallow divider [5–8]. In the
conventional pulse swallow divider, the swallow counter is
a loadable counter and has a quite complicated structure [9]
that represents a substantial load at the output of the dual-
modulus prescaler, so wastes a large amount of energy and
limits the operating frequency of the frequency divider. In
this paper a new method for designing a frequency divider
has been proposed which replaces swallow counter by a
simple digital circuit that reduces 40 % power consump-
tion of the frequency divider, compared to same previous
works. Proposed frequency divider has been designed and
tested in an Integer-N PLL, based on 2.45 GHz IEEE
802.15.4/ZigBee transceiver with reference frequency of
5 MHz that covers all 16 available channels.
The organization of this article is as follows: In Sect. 2,
the Integer-N pulse swallow frequency divider will be
described briefly and Sect. 3 describes the building blocks
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98
of the proposed frequency divider. Finally, the post layout
simulation results are presented in Sect. 4.
2 Integer-N pulse swallow frequency divider
Figure 1 shows a simple schematic of programmable fre-
quency divider based on conventional pulse swallow
divider. As it is clear, this structure has a dual modulus
(M) prescaler, a fixed program (P) counter and a loadable
swallow (S) counter. The prescaler has the ability
of dividing its high frequency input by M ? 1 or M,
depending on the logic level of the modulus control bit.
The program counter divides the output of the prescaler by
a fixed count P. Finally the Swallow counter also divides
the prescaler output by S and controls the modulus selec-
tion of the prescaler. The swallow counter is reset by the
program counter, every time it counts P input cycles.
To explain the operation of the frequency divider, let us
assume the prescaler starts dividing by M ? 1; this process
continues until the swallow counter reaches its count S and
the modulus control of the prescaler is changed to divide by
M. At this point, (M ? 1) 9 S input cycles have been
counted, and (P - S) counts are left in the program
counter. The program counter continues counting until it
reaches P counts, which is reached with M 9 (P - S)
input cycles. From the previous explanation it can be
noticed that one complete cycle is achieved with
(M ? 1) 9 S ? M 9 (P - S) = M 9 P ? S cycles at the
input. This equation implies that the product M 9 P sets
the lower limit of the frequency band that needs to be
synthesized and S selects the desired channel [10].
The conventional swallow divider has some undesirable
characteristics. One readily notices the lack of modularity
of the concept: besides the dual-modulus prescaler, the
architecture requires two additional counters for the gen-
eration of a given division ratio; the fixed P counter and a
separate loadable S counter which is in fact fully
Fig. 1 Pulse swallow frequency divider
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Analog Integr Circ Sig Process (2013) 74:97–103
Fig. 2 Proposed frequency divider
programmable counter that consists of K number of loa-
dable bit-cells for K-bit counter. S counter wastes energy
and increases capacitance load at the output of the dual-
modulus prescaler too, so the power dissipation is
increased. Figure 2 illustrates the proposed frequency
divider. As it is obvious, we have merged P counter and S
counter in the integrated P&S counter that works as a
fixed P counter and also detects count S to control the
modulus logic bit of prescaler. By using this method,
the swallow counter is eliminated, capacitance load at the
output of dual-modulus prescaler is reduced, design of high
frequency dividers becomes simpler and the power con-
sumption of frequency divider decreases.
As 2,450 MHz frequency band in ZigBee standard is
universal unlicensed band, the most of applications use this
range that consists of 16 frequency channels with space of
5 MHz, from 2,405 to 2,480 MHz. So the frequency divi-
der needs division ratio from 481 to 496 to cover all 16
available channels. These numbers are obtained by a
divide-by-7/8 dual modulus prescaler (M = 7), P = 64 and
33 B S B 48 in the swallow equation.
3 Building blocks of the proposed structure
In this section the proposed structure will be introduced. As
the structure is based on swallow divider, internal blocks
are designed respectively similar to swallow divider.
3.1 Dual modulus prescaler
As mentioned in previous section, we have used a divide-
by-7/8 dual modulus prescaler. Figure 3(a) illustrates the
block diagram of dual modulus prescaler used in this
structure. This prescaler consists of a divide-by-3/4 dual
modulus prescaler and a divide-by-2. Table 1 shows
sequential operation of dual modulus prescaler. When the
modulus bit is zero, M1 transistor is off and the prescaler
divides input frequency by 8. When the modulus bit
changes to 1, in state 3 (in Table 1), output of Q1 is reset by
M1–M3, as Q2Q3= 11 and the prescaler jumps to state 4
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Analog Integr Circ Sig Process (2013) 74:97–103 99

Table 2 Size of transistors used in prescaler

Width(lm) Length(lm) Type

M1–M3 2 0.18 N
M4–M9 0.5 0.18 N
M10–M14 1 0.18 P

Fig. 3 a 7/8 Dual modulus prescaler, b conventional true-single-

phase-clocking (TSPC) D-flip flop (DFF)

Fig. 4 Proposed integrated P&S counter

Table 1 Sequential operation of dual modulus prescaler Table 3 Truth table of XNOR gate
Row Q1 Q2 Q3 Input 1 Input 2 Output

1 0 0 0 0 0 1
2 1 0 0 0 1 0
3 1 1 1 1 0 0
4 0 1 1 1 1 1
5 0 0 1
6 1 0 1
3.2 Integrated P&S counter
7 1 1 0
8 0 1 0
Figure 4 shows the block diagram of the integrated P&S
counter. This block consists of a divide-by-64 (P counter)
and a digital circuit that consists of XNOR gates (X0–X4),
according to Table 1, so the number of Q1Q2Q3 = 111 is AND gates (A0–A2) and a reset-set flip flop (RSFF). This
eliminated and the input frequency is divided by 7. digital section has replaced S counter in conventional ones
In conventional dual modulous prescalers, logic gates and has duty to control the modulus bit of dual modulus
are used to produce second division ratio [11], so using prescaler.
high speed DFFs and logic gates are essential. But in Table 3 shows the output of XNOR block for four
proposed structure, because of simple scheme, the use of available inputs. XNOR gate is an equality block so when
simple logics like TSPC, can decrease power dissipation. inputs of XNOR are equal (both of them are 0 or 1), output
Figure 3(b) shows a conventional TSPC DFF that has of XNOR gate is logic one. Therefore when the value of P
been used in the dual modulus prescaler. Table 2 listed the counter (P5P4P3P2P1P0) is equal to predefined S number
size of transistors used in dual modulus prescaler. (1S4S3S2S1S0), RSFF is set by A2 gate and when P5 changes

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100
to 0, RSFF is reset. (S4–S0 bits are defined by transceiver
system that specifies the frequency channel of PLL). For
more details, assume the P counter is in ZERO condition
{P5P4P3P2P1P0 = 000000}. As P5 is equal to 0, RSFF is
reset and dual modulus prescaler divides input frequency
by 8. Suppose we want the PLL to work in 6th frequency
channel so we load the number of 6 on S4–S0 {S4S3S2
S1S0 = 00110}. Input signal is applied and P counter
increases until the value of P counter reaches the prede-
fined S {P5P4P3P2P1P0 = 1S4S3S2S1S0}. (For this exam-
ple: P5P4P3P2P1P0 = 100110; as mentioned in Sect. 2, for
all channels S [ 32 so P5 must be logic 1 to set modulus
bit, thus P5 is applied to A1 gate directly). In this value of P
counter, output of XNOR blocks and P5 are logic 1 that
causes RSFF to be set by A2 gate. After this, the prescaler
divide input frequency by 7 till the P counter reaches to its
maximum value (111111) and next value is {000000}.
RSFF is reset by P5, prescaler returns to divide-by-8 situ-
ation and the cycle starts again. In this cycle the events
occurred similar to conventional pulse swallow divider.
Hence for the quantity of predefined S (1S4S3S2S1S0 = S),
prescaler divide input frequency by 8 and for rest of
number (64 - S) it divides input frequency by 7. For a
complete cycle we will have:
N ¼ 8  S þ 7  ð64  SÞ ¼ 7  64 þ S ð1Þ
fvco ¼ fref  N ¼ 5 MHz  ð448 þ SÞ ð2Þ
2405 MHz  fvco  2480 MHz; 33  S  48 ð3Þ
For the example that was stated above, S = 32 ? 6, so
fvco = 2,430 MHz, that is center frequency of 6th fre-
quency channel of the ZigBee standard.
To increase operating speed, XNOR block has been
implemented by pass-gate logic and divide-by-2 block has
been made by TSPC DFF, similar to DFFs used in presc-
aler block.
Frequency dividers based on DFFs are classified in two
main groups: synchronous dividers and asynchronous
Fig. 5 Divide-by-4 a asynchronous, b synchronous
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Analog Integr Circ Sig Process (2013) 74:97–103
dividers [11]. Figure 5 illustrates divide-by-4 frequency
divider based on DFFs. In synchronous dividers all of the
DFFs work by main input frequency whereas in asyn-
chronous dividers input frequency of the next DFF is half
of input frequency of prior DFF and the frequency of signal
is halved as it goes into next DFF. Lower frequency leads
to lower power consumption so power dissipation in
asynchronous divider is much smaller than synchronous
divider in large division ratios [11].
Asynchronous dividers have a big drawback that is
propagation of timing jitter in DFFs. Existence of noise in
DFFs causes the time of rising edge (or falling edge) to
vary with noise:
T1 ¼ 2  T0 þ Dt1 ð4Þ
T1 is output signal period of first divider (DFF1), T0 is
average period of oscillator and Dt1 is timing jitter of first
divider in presence of noise. In the next DFF period of
signal is doubled and the jitter of second DFF (Dt2 ) is
added. Therefore asynchronous divider act as a timing jitter
accumulator. For a frequency divider with N number of
DFFs (K = 2N) we will have:
TN ¼ K  T0 þ Dttotal ð5Þ
X
N
Dttotal ¼ ð2Ni ÞDti ð6Þ
i¼1
TN is the period of last DFF, K is division ratio and Dttotal is
total timing jitter. Figure 6 shows distribution of total
timing jitter (Dttotal ) in the output of frequency divider
simulated numberically by Matlab software.
To solve this problem, a synchronizer DFF is placed as
the last DFF (Sync. DFF in Fig. 7) [11]. Existence of this
DFF causes the rising edge of last DFF to be synchronized
with rising (or falling) edge of main signal. Figure 7 shows
spreading of jitter in asynchronous dividers and synchro-
nized output. By using this DFF the total jitter decreases to
jitter of one DFF. To estimate the effect of synchronizer
DFF, output voltage of oscillator must be considered:
Vout ðtÞ ¼ A  Sinðx0 t þ /ðtÞÞ ð7Þ
Vout is output voltage of oscillator with constant amplitude
of A and rectangular frenquency of x0. /(t) is output phase
of oscillator in presence of noise. As computed in [12]
phase error of divider is transferred to output by coefficient
of K. To analyze jitter effect, phase noise of divider is
assumed to be a single tone sinusoidal within loop
bandwidth:
/ðtÞ ¼ /m  Sinðxm tÞ ¼ K  /div  Sinðxm tÞ ð8Þ
That /div is amplitude of divider’s phase error. Phase noise
of frequency divider at frequency offset of xm from carrier
is obtained by [12]:
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Analog Integr Circ Sig Process (2013) 74:97–103
(a)
Fig. 6 Distribution of timing jitter. a Probability density, b Cumulative probability
Fig. 7 Eliminating timing jitter by synchronizer DFF
Fig. 8 Control voltage of VCO while changing from 1st to 16th
channel
L ¼ 10logð/2m =4Þ
/m ¼ K  /div ¼ K  Dteff  x0
Effective timing jitter of asynchronous divider is chosen at
probability of 50 %, in Fig. 7(b) (for S ¼ 0:5 ¼) Dteff ’
ðK=4ÞDt). /div ¼ ðK=4Þ  Dt  x0 : So in asynchronous
divider amplitude of phase error is K/4 times of synchronous
divider. So:
Lasync  Lsync ¼ 10logððK=4  Dt  x0 Þ2 =ðDt  x0 Þ2 Þ
¼ 20logðK=4Þ ð11Þ
101
(b)
Fig. 9 Output spread spectrum of the PLL in 16th channel
In the proposed divider as K = 64, the phase noise related
to frequency divider decreases by 24 dB, so phase noise of
the divider is eliminated and noise of charge pump domi-
nates as close in phase noise of the PLL. Simulation results
show -70 dBc (8 dB reduction) close in phase noise of the
PLL in the designed circuit. To gain better close in phase
ð9Þ noise, a complicated low noise charge pump is required but
obtained results are adequate for ZigBee transceiver.
ð10Þ It requires paying attention, if the total jitter error in
divider (K  Dt) is more than a half period of main signal
(T0/2), the synchronizer DFF may sample wrong output
from last DFF that causes spurious tones at the output of
oscillator. Therefore in large division coefficients, the use
of two or more synchronizer DFFs in signal path is
essential. Another important point is choosing sample
clock of the synchronizer DFF (fin or fin ). This clock must
have maximum interval of the rising (or falling) edge of the
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102 Analog Integr Circ Sig Process (2013) 74:97–103

5 Conclusion

An ultra low power frequency divider for PLL frequency

synthesizer working in ZigBee 2.45 GHz standard has been
proposed. The swallow counter which consumes a large
portion of energy in conventional frequency divider has
been replaced by a simple digital section in this structure.
A simple and low power divide-by-7/8 dual modulus
divider by TSPC logic has been designed as a prescaler to
decrease the total power dissipation of frequency divider.
The post layout simulation results show power consump-
tion of 420 lW for the complete frequency divider that is
40 % lower than same previous works. Proposed divider
occupies area of 36 9 45 lm2.

Fig. 10 Layout of the the proposed frequency divider References

1. ZigBee Specication. (2004). ZigBee Document 053474r06 Ver-

sion 1.0. Baltimore: ZigBee Alliance Std.
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spectrum of the PLL in 16th channel in lock situation. Also 9. Yu, X. P., Do, M. A., Jia, L., Ma, J. G., & Yeo, K. S. (2005).
Fig. 10 illustrates the layout of designed frequency divider Design of a low power wide-band high resolution programmable
with size of 36 9 45 lm2. frequency divider. IEEE transactions on very large scale inte-
gration (VLSI) systems, 13(6), 1098–1103.
All of the circuits have been designed and simulated by
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13. Liu, W., Zhang, X., & Xia, W. (2010). A low power high-speed
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Ali Sahafi received B.S. degree
in electrical engineering from
Urmia University, Iran in 2009.
He received M.Sc. electrical
engineering from University of
Tabriz in 2011. He is currently
working towards the Ph.D.
degree in electrical engineering
in University of Tabriz. His
research interests are RF inte-
grated circuits and system design
focused on low-power RF trans-
ceivers, low-cost biomedical
devices, mixed signal circuits
design and optoelectronics.
Jafar Sobhi was born in Tabriz,
Iran. He received B.S. degree in
electrical engineering from Uni-
versity of Tabriz, Iran. He
received M.Sc. and Ph.D. degree
in electrical engineering from
Urmia University. His research
interests are high-speed high-
resolution Data converter design,
mixed signal circuits design and
RF integrated circuits design. He
is currently with Electrical
Engineering department of Uni-
versity of Tabriz, Iran.
Omid Farhanieh received the
M.Sc. degree in electrical engi-
neering from University of
Tabriz, Tabriz, Iran in 2011.
Since September 2010 He has
been a member of the ZigBee
SOC research group at the
Department of Electrical Engi-
neering of University of Tabriz.
His research interest is RF
microelectronic circuit and sys-
tems design.
Ziaddin Daie Koozehkanani
received his Ph.D. degree in
Electrical Engineering from the
Brunel University of West
London, UK in 1996. He has
been teaching as an assistant
professor in Urmia University
from 1996 to 2004 and in Tabriz
University since 2004. At the
time being he works as an
associated professor in Elec-
tronics Department in Tabriz
University and his position is
Dean of ECE faculty. His cur-
rent scientific interests are ana-
log integrated circuit design including data converters, RF IC design
and optical filter design.

Mahdi Sahafi received B.S. and

M.Sc. degree in electrical engi-
neering from University of Tab-
riz, Iran. His research interests
are optoelectronics focused on
all-optical signal processing and
RF integrated circuits design.

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