Introduction

The goal of this lab was to use VHDL to model a 4-bit ALU for future use in lab #14. ALU
stands for (Arithmetic Logic Unit) the ALU in a computer performs operations such as
arithmetic and logical expressions. An ALU can take in two Integer Operands and
depending on the Opcode that it receives it will perform the function that you want it to do.
Procedure

In the pre-lab, we provided a draft of our VHDL code and gate level schematic for
determining the V signal of the ALU. The ALU that we created had 6 opcodes for addition,
subtraction, AND, OR, CMPL, and IN A instructions. Our ALU is supposed to have four
output signals NZVC: (N) means that alu_out is negative, (Z) alu_out is zero, (V) means that
overflow occurred under 2’s complement arithmetic, and (C) means that carry/borrow
occurred during unsigned arithmetic. In the simulation that we showed to the TA should
include outputs for both ADD and SUB that included the V and C signals, in our simulation
we were supposed to show cases where V=C=0; V=1, C=0; V=0, C=1; C=V=1. We were also
supposed to show all the other Opcodes for our ALU. In order to get the desired outputs for
V and C I just made my test-bench waveform add and subtract numbers that I knew would
either cause overflow under 2’s complement or cause carry/borrow for unsigned numbers.
For example, to cause overflow I added numbers like 1 and 7, –8 and –1, etc. I showed all
the cases required for the lab. Below you’ll see all the simulations I performed.

VHDL Code
Behavioral Simulation

Post-Route Simulation

Design Summary

Conclusion

While designing the ALU, I learned to set up all the opcodes and internal signals of an ALU.
I didn’t really encounter any problems trying to get all the signals that I needed. It did take
me a while to find the right combination of numbers for ADD and SUB to give me the V and
C signals that I wanted. The thing that I still am not sure about is what the opcodes of
CMPL and IN A are supposed to do. But luckily everything my ALU worked out great.