VLSI Physical Design with Timing Analysis

Lecture – 38: Introduction and Optimization goals- Global Routing

Bishnu Prasad Das

Department of Electronics and Communication Engineering

1
 Contents
• Introduction to routing

• Terminology

• Optimization Goals

• Representations of routing regions

2
 Introduction to Routing
• Physical design flow:

Signal Routing

3
 Introduction
• During Global routing, pins with the same electric potential are
connected using wire segments.

• After placement, the layout area is represented as the Routing

region.

4
 Introduction: General Routing Problem
Placement result
Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5} 3 4
N4 = {B1, A1, C3} C
1
A 1 2
4

1 3
B 4 5 6
Technology Information 4
(Design Rules) D

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

5
 Introduction: General Routing Problem

Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5} 3 4
N4 = {B1, A1, C3} C
1
A 1 2
4
N1
1 3
B 4 5 6
Technology 4
Information D
(Design Rules)

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

6
 Introduction: General Routing Problem

Netlist:
N1 = {C4, D6, B3}
N2 = {D4, B4, C1, A4}
N3 = {C2, D5} 3 4
N4 = {B1, A1, C3} C
1
A 1 2
4
N4 N2 N3 N1
1 3
B 4 5 6
Technology 4
Information D
(Design Rules)

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

7
 Introduction
• Full chip Routing is generally performed in three steps:
GLOBAL DETAILED TIMING-DRIVEN
ROUTING ROUTING ROUTING

Coarse-grain Fine-grain Net topology

assignment of assignment of optimization and
routes to routing routes to routing resource
regions. tracks. allocation to
critical nets

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 Introduction

Horizontal
Segment
N3 N3
N1 N1 Vertical
N2 N2 Segment
N3 N3
Via
N3 N3
N1 N1 N2 N1 N1 N2

Global Routing Detailed Routing

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 Placement Wire Tracks Global Routing

Detailed Routing Congestion Map

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Global Routing
• Wire segments used by net topologies are tentatively assigned
(embedded) within the chip layout.

• Chip area is represented by a coarse routing grid.

• Available routing resources are represented by edges with

capacities in grid path.

• Nets are assigned to these routing resources.

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 Detailed Routing
• Wire segments are assigned to specific routing tracks.

- Net ordering

- Pin ordering

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 Terminology
• A routing track(column) is an available horizontal(vertical) wiring path.
• A routing region contains routing tracks and/or columns.
• A uniform routing region is formed by evenly spaced horizontal and
vertical grid lines that induce a uniform grid over the chip area.
• A non-uniform routing region is formed by horizontal
and vertical boundaries that are aligned to external
pin connection or macro-cell boundaries.

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 Terminology
• Channel is a rectangular routing region with pins on two opposite sides
and no pins on other side.

Routing channel

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Terminology
• Channel: Horizontal and Vertical

Horizontal Routing Channel

B B C D B C B

dpitch h
A C A B B C D

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Terminology
• The channel capacity represents the number of available routing tracks or column.
• For single-layer routing, the capacity is the height h of the channel divided by the pitch dpitch.
• For multilayer routing, the capacity σ is the sum of the capacities of all layers.

 

h
σ ( Layers) =  
layerLayers  
B B C D B C B d
 pitch (layer )

dpitch h

A C A B B C D

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure
 Terminology
• T-Junction occurs when a vertical channel meets with horizontal
channel in a macro cell placement.

B C
B C Horizontal
A B Channel

C A B
Vertical
Channel
Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure
 Terminology
• A Switchbox is the intersection of horizontal and vertical channels.
Vertical
Channel

BC
C
B c Horizontal
A B Channel

C AB

Vertical
Channel

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure
 Terminology
• 2D-3D Switchbox Bottom pin connection
Metal5 on 3D switchbox
Metal4 3D switchbox

Top pin connection on cell

Pin on channel boundary

Horizontal
channel 2D switchbox
Metal3
Metal2
Metal1 Vertical channel
Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure
 Optimization Goals
• Determine whether a given placement is routable.
• Determine a coarse routing for all nets within available routing
regions.
• Minimizing total wire length.
• Reducing signal delays on nets.

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 Full Custom Design: Optimization Goals
• The routing regions are non-uniform, often with different shapes and heights/widths

D
D B 4
B V
C E 1 5 C 2 E
A F H 5 H 3
A
F
A 1 B D 4 H
D (2) Channel ordering
B V
F 3
C E
A F C 2 E

(1) Types of channels

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Standard cell design: Optimization Goals

• In case of limited metal layers, the feedthrough cells

are used to route a net across multiple cell rows

• For multi-pin routing, rectilinear Steiner trees are

commonly used

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Optimization Goals
Standard cell design

Steiner tree solution with Steiner tree solution with

minimal wirelength fewest feedthrough cells
Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Gate array design: Optimization Goals
• The sizes of the cells and the sizes of the routing regions between the cells (routing
capacities) are fixed.

A gate array with One possible routing, net

channal height =4 C is remains unrouted

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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Thank You

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