VLSI Physical Design with Timing Analysis

Lecture – 32: Placement Algorithms

Bishnu Prasad Das

Department of Electronics and Communication Engineering

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 Contents
• Terminal propagation
• Quadratic placement

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 Terminal propagation
• Naive min-cut algorithms do not consider the locations of
connection pins within partitions that have already been visited.

• Terminal propagation considers external pin locations during

partitioning-based placement.

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 Terminal propagation
• Min-cut placement with external connections assumes that the
cells are placed in the centers of their respective partitions.

• If the related connections (dummy nodes) are close to the next

partition cutline, these nodes are not considered when making
the next cut.

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 Terminal propagation – Example
• Given: gates a-d of a circuit.

• Task: place the gates in a 2 × 2 grid.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Terminal propagation – Example
• Min-Cut Placement without considering External Connections

TR
2
2 2 3 3
4
3
1 1 4 1 4
BR

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Terminal propagation - Example
• Min-Cut Placement considering External Connections

x TR
p‘ 2
2 4
2 4
4
3
1 1 3 1 3
BR

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Analytic placement
• Analytic placement minimizes a given objective

– Like wirelength or circuit delay.

– using mathematical techniques like numerical analysis or

linear programming.

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 Quadratic placement
• The cost function is the squared Euclidean distance:
𝑛

𝐿 𝑃 = ෍ 𝑐 𝑖, 𝑗 ((𝑥𝑖 −𝑥𝑗 )2 + (𝑦𝑖 −𝑦𝑗 )2 )

𝑖=1,𝑗=1

• Where, n is the total number of cells

• c(i,j) is the connection cost between cells i and j.

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 Quadratic placement
• Similar to Least-Mean-Square Method (root mean square)

• Build error function with analytic form: E (a, b) =  (a  xi + b − yi )2

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Quadratic placement
• Quadratic placement consists of two stages:

• First stage:

– During global placement:

• Cells are placed so as to minimize the quadratic function

with respect to the cell centers.

• This placement is not legal.

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 Quadratic placement
• Second stage:

– During detailed placement:

• Large clusters are broken up and

• All cells are placed such that no overlap occurs.

• legalizes all the cell locations.

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 Quadratic placement
• During global placement, each dimension can be considered
independently.
𝑛

𝐿𝑥 𝑃 = ෍ 𝑐 𝑖, 𝑗 (𝑥𝑖 −𝑥𝑗 )2
𝑖=1,𝑗=1

𝐿𝑦 𝑃 = ෍ 𝑐 𝑖, 𝑗 (𝑦𝑖 −𝑦𝑗 )2
𝑖=1,𝑗=1

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 Quadratic placement
• With the cost functions, the placement problem becomes a
convex quadratic optimization problem.

• Convexity → any local minimum solution is also a global

minimum.

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 Quadratic placement
• Optimal x- and y- coordinates can be found by:

𝜕𝐿𝑥 𝑃 𝜕𝐿𝑦 𝑃
= 𝐴𝑋 − 𝑏𝑥 = 0 and = 𝐴𝑌 − 𝑏𝑦 = 0
𝜕𝑥 𝜕𝑦

• where A is a matrix with

– A[i][j] = -c(i,j) when i ≠ j

– A[i][i] = the sum of incident connection weights of

cell i.

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 Quadratic placement
– X is a vector of all the x-coordinates of the non-fixed cells.
– bx is a vector with
• bx[i] = the sum of x-coordinates of all fixed cells attached to i.
– Y is a vector of all the y-coordinates of the non-fixed cells.
– by is a vector with
• by[i] = the sum of y-coordinates of all fixed
cells attached to i.

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 Quadratic placement
• This is a system of linear equations for which iterative numerical
methods can be used to find a solution.

– The conjugate gradient (CG) method and

– The successive over-relaxation (SOR) method.

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 Quadratic placement - Example
• Given: c p2
a
b
– Placement P with
p1
– two fixed points p1 (100,175) and p2 (200,225),

– Three free blocks a-c

– Nets N1-N4. N1 (p1,a) N2 (a,b) N3 (b,c) N4 (c,p2)

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Quadratic placement - Example
• Task: find the coordinates of blocks (xa, ya), (xb, yb) and (xc, yc).

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 Quadratic placement - Example
Solve for x-coordinates.
𝑳𝒙 𝑷 = (𝟏𝟎𝟎 − 𝒙𝒂 )𝟐 +(𝒙𝒂 − 𝒙𝒃 )𝟐 +(𝒙𝒃 − 𝒙𝒄 )𝟐 +(𝒙𝒄 − 𝟐𝟎𝟎)𝟐

𝜕𝐿𝑥 (𝑃)
• = −2 100 − 𝑥𝑎 + 2 𝑥𝑎 − 𝑥𝑏 = 4𝑥𝑎 − 2𝑥𝑏 − 200 = 0
𝜕𝑥𝑎

𝜕𝐿𝑥 (𝑃)
• = −2 𝑥𝑎 − 𝑥𝑏 + 2 𝑥𝑏 − 𝑥𝑐 = −2𝑥𝑎 + 4𝑥𝑏 − 2𝑥𝑐 = 0
𝜕𝑥𝑏

𝜕𝐿𝑥 (𝑃)
• = −2 𝑥𝑏 − 𝑥𝑐 + 2 𝑥𝑐 − 200 = −2𝑥𝑏 + 4𝑥𝑐 − 400 = 0
𝜕𝑥𝑐

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 Quadratic placement - Example
• Put in matrix form AX = bx

4 −2 0 𝑥𝑎 200 2 −1 0 𝑥𝑎 100
• −2 4 −2 𝑥𝑏 = 0 → −1 2 −1 𝑥𝑏 = 0
0 −2 4 𝑥𝑐 400 0 −1 2 𝑥𝑐 200

• Solve for X: xa = 125, xb = 150, xc = 175.

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 Quadratic placement - Example
• Solve for y-coordinates.
𝑳𝒚 𝑷 = (𝟏𝟕𝟓 − 𝒚𝒂 )𝟐 +(𝒚𝒂 − 𝒚𝒃 )𝟐 +(𝒚𝒃 − 𝒚𝒄 )𝟐 +(𝒚𝒄 − 𝟐𝟐𝟓)𝟐

𝜕𝐿𝑦 (𝑃)
• = −2 175 − 𝑦𝑎 + 2 𝑦𝑎 − 𝑦𝑏 = 4𝑦𝑎 − 2𝑦𝑏 − 350 = 0
𝜕𝑦𝑎

𝜕𝐿𝑦 (𝑃)
• = −2 𝑦𝑎 − 𝑦𝑏 + 2 𝑦𝑏 − 𝑦𝑐 = −2𝑦𝑎 + 4𝑦𝑏 − 2𝑦𝑐 = 0
𝜕𝑦𝑏

𝜕𝐿𝑦 (𝑃)
• = −2 𝑦𝑏 − 𝑦𝑐 + 2 𝑦𝑐 − 225 = −2𝑦𝑏 + 4𝑦𝑐 − 450 = 0
𝜕𝑦𝑐

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 Quadratic placement - Example
• Put in matrix form AY = bY

4 −2 0 𝑦𝑎 350 2 −1 0 𝑦𝑎 175
• −2 4 −2 𝑦𝑏 = 0 → −1 2 −1 𝑦𝑏 = 0
0 −2 4 𝑦𝑐 450 0 −1 2 𝑦𝑐 225

• Solve for Y: ya = 187.5, yb = 200, yc = 212.5.

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 Quadratic placement - Example
• Final solution: a (125,187.5), b (150,200) and c (175,212.5).

c p2
b
a
p1

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Quadratic placement
• During detailed placement, cells are spread out to remove all overlaps

• Methods:

– Adding fake nets that pull cells away from dense regions toward
anchors

– Geometric sorting and scaling

– Repulsion forces, etc.

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 Quadratic placement

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Quadratic placement

• Advantages:

– Captures the placement problem concisely in mathematical terms.

– Leverages efficient algorithms from numerical analysis and available

software.

– Can be applied to large circuits without netlist

clustering (flat).
Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Quadratic placement
• Advantages:

– Stability: small changes in the input do not lead to large changes in

the output

• Disadvantages:

– Connections to fixed objects are necessary:

I/O pads, pins of fixed macros, etc.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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Thank You

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