IET Circuits, Devices & Systems

Research Article

Highly-digital voltage scalable 4-bit flash ADC ISSN 1751-858X

Received on 11th August 2017
Revised 30th April 2018
Accepted on 16th May 2018
E-First on 26th November 2018
doi: 10.1049/iet-cds.2018.5148
www.ietdl.org

Ashima Gupta1, Anil Singh1, Alpana Agarwal1

1Electronics and Communication Engineering Department, Thapar University, Patiala, India
E-mail: alpana@thapar.edu

Abstract: This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can
be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators
used in the ADC consist of complementary metal–oxide–semiconductor (CMOS)-based inverter and NAND-NOR as standard
cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51
mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and
30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and
integral non-linearity (INL) is + 0.6 LSB.

1 Introduction
It is required to use analogue to digital converters (ADCs) for
interfacing the real-world analogue signal to the digital system.
Different ADCs have been developed by altering the architecture
of ADCs like pipelined, integrating, binary search, delta sigma,
successive approximation and flash ADC. Medium- to high-speed
data conversions can be done by using pipelined ADCs at medium
to high resolution. More power is dissipated if low-resolution ADC
is implemented on fixed-resolution ADC because the extra
circuitry is present for a particular performance. In high-speed
applications, flash ADC is the preferable choice for the designer as
it offers high data conversion speed due to its parallel operation but
with low resolution [1, 2]. Flash ADC is used in many applications
like high-speed instrumentation, radar, wireless sensor network,
digital oscilloscopes, digital TVs, camera and optical
communications [3–5].
The most important block of flash ADC is the comparator [6].
The existing comparators are analogue in nature, and consume high
power, large area and require high design effort. With technology
scaling the digital circuits achieve higher efficiency in terms of
area, speed and power density, on the other hand, the analogue
circuit face problem to keep the same pace [7]. Alternative to that,
the digital circuits amplify the signal to rails and also less sensitive
to the noise, automatise the synthesis, and physical layout. In this
paper, gate-based digital comparator design is constructed and its
major part is synthesised using hardware description language
(HDL). Using this comparator, a 4-bit flash ADC is designed in
180 nm complementary metal–oxide–semiconductor (CMOS)
technology. One such gate-based approach is shown in [8]. Also,
the synthesised design of encoder is implemented. Section 2
describes the overall architecture of flash ADC. Simulations and
experimental results are defined in Section 3. The conclusion of the
paper is given in Section 4.

2 Flash ADC architecture

For high-speed ADC application flash ADC is used because of its
known parallel architecture. Fig. 1 shows the basic block diagram
of a flash ADC, which comprises of reference ladder, comparators
and an encoder as suggested by Abualsaud [6]. In this architecture,
the comparators are connected with every reference voltage. The
reference ladder generates the reference voltage that is compared
with the input and the output of the comparators are in the form of
0s and 1s bit stream which forms thermometer code [9] and further
fed into the encoder for ADC processing. The bit stream is
converted to binary output patterns using a Wallace tree encoder
[10] through bubble error correction logic. For making the high
conversion rate all outputs of the comparators must be
synchronised. If the resolution of ADC is increased then the
number of components increases exponentially, which further
increases area and power consumption. For σ-bit flash ADC 2N
resistors are required to generate a reference voltage for the 2N − 1
comparators [11]. The output of the comparator is a bit-string
called thermometer code. A simple 2N − 1: N encoder will
convert thermometer code to binary code.

2.1 Resister ladder

Fig. 1 Conceptual block diagram of flash ADC
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 1, pp. 91-97
© The Institution of Engineering and Technology 2018
A stable voltage reference is provided by a resistive ladder to the
comparators. Ladder network is created by 16 resistors which
generate the reference voltages. There is a difference of one LSB
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Fig. 2 Digital-based fully differential comparator

Fig. 3 Digital comparator with synthesised design

between each comparator. The ladder divides the reference logic comprising of four resistors, of equal value. Summer provides
voltages with the equal spacing of voltages as shown in Fig. 1. In the average of the external inputs and a feedback signal Vf coming
the proposed 4-bit flash ADC implementation, Vrefh = 1.5 V and from the CM extractor block which is stored in a capacitor C f for
Vrefl = 0.7 V. Hence, the LSB of this flash ADC [12] is given by summing. The capacitor (C f ) in the feedback block has been
implemented by metal-oxide-semiconductor capacitor (MOSCAP)
Vre f h − Vre f l (metal–oxide–semiconductor field-effect transistor capacitor) [14–
LSB =
2N 16]. A MOSCAP requires less area, lesser number of fabrication
mask layers and offers more capacitive density as compared to
LSB =
1.5 V − 0.7 V
= 50 mV other monolithic capacitors such as MIMCAP (metal insulator
16 metal capacitor) or MOMCAP (metal oxide metal capacitor) or
PIPCAP (polyinsulator polycapacitor) and so on.
2.2 Proposed comparator structure The synthesisable logic portion of the circuit is the major
contributor. The complete internal working of the circuit is
The schematic diagram of the fully-differential proposed voltage explained in the following text. An inverter provides a logic high
comparator is shown in Fig. 2. It depends on the concept of digital- output when a signal less than the threshold voltage (V th) is applied
in-concept differential circuit [13], and is composed of standard at its input and a logic low output when the input voltage is more
CMOS-based inverters, NAND and NOR gates. It has a summer
92 IET Circuits Devices Syst., 2019, Vol. 13 Iss. 1, pp. 91-97
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Fig. 4 Delay analysis and process variation effect
(a) Circuit to analyse the delay, (b) Monte Carlo simulations of R1 and R2 variations at VS_P node, (c) Output of comparator at (FV OUTP and FV OUTN) at different PVT corners,
(d)Variation of delay at FV OUTP node due to mismatches in M1-M2
than V th. The voltage at which input changes the output is known
as the switching or the trip voltage. Thus, if two inverters with
different inputs are taken and input voltage less than V th is applied
at one inverter and voltage greater than V th is applied at the other
inverter, then differential output will be 1 or 0. However, in case
the input voltages applied at both the inverters are the same, i.e.
both voltages are greater than V th or less than V th, the circuit
becomes non-responsive to the differential mode component and
hence, the output will be uncertain.
The solution to this impasse is a common mode negative
feedback signal (V f ), which is generated with the help of feedback
block. V f gets added up with both the input voltages V INPUT_N and
V INPUT_P with the help of summer.
Summer comprises of four resistors. Summer provides the
average of the feedback signal (V f ) and the external inputs such
that the outputs of summer are VS_P = ((V INPUT_P + V f )/2) and
VS_N = ((V INPUT_N + V f )/2). All inverters used in this circuit are
symmetric such that their switching threshold voltage
(V th) = (V DD /2). These voltages (VS_P and VS_N) are passed from
inverters to get OP and ON, which are the digital inputs of the
circuit. Thus, OP and ON are compared and the correct output is
obtained, eventually. The feedback block comprises of M5-M6
transistors, loaded by a capacitor C f .
Thus, when both input voltages, V INPUT_P and V INPUT_N are less
than V th, then M5 transistor turns ON to increase V f . When both
V INPUT_P and V INPUT_N are greater than V th, then M6 transistor is
turned ON to decrease V f . This is done to obtain V f in such a
range that after adding up, it leads to distinguishable values of the
digital inputs (OP and ON) of the circuit. In these two cases, the
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 1, pp. 91-97
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output transistors are OFF, until comparable digital inputs are
obtained through a feedback mechanism. As soon as the valid
digital inputs are obtained, correct outputs are provided by the
output stage. In the case of different input voltages, V f signal is not
required, hence feedback block is in off condition and the
transistors present at the output stage (M1–M4) are ON
accordingly, to provide correct outputs.
Considering the case of differential inputs, let V INPUT_P be
higher than V INPUT_N, once VS_N and VS_P cross the V th of the
inverters INV1–INV4, respectively, OP rises to logic ‘1’ and OP
decreases to logic ‘0’. Thus, M1 transistor turns ON and M2
transistor turns OFF. Therefore, FV OUTP becomes ‘1’ and FV OUTN
becomes ‘0’. Similarly, when V INPUT_P decreases and V INPUT_N
rises, FV OUTP becomes ‘0’ and FV OUTN becomes ‘1’. Fig. 3 shows
synthesised design of comparator. The synopsys design vision is
used to synthesise the comparator and complete flash ADC.
As compared to [13], here two output signals
FV OUTP and FV OUTN have been derived in the proposed circuit. As
fully differential circuits have certain benefits over single-ended
circuits like error subtraction, larger output swings, rejection of
common-mode noise, a high closed-loop speed and so on [17].
Usually all this is achieved at the cost of large power requirements
[18–19]. As the proposed comparator is synthesised using digital
gates so the power required is less.
2.2.1 Delay of the comparator: Fig. 4a shows the delay of the
resistive ladder. The worst case delay of the resistive ladder is
observed at node V ref 8 (shown as td) and delay from node V ref 8 to
VS_P is td1. Delay is formulated as
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Table 1 Delay of comparator at different corners
Corner (P) VDD, V
FF 1.92
TT 1.8
SF 1.8
FS 1.8
SS 1.62
Fig. 5 Simulation results of proposed comparator
(a) Transient analysis, (b) DC analysis, (c) Variation of propagation delay with change in input voltage amplitude Vp
VS_P(t) = VS_Po(t)(1 − e( − t / τ))
where VS_Po(t) = V refl + LSB ∗ 8 with = 36 RC
V ref 8 is settling to its final value within its confined time. From
the simulations, the total delay observed from V refh node to VS_P
node is 0.3 ns. R1−R4 resistances are implemented using
polysilicon resistance. Sensitivity to the process variations like
matching of R1−R4 has been done using Monte Carlo simulations
in Fig. 4b. In the comparator, the critical path from input to output
is observed from VS_P to FV OUTN as shown in Fig. 2. Hence, the
total delay from V INPUT_P to FV OUTN is typically 2.9 ns and varies
from 2.5 to 4.0 ns as shown in Fig. 4c (Table 1).
Fig. 4d shows the variation of delay due to mismatches in M1–
M2. It is observed from Fig. 4d that the mean value of the delay is
2.9 ns and 1 and 3 values of this variation are 0.16 and 0.51 ns,
respectively.
A propagation delay analysis is done for the path from V INPUT_N
to FV OUTP as shown in Fig. 5a. Some internal node voltages are
also plotted. DC analysis of the present HDL based voltage
comparator is shown in Fig. 5b, showing fast transition of outputs
when V INPUT_P crosses V INPUT_N. Also, the delay is calculated for
the different values of input voltage amplitude Vp and its plot as
shown in Fig. 5c. Minimum delay with change in Vp is 2.9 ns at
550 mV.
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Temp. (T), °C Delay, ms
0 2.5
27 2.9
27 3.1
27 3.4
125 4.0
2.2.2 Input offset voltage of the comparator: The performance
of the digital-based differential voltage comparator depends on the
delay of the buffers, mismatches in the resistances and the
threshold voltages. As there is a voltage divider at the input side,
the process variations in resistive network do not affect the
voltages at VS_P and VS_σ much as shown in Fig. 4b. Hence,
resistive network does not affect the offset voltage. The signal
amplitude at VS_P and VS_σ nodes is very less; hence inverters
(INV1, INV2, INV3 and INV4) are used in the design to amplify
the signal to the rails. The main source of the offset in the circuit is
the mismatches in rising (falling) time delays td_rise1, td_rise2 of
digital buffers. It leads to the increase in the offset voltage,
V offset 1 = (Io/Co) dV and mismatches in the threshold voltages
V offset 2 = V th 1 − V th 2 = dV. The total offset voltage is given by
[13]
V offset = V offset 1 + V offset 2
=
Io
dV + V th 1 − V th 2
Co
To see the variations in offset voltage, the Monte Carlo simulations
for 200 runs are performed and results are shown in Fig. 6. It is
observed that the mean value of the offset voltage is 4.97 mV.
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 1, pp. 91-97
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Fig. 6 Monte Carlo simulations of offset for 200 runs
Fig. 7 Synthesised design of 4-bit Wallace tree encoder
(a) Without timing constraints, (b) With timing constraints
2.2.3 Power analysis of comparator: The proposed comparator
designed in 1.8 V 180 nm CMOS technology gives an average
power dissipation of 192 µW. Of this, most of the power is
consumed by the inverters INV1 and INV3 because of the large
short-circuit current flowing through them as they are biased
around the midpoint of supply voltage to maximise the
amplification. The remaining circuit consumes almost negligible
power. Total number of comparators used in this flash ADC is 15
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so power dissipation by 15 comparators is about 192 µW × 15 =
2.88 mW.
2.3 Implementation of flash ADC encoder
One of the challenges in a high-speed flash ADC design is the
conversion of the thermometer code to binary code [20]. The
encoder is implemented using Wallace tree architecture which
comprises of full adders. It is also called ones counter as it counts
the number of one's [21, 22] and accordingly gives the binary
95

Fig. 8 Simulation result of 4-bit flash ADC
(a) With the ramp signal as input, (b) With sinusoidal as input where input frequency
is 10 MHz
Fig. 9 IσL and DσL of the proposed 4-bit flash ADC
output. As it counts the number of one's so it removes bubble error
of any order [23]. The power dissipation of Wallace tree encoder is
less than ROM-based encoder. Another advantage of this encoder
is that, all the inputs traverse through an equal number of full
adders so the propagation delay is equal. Also, it is flexible and
gives good result for any resolution. This circuit is also digitally
synthesised where the total number of full adders required for the
σ-bit encoder is 2N − N − 1.
Fig. 7a shows the synthesised design of 4-bit Wallace tree
encoder with a zoomed full adder design. Digital design flow,
placement and routing can also be done easily. The design vision of
synopsys tools is used to synthesise the encoder by applying the
timing constraints. The minimum delay of encoder is 1.89 ns after
applying the timing constraints. The insertion of buffers further
reduces the wire delay in long wires by maintaining the same
signal strength. Fig. 7b shows the synthesised design of 4-bit
Wallace tree encoder after applying timing constraints.
3 Simulation and experimental results
A 4-bit flash ADC is designed by the combination of all three
blocks, namely the resistive network, comparators and encoder. It
is simulated using HSPICE with SCL 1.8 V 180 nm CMOS
process parameters. Fig. 8a shows the digital 4-bit output of the
ADC with respect to input ramp signal (Vin).
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Fig. 10 Frequency response of ADC at 100 MHz sampling rate
(a) FFT of the proposed 4-bit flash ADC with input frequency of 1.66 MHz, (b)
SNDR, (c) ENOB
The transient analysis of complete 4-bit flash ADC with the
sinusoidal input at frequency 10 MHz is shown in Fig. 8b. The
differential non-linearity (DNL) and integral non-linearity (INL) of
4-bit flash ADC are shown in Fig. 9. The DNL of the proposed
flash ADC is ± 0.25 LSB and INL is + 0.6 LSB. The linearity is
restricted in between 1 LSB.
The fast Fourier transform (FFT) spectrum of reconstructed
signal is used to calculate the dynamic performance of flash ADC.
Figs. 10a and 11a show the reconstructed signal spectrum for an
input signal frequency of 1.66 and 31 MHz and sampled at 100 and
200 MHz, respectively. The dynamic performance of the ADC is
shown in Figs. 10 and 11. When input frequency is 1.66 MHz and
the clock frequency is 100 MHz, the value of effective number of
bits (ENOB), signal-to-noise and distortion ratio (SNDR), signal-
to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are
obtained as 3.7, 24.4 dB, 25.9 dB and 30.2 dB, respectively. The
value of ENOB, SNDR, SNR and SFDR are obtained as 3.5, 23.3
dB, 25.2 dB and 30.1 dB, respectively, when the input frequency is
33.20 MHz and the clock frequency is 200 MHz.
The power consumed by resistive ladder, comparators and the
encoder is 0.85, 2.88 and 0.78 mW as shown in Fig. 12. Also, the
delay of encoder is 1.89 ns. The total achieved delay of ADC is
4.83 ns.
4 Conclusion
The proposed work presents a highly digital 4-bit 200 MS flash
ADC whose major parts are synthesisable, reducing the design
efforts, time-to-market and power requirement. It is scalable with
the technology. Synthesis part was done in synopsys design vision.
The SNDR, SNR and SFDR are equal to 23.3, 25.2 and 30.1 dB. It
provides an ENOB equal to 3.5. The DNL of this 4-bit flash ADC
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 1, pp. 91-97
© The Institution of Engineering and Technology 2018

Fig. 11 Frequency response of ADC at 200 MHz sampling rate
(a) FFT of the proposed 4-bit flash ADC with input frequency of 33.20 MHz, (b)
SNDR, (c) ENOB
Fig. 12 Power (in mW) of 4-bit flash ADC
is ± 0.25 LSB and INL is + 0.6 LSB. The achieved delay and power
of ADC is 4.8 ns and 4.51 mW, respectively.
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© The Institution of Engineering and Technology 2018
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5 Acknowledgment
The authors gratefully acknowledge the financial support from the
Ministry of Electronics and Information Technology (MeitY), GoI
through SMDP Chips to System Design project.
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