Design of Versatile Reconfigurable ADC for Wide

Range of Resolution and Conversion Time

Jayamala Adsul1, P. P. Vaidya2, J. M. Nair2,

1
Department of Electronics Engineering, VESIT, University of Mumbai, Mumbai, India
2
Department of Instrumentation Engineering, VESIT, University of Mumbai, Mumbai,
India
{jayamala.adsul, pp.vaidya, principal}@ves.ac.in

Abstract. A new reconfigurable ADC (Analog to Digital Converter) has been

proposed for low conversion time and high resolution. An ADC gives optimum
resolution and conversion time as required by the user. The proposed design
works like a flash ADC as well as subranging ADC to give high speed at low
resolution and high resolution at low speed, respectively. It is possible to make
a flash ADC of resolution as high as 8-bit working at hundreds of MHz
frequency and ADC having a resolution of up to 20-bit with few us conversion
time using the method suggested in the paper. To verify the working of
reconfigurable ADC, an ADC has been designed and simulated using NI
Multisim 14.1 for giving a resolution of 4-bit, 6-bit,10-bit, and 12-bit. The
reconfigurability is achieved by selecting the condition of analog switches
which is programmable, as explained in the paper.

Keywords: Flash ADC, Subranging ADC, Priority encoder, Recirculating

ADC, Figure of Merit

1 Introduction

The different types of conventional ADCs (flash, pipeline, successive approximation,

subranging, delta-sigma, etc.) have fixed resolution and fixed conversion time, so
these conventional ADCs won’t be useful for extensive range of applications [1],[2],
[3],[4]. Also, researchers have designed different types of reconfigurable ADCs
whose resolution and operating speed can be varied, but its reconfigurability factor is
small, i.e., the range of application is narrow [5],[6],[7],[8],[9],10].

This reconfigurability factor can be improved by designing a single ADC [11] for a
wide range of applications (high resolution, low speed, medium resolution, medium
speed, and low resolution high speed). Fig.1 shows many high speed applications
(Satellite Communication, Radar Processing, Video, IF Sampling, Software Radio,
etc.) in the range of high hundreds MHz where flash ADC is useful and high
resolution applications (Data Acquisition, Measurement, Instrumentation, etc.) in the
range of 8-bit to 20-bit where subranging and interpolation ADCs are useful.
Generally, in this range of resolution, successive-approximation (SAR), sigma-delta
ADCs are useful. So to achieve conversion for extensive range of applications(High
speed Low resolution -High resolution Low speed), a single ADC which is
reconfigurable can be designed. The flash ADC is a basic block in the subranging
ADCs. This flash ADC consists of a resistive string, comparators, and priority
encoders, while subranging ADC consists of flash ADCs, DACs (Digital to Analog
converter), and residue amplifiers. The same building blocks are configured in
different ways to achieve the operation of flash ADC, subranging ADC, and
interpolation ADC.

Fig. 1. Application of flash and subranging ADC [1],[2],[3],[4],[12],13]

2 A New Proposed Design

In this paper a new ADC architecture has been introduced that makes use of same
hardware in a flash and subranging ADC to capably adapt the operation at the
architectural level, to obtain ADC with optimum resolution, conversion time as
required for the specific application. The novel hybrid flash/subranging /interpolation
ADC is designed and simulated using NI Multisim 14.1, and results are presented.

A new ADC design has been conceptualized, which is shown in Fig. 2. This would
be useful for extensive range of applications as its resolution can be adjusted as 4-bit,
6-bit, 8-bit, 10-bit, 12-bit, and 16-bit with different conversion times. A single
reconfigurable ADC consists of basic components such as 16 comparators, 15 residue
amplifiers (gain 2), a 16-bit DAC, priority encoders, and a resistive string of 16
resistors. These components could be arranged and interconnected to obtain the
required resolution and conversion time. This would behave as 4-bit flash ADC, 6-bit
subranging ADC, 8-bit recirculating ADC, 10-bit subranging ADC, 12-bit
interpolation ADC, 16-bit subranging ADC and 20-bit interpolation ADC.

2
 Fig. 2. Reconfiguration of ADC

Generally, conventional reconfigurable designs are implemented using discrete

components in hardware which are reconfigured manually to achieve the different
configurations of ADC. But in this proposed design, interconnection is done
automatically through programmable devices to achieve the different configurations
of ADC, as shown in Fig.2.

2.1 Reconfiguration for 4-bit flash ADC

This is an architectural reconfiguration of ADC. For 4-bit flash, ADC as shown in

Fig.3, the components requirement generally are 24 -1 comparators (15),16 resistors,
and priority encoder. So these components are interconnected, as shown in Fig.3,
which converts the input signal with a 4-bit resolution and lower conversion time. The
resistive string is formed with 16 resistors to generate reference voltage (ref1to ref15)
for comparators (C1 to C15). The output of each comparator (LSB1 to LSB15) is
given as an input to the priority encoder to obtain 4-bit (b0 to b3) digital signal. So
this is like a conventional flash ADC which provides low resolution and high
frequency conversion. The conversion time for this 4-bit resolution is T which nearly
equal to comparator response time + priority encoder propagation delay.

2.2 Reconfiguration for 6-bit subranging ADC

For 6-bit subranging ADC, the basic components mentioned in Fig.2 are
interconnected as two 3-bit flash ADC as shown in Fig.4. It consists of two 3-bit flash
ADC, subtractor, residue amplifier, and a 16-bit DAC. So each 3-bit flash consists of
a resistive string of 8 resistors, 23 -1 comparators (7), and a priority encoder.

3
 Fig. 3. 4-bit flash ADC

Fig. 4. Two stage 6-bit subranging ADC

The resistive string is divided into two strings to generate reference voltage for
each 3-bit flash ADC comparator. In the first clock, Vin input signal is converted by
the first 3-bit flash ADC to obtain 3 MSB bits (b0 to b2), and this digital output is
given as an input to a 16-bit DAC (MSB bits of DAC) while the remaining lower bits
of DAC are kept at 0 logic. This DAC output is subtracted from Vin input signal to
extract the remainder signal. This remainder signal is amplified by a gain of 8. This
gain of 8 is achieved by connecting 3 residue amplifiers(gain 2) in a cascade. The
residue has been amplified to obtain the residue signal in the full scale range. Then in
the second clock, the remaining 3 LSB bits (b3to b5) are obtained by converting the
amplified residue signal by the second 3-bit flash ADC. So the conversion is
complete for the current sample, and again this 6-bit subranging ADC is ready to
accept the new sample for conversion. The conversion time for this 6-bit resolution is
2T+16-bit DAC settling time+4opamps setting time.

4
2.3 Reconfiguration for 8-bit recirculating type ADC

For 8-bit recirculating type ADC, the basic components are interconnected as 4-bit
flash ADC followed by a 16-bit DAC and residue amplifiers, as shown in Fig.5. This
4-bit flash ADC internal circuit will be the same as the circuit shown in Fig.3 with
additional components, subtractor, latch and sample and hold amplifier. In the first
clock, Vin input signal is converted by 4-bit flash ADC to obtain 4 MSB bits (b0 to
b3), and it is latched. This digital output is given as an input to a 16-bit DAC (MSB
bits of DAC) while the remaining lower bits of DAC are kept at 0 logic. This DAC
output is subtracted from Vin input signal to extract the remainder signal. This
remainder signal is amplified by a gain of 16. This gain of 16 is achieved by
connecting 4 residue amplifiers (gain 2) in a cascade.

Fig.5. 8-bit recirculating ADC

The residue has been amplified to obtain the residue signal in the full scale range.
Then in the second clock, the remaining 4 LSB bits (b4 to b7) are obtained by
converting the amplified residue signal by the same 4-bit flash ADC. Then the
conversion is complete for the current sample, and again this 8-bit recirculating type
ADC is ready to accept the new sample for conversion. The conversion time for this
8-bit resolution is 2T+16-bit DAC settling time+5opamps setting time.

2.4 Reconfiguration for 10-bit subranging ADC

For 10-bit subranging ADC, the basic components mentioned in Fig.2 are
interconnected as five 2-bit flash ADC as shown in Fig.6. It consists of five 2-bit flash
ADC, subtractor, residue amplifier, and a 16-bit DAC. So each 2-bit flash consists of
a resistive string of 4 resistors, 22 -1 comparators (3), and a priority encoder.

5
 Fig.6. 10-bit subranging ADC

The resistive string is divided into five strings to generate reference voltage for
each 2-bit flash ADC comparator. In the first clock, Vin input signal is converted by
the first 2-bit flash ADC to obtain 2 MSB bits (b0 to b1), and this digital output is
given as an input to a 16-bit DAC (MSB bits of DAC) while remaining lower bits of
DAC are kept at 0 logic. This DAC output is subtracted from Vin input signal to
extract the remainder signal. This remainder signal is amplified by a gain of 4. This
gain of 4 is achieved by connecting 2 residue amplifiers(gain 2) in a cascade. The
residue has been amplified to obtain the residue signal1 in the full scale range. Then
in the second clock, the next 2 bits(b2 to b3 ) are obtained by converting the amplified
residue signal1 by second 2-bit flash ADC, and this digital output is given as an input
to a 16-bit DAC (next 2bits of DAC) while remaining lower bits of DAC are kept at 0
logic. This DAC output is subtracted from Vin input signal to extract the remainder
signal. This remainder signal is amplified by a gain of 16. This gain of 16 is achieved
by connecting 4 residue amplifiers (gain 2) in a cascade. The residue has been
amplified to obtain the residue signal2 in the full scale range. Then in the third clock,
the next 2 bits (b4 to b5) are obtained by converting the amplified residue signal2 by
the third 2-bit flash ADC, and this digital output is given as an input to a 16-bit DAC
(next 2bits of DAC) while remaining lower bits of DAC are kept at 0 logic. This DAC
output is subtracted from Vin input signal to extract the remainder signal. This
remainder signal is amplified by a gain of 64. This gain of 64 is achieved by
connecting 6 residue amplifiers (gain 2) in a cascade. The residue has been amplified
to obtain the residue signal3 in the full scale range.

Then in the fourth clock, the next 2 bits (b6 to b7) are obtained by converting the
amplified residue signal3 by the fourth 2-bit flash ADC, and this digital output is
given as an input to 16-bit DAC (next 2bits of DAC) while remaining lower bits of
DAC are kept at 0 logic. This DAC output is subtracted from Vin input signal to
extract the remainder signal. This remainder signal is amplified by a gain of 256. This
gain of 256 is achieved by connecting 8 residue amplifiers (gain 2) in a cascade. The
residue has been amplified to obtain the residue signal4 in the full scale range. Then
in the fifth clock, the LSB 2 bits (b8 to b9) are obtained by converting the amplified

6
residue signal4 by the fifth 2-bit flash ADC. The conversion is complete for the
current sample, and again this 10-bit subranging ADC is ready to accept the new
sample for conversion. The conversion time for this 10-bit resolution is 5T+16-bit
DAC settling time+9opamps setting time.

2.5 Reconfiguration for 12-bit interpolation ADC

For 12-bit interpolation ADC, the subranging ADC, which has been designed for 10-
bit resolution, is used to convert the signal with a 12-bit resolution by adding circuits
such as 12-bit DAC, analog adder, latches, counter, and a digital comparator. Fig.7.
shows the block diagram of extension of 10-bit resolution into 12-bit.

Fig.7. 12-bit interpolation ADC

The 12-bit DAC output is incremented by LSB equivalent to 12-bit, i.e.2.44mV,

and is added with an analog input (to be converted into 12-bit digital output). Then
the output of the adder is converted into 10-bit, which are MSBs of 12-bit, and the 10-
bit data, which is initially obtained with only analog input, is latched and compared
with the next samples while the counter which is initially loaded with 11 data, starts
counting down. If the next sampled 10-bits are greater than the latched 10-bits, then
the counter stops counting, and the last count is the last 2LSB bits of 12-bit ADC.
Here MSB 10-bits are b0 to b9, and LSB 2-bits are counter output (b10 to b11). This
concept can be extended to more no. of bits at the cost of speed of operation. The
conversion time for this 12-bit resolution is 5T+16-bit DAC settling time+9opamps
setting time+12-bit DAC settling time+ propagation delay of digital comparators and
2-bit counter.

2.6 Reconfiguration for 16-bit subranging ADC

For 16-bit subranging ADC, the basic components mentioned in Fig.2 could be
interconnected as 16 1-bit flash ADC as shown in Fig.8. It consists of 16 1-bit flash
ADC(1comparator), subtractor, residue amplifier, and a 16-bit DAC. So each 1-bit
flash consists of 21-1 comparators(1). The resistive string is made of 2 resistors to

7
generate reference voltage for each 1-bit flash ADC comparator. The working
principle of this 16-bit ADC is the same as 10-bit ADC.

Fig. 8. 16-bit subranging ADC

Here in every clock, 1-bit is obtained, so it takes 16 clocks to obtain the 16-bit
digital output. This ADC doesn’t require any priority encoder, the output of the
comparator itself is the digital output. The conversion time for this 16-bit resolution is
16 comparators settling time +16-bit DAC settling time+17opamps setting time. For
20-bit interpolation ADC, the subranging ADC, which has been designed for 16-bit
resolution, is used to convert the signal with the 20-bit resolution by adding circuits
such as 20-bit DAC, analog adder, 16-bit latch, 20-bit counter, 16-bit digital
comparator, and 4-bit counter. The block diagram for 20-bit interpolation ADC would
be similar to 12-bit interpolation ADC, as shown in Fig. 7.

3. Design of the switches to configure resistive string, input signal,

and residue signals

The reconfigurability of ADC is achieved automatically by configuring the

interconnection among the components through different switches. A reconfigurable
ADC has been designed and simulated using NI Multisim 14.1 for giving a resolution
of 4-bit,6-bit,10-bit, and 12-bit. So, in this section configuration of switches for a
resistive string and an input signal for comparators (4-bit,6-bit, and 10-bit resolution)
is described.

8
3.1 Arrangement of basic components

Fig.9. shows the arrangement of 15 comparators and a resistive string of 16 resistors

(additional few resistors for reconfigurability) in 5 stages. Each stage (1-5) includes 3
comparators and 4 resistors. Users can program the resolution and conversion time of
the proposed ADC by changing the control signals named as 4or6bit, and EN
mentioned in Table 1.

Fig. 9. Arrangement of comparators and resistive string in 5 stages

9
 Table 1. Selection of control signal

EN 4or6bit Resolution
0 0 4-bit
0 1 6-bit
1 0 10-bit
1 1 12-bit

For 4-bit resolution the user can give control signal 4or6bit = 0 and EN = 0.For 6-bit
resolution 4or6bit =1and EN= 0. For10-bit resolution 4or6bit = 0 and EN=1. For 12-
bit resolution 4or6 bit = 1 and EN=1.

3.2 Switches for resistive string configuration for 4-bit flash ADC

Fig.10. shows analog switches used to configure the connection of resistive string for
4-bit flash ADC according to a conventional 4-bit flash ADC. So, according to this
conventional 4-bit flash ADC, these 16 resistors are connected to each other in series
to generate the reference voltages ref1 (LSB) to ref15 (MSB).
Fig. 10. Control signals and switches for resistive string configuration for 4-bit flash ADC

So, to obtain the connectivity of 16 resistors in series, Table 2 shows the

interconnection among the stages (1 to 5) through different switches(SW1 to SW6).

Table 2 Interconnection of different signals for 4-bit flash ADC resistive string

Switch Control signal Signal1 Signal2

SW1 eninv ref12 of stage2 8bitgnd1 of stage1
SW2 eninv ref9 of stage3 8bitgnd2 of stage2
SW3 6bitbreak1 ref8 of stage3 6bitgnd1 of stage3
SW4 eninv ref6 of stage 4 8bitgnd3 of stage3
SW5 eninv ref3 of stage 5 8bitgnd4 of stage4
SW6 6bitbreak1 6bitgnd2 of stage5 ref1 of stage 5

10
 Now all the resistors are connected in series through switches (SW1 to SW6) to
provide the 15 reference voltages for all 15 comparators like conventional 4-bit flash
ADC.

3.3 Switches for resistive string configuration for 6-bit 2 stage subranging ADC

Fig.11 shows analog switches used to configure the connection of resistive string for
6-bit two stage subranging ADC similar to conventional 6-bit subranging ADC. Each
stage consists of 3-bit flash ADC. According to this conventional 6-bit two stage
subranging ADC these 16 resistors are divided into two strings (8+8) for each 3-bit
flash ADC.

Fig. 11. Switches for resistive string configuration for 6-bit 2 stage subranging ADC

So, to obtain the connectivity of (8+8) resistors in two stages, Table 3 shows the
interconnection among the stages (1 to 5) through different switches (SW7 to SW13)
where some of the switches are common (SW7,SW8,SW11, and SW12).

Table 3 Interconnection of different signals for 6-bit two stage subranging ADC
resistive string
Switch Control Signal1 Signal2
signal
SW7(SW1) eninv ref12 of stage2 8bitgnd1 of stage1
SW8(SW2) eninv ref9 of stage3 8bitgnd2 of stage2
SW9 4bitconnect ground 6bitgnd1 of stage3
SW10 4bitconnect 6bitref1 of stage3 ref8 of stage 3
SW11(SW4 eninv ref6 of stage 4 8bitgnd3 of stage3
)
SW12(SW5 eninv ref3 of stage 5 8bitgnd4 of stage4
)
SW13 4bitconnect ground 6bitgnd2 of stage5

11
3.4 Switches for resistive string configuration for 10-bit 5 stage subranging ADC

Fig.12 shows analog switches used to configure the connection of resistive string for
10-bit five stage subranging ADC similar to a conventional 10-bit subranging ADC.
Each stage consists of 2-bit flash ADC. According to this conventional 10-bit, five
stage subranging ADC, these 16 resistors are divided into five strings (4+4+4+4+4)
for each flash ADC.

Fig. 12. Switches for resistive string configuration for 10-bit 5 stage subranging ADC

So, to obtain the connectivity of (4+4+4+4+4) resistors in five stages, Table 4

shows the interconnection among the stages (1 to 5) through different switches
(SW14 to SW23) where switch SW23 is common.

Table 4. Interconnection of different signals for 10-bit five stage subranging ADC resistive
string

Switch Control signal Signal1 Signal2

SW14 EN ground 8bitgnd1 of stage1
SW15 EN 8bitref1(Ref voltage) ref12 of stage2
SW16 EN ground 8bitgnd2 of stage2
SW17 EN 8bitref2(Ref voltage) ref9 of stage 3
SW18 6bitbreak1 ref8 of stage 3 6bitgnd1 of stage3
SW19 EN ground 8bitgnd3 of stage3
SW20 EN 8bitref3(Ref voltage) ref6 of stage4
SW21 EN ground 8bitgnd4 of stage4
SW22 EN 10bitref4(ref voltage) ref3 of stage5
SW23(SW6) 6bitbreak1 6bitgnd2 of stage5 ref1 of stage5

12
3.5 Switches for comparator input signal configuration (4-bit flash ADC)

Fig.13 shows switches (SW24 to SW 30) to apply the input for 4-bit flash ADC.

Fig. 13. Switches to configure input for comparators for 4-bit flash ADC

Table 5 shows the connection between input signals through switches (SW24 to
SW 30)for 4-bit flash ADC.

Table 5 Interconnection of different signals for 4-bit flash ADC comparators input signal
Switch Control signal Signal1 Signal2
SW24 4bvin stepvin(input vin1(input to comparators of stage1)
signal)
SW25 4bvin stepvin(input vin2(input to comparators of stage2)
signal)
SW26 4bvin stepvin(input vin31(input to comparators of
signal) stage3)
SW27 4bvin stepvin(input vin32(input to comparators of
signal) stage3)
SW28 4bvin stepvin(input vin4 (input to comparators of stage4)
signal)
SW29 4bvin stepvin(input vin51(input to comparators of
signal) stage5)
SW30 4bvin stepvin(input vin52(input to comparators of
signal) stage5)

3.6 Switches for comparator input signal configuration (6-bit subranging ADC)

Fig.14. shows switches (SW31 to SW36) to apply input for 6-bit two stage
subranging ADC.

13
 Fig. 14. Switches to configure input for comparators for 6-bit two stage subranging ADC

Table 6 shows connections among different terminals through switches (SW31 to

SW 36) for 6-bit two stage subranging ADC.

Table 6 Interconnection of different signals for 6-bit 2 stage subranging ADC comparators
input signal

Switch Control signal Signal1 Signal2

SW31 6and10bvin vinhold (sampled input signal) vin1 (input to comparators of stage1)
SW32 4bitconnect vinhold (sampled input signal) vin2 (input to comparators of stage2)
SW33 4bitconnect vinhold (sampled input signal) vin31(input to comparators of stage3)
SW34 4bitconnect stage2hold (residue signal) vin32 (input to comparators of stage3)
SW35 4bitconnect stage2hold (residue signal)) vin4 (input to comparators of stage4)
SW36 4bitconnect stage2hold (residue signal) vin51(input to comparators of stage5)

3.7 Switches for comparator input signal configuration (10-bit subranging ADC)

Fig.15 shows switches (SW 37 to SW 43) to apply input for 10-bit five stage
subranging ADC.

14
 Fig. 15. Switches to configure input for comparators for 10-bit five stage subranging ADC

Table 7 shows connection among different terminals through switches (SW37 to

SW43) for 10-bit five stage subranging ADC

Table 7 Interconnection of different signals for 10-bit 5 stage subranging ADC comparators
input signal

Switch Control Signal1 Signal2

signal
SW37 6and10bvin vinhold(sampled input signal) vin1(input to comparators of stage1)
SW38 EN stage2hold(residue signal) vin2(input to comparators of stage2)
SW39 EN stage3hold(residue signal) vin31(input to comparators of stage3)
SW40 EN stage3hold(residue signal) vin32(input to comparators of stage3)
SW41 EN stage4hold(residue signal)) vin4 (input to comparators of stage4)
SW42 EN stage5hold(residue signal) vin51(input to comparators of stage5)
SW43 EN stage5hold(residue signal) vin52(input to comparators of stage5)

Similarly, the configuration of switches could be designed for the remaining

resolution(8-bit, 16-bit, and 20-bit) for a wide range of applications which has not
been simulated here.

4. Timing analysis of reconfigurable ADC

Fig.16. shows timing analysis for the various resolution of ADCs such as 4-bit, 6-bit,
8-bit, 10-bit, 12-bit, and 16-bit. It shows as resolution increases the conversion time of
reconfigurable ADC also increases.

15
 Fig.16. Timing analysis of reconfigurable ADC

Table 8 shows the conversion time for each type of ADC.

Table 8. Resolution and conversion time of ADCs

Resolutio Conversion time
n
4-bit comparator settling time + priority encoder propagation delay = T(<ns)
6-bit 2T+ 16-bit DAC settling time(T1) + 4 opamps settling time(4T2)
8-bit 2T+ T1 + 5T2
10-bit 5T+ T1 + 9T2
12-bit 5T+ T1 + 9T2+ 12-bit DAC settling time+ propagation delay (digital
comparator & 2-bit counter)
16-bit 16 comparators settling time + T1 + 17 T2

5. Validation
Table 9 to Table 12 shows validation for 4-bit flash ADC, 6-bit 2stage
subranging,10-bit 5stage subranging ADC and 12-bit interpolation ADC for different
input signals with 1LSB error, respectively.

16
 Table 9. Validation of 4-bit flash ADC (b0-b3)

b b b b b4 b5 b6 b7 b8 b9 Vin(V)
0 1 2 3
0 0 0 1 0 0 0 0 0 0 0.625
0 0 1 0 0 0 0 0 0 0 1.25
0 0 1 1 0 0 0 0 0 0 1.88
0 1 0 0 0 0 0 0 0 0 2.5
1 0 0 0 0 0 0 0 0 0 5
1 0 0 1 0 0 0 0 0 0 6.25

Table 10.Validation of 6-bit 2 stage subranging ADC (b0-b5)

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 Vin(V)
0 0 0 0 0 1 0 0 0 0 0.15625
0 0 0 0 1 0 0 0 0 0 0.3125
0 0 0 0 1 1 0 0 0 0 0.46875
0 0 0 1 0 0 0 0 0 0 0.625
0 0 0 0 1 1 0 0 0 0 1.25
0 0 1 1 1 1 0 0 0 0 2.5

Table 11 Validation of 10-bit 5 stage subranging ADC (b0-b9)

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 Vin(V)
0 0 0 0 0 0 0 0 0 1 0.0097
0 0 0 0 0 0 0 0 1 0 0.0195
0 0 0 0 0 0 0 1 0 0 0.0293
0 0 1 0 0 0 0 0 0 0 1.25
0 0 1 0 0 0 0 0 0 1 1.26
0 0 1 0 0 0 0 0 0 1 1.27

Table 12 Validation of 12-bit interpolation ADC (b0-b11)

b b b b b b b b b b b1 b1 Vin(V
0 1 2 3 4 5 6 7 8 9 0 1 )
0 0 0 0 0 0 0 0 1 0 1 0 25m
0 0 0 0 0 0 0 1 0 1 1 0 55m
0 0 0 0 1 1 0 0 1 1 1 1 0.508
0 0 0 1 1 0 0 1 1 1 0 1 1.01
1 0 0 0 0 0 0 0 0 0 0 0 5.00
1 0 0 0 0 0 0 0 0 0 0 1 5.003

6. Figure of Merit

17
Figure of merit of a reconfigurable ADC is defined in different ways by various
researchers depending upon the targeted applications. For example, some researchers
[9], [14] have defined FOM as:

Their application is targeted towards optimisation of power for achieving

reconfigurability.
where PADC is the total power consumption, BW is the input signal bandwidth, and
ENOB is the effective number of bits of the ADC. Similarly other researchers have
defined FOM[6] as:
FOM = 22N x (Data Rate) / Power. (2)
Also, according to researcher the ADC flexibility can be measured by its wide
resolution, bandwidth and it is defined as reconfigurability factor (RF) [15] which is
proposed here:
RF = (2ENOB,max / 2ENOB,min) / (fs,max / fs,min ). (3)
In most of the reconfigurable ADC research papers, the power is optimized while
reconfiguring resolution and bandwidth by keeping unused stages in standby mode
and/or designing low power components used in ADCs. But in this proposed design,
the main objective is to reconfigure the resolution and conversion time to meet a wide
range of applications. So here, a new figure of merit is proposed:

FOM = (fs,max x No. of Possible Resolutions ). (4)

Where fs,max - highest sampling rate

The fs,max can be as high as 100MHz, lowest sampling rate can be as low as dc,
maximum resolution can be as large as 20-bit and min can be 1-bit. Also, in this
proposed design PADC can be optimized while reconfiguring resolution and bandwidth
by keeping unused stages in the standby mode, then the FOM can be defined as:
FOM = (fs,max x No. of Possible Resolutions ) / PADC. (5)

7. Conclusion and Future Scope

The new hybrid flash-subranging ADC combines features of the conventional 4-
bit flash ADC and the sub-ranging ADC topologies to achieve flexibility of operation
well suited to many high speed and high resolution applications. This design has been
simulated and validated in NI Multisim 14.1, which proves the functionality of the
proposed concept. This reconfigurable ADC utilises all comparators to achieve 4-bit,
6-bit, 10-bit, and 12-bit resolution instead of keeping those comparators in standby
mode. So hardware utilisation while reconfiguring the parameters is optimum. But to
meet the specific high speed and high resolution applications, it is desirable to
implement in VLSI.

18
 References
1. MT-020: ADC Architectures I: The Flash Converter. Analog Devices by Walt Kester,
https://www.analog.com/media/en/training-seminars/tutorials/MT-020.pdf (accessed
on 21 June 2021)
2. MT-024: ADC Architectures V: Pipelined Subranging ADCs, Analog devices by Walt
Kester, https://www.analog.com/media/en/training-seminars/tutorials/MT024.pdf (accessed
on 21 June 2021)
3. MT-021 ADC Architectures II: Successive Approximation ADCs. Analog devices by Walt
Kester,https://www.analog.com/media/en/training-seminars/tutorials/MT-021.pdf (accessed
on 21 June 2021)
4. MT-022: ADC Architectures III, Sigma-Delta ADC Basics. Analog devices by Walt
Kester,https://www.analog.com/media/en/training-seminars/tutorials/MT-022.pdf (accessed
on 21 June 2021)
5. Jincheol Yoo, Daegyu Lee, Kyusun Choi, Jongsoo Kim: A power and resolution adaptive
flash analog-to-digital converter: Proceedings of the International Symposium on Low
Power Electronics and Design (2002). https://doi.org/10.1109/LPE.2002.146744
6. Kush Gulati, Hae-Seung Lee: A Low-Power Reconfigurable Analog-to-Digital Converter:
IEEE Journal of Solid-State Circuits, VOL. 36, NO. 12 (2001) pp. 54-55.
https://doi.org/10.1109/4.972140
7. Cheong Kun, Andrew Mason, Shantanu Chakrabartty: A Dynamic Reconfigurable A/D
Converter for Sensor Applications: Sensors, IEEE (2005) pp.4.
https://doi.org/10.1109/ICSENS.2005.1597926

8. Salwa Mostafa, Wenchao Qu and Syed K. Islam, Mohamed Mahfouz: A Calibration

Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing: IEEE Computer
Society Annual Symposium on VLSI (2010) pp.185-189.
https://doi.org/10.1109/ISVLSI.2010.85
9. Mohammad Taherzadeh-Sani and Anas A. Hamoui: A Reconfigurable and Power-Scalable
10–12 Bit 0.4–44 MS/s Pipelined ADC With 0.35–0.5 pJ/Step in 1.2 V 90 nm Digital
CMOS: IEEE Transactions on Circuits and Systems I (2012)
https://doi.org/10.1109/TCSI.2012.2215712
10. Aleksandar Stojcevski, Jugdutt Singh, Aladin Zayegh: Scalable Pipeline Analog-to-Digital
Converter for UTRA-TDD Mobile Station Receiver: 9th International Conference on
Neural Information Processing. Computational Intelligence for the E-Age (2002) 19-21.
https://doi.org/10.1109/SMELEC.2002.1217844
11. Kush Gulati: Low Power Reconfigurable Analog-to-Digital Converters: Cambridge Analog
Technologies, Inc. Bedford, Massachusetts, Sixth IEEE Dallas Circuits and Systems
Workshop (2007) 1-8. https://doi.org/10.1109/DCAS.2007.4433193
12. K V Shriram,K Venkateshwaran, V Vaithiyanathan, V Subashri: Design of analog to digital
converter for SDR: International Conference for Internet Technology and Secured
Transactions (2009) https://doi.org/10.1109/ICITST.2009.5402602
13. Shohreh Ghetmiri, C. A. T. Salama: An 8-bit 12.5-GSample/s SiGe ADC: Analog

19
 Integrated Circuits and Signal Processing (2009)
https://doi.org/10.1007/s10470-009-9422-7
14. Schekeb Fateh, Philipp Schönle, Luca Bettini, Giovanni Rovere, Luca Benini, Qiuting
Huang: A Reconfigurable 5-to-14-bit SAR ADC for Battery-Powered Medical
Instrumentation: IEEE Transactions on Circuits and Systems I (2015)
https://doi.org/10.1109/TCSI.2015.2477580
15. Ramy Yousry, Ming-Shuan Chen, Mau-Chung Frank Chang, and Chih-Kong Ken Yang:
An Architecture- Reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC Using Subtractor
Interleaving: IEEE Asian Solid- State Circuits Conference (2013)
https://doi.org/10.1109/ASSCC.2013.6691038

20