INPUT OUTPUT ORGANIZATION Sheet

(Q1) A computer consists of a CPU and an IO device D connected to main memory M via a one-
word shared bus. The CPU can execute a maximum of 105 instructions/sec. An average
instruction requires five machine cycles, three of which use the memory bus. A memory read
or write operation uses one machine cycle. Suppose that the CPU is continuously executing
"background" programs that require programs that require 95% is to be used to transfer very
large blocks of data to and from M.
a. If programmed IO is used and each one-word IO transfer requires the CPU to execute
two instructions, estimate the maximum IO data-transfer rate Tmax possible through D.
b. Estimate Tmax if DMA transfer is used.

Answer:
CPU instructions execution rate = 105 instructions/second
An average instruction use 5 cycles where 3 cycles of them use memory bus
95% of instructions are dedicated for  memory operations
∴ Only 5% of instructions  for I/O operations

a- For Programmed IO:

5% of instructions for I/O operations

5
∴ I/O instructions execution rate = 105 × = 5000 instructions/sec
100

Each Word transfer needs  execute two instructions

5000
∴ Maximum I/O data transfer rate “Tmax” = = 𝟐𝟓𝟎𝟎 word/sec
2

b- For DMA:
DMA controller can use cycles where CPU doesn’t need memory bus, to transfer one
word /cycle

For 95% of CPU instructions

Instruction use 5 cycles where 3 cycles of them use memory bus
Only 2 cycles available for DMA controller to use

95
∴ Number of CPU cycles available for DMA = × 105 × 2 = 𝟏𝟗𝟎𝟎𝟎𝟎 cycles
100
 For 5% of CPU instructions
CPU doesn’t perform memory operations and doesn’t need the memory BUS
So, DMA can use all cycles (5 cycles)

5
∴ Number of CPU cycles available for DMA = × 105 × 5 = 𝟐𝟓𝟎𝟎𝟎 cycles
100

ASSUME THAT DMA TRANSFER ONE WORD / CYCLE

∴ Maximum I/O data transfer rate “Tmax” = 190000 + 25000 = 215000 words/sec

(Q2) Is it necessary to have a separate IO chip for each peripheral in the system? If not, how
would this be handled? Where would any additional circuitry be located?
Answer:
It’s not necessary to use a separate IO interface chip for each peripheral device to connect it to
the bus, We can use a 8255 PPI chip to connect multiple peripheral devices to the bus

(Q3) A CPU has a four MB common address space for both memory and IO. It is to be used in
an application where memory capacity will never exceed 2MB.
a. How would you divide the address space between memory and IO so that, the distinction
between memory and IO addresses (by the hardware) becomes very simple?
Answer: using memory mapped I/O addressing where Memory and IO devices share
the address space, 2 MB addresses are dedicated for memory and the other 2MB
addresses for IO devices

b. Assume we need a separate select signal for each 256 KB of memory. Show how you would
generate the memory select signals.
Answer:
Divide memory to blocks where each block is 256 KB
No. of Blocks= 2MB/256KB = 8 Blocks = (23 )
To generate Memory select signals use 3 lines (form Most Significant Bits)
(Q4) What happens in the daisy chain priority interrupt, Fig.57, when device 1 requests an
interrupt after device 2 has sent an interrupt request to the CPU but before the CPU responds
with the interrupt acknowledge?
D1 receives ACK signal (PI=1) and blocks the ACK signal from next devices including D2 by
placing ‘0’ in PO, and sends its own VAD to CPU, So CPU will perform Interrupt Service Routine
of Device 1 (with highest priority).

(Q5) It is necessary to transfer 256 words from a magnetic disk to a memory section starting
from address 1230. The transfer is by means of a DMA.
a. Give the initial values that the CPU must transfer to the DMA controller.
CPU will transfer the following data to DMA controller:
 256  for DC register (Data Count)
 1230  for IOAR register (Address Register)
 Bits corresponding to WRITE operation  for Control register

b. Give the step-by-step account of the actions taken during the input of the 1st two
words.
Answer: DMA TRANSFER
1- IO device(magnetic disk) sends DMA REQUEST to DMA controller
2- DMA enable “BUS REQUEST” BR line to CPU
3- CPU responds by enabling “BUS GRANTED” BG line (high impedance)
4- After DMA registers have been setup, DMA locates address 1230 on address lines
and activate write line for memory and sends DMA ACK to magnetic disk
5- Magnetic disk locates data on data lines
6- After first word transferred, IOAR is automatically incremented to be 1231 and DC
is automatically decremented to be 255
7- Repeat 5 and 6 until all words have been transferred and DC reaches ZERO
8- When DC reaches zero, DMA sends an interrupt signal to CPU to use the bus
(Q6) Design a parallel priority interrupt hardware for a system with eight interrupt sources.
Same as Fig.58 but needs 8 AND gates and an 8 × 3 Encoder where the output of the priority
encoder circuit is A0,A1,A2 and V

(Q7) The three outputs xyz, from the priority encoder are used to provide an 8-bit vector
address in the form 101xyz00. List the eight addresses starting from the one with the highest
priority.
101 000 00 Vector Address for Device0 (Highest Priority)
101 001 00 VAD1
101 010 00 VAD2
101 011 00 VAD3
101 100 00 VAD4
101 101 00 VAD5
101 110 00 VAD6
101 111 00 VAD7