SCHOOL OF ELECTRICAL ENGINEERING

LAB MANUAL / RECORD

On

BEEE 211E
VLSI DESIGN LABORATORY

Name: Utsav Bajaj

Register Number: 21BEI0017
Lab Slot: L29 + L30

This work is submitted in partial fulfilment of the requirement of the award of the degree of
Bachelor of Technology in EEE/EIE

Internal Examiner External Examiner

 INDEX

Sl.No Date Title Marks Page No.

1. 12/1/24 4-BIT RIPPLE CARRY ADDER

2 19/1/24 CARRY LOOK AHEAD ADDER

10

11
Objectives:
• Comprehend the digital VLSI concepts, circuit design and principles
• Understand the design concepts and architecture underlying modern complex
VLSI
• Gain sufficient knowledge on the methodologies and design techniques related
to digital integrated circuits

Outcomes:
On completion of this course, the students will be able to
• Design digital logic circuits using CMOS logic
• Analyze and design digital logic circuits for optimal delay and power
• Design and implement combinational logic circuits using different logic styles
• Design and develop complex arithmetic circuit architectures for various real-
time applications
Exp.No: 2
Date: 19/1/24

CARRY LOOK AHEAD ADDER

AIM:
Design a carry look ahead adder using four full adder circuit.

REQUIRED SOFTWARE:
Xilinx design tool

CIRCUIT DIAGRAM:
Design Code:

Verilog module
module cla(input [3:0]a,b,input cin, output[4:0]s);

wire [3:0]p,g;

wire [4:0]c;

assign p=a^b;

assign g=a&b;

assign c[0]=cin;

assign c[1] = (p[0]&c[0])|g[0];

assign c[2] = (p[1]&p[0]&c[0])|(p[1]&g[0])|g[1];

assign c[3] = (p[2]&p[1]&p[0]&c[0])|(p[2]&p[1]&g[0])|(p[2]&g[1])|g[2];

assign c[4] = (p[3]&p[2]&p[1]&p[0]&c[0])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&g[1])|(p[3]&g[2])|g[3];

assign s[3:0] = p^c[3:0];

assign s[4] = c[4];

endmodule

TESTBENCH:
module cla_testbench();

reg[3:0]a,b;

reg cin;

wire[4:0]s;

reg[4:0]check;

cla uut(a,b,cin,s);

initial repeat(10)begin

a=$random;

b=$random;

cin=$random;

check = a+b+cin;

#10;
$display($time,"%d+%d+%d=%d(%d)",a,b,cin,s,check);

end

endmodule

OUTPUT:

CONSOLE OUTPUT
Output Verification

RESULT:
Successfully the carry look ahead adder has been designed and the output
is verified.

INFERENCE:
In this experiment learnt about how to construct multiple-bit adders.