IEEE International Conference on Computer, Communication and Control (IC4-2015).
Implementation of AMBA APB Bridge with Efficient
Deployment of System Resources
Kiran Rawat1 Kanika Sahni2 Sujata Pandey3
Amity University, Amity University, Amity University,
Noida, Noida, Noida, Uttar Pradesh,
Uttar Pradesh, India Uttar Pradesh, India India
kiran.5gemini@gmai kanikasahni27@gma spandey@amity.edu
l.com il.com
Abstract -Themainchallenge for a design engineer is not only
to design a successful SoC with a well-structured and
synthesizable RTL code but also to design it with efficient in
energy and optimized in power consumption. The aim of the
paper is to implementAMBA APB (advanced microcontroller
bus architecture - advanced peripheral bus) Bridge with efficient
deployment of system resources. For this, simulation and
synthesization of the complex bridge interface is designed which
can provide minimum power consumption and low
bandwidthbetween AMBA high speed ASB and low speed APB
buses.Clock is a major concern in designing of any digital
sequential system. Clock skew is introduced when the difference
is generated between the arrival times of clock signal. One of the
approaches to minimize clock skew is ripple counter. One can use
three bit up or down ripple counter approach. APB Bridge with
clock skew minimization technique isimplemented in the paper
using verilog HDL. For the simulation purpose,ModelSim
Version 10.3 has been used. For the synthesization purpose,
design utilization summary and power details Xilinx-ISE design
suite, version 13.4 has been used.Power report is introduced for
developing better understanding of the power utilization in any
system.The power reportgives thepower consumption
summary.Hence, the totalclocks power consumption is of0.39
mW, total hierarchy powerconsumption of 0.57 mWand totalon
chip logical power consumption of 0.113 W have been extracted
from Xilinx XPower analyzer tool when APB bridge is designed
under the proposed design approach.
Keyword used- AMBA; Verilog; System on Chip (SoC); APB
Bridge; IP; ASIC (application specific integrated circuits)
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Jyoti Rawat4 SudhanshuTripathi
Graphic Era 3ST Technologies
University, Pvt. Ltd. ,Noida,
Dehradun, India Uttar Pradesh ,India
jyoti.aries@gmail.co er.sudhanshutripathi
m @gmail.com
I. INTRODUCTION
The feature size of process technology is scaled down day by
day. While designing a block or an Intellectual Property (IP)
of SoC, specific set of recommendations should be planned.
Asarchitectures of SoC have been shifted toadvanced design
approaches,more complexities get introduced into the design
considerations and power consumptiongets introduced into
picture. So, the guidelines should be planned in such a way
that it providesless integration efforts and helps to the
designers for designing a successful SoC with a well-
structured and synthesizable RTL code with efficient in
energy and optimized in power consumption.AMBA which is
known as advanced microcontroller bus architecture is a well
known name in system on chip design considerations in VLSI
domain. Modern portable mobile devices like Smartphone,
hard disk andvariousASIC products cannot evenimagine
without AMBA buses (advanced microcontroller bus
architectures). Simple AMBA Architecture plan is as
following:
Figure 1: Simple AMBA architecture plan [1][6]
 IEEE International Conference on Computer, Communication and Control (IC4-2015).
II. SYSTEM DESIGN
A.Clock Skew Minimization Approach
Though clock net doesn’t have any significant role in digital
computation, it only provides synchronization to the
sequential circuits. But, unnecessary switching activities of
clocks may cause a huge amount of power dissipation around
15% to 50%. So, clock is a major concern in designing of any
digital sequential system. Clock skew is introduced when the
difference is generated between the arrival times of clock
signal. Clock timing concept reveals that the data propagation
delay and clock skew play an important role in clock timing
calculations. Undesired clock skew may potentially cause
timing violations, functional errors or design failures. Clock
skew can be defined in terms of two sequentially adjacent flip
flops (Fa, Fb) which have the clock delay differences (Ta –
Tb) between the first flip flop (Fa) and second flip flop (Fb)
with respect to the clock source. There are various techniques
which can be used to reduce the clock skew. One of the
approaches is known as ripple counter. One can use three bit
up or down counter approach to minimize the clock skew.In
ripple clocking structure, it is quite similar to theripple counter
implementation. In this, output of each flips flop drives the
next flip flop clocking port. That means data output of source
flip flop can only derive the clock of sink flip flop. Though
the flip flops cannot toggle on the same clockhence, this will
reduce the chances of clock skew generation [3].
Figure 2: Three bit ripple down counter approach [3]
In figure 2, the first flip flop is clocked on the positive edge of
clock signal (CLK). Then only the second flip flop is clocked
on the positive edge of the output of the preceding first flip
flop. And, then third flip flop is clocked on the positive edge
of the output of the preceding second flip flop. The simulation
of the approach is shown in results section.
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B.APB Bridge
Advanced Peripheral Bus (APB) Bridge is an essential part in
AMBA shown in Figure 1. Itperforms some operations like
address, data and
control signal latching for connected peripherals [3]. APB
Bridge behaves as single master for the APB bus, shown in
left side of the figure1. APB Bridge performs two important
operations: read and write transfers. Control signal gives the
necessary information whether a read or write transfer is
required for the desired operation. The implementation of
APB Bridge consists of the blocks as: APB state machine
[2][5], Reset Controller [2] and ripple down counter
block.APB state machine and reset controller has been
implemented in somewhere else [4]. Three bit ripple down
counter has been implemented with the help of figure 2 and
connected with the APB Bridge with reset controller [4].
III. SIMULATION RESULTS
For the implementation of various blocks like APB Bridge,
Reset controller and three bit ripple down counter,verilog
HDL is used. For the simulation purpose, ModelSim Version
10.3 has been used. For the synthesization purpose, extraction
of design utilization summary and power reports Xilinx-ISE
design suite, version 13.4 and XPower analyzer tool have
been used.Clock frequency of 50 MHz is considered for the
proposed APB Bridge design simulation.
Figure 3: Simulation result of three bit ripple down counter approach
Figure 3, shows the simulationof the three bit ripple down
counter approach which has been explained in Figure 2.
 IEEE International Conference on Computer, Communication and Control (IC4-2015).

Figure 4, 5, and 6 show the Simulation result of proposed

APB Bridgewith reset controller andthree bit ripple down
counter approach.Hence,by using this approach undesired
clock skew which cause potentially timing violations,
functional errors or design failures can be avoidedupto a
desired level.

Technology view of proposed APB Bridge with reset

controller and three bit ripple down counter approach has been
extracted from Xilinx ISE design suite version 13.4 and
screenshot is shown in figure 7.

Figure 4: Simulation result of proposedAPB Bridge with reset controller and

three bit ripple down counter approach

Figure 5: Simulation result of proposed APB Bridge with reset controller and
three bit ripple down counter approach (continued)

Figure 7: Technology view of APB Bridge with Three bit ripple down
counter approach

IV. CONCLUSION

In this paper,AMBA (Advanced Microcontroller Bus

Architecture) APB (Advanced system bus - Advanced
Peripheral Bus) Bridgeis designed usingVerilog language with
finite state machine modelingand its simulation is performed
in ModelSim version 10.3. Xilinx ISE design suite version
13.4 is used to extract technology view, design summary and
power reports.
Figure 6: Simulation result of proposed APB Bridge with reset controller and
three bit ripple down counter approach (continued)
The objective of the paper was to design an APB bridge with
reset controller and three bit ripple down counter approach for
minimizing the clock skew. Also power reports are included
with the proposed design. Unnecessary switching activities of

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 IEEE International Conference on Computer, Communication and Control (IC4-2015).

clocks may cause a huge amount of power dissipation around x Total on chip power under proposed design approach
15% to 50%. Hence proposed design is used to minimize the is reduced by1.74% than the previous bridge design
clock skew and also provides the less power consumption. with reset controller conditions.
Clock frequency of 50 MHz andKintex 7 FPGA family are
considered for the virtual hardware implementation REFERENCES
purposes.Table 1, is created with thehelp of data collected
from the extracted power report summary. Itgivesthe details
like total clock, hierarchy and on chip powers in the AMBA [1] AMBA Specifications 2.0, Copyright ARM Limited 1999
APB Bridgewhen designed under reset controller and three bit [2] ASB Example AMBA System, Technical Reference Manual.
ripple down counter approach. [3] Springer, The art of hardware architecture, Design method and
techniques for digitals circuits, Arora M, 2012, XV, 221 p. 205 illus.,
Hardcover, ISBN 978-1-4614-0396-8
[4] KiranRawat, KanikaSahni, SujataPandey, “Design of AMBA APB
Frequency Power Report Power Reports Bridge with Reset Controller for Efficient Power Consumption”, 9 th
(MHz) of proposed of previous IEEE International Conference on Industrial and Information System
APB bridge APB bridge (ICIIS2014), Indian Institute of Information Technology and
with reset withonly reset Management, Gwalior, 15-17 December 2014.
[5] KiranRawat, KanikaSahni, SujataPandey,Ziauddin Ahmad “A Novel
controller and controller Low Power Design Approach To Exploit The Power Usage Of AMBA
three bit ripple approach APB Bridge “in 1st International Conference on Recent cognizance in
down counter (W) wireless communication & image processing – ICRCWIP-2014,
approach (W) Springer Publication, Jaipur , 16-17 Jan 2015
[6] KiranRawat, KanikaSahni, SujataPandey, “RTL Implementation for
AMBA ASB APB Protocol at System on Chip Level “in 2nd
Total clock Total clock International Conference on Signal Processing & Integrated Networks",
domain = domain = SPIN 2015, Amity University, Noida, 19-20 Feb 2015
0.00039 0.00043
50

Total Hierarchy Total Hierarchy

power = power =
0.00057 0.00065

Total On chip Total On chip

power = 0.113 power = 0.115

TABLE 1: POWER REPORT COMPARISONS BETWEEN APB BRIDGE WITH THE

PROPOSED DESIGN APPROACH (THREE BIT RIPPLE DOWN COUNTER) AND
PREVIOUS BRIDGE APPROACH

Table 1, represents that only total clock domain power of 0.39

mW, total hierarchy power of 0.57 mWand total on chip
power of 0.113 W are consumed by the proposed design
approach. The difference between the power factors has been
observed when reset controller and three bit ripple down
counter approach is implemented over the AMBA APB
Bridge.The differences can be observed as:

x Total clock domain power under proposed design

approach isreduced by9.30% than the previous bridge
designwith reset controller conditions.
x Total Hierarchy power under proposed design
approach is reduced by12.31% thanthe previous
bridge design with reset controller conditions.

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