Board Manual

C&C08 Digital SPC Switching System B-0304

CKS Clock Board (Combining the Second-level

and Third-level Clock)

Functions
Functioning as the board that generates the reference clock source for the SPCE
clock system, the CKS board contains the second-level high-stability constant
temperature crystal chip. By tracing the external reference signal, screening jitter and
wandering of the external reference signal, it is capable of ensuring the high accuracy
and stability of the timing signal and then supplies the high-quality clock reference to
SPCE. Since the CKS board combines the second-level and third-level clock system
in the board, it can provide either the second-level or the third-level clock as required.
It is capable of providing three types of ports for the input reference signal: 8kHz,
2048kHz and 2048kbit/s. Besides these, it also provides the BITS interface that can
provide both 2048kHz and 2048kbit/s standard output interfaces.

Implications of the indicator light

There are seventeen indicator lights on the CKS board, of which, only one is the red
light and all other lights are green. Please see Table 1 for implications of the indicator
light.

Table 1 Implications of the indicator light on the CKS board

Name Color Implications Normal state
RUN Red It flashes every two seconds (at the interval of one second) if the Flash every two
communication is proper and flashes every 0.25 second if the seconds
communication goes wrong.
ACT Green It is constantly on while the board is the active one and constantly off On/Off
while the board is the standby one.
F0 Green Indication of the selected external reference source: On/Off
Constantly On:abnormal reference source (not available) Flashes every
Constantly Off:proper reference source second (*Note
Flash every two seconds (in the tracing state): resetting the phase 1)
F1 Green It is off while the system runs properly (including the integrated Off
information such as VCXO, DDS and 88915)
LOF Green It is on when 88915 loses lock Off
DDS Green It is off when the output of DDS is proper Off
LOCK Green It is on when 88915 loses lock Off
CLK Green It is off when the 58274 chip has been adjusted and the works well, Off
otherwise, it will flash
R8K0 Green Reference source of 8K signal from the trunk (one of the two groups)It is On/Off
constantly on while the reference source is selected

R8K1 Green Reference source of 8K signal from the trunk (one of the two groups) On/Off(*Note 2)
It is constantly on while the reference source is selected
2MB0 Green Reference source of 2048kb/s (E1) from the trunk or parent office (one of On/Off
the two groups)
It is constantly on while the reference source is selected
2MB1 Green Reference source of 2048kb/s (E1) from the trunk or parent office (one of On/Off

Huawei Technologies Proprietary

Page 1 of 4
Board Manual
C&C08 Digital SPC Switching System B-0304
Name Color Implications Normal state
the two groups)It is constantly on while the reference source is selected
2M0 Green Reference source of 2048kb/s (E1) from the trunk or parent office (one of On/Off
the two groups)It is constantly on while the reference source is selected
2M1 Green Reference source of 2048kb/s (E1) from the trunk or parent office (one of On/Off
the two groups)It is constantly on while the reference source is selected
REFA Green It is on when the frequency deviation of the selected external reference On/Off(*Note3)
source is too large
MOD Green Operating indicator light, indicating four operating modes of the CKS It varies with
board: the operating
Off:free oscillation mode
Fast flash: fast mode
Slow flash: tracing
Constantly On:memory
+12V Green It is on when the indicated 12V power supply works well. On

*Note 1: While operating in the tracing mode, the CKS board will reset the phase if
the phase jumping or unstable frequency occur in the reference source and surpass
the specificated threshold. At this time, the F0 indicator light flashes every second
until the phase resetting is completed.
*Note 2: There are six indicator lights of the reference source on the C841CKS board,
including R8K0, R8K1, 2MB0, 2MB1, 2M0 and 2M1. The light is turned on while the
corresponding external reference source is selected. Lights corresponding to the
reference source not selected will be turned off. Of six reference sources, R8K0 has
the highest priority (except another source is set via the background as the highest
priority). The default reference clock is R8K0 if it is available. If R8K0 is not available,
then R8K1 will be taken as the reference source. Therefore, we can deduce that if all
reference sources are not available after turning on the power, F0 light is on and
R8K0 is on as well (default). The changeover from the "not available" to the
"available" is indicated by the state changeover of the F0 light from On to Off.
*Note 3: While the board is set as the second-level clock, the REFA indicator light is
turned on when the frequency deviation surpasses 0.4ppm. Compared with this,
when the board is set as the third-level clock, the REFA indicator light is turned on
when the frequency deviation surpasses 4.6ppm. Checks of the frequency deviation
will only be performed when the board enters the tracing state. If the frequency
deviation is too large, the board will automatically enters the memory state, which will
last until the reference source is restored to the normal state.

Implications of the switch and jumper

There are five jumpers on the C841CKS board. Specific settings of these jumpers are
as follows:
1) S1 and S2 are the 4-bit jumper that controls two 2048kbit/s (E1) channels of the
reference source. If the 2048kbit/s (E1) signal is employed as the reference
source, the matched resistance of the port may be selected from 120Ω or 75Ω. A
variety of line matching will be achieved by setting S1 and S2 in different way.
(Note: when both CKS boards are in the position, they should have the same
matched resistance.)
A. S1 and S2 are set as follows while the transmission line of the reference source
employs the twisted pair line of 120Ω:

Huawei Technologies Proprietary

Page 2 of 4
Board Manual
C&C08 Digital SPC Switching System B-0304

Table 2 The setting of S1 and S2 for 120 Ω

Switch position of the S1 and S2 State of the switch
1 OFF
2 OFF
3 ON
4 ON

B. S1 and S2 are set as follows while the transmission line of the reference source
employs the twisted pair line of 75Ω:

Table 3 The setting of S1 and S2 for 75 Ω

Switch position of the S1 and S2 State of the switch
1 ON
2 ON
3 OFF
4 OFF

2) S3 is the 4-bit that controls two 2048kbit/s (E1) channels of the reference source.
If the 2048kbit/s (E1) signal is employed as the reference source, the matched
resistance of the port may be selected from 120Ω or 75Ω. A variety of line
matching will be achieved by setting S3 in different way. (Note: when both CKS
boards are in the position, they should have the same matched resistance.)
A. S3 is set as follows while the transmission line of the reference source employs the
twisted pair line of 120Ω:

Table 4 The setting of S3 for 120 Ω

Switch position of the S1 and S2 State of the switch
1 ON
2 OFF
3 ON
4 OFF

B. S3 is set as follows while the transmission line of the reference source employs the
twisted pair line of 75Ω:

Table 5 The setting of S3 for 75 Ω

Switch position of the S1 and S2 State of the switch
1 OFF
2 ON
3 OFF
4 ON

3) S4 is the three-core short line that is equal to the monopole double throw switch.
It is used for loading ROM.
The system works properly while short-connect the 1 and 2 and ROM is loaded by
short-connect the 2 and 3.

Huawei Technologies Proprietary

Page 3 of 4
Board Manual
C&C08 Digital SPC Switching System B-0304
4) S5 is the 4-bit jumper that is used to set the information byte of the embedded
software to identify the software version. Implications of the jumper are as
follows:
Table 6 Implications of the S5
Switch position of S5 State and implications of the switch
ON indicates the low baud rate communication with the SLT board in the clock frame
1
OFF indicates the high baud rate communication
ON indicates that the CKS board adopts the phase-lock of PDH that locks the clock
source of PDH and SDH (when all SDH sites are synchronous)
2 (*Note 4) OFF indicates that the CKS board adopts the phase-lock of SDH that locks the code
stream of SDH (if certain SDH sites are not synchronous, 8K clocks extracted from the
code stream of the trunk board)
ON indicates that the CKS is set as the third-level clock
3 (*Note 5)
OFF indicates that the CKS board is set as the second-level clock
ON indicates that the CKS board employs the 8.192M chip.
4
OFF is not used by far

(*Note 4): Phase-lock mode of the CKS board can be set at the terminal maintenance
console. The mode is determined by the setting of the background.
(*Note 5): Clock level of the CKS board can be set at the terminal maintenance
console. The level is determined by the setting of the background.

External distribution
None.

Note:
Maintenance staff should not plug/unplug the active CKS board randomly.

Huawei Technologies Proprietary

Page 4 of 4