Electric Power Systems Research 214 (2023) 108910

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

Distributed hierarchal control strategy for multi-bus AC microgrid to

achieve seamless synchronization
Muhammad Yasir Ali Khan , Haoming Liu *, Jie Shang , Jian Wang
College of Energy and Electrical Engineering, Hohai University, Nanjing, 211100, China

A R T I C L E I N F O A B S T R A C T

Keywords: In this research work, a distributed hierarchal control scheme is proposed that ensures a smooth synchronization
Adaptive control of islanded microgrid with the utility grid. In this method, a pinning consensus-based distributed controller is
Grid connected mode designed where all Distributed Generation Units (DGs) are allowed to regulate their frequencies and output
Islanded mode
power in proportion to their capacities while only regulating DGs are responsible for eliminating the phase angle
Microgrid
Seamless transition
and voltage magnitude mismatch. Hence, the magnitude, phase angle, and frequency are controlled explicitly
Synchronization while ensuring proportionate power sharing. To enhance the performance of the system, the fixed gain pa­
rameters of the secondary controller are made adaptive by using a back propagation based proportional integral
controller. Moreover, a fuzzy proportional integral controller and steepest descent based fuzzy logic controller
are designed that use an adjustable parameter to generate the compensation correction signals for the secondary
controller to eliminate the voltage magnitude and phase angle mismatch. Furthermore, to ensure a seamless
reconnection, a control strategy based on the synchronization criteria is designed that control the operation of
the static switch. Finally, the effectiveness of the method under different scenarios is validated through simu­
lation results.

1. Introduction
The depletion of fossil fuels and the condition of the environment
due to emission of greenhouse gasses has increased the popularity and
demand for renewable, more sustainable, and clean sources of energy. A
vast number of individuals and communities are motivated to switch
over to Renewable Energy Resources (RESs), i.e., wind, solar, etc. These
integrated RES acts as DGs; as a result, the incumbent power systems are
changing and moving toward a distributed future. Thus, a concept of a
Microgrid (MG) arose and continuously gained popularity due to its
scalable nature, renewable integration, and prosumer friendly archi­
tecture [1].
In an MG, the energy generation is relatively mixed; it can be either
in the form of AC (micro-turbines, wind turbines) or DC (PV, fuel cells)
and are synchronized with Utility Grid (UG) or operated in Islanded (IS)
mode through power inverter interface. Hence, the control of an inverter
is of great importance, as it ensures synchronization, power balance,
voltage (E) regulation, frequency (f) restoration, and load sharing.
Generally, an inverter acts as a Current Controlled Source (CCS) in a
Grid Connected (GC) mode or Voltage Controlled Source (VCS) in an IS
mode. In a GC mode, all the DGs in an MG are supported by the UG [2].
In an IS mode, an MG does not get any support from the UG; thus, an
inverter is responsible to regulate the Voltage Phasor (VP) (VP contains
voltage magnitude, frequency, and phase angle) and ensuring a pro­
portionate power sharing [3]. In IS mode, the VP of UG is considered
constant and uncontrollable; therefore, an inverter is responsible for
eliminating the VP mismatch between the Point of Common Coupling
(PCC) of an MG and the UG [4]. Any VP mismatch after reconnection
will result in high transients and inrush current, damaging the frequency
sensitive components and affecting the system stability [5].
Therefore, different control techniques have been developed to
ensure a seamless reconnection. The authors in [6] proposed a method
in which a traditional synchronizer is used to synchronize the two par­
allel connected generators. Although the voltage difference, slip fre­
quency, and phase angle errors between the two generators are
significantly minimized but this method is not feasible for today’s
multi-bus MG system. In today’s MG, multiple DGs are connected to
different buses; therefore, it is impractical to synchronize every single
DG with UG through a traditional synchronizer. In [7], a synchroniza­
tion method is proposed where a frequency regulation is initiated in an

* Corresponding author.
E-mail address: liuhaom@hhu.edu.cn (H. Liu).

https://doi.org/10.1016/j.epsr.2022.108910
Received 18 August 2022; Received in revised form 9 October 2022; Accepted 17 October 2022
Available online 27 October 2022
0378-7796/© 2022 Elsevier B.V. All rights reserved.
M.Y.A. Khan et al.
initial stage with a minute frequency mismatch conserved for phase
regulation. As in this method, a frequency mismatch is not completely
eliminated; therefore, it is only suitable for those systems where a small
frequency mismatch did not result in undesired transients after
reconnection.
The authors in [8] proposed Phase Locked Loop (PLL) based control
strategy to achieve synchronization. In the method, two dual second
order integrators and two stationary frames PLLs are used to eliminate
the VP mismatch. However, a numerical analysis of the synchronization
is not taken into consideration. Moreover, neither droop nor its function
is considered, which can affect the system performance in case of a
multi-bus system. The authors in [9] use a sliding Fourier
transform-based PLL to extract the load current and to ensure seamless
synchronization of the PV system with the UG. This technique can
mitigate the non-linear load harmonics and deliver current to the UG
with a unity power factor. Although this technique shows efficient
performance but the authors did not consider the performance of the
controller in a case of multiple DGs. In [10], another PLL-based syn­
chronization method is proposed in which three PLLs are used to syn­
chronize the frequency and phase of all DGs. In this method, the phase
and frequency are synchronized in a sequence; as a result, the syn­
chronization time is long. The authors in [11] proposed a
self-synchronized method to avoid the use of a dedicated PLL unit. In
this method, an MG can automatically synchronize with the UG through
virtual synchronization. However, a high bandwidth centralized cyber
network is required in case of a multi-bus system to gather the instan­
taneous grid voltages that can increase the expense and of the system.
Moreover, synchronization through this method is achieved only in a
situation when the system has no local loads.
In [12], a droop based synchronization method is proposed. In this
method, the authors only consider the synchronization of phase angle
and frequency while the synchronization of voltage magnitude is avoi­
ded. Moreover, it cannot realize an appropriate power flow between the
MG and UG [13]. Similarly, the authors in [14] use two PLLs to detect
and Proportional Integral (PI) controllers to eliminate the VP mismatch
from both sides of PCC in a droop based MG system. The PLLs are used to
detect the phase angle and frequency of PCC and UG, and the error is fed
to a PI controller that generates compensation signals for the droop
controller. However, in this method, the smoothness of the synchroni­
zation process is not discussed and does not ensure an appropriate power
flow. An adaptive droop based synchronization control scheme for
inverter interfaced DGs is proposed in [15]. In this method, the structure
of a conventional droop controller is modified so that it injects an
appropriate power in a GC mode and regulates the frequency and
voltage in an IS mode. Although a synchronization is achieved but the
authors have only considered a transition of a single DG from IS to GC
mode and vice versa. Moreover, the stability analysis and performance
of the proposed method under different scenarios, such as load variation
and PnP, are not considered.
Although synchronization is achieved using a droop controller but it
pushes the bus voltage and the network frequency from their reference
values and cannot guarantee a proportionate power flow. Moreover,
high performance degradation is observed during system uncertainties
or disturbances. This automatic leads to the next hierarchy level, i.e. a
Secondary Control (SC) level. A hierarchical structure can be employed
using three approaches, i.e. centralized, decentralized, and distributed.
The authors in [16,17] use a centralized control structure to achieve
synchronization. A centralized architecture requires a high bandwidth
cyber network as every DG is individually connected to a controller;
moreover, it is also sensitive to single point (cyber link) failure.
Due to the above discussed disadvantages of centralized control ar­
chitecture, a distributed control structure is more effective. It is gaining
popularity among a vast number of communities and utilities due to (a)
high feasibility for Plug and Play (PnP) functionality, (b) low cyber cost,
(c) low bandwidth cyber network, and (d) robustness to single point
failure [18]. A distributed controller was initially proposed in [19]. This
2
Electric Power Systems Research 214 (2023) 108910
method implements a Proportional Integral (PI) control strategy at the
secondary level to regulate the voltage and frequency and ensure
appropriate power distribution among the DGs. In [20], a generalized
Distributed Averaging Proportional Integral (DAPI) controller is devel­
oped. This method successfully solves the natural conflict between
reactive power sharing and voltage restoration. Therefore, based on the
distributed architecture, different methods were adopted for seamless
reconnection.
In [21], a predictive controller is designed to predict the phase angle
and voltage magnitude to achieve synchronization. In this method,
frequency of the DGs is controlled directly through the phase angle of
the DGs’ output voltages in IS mode. In case of GC mode, a PI controller
is used to control the phase and voltage magnitude while a frequency
regulation is ignored. Thus, unbounded frequency variation may affect
the stability of the system and damage the frequency sensitive compo­
nents. The authors in [22] proposed a Virtual Oscillator Control (VOC)
based hierarchical control structure to achieve synchronization. In a
proposed method, a non-linear VOC is used in a SC level while the
tracking of power references along with the notch filter to suppress the
harmonics in the current are exhibited in a tertiary control level.
Although this method improves the MG operation and achieves seamless
transition but the initial fast response of VOC can affect the system
stability. To achieve synchronization, the authors in [23] proposed a
distributed control architecture in which the primary droop and sec­
ondary control levels are replaced with three separate regulators, i.e.
active power, reactive power, and voltage regulators. Although this
approach enhances the system performance and ensures proportionate
power sharing but it is unable to eliminate the VP mismatch at a node
closest to PCC. In [24], the authors proposed a synchronization method
that focuses on eliminating phase mismatch. In this method, a phase
mismatch is calculated from the cross product of the VP from both sides
of PCC and is then used as a feedback control parameter in the syn­
chronization technique. Eliminating only phase mismatch while
ignoring the dynamics of frequency mismatch cannot resolve the natural
conflict between phase and frequency. Moreover, unbounded frequency
variation may affect the system’s stability.
The authors in [25–27] use a leader-follower consensus-based hier­
archical control strategy to achieve a seamless reconnection. In a pro­
posed method, a droop controller is employed at the primary level while
in the secondary control level, the control law presented in [20] is
modified to ensure synchronization. At a tertiary level, a supervisory
mode control is used for data acquisition and transmission of compen­
sation signals to the SC of a Leader (L) DG only. An L-DG will then share
these compensation signals to the Follower (F) DGs through a sparse
cyber network to adjust their VP at a PCC. Although this method shows
an effective performance but the authors are unable to resolve the
conflict between frequency and phase regulation. Similarly, the authors
in [28,29] proposed a pinning consensus-based distributed controller.
This method explicitly controls the voltage magnitude, phase, and fre­
quency while ensuring appropriate power sharing. All DGs are respon­
sible for restoring the system frequency while only a selected DG known
as Regulating (R) DG is responsible for regulating the voltage magnitude
and phase angle. Although, this method ensures smooth synchronization
but the authors did not consider the controller or mechanism that gen­
erates the compensation correction signals for SC. Moreover, the
mechanism through which the SS is controlled is not discussed. More­
over, in case of any system uncertainty or disturbance (such as PnP
operation, sudden load variation etc.), performance degradation is
observed due to fixed secondary controller gain parameters in [25–29].
Based on the above discussed limitation in the literature, a distrib­
uted hierarchal control structure is presented in this research work for
seamless reconnection. A pinning consensus-based cooperative control
strategy is proposed that eliminates the VP mismatch. The principal
contributions of this research study are:
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Table 1
Comparative analysis of proposed method with other methods.
Ref Controller BS VP Control CS ASCGP PnP APF RCBFP CSG
δ f E

[6] Traditional synchronizer SBS √ × √ M × × × × ×

[7] Remote Sensing MBS √ × √ L × × × × ×
[8] PLL SBS √ √ √ L × × NG × ×
[9] PLL SBS √ √ √ H × × √ × ×
[10] PLL MBS √ √ × M × × NG × ×
[11] Self-Synchronized MBS √ √ √ M × × √ × ×
[12] Droop MBS √ √ × M × × × × ×
[14] Droop MBS √ √ √ M × × × × √
[15] Droop MBS √ √ √ M × × NG × ×
[17] Centralized MBS × √ √ L × √ √ × ×
[21] Distributed MBS √ × √ H × × √ × √
[22] Distributed MBS √ × √ H × × √ × ×
[23] Distributed MBS √ √ √ H × √ √ √ √
[24] Distributed MBS √ √ √ H × × NG × √
[25–27] Distributed MBS √ √ √ H × √ √ × √
[28–29] Distributed MBS √ √ √ M × × √ √ ×
P Distributed MBS √ √ √ H √ √ √ √ √

Abbreviations: √: Presence of Feature, ×: Absence of Feature, BS: Bus System, CS: Convergence Speed, ASCGP: Adaptive Secondary Control Gain Parameters, RCBFP:
Resolve the Conflict between Frequency and Phase, APF: Appropriate Power Flow, CSG: Correction Signal Generator, P: Proposed, H: High, M: Medium, S: Slow, NG:
Not Given, D: Droop.

• In this method, all DGs are connected with its neighboring DGs only 2.1. Physical system
through a sparse cyber-network and are allowed to regulate the MG
frequency and the output power of DGs in proportion to their ca­ An MG is considered that consists of n buses, which can be either
pacity while only a R-DG is responsible to eliminate the phase and loads or DGs. Each DG is composed of DC source, inverter, and filter
voltage magnitude mismatch between the PCC and UG. Hence, the (Inductance-Capacitance-Inductance (LCL)). It is assumed that the ith-
conflict between the frequency and phase regulation is resolved. DG is connected to the PCC through inductive lines having reactance of
• Fixed gain parameters of the secondary controller are updated using Xi, then the injections of active power (Pi) and reactive power (Qi) of DGi
a Back Propagation (BP) based Adaptive Proportional Integral (API) at PCC is given as [30]:
controller. This adaptive technique measures the dynamic behavior
Ei EPCC
of the system in every sampling period and updates the fixed gain Pi = sin(θi ) (1)
Xi
parameters of SC to provide optimal performance.
• To avoid the current surges during the synchronization process and 2
Ei EPCC cos(θi ) − EPCC
ensures a smooth and seamless transition, a Fuzzy Proportional In­ Qi = (2)
Xi
tegral (FPI) controller and Steepest Descent (SD) based Fuzzy Logic
Controller (FLC) are designed. The proposed controllers use an where, Ei and EPCC represents the voltage magnitude of DGi and PCC
adjustable parameter to control the transient behavior and provide respectively; θi = δi - δPCC , where δi presents the phase angle of DG
the regulated compensation signals to the SC to perform its manda­ (inverter) output voltage while δPCC shows the voltage phase angle at
tory control functions. ∑
PCC, and Xi = 1 /( nj=1 Xij− 1 ).

Moreover, a comparative analysis of the presented methodology

with state-of-the-art methods present in the literature is shown in
Table 1.
The rest of the manuscript is structured as follows. The preliminaries
of graph theory, cyber-physical modeling of MG, and a review of zero
and primary control levels are discussed in Section 2. A proposed
adaptive distributed SC scheme is presented in Section 3. The controllers
that generate the compensation signals for the SC are discussed in Sec­
tion 4. The synchronization criteria and control of an SS are elaborated
in Section 5. The performance validation of the proposed method under
different scenarios is presented in Section 6. Finally, the concluded re­
marks are expressed in Section 7.
2. Preliminaries
In this research work, an inverter based MG consisting of N number
of parallel connected DGs is considered and the communication among
them is performed through a cyber-network. Therefore, this section
discusses details of the cyber-physical network along the zero and pri­
mary level control of MG. Moreover, the description of the grid syn­
chronization technique is also elaborated.
2.2. Cyber system
A graph theory is used to present the cyber-network between the
DGs. It is assumed that the communication among the DGs are per­
formed through meshed cyber-network and every DG acts like an agent.
A cyber-network can be modelled by a digraph as G(V, E, A), where V =
{1, 2, ⋯⋯n} presents a set of vertices (DG tagging or agents), E ⊆ [V] ×
[V] is the set of edges (cyber links). If node i share information with node
j then (ai , aj ) ∈ E. Furthermore, if all (ai , aj ) ∈ E, then G can be
considered as undirected. A = R|N|×|N| defines the associated adjacent
matrix of the graph whose element aij means the connection weight. In
detail, if there is an existence of edge between node i and j then elements
aij = aji > 0, otherwise aij = 0. If the nodes are arranged in such a
manner that the edges of the consecutive pair of nodes are linked in a
sequence then there exist a path between the nodes i to j, i.e. ⍱(ij) = [Ѵ]
× [V], then the graph is said to be strongly connected. Thus, the dy­
namics of a DG under consensus can be expressed as [31]:
∑ ( )
ġi = − aij gi − gj (3)
i,j∈ν

where, gi represents the state of ith-DG. The formulation in (3) only re­
quires the knowledge of the states that are accessible to the DGs locally i.
e. state gi is accessed by ith-DG. However, in a scenario, when the states of

3
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Fig. 1. Generalized zero and primary level control structure of an inverter based DG.

concerns are not accessible by the DGs locally, then a pinning based 2.3. Zero and primary level control
consensus algorithm is used and is given as:
∑ ( ) Control of an MG is practiced hierarchically and is composed of four
ġi = − aij gi − gj − hi (4) control levels, i.e., zero level, primary droop level, secondary level, and
i,j∈ν
tertiary level. A zero level control of an inverter is composed of an inner
In (4), hi presents a pinning control input and is given as: current loop, an outer voltage loop, and a virtual impedance loop.
Different control strategies have been developed for current and voltage
hi = αi [j(gi ) − ̃j] (5)
loops, a detailed review of which is presented in [32]. However, among
all the control strategies, a Proportional Resonant (PR) controller is
where, αi shows the weighted pinning gain, j(gi) shows the state of
widely used due to its fast dynamic response and high tracking capa­
concern that is non-accessible by the DGs locally and is controlled by gi,
bility of sinusoidal references [33]. Moreover, a virtual impedance loop
and̃j denotes its desired value. Moreover, if the ith-DG is pinned then αi with inductance (Lv) is used in the zero-level control structure to make
> 0, else αi = 0. When the system reaches consensus, then the state of the MG predominantly inductive [34]. In addition, it significantly limits
concern converges as: the inverter current during the transition from IS mode to GC mode.
( ) A primary droop controller that mimics the behavior of synchronous
lim gi − gj = 0 (6)
t→∞
generator plays an important role in regulating frequency/voltage and
ensuring proportional power sharing. A droop control law of an ith-DG

Fig. 2. Schematic of a MG with sparse distributed cyber network.

4
M.Y.A. Khan et al.
Fig. 3. Schematic of distributed hierarchical control for R-DG.
can be presented as [35]:
ωi = ωref − mi Pi (7a)
Ei = Eref − ni Qi (7b)
where, ωref and Eref are the reference values for frequency and voltage
respectively, whereas; the mi and ni are P-ω and Q-E droop coefficients
respectively and can be designed as;
Δωi ΔEi
mi = , ni = (8)
Pimax Qimax
where, Δωi and ΔEi are the maximum allowable deviation in ωi and Ei
respectively. In IS mode, an MG does not get any support from UG; as a
result, it becomes susceptible to uncertainty. Thus by using only a droop
controller, the stability of the system cannot be guaranteed; thus, it
naturally leads to a secondary control level of the hierarchical structure.
A detailed analysis of the proposed SC level is discussed in Section 3
while the tertiary control level is out of the scope of this research work;
hence it is not discussed here. A generalized control structure that in­
cludes the zero level control (inner, outer, and impedance loops) and
primary droop control is presented in Fig. 1.
2.4. Description of grid synchronization technique
A generalized structure of an MG connected to a UG consists of DGs,
PCC, transmission lines, cyber links, loads, SS, and a controller that
generates the compensation correction signals for the SC is presented in
Fig. 2. The PCC must be synchronized with the UG before triggering an
SS and initiating a GC operation. Any VP mismatch results in a high
inrush current that can affect the system’s stability and damage the
components. Therefore, to ensure the system stability and decrease the
inrush current EPCC must be in synchronization with Eg before triggering
an SS. In the proposed method, the VP difference between the PCC and
UG is measured and sent to the controller to generate the phase angle
(Δδs*) and voltage magnitude (ΔEs*) correction signals and are then fed
to the SC to perform its mandatory control actions and achieve a
seamless reconnection. Moreover, the proposed system is based on
distributed architecture; therefore, its performance is not affected by
signal point failure, thus increasing the system’s flexibility and
reliability.
5
Electric Power Systems Research 214 (2023) 108910
3. Proposed distributed secondary control scheme
In this research work, a pinning consensus based distributed
controller is designed to regulate frequency, phase angle, and magnitude
while ensuring appropriate active and reactive power sharing.
3.1. Distributed frequency/phase regulation
To eliminate the frequency and phase angle mismatch between the
UG and PCC while ensuring accurate power sharing a secondary
controller is defined as:
ωi = ωref − mi Pi + ui (9a)
[ ]
dui ∑n
( ) ( )
= Gf aij uj − ui − ωi − ωref − αi Δδ∗s (9b)
dt j=1
where ωi is the measured frequency of the ith-DG (i = 1, 2,………., n);
ωref is the grid frequency; ui is the secondary control variable; Gf is the
designed controller positive gain; aij = 1 if there is a cyber-link between
ith-DG and jth-DG, otherwise aij = 0; αi is the designed phase regulation
gain; if an ith-DG is chosen as R-DG then αi = 1, otherwise αi = 0; Δδ*s is
the correction compensation signal from the controller. An adjacency
matrix for the frequency/phase regulation is presented as A = {aij}. A
schematic of distributed hierarchical control structure is presented in
Fig. 3. In Fig. 3 VDC represents the DC voltage source, Z represents the
impedance, L denotes a load
In a steady state, the derivative term on the left side of (9b) becomes
zero and the subsequent declarations are true: (a) ωi = ωj = ωref, means
that a uniform frequency shift is obtained for all the DGs according to its
rated frequency and the frequency mismatch from both sides of the PCC
is eliminated [20]; (b) phase mismatch from both sides of PCC is
eliminated; and (c) ui = uj, means that the droop curves of all the DGs are
shifted equally and active power sharing is maintained.
3.1.1. Adaptive control scheme
From (9b), it can be observed that the secondary controller gain, i.e.,
Gf is a constant and is unable to update in case of any uncertainty that
can affect the transient response of the controller and stability of the
system. Therefore, in this subsection, a BP based API distributed control
scheme is designed that continuously measures the dynamic behavior of
the system, updates the control law gain parameter, and provides
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

optimal performance. To update the Gf, a generalized PI controller is Table 2

given as: If-Then rules for PI based FLC.
∫t If-then Rules Input Membership Input Membership
Gf = kpf (t)ef (t) + kif (t) ef (t)dt (10) Function Function
0 If |e Then (kps, Linguistic Range Linguistic Range
(t)| kis) Terms Terms
where, ef = (ωi - ωref). In this research work, a BP algorithm is used to
Zero Zero Zero [0, 0.2] Zero [0, 0.2]
designed an API controller that uses a gradient descent function to Small Small Small [0.3, Small [0.3,
minimize the error and improve the transient response [36], and is given 0.7] 0.7]
as: Large Large Large [0.8, Large [0.8,
1.0] 1.0]
1
J = ef 2 (t) (11)
2
The gain of BP algorithm can be calculated as: where Ei is the measured voltage of the ith-DG; Eref is the rated voltage; vi
is the SC variable; GE is the designed secondary controller regulating
gain; Qiref and Qjref symbolizes the rated reactive power of ith-DG and its
dJ
kf − new =− γ (12)
neighbouring jth-DG respectively; ΔE*s represents the correction signal
dkf

In (12), γ denotes a learning rate, kf− new ∈ {kpf− new , kif− new }, where from the controller; and βi represents the designed magnitude regulating
kpf− new and kif − new are the new proportional and integral gains of gain, if an ith-DG is chosen as R-DG then βi = 1, else βi = 0. An adjacency
controller and are given as: matrix for the voltage regulation is presented as B = {bij}. Moreover, to
[ ] avoid extra cyber channels it is assumed that B = A i.e. {bij} = {aij} and
kpf − new = − γ
dJ
=− γ
∂J ∂ω ∂u
= − γe2f (t)kpf (t) (13a) βi = β > 0 if αi = α > 0. In a steady state, the following declarations are
dkpf ∂ω ∂u ∂kpf true: (a) voltage magnitude mismatch between PCC of MG and UG is
[ ] eliminated and (b) Qi / Qiref = Qj / Qjref Qi /Qiref = Qj /Qjref means that a
dJ ∂J ∂ω ∂u proportional Q-sharing has been achieved.
kif − new =− γ =− γ = − γe2f (t)kif (t) (13b)
dkif ∂ω ∂u ∂kif An expression presented in (17b) is a special case of a DAPI controller
The esteemed updated values of proportional and integral gains of proposed in [20]. In [20] it is mentioned that the ith-DG can either
the controller can be presented as: contribute in the Q-sharing (βi = 0, bij ∕
= 0) or in voltage regulation ((βi ∕
=
[ ] 0, bij = 0)) else both regulators will be subjected to steady-state errors.
kpf (t + 1) = kpf (t) + kpf − new (t) = kpf (t) 1 − γe2f (t) (14a) This formulation allows a single DG to regulate the voltage according to
its reference while other DGs participate in Q-sharing. If the line power
[ ] flows and impedances are not very high, then the voltages of the other
kif (t + 1) = kif (t) + kif − new (t) = kif (t) 1 − γe2f (t) (14b)
remaining nodes will certainly cluster around it [37]. An expression in
The updated values of kpf and kif enable the controller to return to the (17b) uses this methodology and aims to regulate the voltage at the PCC.
condition where the steady state error is almost zero. Hence, the pa­ However, in the formulation, single or multiple DGs can contribute in
rameters of PI controllers in (10) can be updated as: voltage regulation and Q-sharing. The regulators will not be subjected to
steady state errors, resulting in fast convergence and strengthening the
[{ ( )} ] [{ ( )} ∫ ]
cyber network [38]. A corresponding proof is described in Appendix 1.
Gf = kpf (t) 1 − γe2f (t) ef (t) + kif (t) 1 − γe2f (t) ef (t)dt (15)
Moreover, to update the SC gain (GE) in (17b) in order to withstand
with system uncertainties, a BP based API control scheme is applied. A
As Gf is the updated parameter of the controller, therefore the sec­
detailed description and numerical derivation of the API controller for
ondary controller in (9b) becomes:
(17b) is elaborated in Appendix 2.

[[{ ( )} ] [{ ( )} ∫ ]] [ ∑n
]
dui ( ) ( )
= 2 2
kpf (t) 1 − γef (t) ef (t) + kif (t) 1 − γef (t) ef (t)dt . ∗
aij uj − ui − ωi − ωref − αi Δδs (16)
dt j=1

4. Controllers for generating correction signals

A proposed API controller ensures that each DG operates at the
reference frequency to attain synchronization while maintaining
optimal power sharing among the DGs.
3.2. Distributed voltage regulation
In this work, to eliminate the phase angle and voltage magnitude
mismatch between the PCC and the UG, an FPI and SD based FLC are
designed that provides compensation corrections signals to SC.

The voltage phase/frequency regulation and magnitude regulation 4.1. Fuzzy proportional integral controller
are decoupled from each other; therefore, they can be controlled indi­
vidually. A voltage regulation methodology based on formulation The proportional and integral gains of a conventional PI controller
expressed in [20] and can be described as: are fixed constant and cannot work efficiently in case of any system
disturbance or uncertainty. Therefore, to enhance the performance of
Ei = Eref − ni Qi + vi (17a) the traditional PI controller, their gains are made adaptive using Fuzzy
[ ( ) ] Rules (FR). The FR used to regulate the controller output variable are
∑ presented in Table 2.
n
dvi Qj Qi
= GE bij − − βi ΔEs∗ (17b)
dt j=1
Qjref Qiref The FLC structure comprises four main components, i.e., fuzzifica­
tion, rule base, inference mechanism, and defuzzification. During the

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M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Fig. 4. Proposed FPI controller design.

fuzzification process, the crisp inputs are collected and transformed into
1
a fuzzy set using membership functions and linguistic terms. The fuzzy f (y) = ‖ d(y) ‖2 (23)
2
sets are then compared with the rules defined in the rule base. The rules
are examined in the inference mechanism that chooses the best appli­
4.2.1. Controller design
cable rule according to the condition. During defuzzification, the data is
This controller can optimize linear and non-linear functions and uses
again converted in crisp form using the center of gravity method and are
a first derivative to reduce the error [39]. The learning error function
used to update the PI controller gain. The schematic of the proposed PI
materialized from the cost function is given as:
based FLC i.e. FPI is presented in Fig. 4. A Gaussian Membership
Function (GMF) that depends on the center and variance is usually used 1( )2
ec = fc − yref (24)
in the fuzzification and defuzzification process and is expressed as: 2
( ( )2 )
xi − ci where, ec is the error, fc is the controller output, and yref is the controller
μ(x) = exp − 0.5 (18)
σi reference. In order to defuzzify the output, a center of gravity method­
ology is used and is given as:
where, ci denotes the center while σ i shows the variance. A conventional ∑
R
PI controller can be mathematically expressed as: μi bi (y)
∫ fc = i=1R (25)
∑
ΔA∗ (PI) = kps e(t) + kis e(t) dt (19) μi (y)
i=1

where, ΔA (PI) is the output of the fuzzy PI controller that is fed to the
∗
where, μi is the GMF and can be defined as:
SC as a compensation signal i.e. ΔA∗ = Δδ∗s or ΔA∗ = ΔE∗s , kps is the ( ( )2 )
proportional gain of PI controller, and kis is the integral gain of PI ∏ 1 xmj − cij
n
μi (y) = exp − (26)
controller hence, e(t) denotes the error and is minimized by updating the j=1
2 σij
kps and kis gains of the PI controller using FR. Thus, the designed
controller is given as: where, xm i i
j is the crisp value, σ j is the spread of GMF, and cj is the center
∫ of GMF.
ΔA∗ (AFPI) = X1 γ 1 e(t) + X2 γ 2 e(t)dt (20)
4.2.2. Adaptation of output GMF
where, X1 and X2 are the fuzzy controller outputs, γ1 and γ2 are the In order to minimize the error, the output GMF (bi) need to be
learning rate of kps and kis respectively. updated according to the plant’s output. To achieve this, take the de­
rivative of the error function in (24) with respect to bi as:
4.2. SD based FLC ⎡ ( ( )2 )⎤
∑R ∏ 1 xm − cij
⎢ bi exp − 2 σi j
⎥
An FLC based on the SD algorithm is proposed to eliminate the phase ∂ec ∂ε ∂ ⎢⎢i=1 j ⎥
⎥
angle and voltage magnitude mismatch between the PCC and the UG. An =ε =ε ⎢ ( ( ) ) ⎥ (27)
∂bi ∂bi ∂bi ⎢ ∑R ∏ x m − ci
2 ⎥
⎣ ⎦
FLC based SD does not require the exact mathematical model of the
1 j j
exp − 2 σi
j
system and is updated as:
i=1

zk = zk− 1 − αxk (21) Hence, the update law for output MF according to (21) can presented
as:
where, zk+1 denotes the updated value, zk shows the previous value, α is ⎡ ( ( m i )2 )⎤
the learning rate or step size constant, and xk presents the current value. ∑ ∏
R x − c
1
⎢ bi exp − 2 j σi j ⎥
According to SD algorithm, the output GMF, center, and variance of the ∂ ⎢⎢ i=1 j ⎥
bi (k) = bi (k − 1) − εα ⎢ ( )⎥
⎥ (28)
FLC are updated to provide an optimized solution. The controller cost ∂bi ⎢ ∑ R ∏
(
m
x − c i
)2 ⎥
⎣ ⎦
function optimized by SD algorithm is given as: exp − 12 j σi j
j
i=1

1∑ m
f (y) = d2 (y) (22)
2 j=1 k 4.2.3. Adaptation of center
The maximum value of GMF occurred at center while the rest of the
where, y = [y1 y2 y3 , ............. yn ]T ∈ Rn×1 ; dk is the residuals function value is spread equally on both sides. Hence, to update the center of the
from Rn →R and a residual vector d(y) is defined as d(y) = [d1 (y), d2 (y), GMF take a derivative of (24) with respect to ci(k) and then put the value
d3 (y), ............. dm (y)]. Hence, (22) can be rewritten as: in (21) would yield us to:

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M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

⎡ ⎡( ) ⎤ ⎤
Table 3 ∑
R ⎛( )⎞
Controllers’ parameters of compensation correction signals generation. ⎢ ⎢ bi − fc ⎥ xm − ci ( )⎥
⎢ ⎢ ⎥⎝ j j ⎥
ci (k) = ci (k − 1) − εα⎢ε⎢ i=1
( i )2 ⎠μi xj , k ⎥
m
(29)
Controller Parameter Symbol Value ⎣ ⎣ ∑
R ( m )⎥ ⎦ σ ⎦
μi x j , k j
FPI Learning parameter for kps γ1 2 i=1
Learning parameter for kis γ2 130
SD based FLC Learning parameter 0.001
α1 4.2.4. Adaptation of variance
α2 0.025
Output of GMF b1 2
From (26), it can be observed that the variance has an inverse rela­
b2 0.2 tion with magnitude of GMF i.e. if variance increases then the magni­
Center of GMF c1 0.9 tude of GMF decreases and vice versa. Hence, to update the variance of
c2 0.6 the GMF, initially differentiate (24) on both sides with respect to σi(k)
Variance of GMF 0.01
and then put the value in (21) to get an updated equation as given below:
σ1
σ2 1
⎡ ⎡( ) ⎤ ⎤
∑
R ⎛( )2 ⎞
⎢ ⎢ b − fc⎥ m i ( )⎥
⎥⎜ xj − cj ⎟
i
σ i (k) = σi (k − 1) − εα⎢ ⎢ i=1
⎢ε⎢ R ( ⎥⎝ ( )3 ⎠μi xjm , k ⎥
⎥
(30)
⎣ ⎣∑ m
) ⎦ σ i ⎦
μi xj , k j
Table 4 i=1
Standards of resynchronization criteria.
The output of the controller is obtained according to the updated
Standards DG power Phase angle Frequency Magnitude
equations of output GMF, center, and variance by passing through fuz­
rating (kVA) difference difference Difference
(◦ ) (Hz) (%) zification, rule base, interference mechanism, and defuzzification stages.
The initial parameter values of the proposed SD based FLC controller are
IEEE Standard 0–500 20 0.3 10
1547–2003 >500–1500 15 0.2 5 tabulated in Table 3. The values of these parameters are updated itself
[40] >1500–10,000 10 0.1 3 according to 28–(30) to minimize the error function. As a result, the
[27] Criteria used <5 < 0.05 < 0.01 pu controller becomes more robust and adaptive.

Fig. 5. Flowchart of SS control.

Fig. 6. Schematic of a MG test system.

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M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Table 5 the authors in [27] proposed more strict criteria for MG resynchroni­
MG system parameters. zation as presented in Table 4. Based on the set limits, a control algo­
Parameter Symbol Value rithm for triggering a SS is proposed as shown in Fig. 5. In the proposed
algorithm, the VP difference is measured in every sampling time and
Electrical Parameters
Nominal Frequency f 50 Hz compared with the set limits. Once the set limits are achieved, the al­
Nominal Voltage E 310 V gorithm checks if the criteria is met for 0.1 s or not [41]. If the system
Loads (Pload + jQload) L1= L2= L3= L4 1 kW + 1 kVar attains the set limits for less than 0.1 s, then the algorithm returns to
Local Load (Pload + jQload) L0 2 kW + 3 kVar measure the VP and repeats the procedure. On the contrary, if the set
Line Impedance Z01 0.9 Ω + 4 mH
Z02 1.2 Ω + 5 mH
limits are attained for more than 0.1 s, then the command will send for
Z23 0.8 Ω + 3 mH triggering the SS and a seamless synchronization is achieved and thus
Z04 1.6 Ω + 6 mH results in a negligible inrush current.
Primary Droop Control Parameters
5
Droop coefficients mi (P-ω) 10− rad / (W s)
3 6. Performance validation
ni (Q-E) 10− V/Var
Distributed Control Parameters
Voltage gain GE 0.01 The simulations are carried out on a four-bus MG system in MAT­
Frequency gain Gf 0.1 LAB/SimPower Systems software as presented in Fig. 6. It consists of 4-
Learning rate for f-regulation γ 2.4 DGs (DG1-DG4), 4 radial buses, 1 public load (L0), and 4 independent
Learning rate for E-regulation 3.6
local loads (L1-L4). DG1 is chosen as an R-DG while all the other DGs
γ

(DG2-DG4) are the GF-DGs. All the DGs communicate with each other
5. Synchronization criteria and static switch control through a cyber-network and the adjacency matrices A = [aij] and B=
[bij] are given as:
The main goal of the proposed method is to eliminate the VP ⎛ ⎞ ⎛ ⎞
0 1 0 1 0 1 0 1
mismatch between the PCC and the UG. Once the synchronization is ⎜1 0 1 0⎟ ⎜1 0 1 0⎟
achieved, the synchronization controller will send information to an SS A = ⎜ ⎟ ⎜
⎝0 1 0 1⎠ , B = ⎝0 1 0 1⎠
⎟ (31)
controller for triggering (closing) a switch. However, some set limits are 1 0 1 0 1 0 1 0
defined by IEEE-1547, which should be met before triggering an SS, as
listed in Table 4 [40]. However, with the advancement in technology in The performance of controller is analyzed in three different scenarios
inverter based DGs that have a fast dynamic response and low inertia, that are discussed below in detail. The parameters utilized in this

Fig. 7. Plug-and-play capability of secondary PI controller (a) frequency, (b) voltage, (c) active power, and (d) reactive power.

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M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Fig. 8. PnP capability of a BP algorithm based API controller (a) frequency, (b) voltage, (c) active power, and (d) reactive power.

Table 6
Load variation according to time span.
Time Period (sec) Loads
L1 (kW+ kVar) L2(kW+ kVar) L3(kW+ kVar) L4(kW+ kVar) L0(kW+ kVar)

0≤t≤1 1+1 1+1 1+1 1+1k 2+3

1≤t≤2 2+2 2+2 0.5 + 0.5 0.5 + 0.5 2+3
2≤t≤3 1+1 1+1 1+1 1+1 2+3

simulation are shown in Table 5. performance is presented in Fig. 7. It can be observed that when a DG5 is
plug-in to the system it automatically synchronized with the existing
DGs (DG1~DG4) and achieve an updated and appropriate power
6.1. Plug-and-Play capability in GC mode
sharing. At t = 2 s, when DG5 is plug-out from the system, the controller
restores the voltage and frequency while readjusting the power-sharing
Due to the intermittency of renewable power generating units’, it
among the DG1~DG4.
performs plug-in or plug-out phenomenon in an MG. A distributed MG
From Fig. 7, it can be observed that during the PnP operation, the
architecture allows the existing DGs to be plug-out or allows new DGs to
controller with fixed gain (control) parameters cannot accurately track
be plug-in without redesigning an existing MG architecture. As an MG
its reference values (frequency/voltage) and cannot precisely handle the
can operate in both IS and GC modes, it is assumed that for this specific
system uncertainty. The frequency/voltage of DGs deviates from their
scenario, an MG operates in a GC mode. It is considered that at bus 4, a
reference values and generates an arbitrary consensus above or below
DG5 is plug-in at t = 1 s and plug-out at t = 2 s (along with its cyber-
their reference values. Therefore, to cope with this problem, a BP al­
physical links) as presented in Fig. 6. By applying a distributed SC
gorithm based API controller discussed above is applied that update the
with fixed gain parameters, the impact of DG5 on the controller

10
M.Y.A. Khan et al.
Fig. 9. Robustness to load variation using a BP based API controller (a) frequency, (b) voltage, (c) active power, and (d) reactive power.
control law parameters in case of any uncertainty and provide optimal
performance as shown in Fig. 8. It can be detected that the voltage and
frequency of DGs suffer from some deviation during connection and
disconnection of DG5 into the system. However, the proposed controller
keeps the MG frequency and voltage within the adequate range of
esteemed values and tracks its references in approximately 0.1 s while
attaining accurate power sharing.
6.2. Load variation in IS mode
In an MG, load varies at any specific time according to consumer
behavior, affecting the system’s stability and performance. Therefore, in
this scenario, the transient response and robustness of an API controller
is evaluated according to the load variation when an MG is operated in
an IS mode. An SC with fixed control gain parameters cannot track its
reference accurately in case of any uncertainty as discussed above;
therefore, the simulation results for this scenario are discussed only for a
BP based API distributed SC. The variation in different loads with
respect to time is listed in Table 6.
Without prior knowledge of load dynamics, the adaptive controller
restores the frequency and voltage of DGs according to their nominal
values while ensuring appropriate power sharing. From Fig. 9, it can be
seen that at t = 1 s, due to load variation, the frequency and voltage of
DGs suffer from deviations, i.e., 0.08 Hz in frequency and 4.3 V in
voltage. These deviations from their references are restored by the
proposed controller very efficiently and within 0.12 s, it comes to its
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Electric Power Systems Research 214 (2023) 108910
steady-state, which demonstrates the robustness of the controller against
load variations. At t = 2 s, the loads L1 and L2 are half, and loads L3 and
L4 are doubled, then the same steady performance and transient
response can be observed as shown in Fig. 9.
6.3. Synchronization from IS to GC mode
The performance of controllers is tested during the transition from IS
to GC mode. It is considered that initially, an MG works in an IS mode. At
t = 1 s, a distributed synchronization controller is activated and an
Active Synchronization (AS) mode is initiated. An SS will remain open at
this stage until the VP difference between PCC and UG meet the syn­
chronization criteria defined in Table 5. The simulation results of a
conventional PI controller used to generate the correction signals for the
SC are presented in Fig. 10. The frequency and voltage magnitude at PCC
and UG are shown in Fig. 10(a) and 10(d). It can be observed that when
the AS mode is activated at t = 1 s, the frequency error between the UG
and PCC (Fig. 10(b)) and phase angle error (Fig. 10(c)) decreases
gradually and at t = 2.3 s it meets the synchronization criteria. At the
same time, the instantaneous voltage differences between PCC and UG
also decrease gradually as exhibited in Fig. 10(e) while the instanta­
neous grid currents are shown in Fig. 10(f). After attaining the syn­
chronization criteria for 0.1 s, an SS changes its state and an MG is said
to be synchronized with the UG.
Although a smooth synchronization is achieved using a PI controller,
compared to the advancement in MG technology, performance
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Fig. 10. Results of synchronization process using PI controller (a) frequency of PCC and grid, (b) frequency difference among PCC and grid, (c) phase angle difference
among PCC and grid, (d) voltage magnitude at PCC and grid, (e) voltage magnitude error of 3ϕ between PCC and grid, and (f) grid current.

12
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Fig. 11. Results of synchronization process using FPI controller (a) frequency of PCC and grid, (b) frequency error among PCC and grid, (c) phase angle error among
PCC and grid, (d) voltage magnitude at PCC and grid, (e) voltage magnitude error of 3ϕ among PCC and grid, and (f) grid current.

13
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

Fig. 12. Results synchronization process using SD based FLC (a) frequency of PCC and grid, (b) frequency error among PCC and grid, (c) phase angle error among
PCC and grid, (d) voltage magnitude at PCC and grid, (e) voltage magnitude error of 3ϕ between PCC and grid, (f) grid current, (g) single phase voltage phasor
waveforms of grid and PCC without regulation, and (h) single phase voltage phasor waveforms of grid and PCC with regulation.

14
M.Y.A. Khan et al.
Fig. 12. (continued).
degradation is observed from the simulation results. Hence, the con­
trollers discussed above are used to achieve a seamless reconnection
with a fast transient response and minimal steady-state deviation. The
performance of the FPI controller addressed in Section 4.1 is depicted in
Fig. 11. The frequency and voltage magnitude at PCC and UG are pre­
sented in Fig. 11(a) and 11(d). It can be observed that when an AS mode
is activated at t = 1 s, the frequency error between the UG and PCC
(Fig. 11(b)) and phase angle error (Fig. 11(c)) decreases gradually and at
t = 1.5 s it meets the synchronization criteria. Simultaneously, the
instantaneous voltage differences between PCC and UG and grid injected
currents reach their desired values as exhibited in Fig. 11(e) and 11(f).
After attaining the synchronization criteria for 0.1 s, an SS changes its
state from open to close and a MG is said to be synchronized with the UG.
The performance of the system is further enhanced by using an SD
based FLC (discussed in Section 4.2). The simulation results of this
controller during the synchronization process are depicted in Fig. 12.
The results show that the controller meets the synchronization criteria at
t = 1.4 s and the signal for triggering a SS is sent at 1.5 s and; hence a
seamless synchronization is achieved. When an SS closes, at that instant,
the grid currents are very minute, thus resulting in no inrush current as
presented in Fig. 12(f). Moreover, the simulation results of a VP without
a correction signal generated controller (a secondary controller did not
receive compensation signals) are presented in Fig. 12(g). The result
shows that without the correction signals, a smooth transition is not
achieved and there will always be a phase angle difference between the
UG and PCC. On the contrary, a smooth synchronization is attained by a
proposed control architecture as shown in Fig. 12(h).
7. Conclusion
This manuscript presents a pinning consensus-based distributed
control strategy for a multi-bus system to ensure a seamless reconnec­
tion of IS microgrid with the UG. The phase, frequency, and magnitude
of the system are regulated explicitly and simultaneously while ensuring
appropriate power sharing among the DGs; thus, the reliability and
resiliency of the system are improved. The efficacy of the proposed
method is validated through simulation results under different scenarios
such as (a) PnP capability in GC Mode, (b) robustness to load variation in
Appendix 1
Proof: Let [1]n,m denotes an n × m all ones matrix. If the secondary controller in (17b) converges then the term of the left hand side becomes zero
and the formulation for voltage regulation and Q-sharing of an ith-DG can be expressed as:
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Electric Power Systems Research 214 (2023) 108910
IS mode, and (c) synchronization from IS to GC mode. From the simu­
lation results, it can be concluded that the proposed secondary controller
shows a fast dynamic response and low steady-state deviation in all
scenarios compared to a conventional controller with fixed gain pa­
rameters. Moreover, it can be observed that during the synchronization
process, FPI and SD based FLC show stable, superior, and robust per­
formance compared to PI controller. Besides, the proposed controllers
have a fast dynamic response, less sensitivity to uncertainties or dis­
turbances, and fewer oscillations than the conventional fine-tuned PI
controller.
In the future, it is aim to investigate the robustness of the proposed
controller with prosumer activities. Moreover, the communication in an
MG was considered ideal in this article; therefore, the performance of
the controller under constant, fast, and stochastic communication delays
can be investigated in the future.
Funding information
This research work is supported by “Natural Science Foundation of
Jiangsu Province, China (BK20220977)”.
CRediT authorship contribution statement
Muhammad Yasir Ali Khan: Conceptualization, Methodology,
Writing – original draft, Validation, Visualization. Haoming Liu:
Conceptualization, Supervision, Writing – review & editing, Formal
analysis, Investigation. Jie Shang: Software, Resources, Data curation,
Visualization. Jian Wang: Formal analysis, Writing – review & editing,
Supervision, Project administration, Funding acquisition.
Declaration of Competing Interest
The authors declares no conflict of interest.
Data availability
No data was used for the research described in the article.
M.Y.A. Khan et al. Electric Power Systems Research 214 (2023) 108910

∑
n ( )
Qi Qj
bij − = − βi ΔEs∗ (32)
i=1
Qiref Qjref

It is stated above that a minimum of one DG must be selected as an R-DG, i.e. [β] = diag(β1 , β2 , ........, βn )[1]n,1 where βi ≥ 0. Hence, (32) can be
presented in matrix form as:
L[Q] = − [β]ΔEs∗ (33)

where L represents the Laplacian matrix of the cyber network. Hence, (33) can be written as:
L[Q] + L[ΔQ] = − [β]ΔEs∗ (34)

where, [Q] = avg(Qi /Qiref ).[1]n,1 and [ΔQ] = [Q] − [Q] = (ΔQ1 , ΔQ2 , .................., ΔQn ) denotes the steady state errors of Q-sharing in each DG. Hence
L[ΔQ] = 0 and multiply [1]n,1 on both sides of (34) we get,

L[Q][1]n,1 = − ΔEs∗ [1]n,1 [β] (35)

It can be proved easily that [1]n,1 L = 0 thus − ΔE∗s [1]n,1 [β] = 0. Recall that the [β] is a non-zero vector, thus it can be concluded that ΔE∗s = 0 and [Q]
= [Q]. Hence, it can be concluded that the proposed controller will converge without introducing any steady state error in either of voltage regulation
or Q-sharing regulator. Moreover, it also indicates that any DG can be selected for regulation, as the selection of βi > 0 does not affect the controller
performance.

Appendix 2

To update the SC gain (GE) in (17b) in order to withstand with system uncertainties, a general PI update law is given as:
∫t
GE = kpE (t)eE (t) + kiE (t) eE (t)dt (36)
0

where, eE = (Ei − Eref ). In this research work, a BP algorithm is used while designing an API controller and is given as:
1
J = eE 2 (t) (37)
2
The gain of BP algorithm can be calculated as:
dJ
kE− new =− γ (38)
dkE− new
The controller’ new gain parameters and learning procedure are given as:
[ ]
dJ ∂J ∂E ∂v
kpE− new = − γ =− γ = − γe2E (t)kpE (t) (39a)
dkpE ∂E ∂v ∂kpE
[ ]
dJ ∂J ∂E ∂v
kiE− new =− γ =− γ = − γe2E (t)kiE (t) (39b)
dkiE ∂E ∂v ∂kiE
The desired updated values of proportional and integral gains of the controller can be presented as:
[ ]
kpE (t + 1) = kpE (t) + kpE− new (t) = kpE (t) 1 − γe2E (t) (40a)
[ ]
kiE (t + 1) = kiE (t) + kiE− new (t) = kiE (t) 1 − γe2E (t) (40b)

The parameters of PI controllers in (36) can be updated as:

[ ∫ ]
[{ ( )} ] { ( )}
GE = kpE (t) 1 − γe2E (t) eE (t) + kiE (t) 1 − γe2E (t) eE (t)dt (41)

As GE is the updated parameter of the controller, therefore the secondary controller in (17b) becomes:
[ [ ∫ ]] [ ∑n
]
dui [{ ( )} ] { ( )} ( ) ( )
= 2 2
kpE (t) 1 − γeE (t) eE (t) + kiE (t) 1 − γeE (t) eE (t)dt . ∗
aij uj − ui − Ei − Eref − βi ΔEs (42)
dt j=1

A proposed BP based API controller ensures that each DG operates at the reference voltage to attain synchronization while maintaining optimal Q-
sharing among the DGs.

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