Q-15 is Mandatory and must be completed by every student and provide your answers for

additional four questions.

1. A four-bit ring counter and a four-bit Johnson counter are in turn clocked by a 10 MHz clock
signal. Determine the frequency and duty cycle of the output of the output flip-flop in the two
cases.
2. Determine the number of flip-flops required to construct (a) a MOD-10 ring counter and (b) a
MOD-10 Johnson counter. Also, write the count sequence in the two cases.
3. Show state diagram of a modulo-4 counter?
4. What do we mean by shifting left (i) a binary word 1001 0101 (ii) word 0010 0101 1001 0100? If
we shift twice then what will be the result.
5. The output frequency of a Mod-16 counter, clocked from a 10kHz clock input signal is a) 10 kHz
b) 26 kHz c) 160 kHz d) 625 Hz
6. The number stored in a 4-bit binary up-counter is 0101. What will be state of the counter after
the following clock pulses? (a) 3rd clock pulse (b) 5th clock pulse (c) 8th clock pulse (d) 12th
clock pulse
7. A binary number is to be divided by 64. By how many positions will you shift the number and in
what direction.
8. With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in ___
seconds.
9. The sequence 1011 is applied to the input of a 4-bit serial shift register that is initially cleared.
What is the state of the shift register after three clock pulses?
10. A shift register has seven flip flops. What is the largest binary number that can be stored in it?
Octal number? Decimal number? Hexadecimal number?
11. What is the basic difference between a latch and a flip-flop?
12. Assume the clock for a 4-bit binary counter is 80 kHz. The output frequency of the fourth stage
(Q3) is
13. A four-bit binary UP counter is initially in the 0000 state. Then the clock pulses are applied. Some
time later the clock pulses are removed, and at that the counter is observed to be in the 0011
state. What is the minimum number of clock pulses that could possibly have occurred?
14. An eight-bit binary ripple UP counter with a modulus of 256 is holding the count 01111111.
What will be the count after 135 clock pulses be?
15. Design of a 2 bit SISO shift register which shifts from left to right if mode is 1 and right to left if
mode is 0.