UART I2C SPI

about 230 Kbps to 460 100 kbps, 400 kbps, and 3.4
Data rate Kbps Mbps about 10 Mbps to 20 Mbps
four signals: clock (SCLK),
master output/slave input
(MOSI), master input/slave
output (MISO), slave select
Num of Transmitter Tx, Receiver (SS), each slave needs its
Lines Rx 2-wire (data and clock) own slave select line
Type Asynchronous Synchronous Synchronous
Commn full duplex full duplex
Distance about 50 feet Higher highest
devices use independent
clocks. common clock signal
necessary for the baud between multiple masters one common serial clock
Clock rates and multiple slaves. between master and slave.
Hardware
complexity lesser more less
8 bits of data, one start bit start and stops bits. an ACK specific protocols per
Protocol and one stop bit bit for every 8 bits of data manufacturer
error checking error checking mechanisms:
Error mechanisms: parity bit ACK/NACK bit
slave connected with the
Software Each master, slave devices master is addressed by a
addressing no need for addressing have soft addresses slave select line.
Master- cannot support a multi- master/slave, supports master/slave, cannot
slave arch master multi-master support a multi-master
good choice for short-
distanced, low-speed
peripheral devices like
sensors memory devices

CAN & LIN

LIN and CAN bus integration
 LIN CAN FlexRay
1 - Wire 2 - wire, differential pair
messages are initiated by the multi master, broadcast
single master
16 nodes (1 master and 15 slaves) Multiple nodes (20, 32)
typically 12 V 3.3v
8v to 9v
(<20 kbps) up to 1 Mbps
1k ohms 120 ohms
less critical non-safety functions high integrity, excellent error detection and correction

Checksum over the Protected CRC computation over the entire frame
Identifier and Data fields
Lower cost
maximum length 40 meters 40 meters
or
1-5 kilometers ???
Synchronous Asynchronous