Tessent® Scan and ATPG

Lab
Understanding ATPG Messaging

 Mentor Graphics Corporation

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 Table of Contents
Before you Begin ......................................................................................................4

Lab Understanding ATPG Messaging ...................................................................6

Introduction ............................................................................................................6
Objectives...............................................................................................................6
Exercise 1: Analyzing ATPG Messaging ..............................................................7
Exercise 2: Determining the Cause of Undetected Faults ...................................19
Exercise 3: Getting a Quick Estimate of Test Coverage .....................................29

Appendix: Answers to Questions ..........................................................................32

Exercise 1 .............................................................................................................32
Exercise 2 .............................................................................................................36
Exercise 3 .............................................................................................................39

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 Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must
download and extract the lab data as described in the "Obtaining Lab Data
Caution
section below.

Whenever you are using the VM for lab exercises and are finished with your
session, please use the "Disconnect" feature of the Desktop Viewer before the
VM times out to preserve the data from one session to the next. Failure to do
so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you
to follow the download and extract process. This allows you to "refresh" the
lab data so you can go through the labs again with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed
environment variables already setup.

Obtaining Lab Data

If the atpg_data directory, with lab subdirectories, is located in the home

directory (e.g. cd ~), please proceed to the lab exercises as you have already set
up the lab database on this VM.

If this is the first time you are starting a session for this VM, the atpg_data
directory will not be in the home directory and you will need to download and
extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a

web browser.

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 2. On the resulting web page, select the file named
tessent_atpg_data_v2020.1_20200611.tgz,

3. In the resultant window, select the Download button, enable the Save File
button, then select the OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using
the terminal (Applications>Favorites>Terminal) you can use the following
command:

mv ./Downloads/tessent_atpg_data_v2020.1_20200611.tgz .

4. In a terminal window, extract the files from the compressed tar file using the
command:

tar xzvf ./tessent_atpg_data_v2020.1_20200611.tgz

You should now have a directory named atpg_data in your $HOME directory.
That directory contains all the files you need to perform the exercises, in this
learning path.

You are now ready to proceed with lab exercises.

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 Lab
Understanding ATPG Messaging

Introduction
In this lab you will gain some experience with reading and analyzing ATPG
messaging, as well as determining the cause of undetected faults. You will also
obtain a quick estimate of test coverage.

All the exercises in this lab are performed from the command line using
Tessent Shell, which checks out a Tessent FastScan license to perform ATPG.

Objectives
Upon completing this lab, you should be able to:
 Interpret the following reports and messages generated by the ATPG tools:
o Invocation messages/warnings
o DRC reports/messages
o ATPG reports
o Fault classifications
o Special messages
o Test coverage report

 Determine the cause of an undetected fault

 Use common methodologies to attain a quick estimate of pattern coverage

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Exercise 1: Analyzing ATPG Messaging

In this exercise you:
 Invoke Tessent Shell on a design and generate test patterns.
 Read and analyze invocation, warning, exiting setup mode, DRC, ATPG,
fault classifications, special, and test coverage messages.
 Create test patterns using the create_patterns command and observe
the messaging.

Setup Instructions
1. Log in to your workstation if you are not already logged in.
2. Change to the $ATPG_LABS/Lab4/Exercise1 directory.
shell> cd $ATPG_LABS/Lab4/Exercise1

Invoke Tessent Shell and Observe Messaging

Invoke Tessent Shell with the following:
Design: design/piccpu.v
Library: ../../libs/adk.atpg
Log file: logs/ex1.log

Be sure to use the –replace switch with the log file or you could generate
an error message if that file already exists.
Note

1. Invoke Tessent Shell and designate a logfile.

shell> tessent -shell -logfile logs/ex1.log -replace

You are inside of the tool and should have the SETUP prompt.

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2. Now you have to set the context.

SETUP> set_context patterns -scan

3. Next read in the Verilog file.

SETUP> read_verilog design/piccpu.v

4. Read in the library files.

SETUP> read_cell_library ../../libs/adk.atpg

5. Now elaborate the design using set_current_design.

SETUP> set_current_design

6. Study the session transcript window and identify the following:

Notes and warning messages:

What is defined as the top of the design? ______________________

Which modules are undefined?

_______________________________________________________

What is the issue with the nets?

_______________________________________________________

What is the issue with some of the pins in the undefined module?

_______________________________________________________

7. Specify the undefined module as black box. (Use the command listed in
the session transcript window as a warning.)

At the SETUP prompt, enter:

SETUP> add_black_boxes -Auto

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8. Show the usage help message for the add_black_boxes command and
explain what the -Auto switch does.

a. At the SETUP prompt, enter:

SETUP> help add_black_boxes

Does this give you the information you need? ______________________

b. Display the reference manual page for add_black_boxes.

SETUP> help add_black_boxes -manual

What does -Auto do?

___________________________________________________________

___________________________________________________________

Black boxing can be used for the following:

o Analysis and coverage investigations of incomplete designs

o Defining blocks that test patterns will not be generated such as

analog blocks, TAP controllers, or proprietary Intellectual Property
(IP).

Add Clocks and Observe Messaging

1. Use the analyze_control_signals -auto_fix command to define the
clocks.

SETUP> analyze_control_signals -auto_fix

2. Study the various messages and warnings that display in the session
transcript window and answer the following questions. Remember to look
in the documentation if you need help answering the questions.

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Understanding ATPG Messaging

a. What is an FN1 violation?

_________________________________________________________

You also can find FN1 rule violations by entering the following
command:
SETUP> report_flattener_rules FN1 -verbose

b. What is a FN4 violation?

___________________________________________________________

c. This time, save the reported FN4 rule violations to a file:

SETUP> report_flattener_rules FN4 -verbose > FN4.txt

FN rules (flattening rules) serve to notify users of issues encountered

during the flattening of the design netlist. Rules are checked during the
flattening, which is the merging of the Verilog netlist and the ATPG cell
library into internal data structures for ATPG.

The tool replaces the design cells in the netlist with DFT primitives. The
netlist is flattened and stored in an internal format.

Find the following information reported after flattening:

Number of simulation gates (gates): _____________________________

Number of primary inputs: _________ primary outputs: ___________

The tool classifies characteristics of the design in order to improve ATPG

efficiency. This process is called circuit learning.

3. Look at the results of the circuit learning analyses and identify the
following:
How many control signals were identified in all? ______________

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Understanding ATPG Messaging

a. How many clocks are there? ______________________________

4. (Optional) Using any text editor, view FN4.txt that was created in the step
above.
How many unused instance nets are there? ________________________

Add Scan Group, Test Procedure File, and Scan Circuitry

This design has been scan inserted. In most cases, no matter what scan insertion
tool is used, the dofile and test procedure file is also generated. For this part of
the lab, you will manually create what would normally be the dofile.

1. Create a scan group.

Group Name: grp1

Test Procedure file: results/gate_afterdft_100.testproc

SETUP> add_scan_groups grp1 \
results/gate_afterdft_100.testproc

2. Open any text editor and view results/gate_afterdft_100.testproc

a. Examine the file.

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Figure 4-1. Test Procedure File

3. Create four scan chains.

SETUP> add_scan_chains chain1 grp1 /scan_in5 /scan_out1

Use the example above and the following table to add the rest of the scan
chain definitions.

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Chain Group Scan_in Scan_out

chain1 grp1 scan_in5 scan_out1

chain2 grp1 scan_in6 scan_out2

chain3 grp1 scan_in7 scan_out3

chain4 grp1 scan_in8 scan_out4

Table 4-1. Scan Chain Definitions

4. Run design rule checks.
SETUP> check_design_rules

Tessent Shell performs Design Rule Checks using the information in the test
procedure file.
Several messages are written to the session transcript window:

How many memory elements are there? ___________________

What is the length of each of the four scan chains?

chain1______chain2______chain3______chain4______

What is an E5 violation?

____________________________________________________

What does the manual say about E5 violations with regards to regular
(uncompressed patterns) ATPG?

____________________________________________________

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Understanding ATPG Messaging

How many scan clock/set/reset lines have been identified?

____________________________________________________

5. Generate test patterns (create_patterns).

Observe the reported messages and status in the session transcript window
during test pattern generation and answer the following questions.

How many patterns were generated?

_________________________________________________________

6. Scroll up in the session transcript window until you come to the place
where the tool does an analysis on the design. This analysis is done right
after you enter the create_patterns command. You should see a
section called “Analyzing the design”. Adjust the window as needed so
that you can view the report. If you have trouble scrolling up to the
“Analyzing the design” report, open the logfile and view it there.

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Understanding ATPG Messaging

Figure 4-2. Log File

A record of the session is kept in the logfile, which you created at the
beginning when you launched Tessent Shell (logs/ex1.log). You always can
Note refer to the logfile whenever you want to glean information or troubleshoot a
problem in the session. For this reason, Mentor Graphics recommends that
you always create a logfile when you invoke Tessent Shell.

This report shows the results of analyzing the design and design rule
checking. Tessent Shell will modify parameters to improve coverage.

We will discuss the details of the DRC analysis and how it affects the
pattern generation in the Design Rule Check module.

7. Observe the detailed report issued by the create_patterns command.

The test pattern statistics display in the session transcript window. This
information provides data about faults in each class and across all classes.
Details of coverage, pattern count, and the number of simulations performed
during pattern generation are reported here.

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8. Refer to the session transcript window and fill in the following tables.

Fault Class # Faults

FU (full)

UO (unobserved)

DS (det_sim)

DI (det_imp)

PU
(posdet_untestable)

PT (posdet_testable)

UU (unused)

TI (tied)

RE (redundant)

AU (atpg_untestable)

Table 4-2. Statistics Report

Regarding the AU faults, how are they further broken down? __UDN, BB,
WIRE, SEQ, Unclassified__________
_____________________________________________________________

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The aborted faults are those that are still untested after the abort limit was
increased.
For more information on fault classes, see “Fault Modeling” and “Fault
Classes” in Chapter 2 of the Tessent Scan and ATPG User’s Manual.
Note

# Total Faults
Coverage/Effective
ness

test_coverage

fault_coverage

atpg_effectiveness

#test_patterns

#basic_patterns

#clock_sequential_patterns

# simulated_patterns

CPU_time (secs)

Table 4-3. Test Coverage Effectiveness Statistics

9. Notice that the faults are grouped into classes.

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Understanding ATPG Messaging

How many faults are untestable? ______________

Note: Remember, untestable faults are classified as unused, tied, blocked,
redundant.

How many faults are undetected? _________________

Note: These are faults that have not been detected with a test pattern yet.

What sub-groups are categorized as atpg_untestable?___________________

_____________________________________________________________

How many faults are UC+UO, and what fault sub-type is reported?
________________________
Looking at the results, what observation can you make regarding the sub-
category black_boxes? __________________________________________

_____________________________________________________________

10.Exit Tessent Shell without saving patterns.

ANALYSIS> exit -f

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Understanding ATPG Messaging

Exercise 2: Determining the Cause of Undetected Faults

In this exercise, you use Tessent Shell to create test patterns. After test pattern
generation, you determine the cause of one of the undetected faults by using the
following commands:
 report_faults
o Display fault information from the current fault list
 analyze_fault
o Identify why a fault is not detected

Setup Instructions
1. Change to the $ATPG_LABS/Lab4/Exercise2 directory.
shell> cd $ATPG_LABS/Lab4/Exercise2

Invoke Tessent Shell and Add Clocks

By now you should realize the value of invoking Tessent Shell with an
invocation dofile. After all, it will save you a lot of typing! In this next exercise,
you startup Tessent Shell using setup_tessent_shell.do.
1. The solutions/setup_tessent_shell.do file does the following :

o Sets the Tessent Shell context (patterns -scan)

o Reads the design: design/piccpu.v
o Reads the ATPG cell library: ../../libs/adk.atpg
o Elaborates the design (set_current_design)

Invoke Tessent Shell at the system prompt.

shell> tessent -shell -dofile \

solutions/setup_tessent_shell.do -logfile \
logs/ex2.log -rep

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Understanding ATPG Messaging

2. Study the session transcript window and identify the following:

Information messages:
 Reading Verilog netlist and cell library

Warning messages:

What warning messages do you see?

_________________________________________________________

_________________________________________________________

3. Specify undefined modules as black boxes. (Use the command listed in

the session transcript window as a warning.)

4. Add clocks.

Various messages and warnings display in the transcript. What warning

messages do you see?

____________________________________________________________

____________________________________________________________

Add the Scan Group, Test Procedure File, and Scan Circuitry
A dofile has been saved for you to add the scan groups and scan chains. The
exact same commands from the previous exercise have been saved into a file
called results/add_scanchains.do. Use this file instead of typing the commands as
you did in the previous exercise.
1. Set up the scan group and scan chains.
SETUP> dofile results/add_scanchains.do

2. Run design rule checks.

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Several informational messages are output as it goes through the procedure.

a. How many memory elements are there?

_________________________________

b. What happens during the scan chain identification process?

_______________________________________________________

What warning is generated about the effect of the scan chains and the
patterns that will be generated? _________________________________
___________________________________________________________

3. Ignore any DRCs and generate test patterns for stuck-at faults.
ANALYSIS> create_patterns

4. Note the number of untestable faults Unused (UU) Redundant (RE), and
Tied (TI) fault classes.

Unused (UU) __________________

Redundant (RE) ______________

Tied (TI) ________________________

5. How many faults are classified as AU faults and what are the sub
classifications?

Number of AU faults: _________

Sub-classifications of AU ______________________________________

How might black boxes affect test coverage?

_________________________

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Understanding ATPG Messaging

Figure 4-4. Statistics Report

Also note the undetected faults UC+UO. What sub-heading is listed under this
fault type?
________________________

Remember that AU, UC and UO are sub classifications of Undetected.

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Understanding ATPG Messaging

6. What types of test patterns make up the complete set, and how many patterns
of each type are there?

________________________ No. of patterns ___________________

________________________ No. of patterns ___________________

Analyze the Various Fault Classes

Notice that there are still undetected faults affecting test coverage. You analyze
these and determine their cause. First, take a look at the various fault classes and
analyze them. What does fault grouping tell you about the undetected faults?
_________________________________________________________________
_________________________________________________________________

For more information on fault modeling and fault classes, see Chapter 2 of
the Tessent Scan and ATPG User’s Manual.
Note

Analyze an Individual Fault

1. In this exercise, you practice searching for and analyzing ATPG
undetected fault. First, report a specific fault classification and direct the
report output to a file. You get fault information from the fault list for
your analysis from this file.
ANALYSIS> report_faults -class au > AU_faults.txt

2. Open AU_faults.txt in a text editor.

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Understanding ATPG Messaging

Figure 4-5. Fault List File

3. Search for instance/pin /p4/pic1/U1511/Y to find the pin path example.

The following information for every fault in the AU class displays:

o Type (fault value) — stuck at 1 or 0
o Code (fault code) — AU (in this case) — what additional
information about the AU fault can you discern?
________________________________________________
o Pin Pathname (fault site) — example: /p4/pic1/U1511/Y

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Understanding ATPG Messaging

This gives you all the information needed to further investigate individual
faults.

4. Further investigate the fault.

ANALYSIS> analyze_fault /p4/pic1/U1511/Y -stuck 0

Why did you use -stuck 0?

What does the resulting fault analysis tell you about the fault?

_________________________________________________________

_________________________________________________________

Where is the fault blocked? ___________________________________

5. Analyze another fault and investigate further. This fault is reported as

AU.BB in the fault list. Recall that BB stands for ________________.
ANALYSIS> analyze_fault /p7/pic1/add_794/U8/Y -stuck 1

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What does the resulting fault analysis tell you about the fault?
_________________________________________________________

_________________________________________________________

_________________________________________________________

Analyze Faults Using the Fault Analysis in Tessent Visualizer

Schematic Window

Another useful way to analyze faults is through the Tessent Visualizer Flat
Schematic window. Analyze the fault /p5/pic1/U1511/A2 using this method.

1. Analyze the fault and display the debug window in Tessent Visualizer

ANALYSIS> analyze_fault /p5/pic1/U1511/A2 -stuck 1 \

-display

This performs the analysis we’ve seen previously and reports the results
to the transcript and opens the Flat Schematic window and displays the
instance where the AU fault resides, and the instance that is driving the
specific port.

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a) Click with your LMB on pin /U1511/A2 to show the connection

of the two instances

In Tessent Visualizer menu bar, select Settings > Gate Report.

From the Gate Report Settings dialogue box, select Fault Status and click
OK.

This will display the fault classifications for the displayed instances.

Notice that the faults are reported in the form of AU.BB-AU.BB. The first
set before the colon is the fault class for stuck-at-0 followed by the fault
class for stuck-at-1. So, for this example, the node at the Y output of the
NOR gate is AU.BB for stuck-at-0, and AU.BB for stuck-at-1. Notice that
the fault designation is BB.

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Recall from the analyze_fault report in the transcript window, the fault is
said to be blocked at what instance? ________________________________

_____________________________________________________________

What behavior is causing the fault to be blocked? _____________________

_____________________________________________________________

2. Click the LMB on the Y output of U1511. Notice that this displays the
picdram that you placed into a blackbox at the beginning of the lab.
This is what is causing the blockage.

3. When you are finished, exit Tessent Shell.

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Tessent Scan and ATPG – Lab Answers

Exercise 3: Getting a Quick Estimate of Test Coverage

In this exercise, you invoke a design in Tessent Shell and use fault sampling at
10% to obtain a quick estimate of test coverage. Then, you use fault sampling
again at 100% and apply pattern types to determine full test coverage.

Setup Instructions
1. Change to the $ATPG_LABS/Lab4/Exercise3 directory.
shell> cd $ATPG_LABS/Lab4/Exercise3

Invoke Tessent Shell and Add Clocks

1. Invoke Tessent Shell using the dofile setup_tessent_shell.do. The dofile
performs the following steps:

o Sets the Tessent Shell context (patterns –scan)

o Reads the design: design/piccpu.v

o Reads the ATPG Libraries: ../../libs/adk.atpg, ../../libs/picdram.atpg

o Elaborates the design

shell> tessent -shell -dofile \

solutions/setup_tessent_shell.do \
-logfile logs/ex3.log -replace

Various messages and warnings appear in the transcript. What warning

messages do you see?

____________________________________________________________

____________________________________________________________

2. Add clocks.

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Tessent Scan and ATPG – Lab Answers

Add Scan Group, Test Procedure File, and Scan Circuitry

A dofile has been saved for you to add the scan groups and scan chains. The
exact same commands from the previous exercise have been saved into a file
called add_scanchains.do. Use this file instead of typing the commands at the
SETUP prompt.
1. Set up the scan group with the following information:
SETUP> dofile results/add_scanchains.do

2. Run design rule checks

Assess Test Coverage Through Fault Sampling

Fault sampling is a method for obtaining a quick estimate of pattern coverage for
large circuits. Fault sampling creates a smaller pattern set for simulation. Use the
set_fault_sampling command to specify a percentage (between 0 and 100) of
the total number of faults you want to process.

1. Specify a fault sampling of 10%.

ANALYSIS> set_fault_sampling 10

2. Generate test patterns.

3. Examine the statistics report and complete the “Fault Sample 10%
column.

Fault class Fault Sample 10% Fault Sample 100%

Total Faults

det_simulation (DS)

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det_implication (DI)

Test Coverage

Fault Coverage

Total Patterns

Table 4-4. Fault Statistics

4. Next, remove the fault sample.
ANALYSIS> set_fault_sampling off

5. Reset circuit status and delete internal patterns.

ANALYSIS> reset_state

6. Create patterns.

7. Complete the Fault Sample 100% column in the table.

8. Exit Tessent Shell.

Review

What command do you use to show fault classifications and coverage?

___________________________________________________________

What command do you use to generate a report of a specific fault classification?

___________________________________________________________

What command do you use to analyze a specific fault?

__________________________________________________________

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Tessent Scan and ATPG – Lab Answers

Appendix: Answers to Questions

These labs were qualified using Tessent 2020.1 and ModelSim 2020.2, if
other Tessent versions were used, results contained in tables in these labs
Note may differ slightly from those shown in this Lab Answers section.

Exercise 1

Invoke Tessent Shell and Observe Messaging

Step 6
What is defined as the top of the design? cpu_top
Which modules are undefined? tbuf, picdram, nand02_tst
What is the issue with the nets? Undriven net in netlist module.
What is the issue with some of the pins in the undefined module?

Undefined module pins, 3 assumed to be inputs, 1 assumed to be inout

Step 8
 Does this give you the information you need? Yes

 What does -Auto do?

o Use add_black_boxes with the -Auto switch to automatically
blackbox all instances of models that are considered to be
undefined

Add Clocks and Observe Messaging

Step 2
 What is an FN1 violation? This rule determines if a module net is floating

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 What is a FN4 violation? This rule determines if an instance net is not

used
 Number of simulation gates (gates): 30207
 Number of primary inputs: 44 primary outputs: 91

Step 3
 How many control signals were identified in all? 4 control signals
 How many clocks are there? 4 clocks

Step 4
 As you did in Lab 2, open the Text Viewer, then view FN4.txt that was
created in the step above.
How many unused instance nets are there? 1484

Add Scan Group, Test Procedure File, and Scan Circuitry

Step 4
How many memory elements are there? 1484 memory elements
What is the length of each of the four scan chains?

chain1 722; chain2 381; chain3 254; chain4 127;

What is an E5 violation?

When the application places constrained states on constrained pins and

binary states on PIs and scan cells, X states must not propagate to an
observable point. Failure to satisfy this rule will result in the risk of X
states propagating to an observable point
What does the manual say about E5 violations with regards to regular
(uncompressed patterns) ATPG?
With regards to regular ATPG (E5): has no effect on
uncompressed ATPG
How many scan clock/set/reset lines have been identified? 4 scan
clock/set/reset lines

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Step 5
How many patterns were generated? 302 patterns were generated

Step 8
Table 4-2: Report Statistics

Report Statistics

Fault Class # Faults

FU (full) 142594

UO (unobserved) 70

DS (det_sim) 117742

DI (det_imp) 9884

PU 40
(posdet_untestable)

PT (posdet_testable) 7

UU (unused) 56

TI (tied) 91

RE (redundant) 12159

AU (atpg_untestable) 2545

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Regarding the AU faults, how are they further broken down?

UDN (undriven) 574 ( 0.40%)
BB (black_boxes) 870 ( 0.61%)
WIRE (dominated_by_wire) 196 ( 0.14%)
SEQ (sequential_depth) 42 ( 0.03%)
Unclassified 863 ( 0.61%)

 Table 4-3: Test Coverage Effectiveness Statistics

Coverage/Effectiveness # Total Faults

test_coverage 97.97%

fault_coverage 89.52%

atpg_effectiveness 99.95%

#test_patterns 302

#basic_patterns 82

#clock_sequential_patterns 220

# simulated_patterns 302

CPU_time (secs) 12.6

Step 9
How many are faults are untestable? UT: 12306
How many faults are undetected? UD (UC+UO): 70

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Tessent Scan and ATPG – Lab Answers

 What sub-groups are categorized as atpg_untestable? UDN (undriven), BB

(black_boxes), WIRE (dominated_by_wire), SEQ (sequential_depth),
Unclassified

 How many faults are UC+UO, and what fault sub-type is reported? 70
UC+UO [AAB (atpg_abort) 70 ( 0.05%)]

Looking at the results, what observation can you make regarding the sub-
category black_boxes? 870 faults are contributed by black boxes in the
design but ATPG could not find patterns for it

Exercise 2

Invoke Tessent Shell and Add Clocks

Step 2
What warning messages do you see?
Warning: Undefined modules were found
Warning: 5 cases: Undriven net in netlist module
Warning: 1 case: Undefined module pin assumed to be inout
Warning: 3 cases: Undefined module pin assumed to be input

Step 4
Various messages and warnings display in the transcript. What warning
messages do you see?
Warning: Total number of loops broken = 7
Warning: Number of loops broken without duplication = 7
Warning: Rule FN1 violation occurs 6 times
Warning: Rule FN4 violation occurs 1484 times

Add the Scan Group, Test Procedure File, and Scan Circuitry

Step 2

 How many memory elements are there? 1484 memory elements

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Tessent Scan and ATPG – Lab Answers

 What happens during the scan chain identification process?

Scan chain identification process:

Reading group test procedure file results/gate_afterdft_100.testproc.
Simulating load/unload procedure in grp1 test procedure file.
Chain = chain1 successfully traced with scan_cells = 722.
Chain = chain2 successfully traced with scan_cells = 381.
Chain = chain3 successfully traced with scan_cells = 254.
Chain = chain4 successfully traced with scan_cells = 127.

1484 scan cells have been identified in 4 scan chains

 What warning is generated about the effect of the scan chains and the
patterns that will be generated?
Warning: Each pattern is 95% larger than if the scan chains were
perfectly balanced. Average chain length is 371 vs. 722 for the
longest

Step 4
Unused (UU) : 56
Redundant (RE) : 12159
Tied (TI) : 91

Step 5
Number of AU faults: 2545
Sub-classifications of AU:
UDN (undriven) 574 (0.40%)
BB (black_boxes) 870 (0.61%)
WIRE (dominated_by_wire 196 (0.14%)
SEQ (sequential_depth) 42 (0.03%)
Unclassified 863 (0.61%)
How might black boxes affect test coverage?
Black-Boxes fault contribute to 0.61% of total untestable faults and
affect test-coverage significantly since they go undetected

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Tessent Scan and ATPG – Lab Answers

Also note the undetected faults UC+UO. What sub-heading is listed under
this fault type?
UC+UO: [AAB (atpg_abort) - 70 ( 0.05%)]

Step 6
Basic patterns; No. of patterns: 82
Clock Sequential patterns; No. of patterns: 220

Analyze the Various Fault Classes

What does fault grouping tell you about the undetected faults?
According to Fault grouping, sub-classes that have undetected faults,
significantly affect the test coverage.

Analyze an Individual Fault

Step 3
 Code (fault code) — AU (in this case) — what additional information about
the AU fault can you discern? It says AU.BB meaning it is an ATPG
untestable fault with sub-class black boxes.

Step 4

Why did you use -stuck 0? To specify that we need to analyze “stuck-0”
fault.

What does the resulting fault analysis tell you about the fault? The fault site
cannot propagate to any observation point
Where is the fault blocked? Fault is blocked at /p4/pic1/regs/picdram (182)
due to tieX behavior

Step 5
 AU.BB in the fault list. Recall that BB stands for? Black-Boxes

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Tessent Scan and ATPG – Lab Answers

 What does the resulting fault analysis tell you about the fault?
Fault analysis for /p7/pic1/add_794/U8
Current fault classification = AU.BB (atpg_untestable).
Fault site cannot be set to 0 or 1 due to constrained logic and no tie
gate sources were identified.

Analyze Faults Using the Fault Analysis Dialog Window in

Tessent Visualizer

Step 1
 Recall from the analyze_fault report in the transcript window, the fault is
said to be blocked at what instance? Fault is blocked at
/p5/pic1/regs/picdram (153)

 What behavior is causing the fault to be blocked? tieX behavior

Exercise 3

Invoke Tessent Shell and Add Clocks

Step 1
Various messages and warnings appear in the transcript. What warning
messages do you see?
Warning: 2 cases: Undriven net in netlist module
Warning: Net 'CO' in module 'picalu_DW01_sub_9_0' is not driven
Warning: Net 'CO' in module 'picalu_DW01_add_9_0' is not driven

Assess Test Coverage Through Fault Sampling

 Table 4-4: Fault Statistics

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Tessent Scan and ATPG – Lab Answers

Fault Statistics

Fault class Fault Sample 10% Fault Sample 100%

Total Faults 14284 142986

det_simulation (DS) 12051 120212

det_implication (DI) 978 9935

Test Coverage 99.98% 99.95%

Fault Coverage 91.21% 91.02%

Total Patterns 154 329

Review
 What command do you use to show fault classifications and coverage?
‘create_patterns’ or in cases ‘report_statistics’

 What command do you use to generate a report of a specific fault

classification?
report_faults –class {<class name …. au/uu/etc>} > fault_name.txt
 What command do you use to analyze a specific fault?
analyze_fault {<pathname>} {-stuck/<any type>} {0/<type value>}

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