See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/220455832

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by

applying wafer level package (WLP) technology using anisotropic conductive
films (ACFs)

Article in Microelectronics Reliability · January 2012

DOI: 10.1016/j.microrel.2011.08.003 · Source: DBLP

CITATIONS READS

13 2,474

6 authors, including:

Kyoung-Lim Suk Ho-Young Son

Samsung SK Hynix
22 PUBLICATIONS 158 CITATIONS 27 PUBLICATIONS 365 CITATIONS

SEE PROFILE SEE PROFILE

Chang-Kyu Chung Joong Do Kim

Samsung Samsung Techwin Co.
35 PUBLICATIONS 235 CITATIONS 24 PUBLICATIONS 314 CITATIONS

SEE PROFILE SEE PROFILE

All content following this page was uploaded by Jin-Woo Lee on 23 September 2019.

The user has requested enhancement of the downloaded file.

This article appeared in a journal published by Elsevier. The attached
copy is furnished to the author for internal non-commercial research
and education use, including for instruction at the authors institution
and sharing with colleagues.
Other uses, including reproduction and distribution, or selling or
licensing copies, or posting to personal, institutional or third party
websites are prohibited.
In most cases authors are permitted to post their version of the
article (e.g. in Word or Tex form) to their personal website or
institutional repository. Authors requiring further information
regarding Elsevier’s archiving and manuscript policies are
encouraged to visit:
http://www.elsevier.com/copyright
 Author's personal copy

Microelectronics Reliability 52 (2012) 225–234

Contents lists available at SciVerse ScienceDirect

Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages

by applying wafer level package (WLP) technology using anisotropic
conductive films (ACFs)
Kyoung-Lim Suk a, Ho-Young Son a, Chang-Kyu Chung a, Joong Do Kim b, Jin-Woo Lee b,
Kyung-Wook Paik a,⇑
a
Department of Materials Science and Engineering, KAIST, 291 Daehak-ro, Yuseong-gu, Daejeon 305-701, South Korea
b
Samsung Techwin Co., Ltd., 701 Sampyeong-dong, Bundang-gu, Seongnam-si, Gyeonggi-do 463-400, South Korea

a r t i c l e i n f o a b s t r a c t

Article history: Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in
Received 15 April 2010 electronic devices, extensive studies on flexible electronic packages have been carried out. However,
Received in revised form 21 July 2011 there has been little research on flexible packages by wafer level package (WLP) technology using aniso-
Accepted 3 August 2011
tropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires
Available online 30 August 2011
fewer process steps and lower process temperature, and also provides flexible packages. This study dem-
onstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF)
assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.
The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 lm thin
wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump con-
tact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip
thickness is about 700 lm. To evaluate the flexibility of the COF assembly, a static bending test was per-
formed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bond-
ing processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully
fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test
(85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF pack-
ages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was sug-
gested by Finite Element Analysis (FEA) for better HTST reliability.
Ó 2011 Elsevier Ltd. All rights reserved.

1. Introduction
One of the new trends in electronic packaging technology is
the demand for flexible and compact electronics with multi-
functionality and good reliability [1–3]. Upon this, new flexible
and embedded electronic packaging technologies have been
developed.
When thin silicon chips and flexible substrates are combined,
flexible packages can be realized, since silicon chips with thickness
less than 100 lm become bendable [4–6]. Moreover, embedded
active and passive technologies, make further compactness of elec-
tronics possible. Accordingly, packages with embedded thin Si
chips in flex substrates become flexible and compact. However,
there are several disadvantages in previously reported chip embed-
ded packages or chip-in-plastic packages. The packages require
high process temperature and many processing steps such as cav-
⇑ Corresponding author. Tel.: +82 42 350 3375; fax: +82 42 350 8124.
E-mail address: kwpaik@kaist.ac.kr (K.-W. Paik).
ity formation, via opening, and metallization [7,8]. Therefore, lower
process temperature and fewer processing steps are needed in CIF
packages.
Wafer level package (WLP) technology is an excellent packaging
method that reduces both materials and process cost, since all pro-
cessing steps are performed at a wafer level [1,9]. When embedded
active technology is combined with WLPs, the package can achieve
the respective advantages of both technologies. Therefore, in this
study, a flexible Chip-on-Flex (COF) assembly and embedded
Chip-in-Flex (CIF) packages by applying WLP using anisotropic
conductive films (ACFs) have been demonstrated. The packages
have many advantages. First, they can lower processing tempera-
ture to a level lower than that 200 °C, which is typically required
for ACFs curing [10]. Second, processing steps of ACF flip-chip
assembly such as ACF slitting, ACF pre-lamination, and removal
of releasing film on each substrate, can be reduced. Third, stable
electrical and mechanical interconnections between the chip and
flex substrates can be obtained. Fourth, dense and flexible pack-
ages can be achieved.

0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2011.08.003
 Author's personal copy

226 K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234

Fig. 1 represents the schematic diagram of CIF package process-

(1) ACF lamination on a 50 µµ thin wafer
ing steps. To realize CIF packages by WLP, a COF assembly should
be performed by using thin chips with pre-applied ACFs, the proce-
dures can be broadly divided into three steps. First, ACF is lami-
nated on a 50 lm thin wafer (1). Second, the ACF pre-applied
wafer is diced into an individual chip (2). Finally, the ACF pre-ap-
plied chip is assembled on the 1st flex substrate to make the COF

(2) ACF pre-applied wafer dicing

(3) COF assembly using ACF pre-applied chip

(4) 2nd PI alignment using ACF

(5) 3rd PI alignment using ACF

Fig. 3. (a) One ninth of 8-in. wafer: 50 lm thickness, (b) chip design, and (C)
electroplated Au bumps.

(6) CIF packages by FOF bonding

Fig. 1. CIF packages processing steps.

Fig. 2. Two kinds of ACFs used in this study (a) ACF1: containing Ni/Au coated
polymer ball and (b) ACF2: containing Au coated Ni ball.

Table 1
Curing behavior of ACFs by DSC measurement.

ACF1 ACF2
Onset temperature (°C) 83 86.4
Curing time at 180 °C (s) 14.1 14.5 Fig. 4. Three kinds of flex substrates for CIF packages (a) 1st PI, (b) 2nd PI: upper
side view, (c) 2nd PI: bottom side view, and (d) 3rd PI.
 Author's personal copy

K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234 227

assembly (3). After the COF assembly process, the CIF packages can
be demonstrated by assembling 2nd and 3rd flex substrates on
pre-assembled COF packages using ACFs (4–6). In this process,
the Flex-on-Flex (FOF) bonding parameters such as bonding tem-
perature, time, and force should be optimized. Under proper bond-
ing conditions, the empty region around a chip can be filled with
ACFs, which have the advantage of easy flow due to the low viscos-
ity of the polymer resin at high temperature. This study mainly fo-
cused on the fabrication and characterization of a flexible COF
assembly using thin chips with pre-applied ACFs and the demon-
stration of CIF packages using flexible COF assembly as well as
evaluation of the reliability of the packages.
2. Experiments
2.1. Materials and test vehicles
Two types of ACFs, ACF for COF assembly (ACF1) and ACF for FOF
assembly (ACF2), were prepared to fabricate CIF packages as there
are two main processing steps: the first COF assembly and the sec-
ond FOF assembly. As shown in Fig. 2, 5 lm size Ni/Au coated poly-
mer balls were used as conductive particles in the case of ACF1 and
8 lm size Au coated Ni balls were used in ACF2. The film size of
ACF1 and ACF2 is 27 cm (w)  70 cm (l)  36 lm (t) and 7 cm
(w)  70 cm (l)  37 lm (t), respectively. The curing behavior of
ACFs is summarized in Table 1. Onset temperatures indicate
the starting points of ACFs curing and curing time indicates the
time it takes to finish the curing reaction of ACFs at 180 °C.
Based on DSC results, bonding temperature and time can be
determined.
One-ninth of a 8-in. wafer was thinned down using the CMP
(chemical mechanical polishing) method to 50 lm thickness. Au
bumps were electroplated on the wafer, which contains 6 mm 
6 mm size chips having 104 peripheral I/O bumps with dimensions
of 100 lm  100 lm  18 lm. Fig. 3 shows the 50 lm thinned test
wafer, chip design, and electroplated Au bumps.
Three kinds of flex substrates, 1st PI, 2nd PI, and 3rd PI, were
manufactured using polyimide. The 1st PI serves as a COF assembly
and for probing pads. It has 10 Kelvin test patterns to measure the
bump contact resistance of a single Au bump/ACF joint. In addition,
the 1st PI also has daisy chain resistance test patterns for measur-

Electrical properties Probing pad No.

Bump contact resistances
(10 points per sample)
1st-2nd PI
(8 points per sample)
Daisy chain
resistance
1st-2nd-3rd PI
(8 points per sample)
3~11, 6~14, 17~25, 18~26,
21~27, 31~39, 34~42,
45~53, 46~54, 48~56
1~2, 8~9, 15~16, 22~23,
29~30, 36~37, 43~44,
50~51
1~10, 9~14, 15~24, 23~28,
29~38, 43~52, 51~56

- Chip bump contact resistances: 10 points

- Daisy chain resistances from 1st PI to 2nd PI (1st-2nd PI): 8 points
- Daisy chain resistances from 1st PI via 2nd PI to 3rd PI (1st-2nd-3rd PI): 8 points
Fig. 6. COF assembly using WLP with pre-applied ACF (a) ACF lamination on a
Fig. 5. Electrical test patterns for measuring electrical properties of CIF packages. wafer, (b) ACF laminated wafer dicing, and (c) COF flip-chip assembly.

Table 2
Specifications of substrates.

Dimension 1st PI 2nd PI 3rd PI

Size (mm2) 26  26 14  14 15  15
PI thickness (lm) 20 80 (including adhesive layer) 20
Cu electrode thickness (lm) 15 Upper: 27 15
Bottom: 27
Total thickness (lm) 35 135 35
Surface finish 3 lm thick-electroless Ni immersion Au
 Author's personal copy

228 K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234

Fig. 7. Cross-sectional SEM images of COF assembly as a function of bonding forces (a) 20 N, (b) 30 N, (c) 40 N, (d) 50 N, and (e) 60 N.

ing the 1st–2nd PI continuity and 1st–2nd–3rd PI continuity of CIF

packages. The 2nd PI is a 2-metal flex substrate that functions as an
interlayer having a punched area in the middle of the PI. The 3rd PI
is for the 2nd PI interconnection and chip coverage. Figs. 4 and 5
show pictures and electrical test patterns of each flex substrate.
The number of daisy chain measurement points from 1st PI to
2nd PI is eight points per sample and each point has 8 I/Os, and
from the 1st PI through 2nd PI to 3rd PI there are eight points
per sample and each point has 12 I/Os. The specifications of all sub-
strates are listed in Table 2.

2.2. COF assembly by WLP with pre-applied ACFs

ACF1 was laminated on a thin wafer with 50 lm thickness at

80 °C for 1 min under pressure of 80 psi using a vacuum laminator.
Based on DSC measurement from Table 1, the lamination temper-
ature and time were determined, since the ACF should maintain a
Fig. 8. Results of contact resistance measurements of COF assembly. non-cured state before COF assembly. The ACF pre-applied wafer

Before curing
After COF assembly
Absorption (arb.unit)

800 1000 1200 1400 1600

-1
Wavenumber (cm )

Fig. 9. FT-IR measurement of ACF1 in COF assembly.

 Author's personal copy
K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234
Fig. 10. Bending test results (a) static bending test of COF assembly without chip
breakage, (b) contact resistances before and after bending test, (c) chip breakage at
20 mm of bending radius.
Before curing
Upper ACFs
Bottom ACFs
Absorption (arb.unit)
800 1000
Wavenumber (cm )
Fig. 11. FT-IR measurement of upper and bottom ACF in FOF assembly.
229
was diced into individual chips by a dicing method with 30 mm/s
dicing speed under 35,000 rpm. The ACF laminated chips were
then flip-chip assembled on a 1st PI at 180 °C bonding temperature
for 20 s with various bonding forces, from 20 N to 60 N. The ACF1
was fully cured within 15 s at 180 °C as shown in Table 1, and
bonding temperature and time were determined according to the
curing behavior of ACF1. After COF assembly, ACF joints between
chip bumps and PI electrodes were observed by cross-sectional
SEM images, and the contact resistances were measured as a func-
tion of bonding forces to determine the optimal bonding force. The
degree of cure of ACF1 before and after the bonding process was
calculated through FT-IR measurement comparing the epoxy peak
area around 910 1 cm. The spectra of 64 scans with a resolution of
4 cm 1 were collected in a range of 700–1700 cm 1. The absor-
bance spectra were normalized by the peak of the benzene ring
around 1507 cm 1, because the benzene ring group does not
change during the ACF bonding process, and the degree of cure
of the ACFs was calculated from the area change of the peak around
910 cm 1 (epoxy ring).
2.3. Static bending test of COF assembly
To evaluate the flexibility of the COF assembly made under opti-
mal bonding conditions at 180 °C for 15 s under a bonding force of
50 N, a static bending test was performed. Bending test samples
were prepared by attaching the COF assembly to a 200 lm thick
plastic substrate using acrylic adhesive. The bending radius of
the static bending tester was 35 mm, 30 mm, 25 mm, and
20 mm, respectively. Contact resistances were measured before
and after the bending test and compared.
2.4. Bonding force optimization of CIF packages
Before the fabrication of CIF packages, FOF assembly conditions
should be optimized. Considering the curing behavior of ACF2, as
shown in Table 1, the bonding process was performed at 180 °C
for 30 s with various bonding forces, from 75 to 150 N. The degree
of cure of ACF2 was calculated through FT-IR measurement, com-
paring the epoxy peak area around 910 1 cm, before and after
1200 1400 1600
-1
 Author's personal copy

230 K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234

Fig. 12. Cross-sectional SEM images of ACF joints of FOF assembly at various bonding forces.

COF and FOF assembly conditions, CIF packages were manufac-

tured. In order to confirm whether the 50 lm thin chip with pre-
applied ACFs was successfully embedded in flex substrates, both
the chip bump contact resistances and the daisy chain resistances
of 1st–2nd PI and 1st–2nd–3rd were measured. Optical images,
cross-sectional SEM images, and SAM images were also observed.

2.5. Reliability test

Reliability of the CIF packages was evaluated by (1) a high tem-

perature/humidity test (85 °C/85% RH), 1000 h and (2) a high tem-
perature storage test (HTST), 150 °C, 1000 h. The chip bump
contact resistances, the 1st–2nd PI daisy chain resistances, and
the 1st–2nd–3rd PI daisy chain resistances of the CIF packages
were monitored during the reliability tests.

3. Results and discussion

3.1. COF assembly by WLP with pre-applied ACFs

According to the COF assembly results shown in Fig. 6, ACF1 was

well laminated on one-ninth of the 50 lm thin wafer without void
formation or wafer breakage, and the ACF1 laminated wafer was
clearly diced into individual chips without ACF delamination or
Si particle contamination. The amount of absorbed moisture was
lower than 1 wt.% after wafer dicing; this was considered negligi-
ble, since it was reported that a small amount of moisture absorp-
tion does not affect the package’s reliability [9]. Also, COF flip-chip
assembly was successfully performed without thin chip breakage.
Cross-sectional SEM images of the COF assembly with different
bonding forces are shown in Fig. 7. Conductive particles mechani-
cally adhered well between chip bumps and PI substrate electrodes
at all bonding forces. However, the chip bump contact resistances
Fig. 13. Results of daisy chain resistance measurements of FOF assembly (a) 1st–
decreased from over 20 mX to below 5 mX and their deviation
2nd PI and (b) 1st–2nd–3rd PI.
also lowered as bonding force increased (Fig. 8). Above 50 N of
bonding force, the bump contact resistances were stabilized below
5 mX with low deviation. In addition, the degree of cure of ACF1
Table 3
was more than 90% as shown in Fig. 9. We can conclude that the
Optimized CIF package process conditions.
COF packages had stable flip chip joints considering well deformed
WLP conditions Bonding conditions COF assembly FOF assembly conductive particles between the bump and electrode, as shown in
Vacuum laminator Bonding temperature Chip: 180 °C 3rd PI: 180 °C Fig. 7, the stable bump contact resistance below 5 mX, and the suf-
1st PI: 80 °C 1st PI: 120 °C ficient degree of cure of ACF1 when the applied bonding force was
80 °C Bonding force 50 N 150 N
50 N. Therefore, the optimal COF assembly bonding force was
80 psi
1 min Bonding time 20 s 30 s determined as 50 N.

3.2. Static bending results of COF assembly

the bonding process. Bonding forces were determined by observa- When the static bending radius ranged from 35 mm to 25 mm,
tion of cross-sectional SEM images and daisy chain resistance mea- none of the thin chips of the COF assembly broke until 2590 h and
surements at various bonding forces. Finally, using the optimized the contact resistances were similar to the initial value (Fig. 10a
 Author's personal copy

K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234 231

and b). However, in the case of 20 mm radius, every sample (we
evaluated four samples per test) was damaged as shown in
Fig. 10c, and the resistances abruptly increased. The flexible COF
assembly could be bent down to a radius of 25 mm without chip
breakage or remarkable resistance changes.
the FOF assembly from the 1st PI to 2nd PI (1st–2nd PI), and from
the 1st PI via 2nd PI to 3rd PI (1st–2nd–3rd PI) as a function of the
bonding forces. The daisy chain resistances decreased as the bond-
ing forces increased. Based on the SEM images and the results of
daisy chain resistance measurement, the optimal bonding force
of the FOF assembly was determined to be 150 N.

3.3. Process optimization of CIF packages

3.3.1. Optimal Flex-on-Flex (FOF) bonding force
The degree of cure of the upper and bottom ACF2 was more than
90% as shown in Fig. 11. Therefore, the bonding temperature and
time were deemed appropriate. Cross-sectional SEM images of
ACF joints of the FOF assembly at various bonding forces are shown
in Fig. 12. The Ni conductive particles were mechanically well con-
tacted between the PI electrodes at all bonding forces except 75 N.
Fig. 13 shows the results of daisy chain resistance measurements of
3.3.2. Demonstration of CIF packages
The optimized process conditions are summarized in Table 3.
The manufacturing procedures are simple, as only two bonding
steps are required: COF bonding and FOF bonding. Optical and
cross-sectional SEM images indicate that the ACF pre-applied thin
chip was embedded in flex substrates (Figs. 14 and 15). The SAM
images in Fig. 16 show that CIF packages were well realized
without any cavity regions or noticeable voids. The cross-stripes
in the SAM images were due to the vacuum line of the chip tool

Fig. 14. Optical images of CIF packages (a) optical mode and (b) transmittance mode.

Fig. 15. Cross-section image of the CIF package.

Fig. 16. SAM images (a) between 3rd PI and 2nd PI and (b) between 2nd PI and 1st PI.
 Author's personal copy

232 K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234

Fig. 17. Results of resistances measurement of CIF packages (a) bump contact
resistances and (b) daisy chain resistances.

of the flip chip bonder. According to the results of bump contact

resistance and daisy chain resistance measurements, the pack-
ages showed stable electrical resistances (Fig. 17). Consequently,
CIF packages fabricated using WLP with pre-applied ACF, a flexi-
ble COF assembly, and FOF assembly were successfully
demonstrated.

3.4. Reliability tests

Reliability of the demonstrated CIF packages was evaluated, and

10 samples were tested per condition. We defined the failure crite-
rion of the packages as completely opened joints. The reliability of
the packages was evaluated by measurement of bump contact
resistances and daisy chain resistances during each reliability test.
A failure analysis was then performed by observation of cross-sec-
tional joints.

3.4.1. High temperature/humidity test (85 °C/85% RH, 1000 h)
Fig. 18 shows the average values of the bump contact
resistances, 1st–2nd PI daisy chain resistances, and 1st–2nd–3rd
PI daisy chain resistances of the CIF packages during 85 °C/85%
RH. There were no change of daisy chain resistances and no contin-
uous increase of contact resistances after 100 h to the end of the
test. The initial increase of the contact resistances from
4.6 ± 2.1 mX to 6.5 ± 3.3 mX is considered due to curing stress
relaxation under elevated temperature after epoxy curing. More-
over, there were any remarkable changes in joint shapes of CIF
packages before and after the test (data was not included). After
100 h, the bump contact resistances slightly increased and
remained stable until 1000 h. The 1st–2nd PI daisy and the 1st–
2nd–3rd PI daisy chain resistances showed stable electrical
Fig. 18. Average values of (a) bump contact resistances, (b) daisy chain resistances
of 1st–2nd PI, and (c) daisy chain resistances of 1st–2nd–3rd PI resistances during
85 °C/85% RH.
behavior up to 1000 h. To sum up, the CIF packages showed excel-
lent 85 °C/85% RH reliability.
3.4.2. High temperature storage test (HTST, 150 °C, 1000 h)
The change of average resistances of CIF packages during HTST
was shown in Fig. 19. The bump contact resistances, 1st–2nd PI
daisy chain resistances, and 1st–2nd–3rd PI daisy chain resistances
increased by 4.6 times, 1.5 times and 2.3 times, respectively as the
test progressed. After the reliability test, small crack was observed
 Author's personal copy
K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234
Fig. 19. Average values of (a) bump contact resistances, (b) daisy chain resistances
of 1st–2nd PI, and (c) daisy chain resistances of 1st–2nd–3rd PI resistances during
HTST.
between 2nd PI and 3rd PI joint (Fig. 20). This is due to loaded
stress to the packages which caused decrease of contact area be-
tween conductive particle and electrode, and therefore the resis-
tances increased. In this reason, it is important to reduce stress
when the packages were stored in high temperature conditions
for better HTST reliability. There are little study how Tg affect the
Von Mises Stress of electronic packages even though many papers
have been reported that packages’ reliability was enhanced by
using ACFs with higher Tg [11,12]. In this study, effects of various
Tg on Von Mises Stress of CIF packages were investigated by per-
233
Fig. 20. Cross-sectional SEM images of ACF joint deterioration between the 2nd PI
and 3rd PI after HTST.
forming Finite Element Analysis (FEA) using ABAQUS program.
The finite element model was illustrated in Fig. 21 and thermo-
mechanical properties of materials were listed in Table 4. Only
one forth of whole assembly was modeled for calculation efficiency
and symmetric boundary conditions were imposed on the cutting
plane. We assumed that the packages were stress free state at
the temperature around Tg, 114–117 °C. As shown in Fig. 22, Von
Mises Stress was highest at interconnection area, which is ACF
joints. The maximum stress between chip and 1st PI reduced from
531.4 MPa to 246.6 MPa when Tg increased from 117.4 °C to
147.4 °C. The maximum stress of 2nd PI and 3rd PI joint also de-
creased by 228.9 MPa which was similar to that of chip and 1st
PI. As a result of FEA, the maximum Von Mises Stress could be re-
duced down to 47% by increasing Tg of ACFs from 117.4 °C to
147.4 °C, and therefore the use of ACFs having higher Tg is recom-
mended in order to guarantee good HTST reliability of CIF
packages.
4. Conclusion
Flexible COF assembly and CIF packages were successfully
demonstrated using WLP technology. In the WLP process, void-
free ACFs lamination was performed on one-ninth of a 50 lm thin
wafer, and a ACFs pre-applied wafer was diced into chips without
ACF delamination or chipping. The COF assembly showed stable
bump contact resistances ranging from 2 mX to 8 mX. From
the results of bending tests, the COF assembly was confirmed to
be flexible and could be bent down to a radius of 25 mm without
electrical or mechanical damage. Using optimized COF assembly
and FOF assembly conditions, CIF packages were successfully
manufactured. Reliability tests of the CIF packages verified that
stable interconnections were maintained at in a 85 °C/85% RH
test. However, the contact resistances and daisy chain resistances
increased during the HTST, because the test temperature was
higher than Tg of the ACFs, thereby causing high Von Mises Stress
at joint area. The maximum stress could be reduced by 47% when
Tg increased up to 30 °C through FEA study. Therefore, the use of
ACFs having higher Tg is recommended in order to guarantee
good reliability.
From this study, a cost-effective CIF package structure with re-
duced processing steps and time was proposed, and successfully
demonstrated. This new packaging technology can be applied to
various flexible electronic products.
 Author's personal copy

234 K.-L. Suk et al. / Microelectronics Reliability 52 (2012) 225–234

Fig. 21. Finite element model image.

Table 4
Thermo-mechanical properties of materials.
Acknowledgment
E (GPa) m Tg (°C) CTE
ACF1 0.665 0.25 117.4 Below Tg: 113/Above Tg: 5977 The authors acknowledge Jae-Won Jan of Mechanical Engineer-
ACF2 0.797 0.25 114.8 Below Tg: 79.4/Above Tg: 2812 ing, KAIST for FEA and discussions.
Polyimide 6.0 0.41 – 21
Silicon 112.4 0.280 – 2.6
References
Gold 77.2 0.420 – 14.4
Copper 110.0 0.343 – 21
[1] Tummala Rao. Fundamentals of microsystems packaging. McGraw-Hill; 2001.
[2] Keser B et al. Advanced packaging: the redistributed chip package. IEEE Trans
Adv Pack 2008;331(1):39–43.
[3] Benkart P et al. 3D chip stack technology using through-chip interconnects.
(a) 600
IEEE Des Test Comput 2005;22(6):512–8.
Original [4] Blade JohnW. Foldable flex and thinned silicon chip packaging
Von-Mises Stress [MPa]

technology. Kluwer Acad.; 2002.

o
500 +10 C [5] Jokinen E, Ristolainen E. Anisotropic conductive film flip chip joining using thin
o chips. Microelectron Reliab 2002;42(12):1913–20.
+20 C
400 [6] Chen KY, Zenner RLD, Arneson M, Mountain D. Ultra-thin electronic device
o
+30 C package. IEEE Trans Adv Pack 2000;23(1):22–6.
[7] Govaerts J, Bosman E, Christiaens W, Vanfleteren J, Christiaens W. Fine-pitch
300 capabilities of the flat ultra-thin chip packaging (UTCP) technology. IEEE Trans
Adv Pack Chip Pack 2010;33(1):72–8.
200 [8] Lee BW, Sundaram V, Wiedenman B, Yoon CK, Kripesh V, Iyer M, et al., Chip-
last embedded active for System-On-Package (SOP). In: ECTC. Reno, Nevada,
100 USA; 2007. p. 292–8.
[9] Son Ho-Young, Chung Chang-Kyu, Yim Myung-Jin, Hwang Jin-Sang, Jung Gi-Jo,
Lee Jun-Kyu, et al. Wafer level flip chip packages using pre-applied anisotropic
0 2 4 6 conductive films (ACFs). IEEE Trans Electron Pack Manuf 2007;30(3):221–7.
[10] Tan SC, Chan YC, Lu NSM. The effect of different bonding temperatures on the
Distance from the chip center (mm) mechanical and electrical performance of NCF-bonded flip-chip-on-flex
packages. IEEE Trans Adv Pack 2006;29(3):570–5.
(b) 600
[11] Chung Chang-Kyu, Paik Kyung-Wook. Nonconductive films (NCFs) with
multifunctional epoxies and silica fillers for reliable NCFs flip chip on
Original
Von-Mises Stress [MPa]

organic boards (FCOBs). IEEE Trans Electron Pack Manuf 2009;32(2):65–73.

o [12] Jang Kyung-Woon et al. Material properties of anisotropic conductive films
500 +10 C
(ACFs) and their flip chip assembly reliability in NAND flash memory
o
+20 C applications. Microelectron Reliab 2008;48(7):1052–61.
400 o
+30 C
300

200

100

0 2 4 6
Distance from the chip center (mm)

Fig. 22. Von Mises Stress distribution from center to edge of CIF packages between
(a) chip and 1st PI (b) 2nd PI and 3rd PI.

View publication stats