Welcome to Maven Silicon - Training
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VLSI Training Services
Setting standards in VLSI Design
Online RN Day Planner
Days Theory Assignment/Labs Module Name
Blended VLSI
Day 1 VLSI Design Flow Introduction to
VLSI
Digital
Number systems & Codes, Logic
Day 2 Assignment-1 & 2
Gates, and Boolean Algebra
Day 3 Combinational Circuits Assignment-3
Blended VLS1
Day 4 Sequential Circuits Assignment-4 &5
Advanced
Day 5 FSM Assignment-6 Digital Design
Glitches and Hazards, Memories:
Day 6 classification, composition of Assignment-7
memories, FIFO Depth Calculation
Blended VLSI
Day 7 & 8 STA Static Timing
Analysis
Verilog Labs & Mini project will be executed on Your Local Machine Using Modelsim &
Quartusprime.
The instruction video to install the tool is available under the section Verilog Labs in the
Blended VLSI Verilog HDL
Day 9 Verilog abstraction levels, Data Types Lab 01
Day 10 Operators Lab 02
Day 11 Operators Lab03
Day 12 Processes
Lab 04
Day 13 Processes Blended VLSI
Day 14 Structured Procedures Verilog HDL
Day 15 Structured Procedures Lab 05
Day 16 Compiler directives & system tasks
Day 17 Synthesis guidelines
Lab 06
Day 18 FSM
Day 19 Router Design Specification
Day 20 FIFO Block
Day 21 Synchronizer Block
Project
Day 22 Synchronizer Block
Solutions
Day 23 FSM Block
Day 24 Register Block
Day 25 Register Block
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VLSI Training Services
Setting standards in VLSI Design
Day 26 Router Top Module
Day 27 Router Top Module
Day 28 Router Top Module
From here all the labs will be run on Maven Server using VPN using Questasim. VPN
configuration user guide is available under Blended VLSI Linux, Labs, and VPN. Please watch
the videos under the Questasim Tool Demo Module before starting the Advanced Verilog Labs
Blended VLSI
Day 29 Linux Linux Labs Linux, Labs
and VPN
Day 30 Advanced Verilog Lab 01
Day 31 Advanced Verilog Lab 02
Blended VLSI
Day 32 Code Coverage Lab 03 Advanced
Day 33 - Lab 04,05 Verilog & Code
coverage
Day 34 - Code Coverage on Router
Day 35 - Code Coverage on Router
Blended VLSI
Day 36 FPGA FPGA
Architecture
Blended VLSI
Day 37 CMOS
CMOS
Day 38 & Fundamentals
RISCV ISA
39 Blended VLSI
Day 40 RISCV RTL Design RISC-V
Blended VLSI
ASIC
Day 41 Verification Methodology -
Verification
Methodologies
Day 42 Datatypes Assignment 1
Day 43 Memories /Tasks and functions Lab 01, Assignment 2
Day 44 Interface and Clocking block Lab 02
Day 45 Basic OOP Lab 03
Day 46 Advanced OOP Lab 04, Assignment 3 Blended VLSI
System Verilog
Day 47 Randomization Lab 05, Assignment 4 HVL
Day 48 Threads, Semaphores, Mailbox Lab 06, Assignment 5
Day 49 TB components Lab 06
Day 50 Functional coverage Lab 07
Day 51 Threads, Semaphores, Mailbox Lab 08
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VLSI Training Services
Setting standards in VLSI Design
Makefile, Regression & Multiple
Day 52 Lab 09
Testcases
Day 53 Lab 10
Day 54 SV Mini Project
Day 55 SV Mini Project
SVA Introduction & Types of
Day 56 Assertions & SVA Building Blocks,
System Functions
Writing Sequences and Implication
Day 57 Blended VLSI
Operators Repetition Operators
Assertion
Sequence Composition &
Based
Day 58 Miscellaneous Concepts and SVA - Inline
Verification-
Connecting Assertions to DUT
SVA
Day 59 - SVA - Binding
Day 60 SVA - Alarm clock
Day 61 SVA - Alarm clock
Blended VLSI
Day 62 & Design
Perl Perl Labs & Assignments
63 Automation
Perl
Day 64 UVM Methodology
Day 65 UVM Factory
Stimulus Modelling, Project
Day 66 Lab 01
Overview,
Day 67 UVM Phases Lab 02
Day 68 Reporting Mechanism, TLM Lab 03
Day 69 TLM -
Day 70 UVM Configuration Configuration Assignment
Configuration, Building TB Blended VLSI
Day 71
Components Universal
Lab 04, Default Sequence Verification
Day 72 Sequence, Default Sequence
Assignment
Sequence Library, Sequencer Assignments on Sequence
Day 73
Arbitration, Sequencer Methods Library, Sequncer Arbitration
Lab05, Assignment on
Day 74 Virtual sequence
Sequencer Methods
Day 75 Configuration of Multiple agents Lab 06
Day 76 UVM Callbacks & events, SB Lab 07
Day 77 UVM RAL Lab 08
Day 78 UVM RAL Lab 09 & 10
Day 79 To Schedule will be shared in a Project
Router Verification
88 separate document Solutions
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VLSI Training Services
Setting standards in VLSI Design
Blended VLSI
Day 89 &
Business Communication Business
90
Communication
Day 91 To Schedule will be shared in a Project
Final Project Implementation
120 separate document Solutions
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