Advanced VLSI Design and Physical Design Course
Number
of
session Start End Start End
Date DAYS Elearn Topic Module No. (or) Name per day Time Time Time Time Review
Introduction & Course Flow
Getting you familiar with the system and
Elearn
Introduction & Course Flow
Getting you familiar with the system and
Elearn
24-Apr- Joining Formality Session
2024 DAY 1 Joining Formality Session
25-Apr- 9:00 10:30
2024 DAY 2 Blended VLSI - M1 - Introduction to VLSI AM AM
29-Apr- Number 9:00 11:00 3:30 5:00
2024 DAY 3 systems Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
30-Apr- 9:00 11:00 3:30 5:00
2024 DAY 4 Codes Assignment-1 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Logic Gates
2-May- and Boolean 9:00 11:00 3:30 5:00
2024 DAY 5 Algebra Assignment-2 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Logic Gates
3-May- and Boolean 9:00 11:00 3:30 5:00
2024 DAY 6 Algebra Assignment-2 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
Combinational-
6-May- Adders, 9:00 11:00 3:30 5:00
2024 DAY 7 Subtractors Assignment-3 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Review 1-number
Combinational- system & boolean
7-May- Encoders, 9:00 11:00 3:30 5:00 algebra
2024 DAY 8 Decoders Assignment-3 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM 12:00 PM to 1:00 PM
Combinational-
8-May- Mutiplexers, 9:00 11:00 3:30 5:00
2024 DAY 9 Demultiplexers Assignment-3 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
9-May- Sequential - 9:00 11:00 3:30 5:00
2024 DAY 10 Latches Assignment-4 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Sequential -
Flipflops, Review 2-
10-May- Flipflop 9:00 11:00 3:30 5:00 Combinational circuits
2024 DAY 11 conversions Assignment-4 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM 12:00 PM to 1:00 PM
Sequential -
13-May- Registers, 9:00 11:00 3:30 5:00
2024 DAY 12 Counter basics Assignment-5 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Sequential -
Counter design,
14-May- Shift register 9:00 11:00 3:30 5:00
2024 DAY 13 counters Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Sequential -
Counter
design, Shift
15-May- register 9:00 11:00 3:30 5:00
2024 DAY 14 counters Assignment-5 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
FSM- Melay ,
Moore Review 3-Sequential
16-May- sequence 9:00 11:00 3:30 5:00 circuits
2024 DAY 15 detectors Assignment-6 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM 12:00 PM to 1:00 PM
FSM- Practical
17-May- applications, 9:00 11:00 3:30 5:00
2024 DAY 16 Arbiter FSM Assignment-6 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
FSM- Practical
20-May- applications, 9:00 11:00 3:30 5:00
2024 DAY 17 Arbiter FSM Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
FSM- Practical
21-May- applications, 9:00 11:00 3:30 5:00
2024 DAY 18 Arbiter FSM Asssignment-7 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Glitches and
Hazards,
Memories:
classification ,
22-May- composition of 9:00 11:00 3:30 5:00
2024 DAY 19 memories Asssignment-7 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
23-May- FIFO depth 9:00 11:00 3:30 5:00
2024 DAY 20 calculation Asssignment-7 Blended VLSI - M2 - Advanced Digital Design 2 AM AM PM PM
Review 4 -
24-May- 9:30 12:00 FSM,memories,glitches
2024 DAY 21 Linux Linux Labs Blended VLSI - M4 - Linux 1 AM PM 12:00 PM to 1:00 PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
24-May-
2024 Digital Module Test 40 Minutes
Write only RTL
Verilog codes for few Digital module test - to
27-May- abstraction combinational 9:30 10:30 11:00 12:00 be scheduled by
2024 DAY 22 levels circuits. Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM process team
28-May- 9:30 10:30 11:00 12:00
2024 DAY 23 Data-types Lab1 Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
29-May- 9:30 10:30 11:00 12:00
2024 DAY 24 Data-types Lab1 assignments Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
30-May- Lab1 assignments 9:30 10:30 11:00 12:00 Lab1 review during
2024 DAY 25 Operators - Lab1 review Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM mentor session
31-May- Operators 9:30 10:30 11:00 12:00
2024 DAY 26 Operators practise Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
3-Jun- 9:30 10:30 11:00 12:00
2024 DAY 27 Processes Lab2 Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
4-Jun- Lab3 - Lab2 9:30 10:30 11:00 12:00 Lab2 review during
2024 DAY 28 Processes review Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM mentor session
5-Jun- Structured Lab3 assignments 9:30 10:30 11:00 12:00
2024 DAY 29 Procedures - Lab3 review Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
6-Jun- Structured 9:30 10:30 11:00 12:00 Lab3 review during
2024 DAY 30 Procedures Lab4 assignments Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM mentor session
Compiler
7-Jun- directives & Lab4 assignments 9:30 10:30 11:00 12:00
2024 DAY 31 system tasks - Lab4 review Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
Compiler
10-Jun- directives & 9:30 10:30 11:00 12:00 Lab4 review during
2024 DAY 32 system tasks Lab5 assignments Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM mentor session
11-Jun- Synthesis 9:30 10:30 11:00 12:00
2024 DAY 33 guidelines Lab5 assignments Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
12-Jun- Synthesis Lab5 assignments 9:30 10:30 11:00 12:00 Lab5review during
2024 DAY 34 guidelines - Lab5 review Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM mentor session
13-Jun- 9:30 10:30 11:00 12:00
2024 DAY 35 FSM Lab6 Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
14-Jun- Lab6 assignments 9:30 10:30 11:00 12:00
2024 DAY 36 FSM - Lab6 review Blended VLSI - M5 - Verilog HDL 2 AM AM AM PM
14-Jun- Verilog Module
2024 Test 30 Minutes
Verilog module test -
to be scheduled by
process team
17-Jun- Router Design 2:00 3:00 Lab6 review during
2024 DAY 37 Specification Blended VLSI - M5 - Verilog HDL 1 PM PM mentor session
18-Jun- Router Design 2:00 3:00
2024 DAY 38 FIFO FIFO Blended VLSI - M5 - Verilog HDL 1 PM PM
19-Jun-
2024 DAY 39 - Blended VLSI - M5 - Verilog HDL
20-Jun- Router Design Synchronizer - 2:00 3:00
2024 DAY 40 SYNC Router review Blended VLSI - M5 - Verilog HDL 1 PM PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
21-Jun-
2024 DAY 41 - FSM Blended VLSI - M5 - Verilog HDL Router review 1
24-Jun- Router Design 2:00 3:00
2024 DAY 42 FSM Blended VLSI - M5 - Verilog HDL 1 PM PM
25-Jun-
2024 DAY 43 Design Test Register 1.5 Hours Design Test
26-Jun- Router Design 2:00 3:00
2024 DAY 44 REG Blended VLSI - M5 - Verilog HDL 1 PM PM
27-Jun-
2024 DAY 45 Coding Test 1.5 Hours Coding Test
28-Jun- Router Design 2:00 3:00
2024 DAY 46 TOP Blended VLSI - M5 - Verilog HDL 1 PM PM Router review 2
1-Jul- Router top - 2:00 4:00
2024 DAY 47 RISC V Router review Blended VLSI - M5 - Verilog HDL 1 PM PM
2-Jul- 2:00 3:00
2024 DAY 48 DC Theory DC on Labs Blended VLSI - M5 - Verilog HDL 1 PM PM
3-Jul- 2:00 3:00
2024 DAY 49 DC Theory DC on Labs Blended VLSI - M5 - Verilog HDL 1 PM PM
4-Jul- 2:00 4:00
2024 DAY 50 RISCV DC on Router Blended VLSI - M5 - Verilog HDL 1 PM PM
5-Jul- 2:00 3:00
2024 DAY 51 Linting Linting on router Blended VLSI - M5 - Verilog HDL 1 PM PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
8-Jul- 2:00 3:00
2024 DAY 52 Linting Linting on router Blended VLSI - M5 - Verilog HDL 1 PM PM
9-Jul- Linting on RISCV 2:00 3:30
2024 DAY 53 soc - Lint review Blended VLSI - M6 - Verilog HDL 1 PM PM DC/lint review
10-Jul- Advanced Advanced verilog Blended VLSI - M6 - Advanced Verilog & 2:00 3:30 BPD batches will
2024 DAY 54 verilog assignments Codecoverage 1 PM PM seperate
Advanced
verilog Advanced verilog
11-Jul- assignments - assignments - Blended VLSI - M6 - Advanced Verilog & 2:00 3:30
2024 DAY 56 Review1 Review1 Codecoverage 1 PM PM
12-Jul- 2:00 3:00 Advance verilog
2024 DAY 57 STA Blended VLSI - M3 - Static Timing Analysis 1 PM PM review
15-Jul- 2:00 3:00
2024 DAY 58 STA Blended VLSI - M3 - Static Timing Analysis 1 PM PM
16-Jul- 2:00 4:00
2024 DAY 59 CMOS Blended VLSI - M8 - CMOS Fundamentals 1 PM PM
17-Jul- 2:00 4:00
2024 DAY 60 FPGA Blended VLSI - M7 - FPGA Architecture 1 PM PM
Maven Silicon Softech Pvt Ltd.
21/1A, III Floor, MS Plaza, Gottigere, Bannerghatta Main Rd, Bengaluru, Karnataka 560076 | [Link]
