Chapter 13 Embedded ARM
Applications
Introduction
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
Introduction
¾ The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The VLSI Ruby II advanced
communication processor(1)
VLSI Technology, Inc.
For used in portable communications devices
The chip is based around an ARM core
2 Kbytes of fast on-chip SRAM
Peripheral modules:
PCMCIA interface
Four byte-wide parallel interface
Two UARTs
The VLSI Ruby II advanced
communication processor(2)
Synchronous communications controller module
supports a range of standard serial communication
protocols
Serial controller module provides a software-
controlled data port such as the I2C bus.
The external bus interface supports devices with 8-,
16- and 32-bit data buses and has flexible wait state
generation
The counter-timer block has three 8-bit counters
connected to a 24-bit prescaler
An interrupter controller gives programmable control
of all on- and off-chip interrupt sources
Support power-management mode
Ruby II advanced communication
controller organization
external
interrupts (3)
clock clock
control ARM 512 x 32 in terrupt co unter/
core SRAM controller timers
pa rallel control
i/f 1,2,3,4
external address (22)
PCMCIA bus
host control
data (8/16/32)
I/O interface ho st
mode FIFOs
select (16 x 8)
UAR T1
se rial I 2 C, ...
UAR T2 controller
serial
FIFOs 8 data bits
serial (16 x 8) & control
hi gh-speed pa rallel
serial i/f interface 0
Introduction
The VLSI Ruby II advanced communication
processor
¾ The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The VLSI ISDN Subscriber
Processor (VIP)
VIP is a programmable engine for ISDN
(Integrated Services Digital Network; a
digital telephony standard) subscriber
communications
A full-feature ISDN terminal, supporting
voice, data and video services down the
same digital line
VIP organization external
interrupts (3)
clock clock
control ARM6 768 x 32 interrupt timer &
core SRAM controller watchdog
ports parallel control
interface
external address (23)
bus
handset/ G.711 control
hands-free codec data (8/16/32)
S0-interface B and D
channels
mux address
DRAM
battery, volume controller ras, cas
ADCs (2)
serial DSP address chip selects
serial i/f decoder
Typical VIP System Configuration
volume
V24 interface
hands-free
Driver
hook switch
S0-ISDN interface ISDN
Subscriber
Processor
power ROM
K E Y
P A D
RAM
Introduction
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
¾ The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
OneCTM VWS22100 GSM Chip
Developed by VLSI technology, Inc.
System-on-Chip design for a GSM
mobile telephone handset
Incorporating an ARM7TDMI core
(6) boot
JTAG ARM7TDMI interrupt ROM
test/debug core controller
(6)
UART1
UART2/ (4)
(13) IrDA
audio i/f PCM i/f
high-speed (5)
(20) DSP radio serial i/f (2)
OneCTM
radio i/f port
(4)
SIM i/f
DSP bus
program program
VWS22100
ROM RAM 32 KHz
hardware
coprocs
RTC
cntrl (6)
GSM Chip Oak DSP memory
external
bus
addr (20)
control
Organization
core controller data (16)
ARM bus
DSP
subsystem (7)
ADC
data data power keypad (10)
ROM RAM manager scanner
interrupt config./ GPIO (11)
controller status PWM
DSP Subsystem
Based around the 16-bit Oak DSP core
Voice coding
Equalization
Channel coding
Echo cancellation
Noise suppression
Voice recognition
Data compression
ARM7TDMI Subsystem
User interface software
GSM protocol stack
Power management
Driving the peripheral interfaces
Running some data applications
Power Management
Global and selective power-down modes
Ability to slow down the system clock in idle
mode
Analogue circuits also can operate at reduced
power
0n-chip analogue-to-digital converters (ADCs)
provide for the monitoring of the temperature
and battery voltage to give optimum
operation
Typical GSM Handset Architecture
SIM
card eeprom IrDA
speaker
radio
mic module
VWS22100
ringer
ROM
K E Y
P A D
RAM
LCD
Introduction
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
¾ The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The Ericsson-VLSI Bluetooth
Baseband Controller
Bluetooth
De-facto standard for wireless data
communication for the 2.4GHz band
Developed by a consortium of companies including
Ericsson, IBM, Intel, Nokia and Toshiba
Support short-range communication (from 10 cm
to 10 m)
Gross data rate of 1 Mbit/s
Piconets: frequency-hopping scheme
Bluetooth Controller Organization
Based around a synthesized ARM7TDMI core
64 Kbytes of fast on-chip SRAM
A 4K byte instruction cache
Peripheral modules
Three UARTs
A USB interface
An I2C-bus interface
External bus interface
Counter/timers
Interrupt controller
EBC: Ericsson Bluetooth Core: Link Controller
functionality within the bluetooth specification
Ericsson-VLSI Bluetooth
Baseband Controller organization
clock clock
control ARM7TDMI 4 Kbyte internal 16K x 32
core I-cache ROM SRAM
JTAG
signals (5)
control
interrupt counter/ external address (20)
controller timers bus
control
data (8/16)
UART1,2,3
I/O EBC radio interface
mode I2 C i/f FIFOs block
select
USB i/f
Typical Bluetooth application
flash address Bluetooth
Baseband radio
memory
flash module
memory Controller
data
control
host interface
(RS232/USB)
Bluetooth characteristics
Process 0.25 um Transistors 4,300,000 MIPS 12
2
Metal layers 3 Die area 20 mm Power 75 mW
Vdd 2.5 V Clock 0 – 13 MHz MIPS/W 160
Introduction
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
¾ The ARM7500 and ARM7500FE
The ARM7100
The SA-1100
The ARM7500 and ARM7500FE
ARM7500 is a highly integrated single-
chip computer which combines the
major components of the Acorn Risc PC
onto a single chip.
ARM7500FE adds the FPA10 floating-
point coprocessor as an on-chip
macrocell
The Principal macrocells
ARM CPU core: ARM710
FPA10 floating-point coprocessor (on
the ARM7500FE only)
Video and sound macrocell
Memory and I/O controller
cas[3:0]
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
RA[11:0]
DRAM
DRAM
DRAM
DRAM
video
analogue
Typical
sound
DRAM
DRAM
DRAM
DRAM
ras[3:0]
ARM7500 ARM7500
D[31:0]
System
ROM
ROM
analogue
inputs
LA[28:0]
Organization module
interrupts
selects
keyboard
& mouse
I/O I/O
module module
BD[15:0]
ARM7500 characteristics
Pro c e s s 0.6 um Tran s i s t o rs 550,000 MIPS 30
2
Me t al l ay e rs 2 Di e are a 70 mm Po we r 690 mW
Vdd 5V Cl o c k 0 to 33 MHz MIPS / W 43
Introduction
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
¾ The ARM7100
The SA-1100
ARM710a
ARM7 8 Kbyte LCD interrupt
MMU core cache controller controller
AMBA
ARM7100 3.6864 MHz
clock PLL
control
Organization power counter/ external address (28)
mgt. timers bus
32.786 KHz control
data (32)
RTC
osc.
UART DRA(13)
FIFOs DRAM RAS, CAS(8)
controller
codec i/f WE , OE(2)
sync serial expansion
parallel I/O PSU control
DRAM ROM Flash
PSU
ARM7100
ADC
The Psion PC cards
Series 5 infrared IrDA Tx/Rx
digitizing
tablet
Hardware RS232
Organization 640 x 240
LCD
audio codec
keyboard
ARM7100 characteristics
Process 0.6 um Transistors N/A MIPS 30
2
Metal layers 2 Die area N/A mm Power 14 mW
Vdd 3.3 V Clock 18.432 MHz MIPS/W 212
Introduction
The VLSI Ruby II advanced communication
processor
The VLSI ISDN subscriber Processor
The OneCTM VWS22100 GSM chip
The Ericsson—VLSI bluetooth baseband
controller
The ARM7500 and ARM7500FE
The ARM7100
¾ The SA-1100
The SA-1100
A high-performance integrated system-
on-chip based around a modified
version of the SA-110 StrongARM CPU
core
Use in mobile phone handsets, modems,
and other hand held applications
Minimal power consumption
Support for Window CE environment
mini-cache
cache
instruction instruction SA-1 data
data
MMU cache core MMU
SA-1100
CPU core write buffer read buffer
system bus
Organization LCD (5)
data (32)
address (26)
LCD DMA memory &
control control bridge PCMCIA control
3.6864 MHz
clock interrupt USB (2)
PLL control serial 0
32.786 KHz
RTC SDLC (2)
osc. RTC serial 1
I/O pins (28) IrDA (2)
general-
purpose I/O serial 2
OS
timer UART (2)
battery (3) serial 3
power
manager
reset (2) reset Codec (4)
serial 4
control
peripheral bus
SA-1100 characteristics
Process 0.35 um Transistors 2,500,000 MIPS 220/250
2
Metal layers 3 Die area 75 mm Power 330/550 mW
Vdd 1.5/2 V Clock 190/220 MHz MIPS/W 665/450
