LI GII THIU

Cng vi s tin b ca khoa hc v cng ngh, cc thit b in t ang v s tip tc c ng dng ngy cng rng ri v mang li hiu qu cao trong hu ht cc lnh vc kinh t k thut cng nh i sng x hi. Vic x l tn hiu trong cc thit b in t hin i u da trn c s nguyn l s. Bi vy vic hiu su sc v in t s l iu khng th thiu c i vi k s in t hin nay. Nhu cu hiu bit v k thut s khng phi ch ring i vi cc k s in t m cn i vi nhiu cn b k thut chuyn ngnh khc c s dng cc thit b in t.

Ti liu gm c 9 chng c b cc nh sau: Chng 1: H m

Chng 3: Cng logic TTL v CMOS

Chng 5: Mch logic tun t.

Do thi gian c hn nn ti liu ny khng trnh khi thiu st, rt mong ngi c gp . Cc kin xin gi v Khoa K thut in t 1- Hc vin Cng ngh Bu chnh vin thng. Xin trn trng cm n.

Chng 6: Mch pht xung v to dng xung. Chng 7: B nh bn dn. Chng 8: Logic lp trnh. Chng 9 : Ngn ng m t phn cng VHDL.

Chng 4: Mch logic t hp.

.4

Chng 2: i s Boole v cc phng php biu din hm

te

ch

Ti liu bao gm cc kin thc c bn v mch cng logic, c s i s logic, mch logic t hp, cc trig, mch logic tun t, cc mch pht xung v to dng xung, cc b nh thng dng. c bit l trong ti liu ny c b xung thm phn logic lp trnh v ngn ng m t phn cng VHDL. y l ngn ng ph bin hin nay dng to m hnh cho cc h thng k thut s. Tt c gm 9 chng. Trc v sau mi chng u c phn gii thiu v phn tm tt gip ngi hc d nm bt kin thc hn. Cc cu hi n tp ngi hc kim tra mc nm kin thc sau khi hc mi chng. Trn c s cc kin thc cn bn, ti liu c gng tip cn cc vn hin i, ng thi lin h vi thc t k thut.

.c

om .v

Ti liu ny gii thiu mt cch h thng cc phn t c bn trong cc mch in t s kt hp vi cc mch in hnh, gii thch cc khi nim c bn v cng in t s, cc phng php phn tch v thit k mch logic c bn.

Chng 1: H m

CHNG 1: H M
GII THIU
Khi ni n s m, ngi ta thng ngh ngay n h thp phn vi 10 ch s c k hiu t 0 n 9. My tnh hin i khng s dng s thp phn, thay vo l s nh phn vi hai k hiu l 0 v 1. Khi biu din cc s nh phn rt ln, ngi ta thay n bng cc s bt phn (Octal) v thp lc phn (HexaDecimal).

C rt nhiu h m, chng hn nh h La M, La Tinh ... H m va c tnh a dng va c tnh ng nht v ph bin. Mi h m c u im ring ca n nn trong k thut s s s dng mt s h b khuyt cho nhau. Trong chng ny khng ch trnh by cc h thp phn, h nh phn, h bt phn, h thp lc phn v cn nghin cu cch chuyn i gia cc h m. Chng ny cng cp n s nh phn c du v khi nim v du phy ng.

NI DUNG
1.1. BIU DIN S

Bng 1.1 l lit k tn gi, s k hiu v c s ca mt vi h m thng dng.

Tn h m

Nguyn tc chung ca biu din l dng mt s hu hn cc k hiu ghp vi nhau theo qui c v v tr. Cc k hiu ny thng c gi l ch s. Do , ngi ta cn gi h m l h thng s. S k hiu c dng l c s ca h k hiu l r. Gi tr biu din ca cc ch khc nhau c phn bit thng qua trng s ca h. Trng s ca mt h m bt k s bng ri, vi i l mt s nguyn dng hoc m.

.4

te

ch
S k hiu

.c
0, 1

H nh phn (Binary) H bt phn (Octal)

0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

H thp phn (Decimal) H thp lc phn (Hexadecimal)

Bng 1.1
Ngi ta cng c th gi h m theo c s ca chng. V d: H nh phn = H c s 2, H thp phn = H c s 10... 2

om .v
2 8

m s lng ca cc i lng l mt nhu cu ca lao ng, sn xut. Ngng mt qu trnh m, ta c mt biu din s. Cc phng php m v biu din s c gi l h m. H m khng ch c dng biu din s m cn l cng c x l.

n
C s (r) 10 16

Chng 1: H m Di y, ta s trnh by tm tt mt s h m thng dng. 1.1.1 H thp phn Cc k hiu ca h nh nu bng 1.1. Khi ghp cc k hiu vi nhau ta s c mt biu din. V d: 1265,34 l biu din s trong h thp phn:

1265.34 = 1 103 + 2 102 + 6 101 + 5 100 + 3 101 + 4 102

Trong phn tch trn, 10n l trng s ca h; cc h s nhn chnh l k hiu ca h. Nh vy, gi tr biu din ca mt s trong h thp phn s bng tng cc tch ca k hiu (c trong biu din) vi trng s tng ng. Mt cch tng qut:

= di 10i
n 1

trong , N10 : biu din bt k theo h 10,

d : cc h s nhn (k hiu bt k ca h),

m : s ch s phn phn s.

Biu din s tng qut:

Trong mt s trng hp, ta phi thm ch s trnh nhm ln gia biu din ca cc h. V d: 3610 , 368 , 3616 . 1.1.2 H nh phn 1.1.2.1. T chc h nh phn H nh phn (Binary number system) cn gi l h c s hai, gm ch hai k hiu 0 v 1, c s ca h l 2, trng s ca h l 2n. Cch m trong h nh phn cng tng t nh h thp phn. Khi u t gi tr 0, sau ta cng lin tip thm 1 vo kt qu m ln trc. Nguyn tc cng nh phn l : 0 + 0 = 0, 1 + 0 = 1, 1 + 1 = 10 (102 = 210). 3

Vi c s bt k r v d bng h s a tu ta s c cng thc biu din s chung cho tt c cc h m:

.4
= a i ri
n 1 m

Nhc im chnh ca h l do c nhiu k hiu nn vic th hin bng thit b k thut s kh khn v phc tp.

= a n 1 r n 1 + ... + a1 r1 + a 0 r 0 + a 1 r 1 + ... + a m r m

te

u im ca h thp phn l tnh truyn thng i vi con ngi. y l h m con ngi d nhn bit nht. Ngoi ra, nh c nhiu k hiu nn kh nng biu din ca h rt ln, cch biu din gn, tn t thi gian vit v c.

ch

.c

n : s ch s phn nguyn,

om .v

N10 = d n 1 10n 1 + ... + d1 101 + d 0 100 + d 1 101 + ... + d m 10 m

Chng 1: H m Trong h nh phn, mi ch s ch ly 2 gi tr hoc 0 hoc 1 v c gi tt l "bit". Nh vy, bit l s nh phn 1 ch s. S bit to thnh di biu din ca mt s nh phn. Mt s nh phn c di 8 bit c gi 1 byte. S nh phn hai byte gi l mt t (word). Bit tn cng bn phi gi l bit b nht (LSB Least Significant Bit) v bit tn cng bn tri gi l bit ln nht (MSB - Most Significant Bit). Biu din nh phn dng tng qut :

N 2 = b n 1b n 2 ....b1b0 .b 1b 2 ....b m
Trong , b l h s nhn ca h. Cc ch s ca h s ng thi cng bng ly tha ca trng s tng ng. V d :

0.

s nh phn phn s

22

21

20

21

22

trng s tng ng.

Cc gi tr 210 = 1024 c gi l 1Kbit, 220 = 1048576 - Mga Bit ... Ta c dng tng qut ca biu din nh phn nh sau:

N2

= b n 1 2n 1 + ... + b1 21 + b0 20 + b 1 21 + ... + b m 2 m = b i 2i
n 1

Trong , b l h s nhn ly cc gi tr 0 hoc 1. 1.1.2.2. Cc php tnh trong h nh phn a. Php cng

b. Php tr

Qui tc tr hai bit nh phn cho nhau nh sau : 0-0 =0; 1-1 =0 ; 1-0=1; 10 - 1 = 1 (mn 1)

u im chnh ca h nh phn l ch c hai k hiu nn rt d th hin bng cc thit b c, in. Cc my vi tnh v cc h thng s u da trn c s hot ng nh phn (2 trng thi). Do 4

Khi tr nhiu bit nh phn, nu cn thit ta mn bit k tip c trng s cao hn. Ln tr k tip li phi tr thm 1. c. Php nhn Qui tc nhn hai bit nh phn nh sau: 0x0=0 , 0x1=0 ,1x0=0 ,1x1=1 Php nhn hai s nh phn cng c thc hin ging nh trong h thp phn. Ch : Php nhn c th thay bng php dch v cng lin tip. d. Php chia Php chia nh phn cng tng t nh php chia hai s thp phn.

.4

Qui tc cng hai s nh phn 1 bit nu trn.

te

ch

.c

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Chng 1: H m , h nh phn c xem l ngn ng ca cc mch logic, cc thit b tnh ton hin i - ngn ng my. Nhc im ca h l biu din di, mt nhiu thi gian vit, c. 1.1.3 H bt phn v thp lc phn 1.1.3.1 H bt phn 1. T chc ca h : Nhm khc phc nhc im ca h nh phn, ngi ta thit lp cc h m c nhiu k hiu hn, nhng li c quan h chuyn i c vi h nh phn. Mt trong s l h bt phn (hay h Octal, h c s 8). H ny gm 8 k hiu : 0, 1, 2, 3, 4, 5, 6 v 7. C s ca h l 8. Vic la chn c s 8 l xut pht t ch 8 = 23. Do , mi ch s bt phn c th thay th cho 3 bit nh phn. Dng biu din tng qut ca h bt phn nh sau:

N8

= O n 1 8n 1 + ... + O0 80 + O 1 81 + ... + O m 8 m = Oi 8i
n 1 m

Lu rng, h thp phn cng m tng t v c gii rng hn h bt phn, nhng khng th tm c quan h 10 = 2n (vi n nguyn). 2. Cc php tnh trong h bt phn a. Php cng

b. Php tr

Php tr cng c tin hnh nh trong h thp phn. Ch rng khi mn 1 ch s c trng s ln hn th ch cn cng thm 8 ch khng phi cng thm 10. Cc php tnh trong h bt phn t c s dng. Do , php nhn v php chia dnh li nh mt bi tp cho ngi hc. 1.1.3.2 H thp lc phn 1.T chc ca h H thp lc phn (hay h Hexadecimal, h c s 16). H gm 16 k hiu l 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Trong , A = 1010 , B = 1110 , C = 1210 , D = 1310 , E = 1410 , F = 1510 . C s ca h l 16, xut pht t yu t 16 = 24. Vy, ta c th dng mt t nh phn 4 bit (t 0000 n 1111) biu th cc k hiu thp lc phn. Dng biu din tng qut:

.4

Php cng trong h bt phn c thc hin tng t nh trong h thp phn. Tuy nhin, khi kt qu ca vic cng hai hoc nhiu ch s cng trng s ln hn hoc bng 8 phi nh ln ch s c trng s ln hn k tip.

te

ch

.c

om .v

Chng 1: H m

N16

= H n 1 16n 1 + .... + H 0 160 + H 1 161 + .... + H m 16 m = Hi 16i

n 1 m

2. Cc php tnh trong h c s 16 a. Php cng Khi tng hai ch s ln hn 15, ta ly tng chia cho 16. S d c vit xung ch s tng v s thng c nh ln ch s k tip. Nu cc ch s l A, B, C, D, E, F th trc ht, ta phi i chng v gi tr thp phn tng ng ri mi cng. b. Php tr

Khi tr mt s b hn cho mt s ln hn ta cng mn 1 ct k tip bn tri, ngha l cng thm 16 ri mi tr. c. Php nhn

Mun thc hin php nhn trong h 16 ta phi i cc s trong mi tha s v thp phn, nhn hai s vi nhau. Sau , i kt qu v h 16.

1.2. CHUYN I C S GIA CC H M

1.2.1. Chuyn i t h c s 10 sang cc h khc

thc hin vic i mt s thp phn y sang cc h khc ta phi chia ra hai phn: phn nguyn v phn s. i vi phn nguyn: ta chia lin tip phn nguyn ca s thp phn cho c s ca h cn chuyn n, s d sau mi ln chia vit o ngc trt t l kt qu cn tm. Php chia dng li khi kt qu ln chia cui cng bng 0.

V d: i s 5710 sang s nh phn.

Bc 1 2 3 4 5 6

.4
chia 57/2 28/2 14/2 7/2 3/2 1/2

te

ch
c 28 14 7 3 1 0

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d 1 0 0 1 1 1 MSB LSB

i vi phn phn s : ta nhn lin tip phn phn s ca s thp phn vi c s ca h cn chuyn n, phn nguyn thu c sau mi ln nhn, vit tun t l kt qu cn tm. Php nhn dng li khi phn phn s trit tiu. V d: i s 57,3437510 sang s nh phn. 6

Vit o ngc trt t, ta c : 5710 = 1110012

om .v

Chng 1: H m Phn nguyn ta va thc hin v d a), do ch cn i phn phn s 0,375.

Bc 1 2 3 4

Nhn 0,375 x 2 0,75 x 2 0,5 x 2 0,0 x 2

Kt qu 0.75 1.5 1.0 0

Phn nguyn 0 1 1 0

Kt qu : 0,37510 = 0,01102 S dng phn nguyn c v d 1) ta c : 57,37510 = 111001.01102

1.2.2. i mt biu din trong h bt k sang h thp phn Mun thc hin php bin i, ta dng cng thc :

N10

= a n 1 r n 1 + .... + a 0 r 0 + a 1 r 1 + .... + a m r m

1.2.3. i cc s t h nh phn sang h c s 8 v 16

V 8 = 23 v 16 = 24 nn ta ch cn dng mt s nh phn 3 bit l ghi 8 k hiu ca h c s 8 v t nh phn 4 bit cho h c s 16. Do , mun i mt s nh phn sang h c s 8 v 16 ta chia s nh phn cn i, k t du phn s sang tri v phi thnh tng nhm 3 bit hoc 4 bit. Sau thay cc nhm bit phn bng k hiu tng ng ca h cn i ti. V d:

Tnh t du phn s, ta chia s ny thnh cc nhm 3 bit nh sau :

110 111 , 011 100 6 3 4

Kt qu: 110111,01112 = 67,348. ( Ta thm 2 s 0 tin bin i). b. i s nh phn 111110110,011012 sang s h c s 16 Ta phn nhm v thay th nh sau : 0001 1111 0110 0110 1000 1 F 6 6 8

Kt qu: 111110110,011012 = 1F6,6816 7

a. i s 110111,01112 sang s h c s 8

.4

te

ch

.c

Thc hin ly tng v phi s c kt qu cn tm. Trong biu thc trn, ai v r l h s v c s h c biu din.

om .v

Chng 1: H m

1.3 S NH PHN C DU
1.3.1 Biu din s nh phn c du C ba phng php th hin s nh phn c du sau y. 1. S dng mt bit du. Trong phng php ny ta dng mt bit ph, ng trc cc bit tr s biu din du, 0 ch du dng (+), 1 ch du m (-). 2. S dng php b 1. Gi nguyn bit du v ly b 1 cc bit tr s (b 1 bng o ca cc bit cn c ly b). 3. S dng php b 2

C th biu din s m theo phng php b 2 xen k: bt u t bit LSB, dch v bn tri, gi nguyn cc bit cho n gp bit 1 u tin v ly b cc bit cn li. Bit du gi nguyn. 1.3.2 Cc php cng v tr s nh phn c du

1. Biu din theo bit du a. Php cng

Hai s cng du: cng hai phn tr s vi nhau, cn du l du chung. Hai s khc du v s m c tr s nh hn: cng tr s ca s dng vi b 1 ca s m. Bit trn c cng thm vo kt qu trung gian. Du l du dng. Hai s khc du v s m c tr s ln hn: cng tr s ca s dng vi b 1 ca s m. Ly b 1 ca tng trung gian. Du l du m. b. Php tr. Nu lu rng, - (-) = + th trnh t thc hin php tr trong trng hp ny cng ging php cng. 2. Cng v tr cc s theo biu din b 1

Hai s m: biu din chng dng b 1 v cng nh cng nh phn, k c bit du. Bit trn cng vo kt qu. Ch , kt qu c vit di dng b 1. Hai s khc du v s dng ln hn: cng s dng vi b 1 ca s m. Bit trn c cng vo kt qu. Hai s khc du v s m ln hn: cng s dng vi b 1 ca s m. Kt qu khng c bit trn v dng b 1. b. Tr thc hin php tr, ta ly b 1 ca s tr, sau thc hin cc bc nh php cng. 8

a. Cng

Hai s dng: cng nh cng nh phn thng thng, k c bit du.

.4

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ch

.c

Nh ni trn, php b 1 v b 2 thng c p dng thc hin cc php tnh nh phn vi s c du.

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L phng php ph bin nht. S dng th hin bng s nh phn khng b (bit du bng 0), cn s m c biu din qua b 2 (bit du bng 1). B 2 bng b 1 cng 1.

Chng 1: H m 3. Cng v tr nh phn theo biu din b 2 a. Cng Hai s dng: cng nh cng nh phn thng thng. Kt qu l dng. Hai s m: ly b 2 c hai s hng v cng, kt qu dng b 2. Hai s khc du v s dng ln hn: ly s dng cng vi b 2 ca s m. Kt qu bao gm c bit du, bit trn b i. Hai s khc du v s m ln hn: s dng c cng vi b 2 ca s m, kt qu dng b 2 ca s dng tng ng. Bit du l 1.

1.4. DU PHY NG
1.4.1 Biu din theo du phy ng

1/ 2 M 1

Ging nh cc php tnh ca hm m. Gi s c hai s theo du phy ng chun ha:

X = 2E x ( M x ) v Y = 2

Tch: Z = X.Y = 2

.4
Ey
E x +E y E x E y

1.4.2 Cc php tnh vi biu din du phy ng

te
( M y ) th:

E v M c th c biu din dng b 2. Gi tr ca chng c hiu chnh m bo mi quan h trn y c gi l chun ha.

Thng: W = X / Y = 2

ch
( M x .M y ) = 2E
Z

( M x / M y ) = 2E

Mun ly tng v hiu, cn a cc s hng v cng s m, sau s m ca tng v hiu s ly s m chung, cn nh tr ca tng v hiu s bng tng v hiu cc nh tr.

TM TT
Trong chng ny chng ta gii thiu v mt s h m thng c s dng trong h thng s: h nh phn, h bt phn, h thp lc phn. V phng php chuyn i gia cc h m . Ngoi ra cn gii thiu cc php tnh s hc trong cc h .

.c
Mz
w

Gm hai phn: s m E (phn c tnh) v phn nh tr M (trng phn s). E c th c di t 5 n 20 bit, M t 8 n 200 bit ph thuc vo tng ng dng v di t my tnh. Thng thng dng 1 s bit biu din E v cc bit cn li cho M vi iu kin:

om .v
Mw

Php tr hai s c du l cc trng hp ring ca php cng. V d, khi ly +9 tr i +6 l tng ng vi +9 cng vi -6.

b. Php tr

Chng 1: H m

CU HI N TP
1. nh ngha th no l bit, byte? 2. i s nh phn sau sang dng bt phn: 0101 1111 0100 1110 a. 57514 b. 57515 c. 57516 d. 57517 3. Thc hin php tnh hai s thp lc phn sau: 132,4416 + 215,0216. a. 347,46 b. 357,46 c. 347,56 d. 357,67

0000 11012 + 1000 10112 a. 0000 0101 b. 0000 0100 c. 0000 0011 d. 0000 0010

5. Thc hin php cng hai s c du sau theo phng php b 2:

a. 1000 1110

10

6. Hai byte c bao nhiu bit? a. 16 b. 8 c. 32 d. 64

b. 1000 1011 c. 1000 1100 d. 1000 1110

.4

te
0000 11012 1001 10002

ch

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4. Thc hin php cng hai s c du sau theo phng php b 1:

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Chng 2: i s Boole v cc phng php biu din hm

CHNG 2: I S BOOLE V CC PHNG PHP BIU DIN HM

GII THIU CHUNG
Trong mch s, cc tn hiu thng cho hai mc in p, v d 0 V v 5 V. Nhng linh kin in t dng trong mch s lm vic mt trong hai trng thi, v d transistor lng cc lm vic ch kha (tt), hoc thng..

CM trng thi Ngt: A= 0

CM trng thi ng: A=1

.4

84 nm sau, i s Boole c Shannon pht trin thnh l thuyt chuyn mch. Nh cc cng trnh ca Shannon, v sau ny, cc nh k thut dng i s Boole phn tch v thit k cc mch vi tnh. Trng thi "ng", "sai" trong bi ton logic c thay th bng trng thi "ng", "ngt" ca mt chuyn mch (CM). Mi quan h nhn qu trong bi ton logic c thay bi mi quan h gia dng in trong mch vi trng thi cc CM gn trn on mch y. Mi quan h ny s c th hin bng mt hm ton hc, c tn l hm chuyn mch. Khi , cc trng thi ca CM : "ng" = 1 v "ngt" = 0. Hnh 2-1 m t iu va ni. y, trng thi ca CM c k hiu bng ch ci A.

te

ch

V thc cht, hm chuyn mch l mt trng hp c th ca hm logic. Do , i s Boole ng vi trng hp ny cng c gi l i s chuyn mch. Mc d vy, trong mt s ti liu ngi ta vn thng gi n l i s logic hay i s Boole.

Ngy nay, i s Boole khng ch gii hn trong lnh vc k thut chuyn mch m cn l cng c phn tch v thit k cc mch s, c bit l lnh vc my tnh. Cu kin lm chuyn mch c thay bng Diode, Transistor, cc mch tch hp, bng t... Hot ng ca cc cu kin ny cng c c trng bng hai trng thi: thng hay tt, dn in hay khng dn in... Do , hai gi tr h nh phn vn c dng m t trng thi ca chng. i s logic ch c 3 hm c bn nht, l hm "V", hm "Hoc" v hm "o". c im ni bt ca i s logic l c hm ln bin ch ly hai gi tr hoc 1 hoc 0. 11

.c

Mt b mn i s c pht trin t cui th k 19 mang tn chnh ngi sng lp ra n, i s Boole, cn c gi l i s logic rt thch hp cho vic m t mch s. i s Boole l cng c ton hc quan trng thit k v phn tch mch s. Cc k s, cc nh chuyn mn trong lnh vc in t, tin hc, thng tin, iu khin.. u cn phi nm vng cng c ny c th i su vo mi lnh vc lin quan n k thut s.

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Do vy, m t hot ng ca cc mch s, ngi ta dng h nh phn (Binary), hai trng thi ca cc linh kin trong mch c m ha tng ng thnh 1 v 0.

Chng 2: i s Boole v cc phng php biu din hm Trong chng ny, ta s cp n cc tin , nh l, cc cch biu bin hm Boole v mt s phng php rt gn hm. Ngoi ra, chng ny cng xt cc loi cng logic v cc tham s chnh ca chng.

NI DUNG 2.1 I S BOOLE

2.1.1. Cc nh l c bn:

STT 1 2 3 4 5 6 7

Tn gi ng nht Phn t 0, 1 B Bt bin Hp th Ph nh p nh l DeMorgan

Dng tch X.1 = X X.0 = 0

Dng tng

X.X = 0
X.X = X X + X.Y = X X=X

Bng 2.1. Mt s nh l thng dng trong i s chuyn mch 2.1.2 Cc nh lut c bn:

+ Kt hp: X. ( Y.Z ) = ( X.Y ) .Z , X + ( Y + Z ) = ( X + Y ) + Z + Phn phi: X. ( Y + Z ) = X.Y + X.Z , ( X + Y ) . ( X + Z ) = X + Y.Z

2.2 CC PHNG PHP BIU DIN HM BOOLE

Nh ni trn, hm logic c th hin bng nhng biu thc i s nh cc mn ton hc khc. y l phng php tng qut nht biu din hm logic. Ngoi ra, mt s phng php khc cng c dng biu din loi hm ny. Mi phng php u c u im v ng dng ring ca n. Di y l ni dung ca mt s phng php thng dng. 2.2.1 Bng trng thi Lit k gi tr (trng thi) mi bin theo tng ct v gi tr hm theo mt ct ring (thng l bn phi bng). Bng trng thi cn c gi l bng s tht hay bng chn l.

12

.4

+ Hon v: X.Y = Y.X , X + Y = Y + X

te

ch

( X.Y.Z...) = X + Y + Z + ... ( X + Y + Z + ...) = X.Y.Z...

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X + X =1 X+X=X X.(X + Y) = X

X+1=1

X+0=X

Chng 2: i s Boole v cc phng php biu din hm

m m0 m1 m2 m3 m4 m5 m6 m7

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

f 0 0 0 0 0 0 0 1

i vi hm n bin s c 2n t hp c lp. Cc t hp ny c k hiu bng ch mi, vi i = 0 n 2n -1 (xem bng 2-2) v c tn gi l cc hng tch hay cn gi l mintex. V mi hng tch c th ly 2 gi tr l 0 hoc 1, nn nu c n bin th s hm m bng

2.2.2 Phng php bng Cc n (Karnaugh)

2.2.3 Phng php i s C 2 dng biu din l dng tuyn (tng cc tch) v dng hi (tch cc tng). + Dng tuyn: Mi s hng l mt hng tch hay mintex, thng k hiu bng ch "mi".

+ Dng hi: Mi tha s l hng tng hay maxtex, thng c k hiu bng ch "Mi". Nu trong tt c mi hng tch hay hng tng c mt cc bin, th dng tng cc tch hay tch cc tng tng ng c gi l dng chun. Dng chun l duy nht. Tng qut, hm logic n bin c th biu din ch bng mt dng tng cc tch:

Mun thit lp bng Cc n ca mt hm cho di dng chun tng cc tch, ta ch vic ghi gi tr 1 vo cc ng vi hng tch c mt trong biu din, cc cn li s ly gi tr 0 (theo nh l DeMorgan). Nu hm cho di dng tch cc tng, cch lm cng tng t, nhng cc ng vi hng tng c trong biu din li ly gi tr 0 v cc khc ly gi tr 1.

f ( X n 1,..., X 0 ) =

.4
2n 1 i =0

Tnh tun hon ca bng Cc n: Khng nhng cc k cn khc nhau mt bin m cc u dng v cui dng, u ct v cui ct cng ch khc nhau mt bin (k c 4 gc vung ca bng). Bi vy cc ny cng gi l k cn.

te
a i mi

T chc ca bng Cc n: Cc t hp bin c vit theo mt dng (thng l pha trn) v mt ct (thng l bn tri). Nh vy, mt hm logic c n bin s c 2n . Mi th hin mt hng tch hay mt hng tng, cc hng tch trong hai k cn ch khc nhau mt bin.

ch

.c
13

trng thi c th thit lp c s l:

N = 22

om .v
n

Bng 2.2. Bng trng thi hm 3 bin

Chng 2: i s Boole v cc phng php biu din hm hoc bng ch mt dng tch cc tng:

f ( X n 1,..., X 0 ) =

2n 1 i =0

( a i + mi )

y, ai ch ly hai gi tr 0 hoc 1. i vi mt hm th mintex v maxtex l b ca nhau.

2.3 CC PHNG PHP RT GN HM

2.3.1. Phng php i s

V d: Hy a hm logic v dng ti gin:

f = AB + AC + BC
p dng nh l, A + A = 1 , X + XY = X ta c:

f = AB + AC + BC ( A + A ) = AB + ABC + AC + ABC = AB + AC

Phng php ny thng c dng rt gn cc hm c s bin khng vt qu 5. Cc bc ti thiu ha: 1. Gp cc k cn c gi tr 1 (hoc 0) li thnh tng nhm 2, 4, ...., 2i . S trong mi nhm cng ln kt qu thu c cng ti gin. Mt c th c gp nhiu ln trong cc nhm khc nhau. Nu gp theo cc c gi tr 0 ta s thu c biu thc b ca hm. 2. Thay mi nhm bng mt hng tch mi, trong gi li cc bin ging nhau theo dng v ct.

3. Cng cc hng tch mi li, ta c hm ti gin. V d: Hy dng bng Cc n gin c hm :

.4

te

2.3.2 Phng php bng Cc n

ch

Vy nu trong tng cc tch, xut hin mt bin v o ca bin trong hai s hng khc nhau, cc tha s cn li trong hai s hng to thnh tha s ca mt s hng th ba th s hng th ba l tha v c th b i.

f ( A, B, C ) = (1, 2, 3, 4, 5 )
Li gii:

.c
A
0 1

14

om .v
BC
00 1 1 01 1 1 11 1 0 10 0 0

Hnh 2-2

n
f1 = B f 2 = AC

Da vo cc nh l hc a biu thc v dng ti gin.

Chng 2: i s Boole v cc phng php biu din hm + Xy dng bng KN tng ng vi hm cho. + Gp cc c gi tr 1 k cn li vi nhau thnh hai nhm (hnh 2-2) Li gii phi tm :

f = f1 + f 2 = B + AC
Nu gp cc c gi tr 0 li theo hai nhm, ta thu c biu thc hm b f :

f = AB + BC
2.3.3. Phng php Quine Mc. Cluskey Phng php ny c th ti thiu ha c hm nhiu bin v c th tin hnh cng vic nh my tnh. Cc bc ti thiu ha:

1. Lp bng lit k cc hng tch di dng nh phn theo tng nhm vi s bit 1 ging nhau v xp chng theo s bit 1 tng dn. 2. Gp 2 hng tch ca mi cp nhm ch khc nhau 1 bit to cc nhm mi. Trong mi nhm mi, gi li cc bin ging nhau, bin b i thay bng mt du ngang (-). Lp li cho n khi trong cc nhm to thnh khng cn kh nng gp na. Mi ln rt gn, ta nh du # vo cc hng ghp cp c. Cc hng khng nh du trong mi ln rt gn s c tp hp li la chn biu thc ti gin. V d. Hy tm biu thc ti gin cho hm:

Bng a Hng tch

.4
Nh phn ABCD 1010 1100 1011 1101 1110 1111

Gii: Bc 1: Lp bng (bng 2.3a):

te

f ( A, B, C, D ) = (10, 11, 12, 13, 14, 15 )

ch
Rt gn ln u. ABCD Bng 2.3

.c

sp xp 10 12

1 0 1 - # (10,11) 1 - 1 0 # (10,14) 1 1 0 - # (12,13) 1 1 - 0 # (12,14) 1 - 1 1 # (11,15) 1 1 - 1 # (13,15) 1 1 1 - # (14,15)

11 13 14 15

Bc 2: Thc hin nhm cc hng tch (bng 2.3b). 15

om .v
Bng b ABCD 11-1-1-

Rt gn ln th 2.

(12,13,14,15) (10,11,14,15)

Chng 2: i s Boole v cc phng php biu din hm Tip tc lp bng la chn tm hm ti gin (Bng 2.4):

A BCD 11-1-1-

10

11

12 x

13 x

14 x x

15 x x

x Bng 2.4

2.4 CNG LOGIC V CC THAM S CHNH

Cng logic c s l mch in thc hin ba php tnh c bn trong i s logic, vy ta s c ba loi cng logic c s l AND, OR v NOT.

2.4.1.1 Cng AND Cng AND thc hin hm logic

hoc nhiu bin:

A B

.4
f f

te

f ( A, B, C, D,...) = A.B.C.D...
A B A B C D E & f

A B C D E

ch

f = f ( A, B ) = A.B

.c
& f

2.4.1 Cng logic c bn

a) Theo tiu chun ANSI

Hnh 2-4a,b. K hiu ca cng AND. Nguyn l hot ng ca cng AND: Bng trng thi 2.5a,b l nguyn l hot ng ca cng AND (2 li vo).

16

om .v
b) Theo tiu chun IEEE

f ( A, B, C, D ) = AB + AC

T bng 2-4, ta nhn thy rng 4 ct c duy nht mt du "x" ng vi hai hng 11-- v 1-1-. Do , biu thc ti gin l :

Chng 2: i s Boole v cc phng php biu din hm

A 0 0 1 1

B 0 1 0 1

f 0 0 0 1

A L L H H

B L H L H

f L L L H

a) Ghi theo gi tr logic

b) Ghi theo mc logic

Khi tc ng ti li vo cc chui xung s xc nh, u ra cng s xut hin mt chui xung nh ch hnh 2-4. th ny thng c gi l th dng xung, th dng sng hay th thi gian.
0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0

.c
1 1 1 1 0 0 0 0 0 1 0 0 t6 t7 t8 t9 t10

ch
0 0 t4 t5

.4

te

t0

t1

t2

t3

T th, ta nhn thy rng, ch ti cc thi im t2 n t3 v t7 n t8 trn c hai li vo u c logic 1 nn li ra cng ly logic 1. ng vi cc khong thi gian cn li v hoc c hai li vo bng 0, hoc mt trong hai li vo bng 0 nn li ra ly logic 0. Hot ng ca cng AND nhiu li vo cng xy ra tng t.

V d : Dng cng AND to "ca" thi gian. Trong ng dng ny, trn hai li vo ca cng AND c a ti 2 chui tn hiu s X, Y c tn s khc nhau. Gi s tn s ca X ln hn tn s ca Y. Trn u ra cng AND ch tn ti tn hiu X, gin on theo tng chu k ca Y. Nh vy, chui s Y ch gi vai tr ng, ngt cng AND v thng c gi l tn hiu "ca". Hot ng ca mch c m t bng hnh 2-5.

C th gii thch d dng mt vi ng dng ca cng AND qua th dng xung.

Hnh 2-4. th dng xung vo, ra ca cng AND

om .v
Li vo A Li vo B t

Theo qui c, logic 1 c thay bng mc in th cao, vit tt l H (High) cn logic 0 c thay bng mc in th thp, vit tt l L (Low) (bng 2-5b). Cng AND c n li vo s c 2n hng tch (dng) trong bng trng thi.

n
Li ra f

Bng 2.5a,b. Bng trng thi m t hot ng ca cng AND 2 li vo.

17

Chng 2: i s Boole v cc phng php biu din hm

X Y

1s

1s

Hnh 2-5. M hnh dng cng AND to ca thi gian

2.4.1.2 Cng OR Cng OR thc hin hm logic: hoc vi hm nhiu bin:

f ( A, B, C, D...) = A + B + C + D + ...

A B F

.c
A B A B C D E

K hiu ca cng OR c biu din hnh 2-6a, b.

a) Theo tiu chun ANSI

.4

A B C D E

te
F

ch
f 0 1 1 1 A L L H H

Hnh 2-6 a, b. K hiu ca cng OR.

Tng t nh cng AND, nguyn l hot ng ca cng OR c th c gii thch thng qua bng trng thi (Bng 2.6a,b) v th dng xung - hnh 2-7. A 0 0 1 1 B 0 1 0 1 B L H L H f L H H H

a) Theo gi tr logic

Bng 2.6 a, b. Bng trng thi ca cng OR.

18

om .v
f ( A, B ) = A + B
1 F 1 F

b) Theo tiu chun IEEE

b) Theo mc in th

Ty theo iu kin cho trc, c th ng dng mch theo cc mc ch khc nhau. Nu bit rng xung ca Y ( thng ly bng 1s ) th s xung xut hin u ra chnh bng tn s ca X. Ngc li, nu tn s ca X cho, chng hn bng 1 Hz ( Tx = 1s ) th ch cn m s xung trn u ra ta c th tnh c rng xung ca Y. y chnh l phng php o tn s v thi gian c ng dng trong k thut hin nay.

Chng 2: i s Boole v cc phng php biu din hm 0 0 0

t0

1 0 1
t1

1 1 1
t2

0 1 1
t3

0 1 1
t4

0 0 0
t5

1 0 1
t6

0 0 0
t9

A
f

1 0 1
t7

1
t8

t10

Hnh 2-7. th dng xung ca cng OR.

Cng NOT thc hin hm logic: f =A

K hiu ca cng NOT c ch ra trn hnh 2-8 a, b.

A

ch
f 1 0

.c
A A

A = 0 th A = 1 ,

.4

Hot ng ca cng NOT kh n gin, nu li vo:

A Hnh 2-9

nu A = 1 th A = 0

Nguyn l ny c minh ho bng th dng xung hnh 2-9. Hot ng ca cng NOT c tm tt bng 2.7a,b. A 0 1 A L H f H L

a) Theo gi tr logic

te

a) Theo tiu chun ANSI.

Hnh 2-8a,b. K hiu ca cng NOT

Bng 2.7a, b. Bng trng thi ca cng NOT. 2.4.2 Logic dng v logic m Logic dng l logic c in th mc H lun ln hn in th mc L (Hnh 2-10).

om .v
A 1

2.4.1.3. Cng NOT

b) Theo tiu chun IEEE.

b) Theo mc logic

n
A A
19

Mt cng OR c n li vo s c 2n hng tch trong bng trng thi ca n.

Chng 2: i s Boole v cc phng php biu din hm

V H L 0 V 0 H 0 L b) Logic dng vi mc m. 1 1 t 0 0 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1

0 t

a) Logic dng vi mc dng.

Logic m th ngc li, logic 1 c in th thp hn mc 0. Khi nim logic m thng c dng biu din tr cc bin. Logic m v mc m ca logic l hon ton khc nhau. 2.4.3 Mt s cng ghp thng dng

2.4.3.1 Cng NAND

Ghp ni tip mt cng AND vi mt cng NOT ta c cng NAND (Hnh 2-11). A AB f = AB

Hm ra ca cng NAND 2 v nhiu bin vo nh sau:

.4
f f

te
f =

Hnh 2-11. S cu to cng NAND

K hiu cng NAND (hnh 2-12a,b) v bng trng thi (bng 2-8).

ch
AB f = ABCD...
A B A B C D E

.c
& &

Khi ghp ba loi cng logic c bn nht s thu c cc mch logic t n gin n phc tp. y ta ch xt mt vi mch ghp n gin nhng rt thng dng.

A B C

a) Theo tiu chun ANSI

Hnh 2-12a,b. K hiu ca cng NAND 20

om .v
f f

Hnh 2-10a,b. th dng xung ca logic dng

b) Theo tiu chun IEEE

Chng 2: i s Boole v cc phng php biu din hm

A 0 0 1 1

B 0 1 0 1

f 1 1 1 0

A L L H H

B L H L H

f H H H L

Bng 2.8a,b. Bng trng thi ca cng NAND

T hnh 2-13 ta c th vit c hm ra ca cng NOR 2 v nhiu li vo nh sau:

f = A + B hay f = A + B + C + ...
A B

A+B

K hiu ca cng NOR 2 li vo nh ch hnh 2-14a,b.

te

ch
f f 1 0 0 0

Hnh 2-13. S cu to cng NOR

.c
A B A L L H H

A B

.4

a) Theo tiu chun ANSI.

Hnh 2-14a, b. K hiu cng NOR 2 li vo

Hot ng ca cng NOR c gii thch bng bng trng thi nh ch bng 2.9a,b.
A 0 0 1 1 B 0 1 0 1 B L H L H f H L L L

Bng 2.9a, b. Bng trng thi ca cng NOR 2 li vo. 2.4.3.3 Cng khc du Cng khc du cn c mt s tn gi khc: cng Cng Modul-2, cng XOR. 21

om .v
A+B
1 f

Cng NOR c thit lp bng cch ni tip mt cng OR vi mt cng NOT.

b) Theo tiu chun IEEE.

2.4.3.2 Cng NOR

Chng 2: i s Boole v cc phng php biu din hm

B A

AB f = AB + AB AB

Hnh 2-15. S ca cng XOR 2 li vo

T hnh 2-15, ta c biu thc ca hm khc du 2 li vo l:

A B f

a) Theo tiu chun ANSI

Hnh 2-16a, b. K hiu ca cng XOR 2 li vo

0 0 1 1

0 1 0 1

te
0 1 1 0

ch

Bng trng thi ca cng XOR hai li vo c trnh by bng 2.10a,b.

.c
A L L H H L L

.4

Hot ng cng XOR nhiu li vo cng tng t nh cng 2 li vo, ngha l nu s bit 1 trn tt cc cc li vo l mt s l, th hm ra ly logic 1; ngc li nu tng s bit 1 trn cc li vo l mt s chn, th hm ra ly logic 0. C th dng cng XOR 2 li vo thc hin hm XOR nhiu bin. 2.4.3.4 Cng ng du (XNOR) Cng XNOR thc hin biu thc logic sau:

22

f = AB + AB hay f = A B = A ~ B
K hiu ca cng XNOR hai li vo c trnh by hnh 2-17.

Bng 2-10a,b. Bng trng thi ca cng XOR 2 li vo

om .v
A B =1 f

K hiu ca cng XOR 2 li vo nh hnh 2-16a, b.

b) Theo tiu chun IEEE

F L H H L

f = AB + AB

hay theo qui c

f = AB

Chng 2: i s Boole v cc phng php biu din hm

A B

A f B

=1

a) Theo tiu chun ANSI

b) Theo tiu chun IEEE

Hnh 2-17. K hiu ca cng XNOR 2 li vo Nu tng s bit 0 trn tt c cc li vo l mt s l, th hm ra ca XNOR s ly logic 1. Nu tng s bit 0 trn tt c cc li vo l mt s chn, th hm ra li ly logic 0.

2.4.4 Cc tham s chnh 2.4.4.1 Mc logic

5v 4v 3v 2v 1v 0v 0,8v VVHmin VVLma NH 2,4v VVHmax VRHmax

om .v
VVHmax VVHmin NH 3,5v VVLma 1,5v NL

VRHmin

Vo

te

NL 0,4v

ch
VRLmax

.c

n
4,9v 0,1v

XOR v XNOR l hai loi cng c rt nhiu ng dng trong k thut s. Chng l phn t chnh hp thnh b cng, tr , so snh hai s nh phn v.v...

VRHmax VRHmin

VRLmax

Ra

Vo

Ra

.4

a) i vi h TTL

b) i vi h CMOS

Mc logic l mc in th trn u vo v u ra ca cng tng ng vi logic "1" v logic "0", n ph thuc in th ngun nui ca cng (VCC i vi h TTL (Transistor Transistor Logic) v VDD i vi h MOS (Metal Oxide Semiconductor)). Lu rng, nu mc logic vo vt qu in th ngun nui c th gy h hng cho cng. Mc TTL Mc TTL l mt chun quc t, trong qui nh: - in th ngun nui VCC , VDD bng + 5 vn hoc bng - 5,2 vn; - Mc in th tng ng vi logic H v L trn u vo, u ra ca cng nh ch hnh 218a,b. Nhn xt: + Mc vo ra i vi cng TTL v CMOS (Complementary Metal Oxide Semiconductor) khc nhau rt nhiu; 23

Hnh 2-19a, b. Mc logic ca cc h cng TTL v CMOS

Chng 2: i s Boole v cc phng php biu din hm + Mc vo ra s nh hng n phng v nhiu ca cng. 2.4.4.2 chng nhiu chng nhiu (hay phng v nhiu) l mc nhiu ln nht tc ng ti li vo hoc li ra ca cng m cha lm thay i trng thi vn c ca n.
VNH VNL

VVL

TT

VRH

VVH

TT

VVH

TT

VRL

VVL

TT

VRH

Cng I

Cng II

a) Tc ng nhiu khi mc ra cao

Hnh 2-20a, b, M t tc ng nhiu n cc cng logic nh hng ca nhiu c th phn ra hai trng hp :

+ Nhiu mc cao: u ra cng I ly logic H (hnh 2-20a), tt nhin, u ra cng II l logic L, nu cc cng vn hot ng bnh thng. Khi tnh ti tc ng ca nhiu, ta c:

VRH min + VNH VVH min

VNH VVH min VRH min

Vi cng CMOS: VNL 3,5V 4,9V = 1, 4V

VRLmax + VNL VVLmax

Vi cng TTL: VNL 0,8V 0, 4V = 0, 4V Vi cng CMOS: VNL 1,5V 0,1V = 1, 4V 2.4.4.3 H s ghp ti K Cho bit kh nng ni c bao nhiu li vo ti u ra ca mt cng cho.

H s ghp ti ph thuc dng ra (hay dng phun) ca cng chu ti v dng vo (hay dng ht) ca cc cng ti c hai trng thi H, L.

24

.4

+ Nhiu mc thp: u ra cng I ly logic L (hnh 2-20b), tng t ta c:

te

Vi cng TTL: VNL 2V 2, 4V = 0, 4V

VNL VVLmax VRLmax

ch

.c

om .v

Cng I

b) Tc ng nhiu khi mc ra thp

n
Cng II

Chng 2: i s Boole v cc phng php biu din hm

Cng chu ti A B IRH H

Cc cng ti

Cng chu ti A B

Cc cng ti

IRL

a) Mc ra ca cng chu ti l H

b) Mc ra ca cng chu ti l L

+Vcc L H ICCH H

ICCH - L dng tiu th khi u ra ly mc H,

Cng sut tiu th trung bnh ca mi cng s l :

2.4.4.5. Tr truyn lan

Tn hiu i qua mt cng phi mt mt khong thi gian, c gi l tr truyn lan.

Vo Vo Ra Ra

.4

Theo thng k, tn hiu s c t l bit H / bit L khong 50%. Do , dng tiu th trung bnh ICC c tnh theo cng thc : ICC = (ICCH + ICCL)/ 2

te

ICCL - L dng tiu th khi u ra ly mc L.

P0 = ICC . VCC

ch

Hnh 2-22. Hai trng thi tiu th dng ca cng logic

.c
tTHL

Hnh 2-23. Minh ho tr truyn lan ca tn hiu 25

om .v
+Vcc H H ICCL L tTLH

2.4.4.4. Cng sut tiu th

Hnh 2-21a,b. M t v h s ghp ti.

Chng 2: i s Boole v cc phng php biu din hm Tr truyn lan xy ra ti c hai sn ca xung ra. Nu k hiu tr truyn lan ng vi sn trc l tTHL v sn sau l tTLH th tr truyn lan trung bnh l: tTtb = ( t THL + t TLH )/2 Thi gian tr truyn lan hn ch tn s cng tc ca cng. Tr cng ln th tn s cng tc cc i cng thp.

TM TT
Trong chng 2 chng ta gii thiu v cc phng php biu din v rt gn hm Boole. Ngoi ra cn gii thiu mt s cng logic thng dng v cc tham s chnh ca chng.

CU HI N TP
Bi 2.1 Rt gn hm sau theo phng php dng bng Karnaugh: 1. F (A, B, C) = (0, 2, 4, 6,7). a. c.

AB + C AB + C

b. AB + C d. AB + C 2. F (A, B, C, D) = (0, 1, 8, 9, 10) a. c.

BC + D

b. BC + ABD

d. BC + ABD

2.2 Rt gn hm sau theo phng php i s

2. A BC . A B + BC + C A

2.3 Rt gn hm sau theo phng php Quine-Mc.CLUSKEY: F (A, B, C, D) = (2, 3, 6, 7, 12, 13, 14, 15). a. 26

1. C D + C D . A C + D a.

CD
CD

b. CD c.

d. CD

AB + AC b. AB + AC + BC c. AC + BC
a. d. AB + BC

AC + AB

.4

te

BC + ABD

ch

.c

om .v

Chng 2: i s Boole v cc phng php biu din hm b. AC + AD

AC + AB d. AC + AB
c. 2.4 Hai mch in hnh di y l tng ng A B a. b. c. d. Do u bng A+B Do u bng B Do u bng AB Do u bng A+AB A B

Bi 2.5 Phn tch ngha cc tham s chnh ca cc h cng logic.

Bi 2.6 Trnh by v phng v nhiu ca cc h cng logic? Tnh phng v nhiu ca mt cng logic h TTL, bit VVL = 0 V 0,8 V, VVH = 2,0 V 5,0 V, VRL = 0 V 0,4 V, VRH = 2,4 V 5,0 V? a. c.

VNH = 0.4V, VNL = 0.4 VNH = 0.4V, VNL = 0.4

.4
A B Hnh 1

Bi 2.7 Cho mch in nh hnh 1. Biu thc hm ra l:

te

d. VNH = 0.4V, VNL = 0.4

ch
F

b. VNH = 0.4V, VNL = 0.4

Bi 2.8 Phn tch ngha ca vic ti u ho mch in ca cc h cng logic? Cho v d minh ho? Bi 2.9 Chng minh cc ng thc: a.

a. b. c. d.

AB + AB AB + AB AB + AB AB + AB

A B = A B + AB
27

.c

om .v

Chng 2: i s Boole v cc phng php biu din hm b. AB (A B C) = ABC c. A B C = A B C Bi 2.10 Lit k 3 phn t logic c bn trong k thut s? a. b. c. d. AND, OR v NOT NAND, AND v NOT AND, NOR v NAND AND, OR v XNOR

Bi 2.11 Phn t logic AND 2 li vo cho u ra bng 1 khi cc u vo l bao nhiu?

Bi 2.12 c biu thc A+B nh th no? a. b. c. d. A AND B A XOR B A OR B A NAND B

28

.4

te

ch

.c

om .v

a. b. c. d.

0 v 0 0 v 1 1 v 0 1 v 1

Chng 3: Cng logic TTL v CMOS

CHNG 3: CNG LOGIC TTL V CMOS

GII THIU
Xt v mt c bn th c hai loi linh kin bn dn l lng cc v n cc. Da trn cc linh kin ny, cc mch tch hp c hnh thnh v c sn trn th trng. Cc chc nng k thut s khc nhau cng c ch to trong nhiu dng khc nhau bng cch s dng cng ngh lng cc v n cc. Mt nhm cc IC tng thch vi cc mc logic ging nhau v cc in p ngun thc hin cc chc nng logic a dng phi c ch to bng cch s dng cu hnh mch chuyn bit c gi l h mch logic. Cc yu t chnh ca mt IC lng cc l in tr, it v cc transistor. C hai loi hot ng c bn trong cc mch IC lng cc: Bo ho. Khng bo ho.

Trong mch logic bo ho, cc transistor c vn hnh trong vng bo ho, cn trong cc mch logic khng bo ho th cc transistor khng lm vic ti vng bo ho. Cc h mch logic lng cc c bo ho l:

Mch logic in tr - Transistor (RTL).

Mch logic Transistor Transistor (TTL).

Cc h mch logic lng cc khng bo ha l:

Cc linh kin MOS l cc linh kin n cc v ch c cc MOSFET c vn hnh trong cc mch logic MOS. Cc h mch logic MOS l:

Trong chng 3 s trnh by cc h cng logic ch yu v c dng ph bin hin nay. Phn cui ca chng trnh by mt s mch cho php giao tip gia cc h logic TTL v CMOS.

Schottky TTL.

Mch logic ghp cc pht (ECL).

PMOS. NMOS. CMOS

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Mch logic it Transistor (DTL).

ch

.c

om .v

29

Chng 3: Cng logic TTL v CMOS

NI DUNG
3.1. CC H CNG LOGIC
3.1.1. H DDL DDL (Diode Diode Logic) l h cng logic do cc diode bn dn to thnh. Hnh 3-1a,b l s cng AND, OR 2 li vo h DDL.
+5V

D2

a) Cng AND

A B

D1 D2 R1

.4

Bng trng thi sau th hin nguyn l hot ng ca mch thng qua mc in p vo/ra ca cc cng AND v OR h DDL
AND OR A (V) 0 0 5 5 B (V) 0 5 0 5 F (V) 0 4,3 4,3 4,3

A (V) 0 0 3 3

B (V) 0

3 0 3

Bng 3-1. Bng trng thi ca cng AND v OR h DDL

u im ca h DDL: Mch in n gin, d to ra cc cng AND, OR nhiu li vo. u im ny cho php xy dng cc ma trn diode vi nhiu ng dng khc nhau; Tn s cng tc c th t cao bng cch chn cc diode chuyn mch nhanh; Cng sut tiu th nh. Nhc im : 30

te

Hnh 3-1. Mch in cng AND v OR h DDL.

ch
F (V) 0,7 0,7 0,7 4,7

.c
b) Cng OR

om .v
f A B f

D1

A B

n
f

R1

Chng 3: Cng logic TTL v CMOS phng v nhiu thp (VRL ln) ; H s ghp ti nh. ci thin phng v nhiu ta c th ghp ni tip mch ra mt diode. Tuy nhin, khi VRH cng b st i 0,6V. 3.1.2. H DTL thc hin chc nng o, ta c th u ni tip vi cc cng DDL mt transistor cng tc ch kho. Mch cng nh th c gi l h DTL (Diode Transistor Logic). V d, hnh 3-2a, b l cc cng NOT, NAND thuc h ny.
+5V +5V +5V

om .v
4k D1 D2 D3 A D4 B 5k b)

4k D1 A 5k a) D2 D3

2k f Q1

n
+5V 2k f Q1

Hnh 3-2. S mch in ca h cng TDL. Trong hai trng hp trn, nh cc diode D2, D3 chng nhiu trn li vo ca Q1 c ci thin. Mc logic thp ti li ra f gim xung khong 0,2 V ( bng th bo ho UCE ca Q1). Do IRHmax v IRLmax ca bn dn c th ln hn nhiu so vi diode nn h s ghp ti ca cng cng tng ln. Bng cch tng t, ta c th thit lp cng NOR hoc cc cng lin hp phc tp hn. V ti ca cc cng l in tr nn h s ghp ti (c bit i vi NH) cn b hn ch, mt khc tr truyn lan ca h cng ny cn ln. Nhng tn ti trn s c khc phc tng phn cc h cng sau. 3.1.3. H RTL

H RTL (Resistor Transistor Logic) l cc cng logic c cu to bi cc in tr v transistor. Hnh 3-3 l s ca mt mch NOT h RTL.

Khi in p li vo l 0 V, in p trn base ca transistor s m nn transistor cm nh vy li ra trn collector ca transistor s mc cao. Do li ra ny c ni ln ngun +5 V thng qua diode D nn gi tr in p li ra lc ny khong 5,7 V, nhn mc logic cao. Khi in p li vo l 5 V do hai in tr li vo c gi tr ln lt l 1 k v 10 k, nn in p ti base s ln lm transistor thng lm cho in p li ra l 0 V. Nh vy logic li ra s l o ca logic ca tn hiu li vo. Tng t nh mch hnh 3-3, nu mt in tr c ni thm li vo nh hnh 3-4 sau mch s tr thnh mch NOR h RTL. 31

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te

ch

.c

Chng 3: Cng logic TTL v CMOS

A (V) 0 0 5 5

B (V) 0 5 0 5

Bng 3-2. Bng trng thi ca cng NOR h RTL

3.1.4. H TTL

Do hn ch v tc , h DTL tr nn lc hu v b thay th hon ton bi h mch TTL. Hn ch tc ca DTL c gii quyt bng cch thay cc it u vo thnh transistor a lp tip gip BE. a. Cng NAND TTL

32

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Hnh 3.4. Cng NOR h RTL

te

ch

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F (V) 5,7 0 0 0

Bng 3-2 th hin quan h in p ca cng NOR h RTL, ch khi c hai li vo A v B cng gi tr 0 V th transistor mi cm v li ra nhn logic cao. Cc trng hp khc u dn n transistor thng v lm gi tr logic li ra mc thp.

Hnh 3-3. Cng NOT h RTL

Chng 3: Cng logic TTL v CMOS

+Vcc R1 4k R2 1,6k R3 300 Q3 A B Q4 D1 Q1 Q2 D3 f A B

Hnh 3-5. S mch in mt cng NAND 2 li vo.

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te

Khi bt k mt li vo mc thp th Q1 u tr thnh thng bo ho, do , Q2 v Q4 ng, cn Q3 thng nn u ra ca mch s mc cao. Li ra s ch xung mc thp khi tt c cc li vo u mc logic cao v lm transistor Q1 cm. Diode D3 c s dng nh mch dch mc in p, n c tc dng lm cho Q3 cm hon ton khi Q2 v Q4 thng. Diode ny nhiu khi cn c mc vo mch gia collector Q2 v base ca Q3.

ch

.c
R3 1,6k D3 Q4 Q3 R4 1 k

Hnh 3-5 l s nguyn l ca mch NAND TTL. N c th c chia ra thnh 3 phn. Transistor Q1, tr R1 v cc diode D1, D2 to thnh mch u vo, mch ny thc hin chc nng NAND. Transistor Q2, cc tr R2, R4 to thnh mch gia Q3, Q4, R3 v diode D3 to thnh mch li ra nh phn tch trn.

om .v
R5 1,6k Q6 Q5 R6 1 k

n
+Vcc R7 130 Q7 D4 f Q8

D2

R4 1k

w w
A B D1

R1 4k

R2 4k

Q1 Q2 D2

Hnh 3-6. S mch in ca mt cng OR 2 li vo.

33

Chng 3: Cng logic TTL v CMOS b. Cng OR TTL Hnh 3-6 l s ca mt cng OR h TTL tiu chun hai li vo. Trong trng hp ny, mch vo s dng cc bn dn n. Tuy nhin, nguyn l hot ng ca mch vo ny cng ging vi cng NAND hnh 3-5. c. Cng collector h Nhc im ca h cng TTL c mch ra khp kn l h s ti u ra khng th thay i, nn nhiu khi gy kh khn trong vic kt ni vi u vo ca cc mch in t tng sau. Cng logic collector h khc phc c nhc im ny. Hnh 3-7 l s ca mt cng TTL o collector h tiu chun. Mun a cng vo hot ng, cn u thm tr gnh ngoi, t cc collector n +Vcc.
R1 4k A D1 Q1

R2 1,6k Q2 Q3 R3 1,6k f

Hnh 3-7. Mch in ca mt cng NOT collector h.

Mt nhc im ca cng logic collector h l tn s hot ng ca mch s gim xung do phi s dng in tr gnh ngoi. d. Cng TTL 3 trng thi

Tng t nh cng collector h, cc h cng logic u c cng 3 trng thi. Hnh 3-8 l mt v d v mch in ca cng NAND ba trng thi h TTL tiu chun . A B

Mt cng logic, ngoi hai trng thi cao v thp ti u ra ca n cn c mt trng thi trung gian c gi l cng ba trng thi. Trng thi trung gian ny cn c tn l trng thi u ra c tr khng Z cao hay trng thi treo. Cng c k hiu nh ch hnh 3-8.

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te

ch
F

.c
F

E
(a)

E
(b)

Hnh 3-8. K hiu ca cng ba trng thi : (a) cng NOT; (b) cng AND. Hot ng ca cng NAND 3 trng thi c gii thch bng bng trng thi 3-3. Khi trn li vo E c mc logic thp, cng hot ng nh mt cng NAND. Trn li ra f s tn ti hai trng thi cao v thp nh thng l. 34

om .v
A f

+5V

Chng 3: Cng logic TTL v CMOS

+5V R1 4k R2 4k D1 R3 1,6k R5 130 Q4 Q3 D2 f Q2 Q5 R4 1k

+Vcc R5

A B E

Q1

Q4 Li ra Z cao

Hnh 3-9. Mch in cng NAND 3 trng thi v s tng ng ca n.

E L L L L H H H H A L L H H x x x x B L H L H x x x x f H H H L -

.4

Ngc li, khi trn li vo E mc cao th bt lun trn hai li vo A, B c gi tr logic no (du x trong bng trng thi mang ngha tu chn) li ra f lun trng thi treo, hay th ni. Trng thi ny tng ng vi trng thi u ra khng c ni ti mt im no trong mch. ng vi trng thi ny, tr khng Z trn u ra ca cng, nhn t pha ti vo s rt ln. Theo s tng ng, lc ny c Q4, Q5 u kho. Li ra f dng nh b treo trong mch. Do , trng thi ny cn c gi l trng thi treo. Trong k thut s, cng ba trng thi thng c dng lm cc b m u ra, kho iu khin hng d liu ...

Cng TTL tiu chun c nhc im chung l thi gian tr truyn lan ln. Nguyn nhn ca nhc im ny l do tt c bn dn trong mch u cng tc ch bo ho. Mt trong nhng bin php gim nh tr truyn lan l s dng diode Schottky chng hin tng bo ho ny. Diode v bn dn Schottky Cu to ca diode Schottky cng ging nh diode Silic. Nh vic chn thm mt lp oxit kim loi vo gia tip gip p-n m in th phn cc ca n l 0,4 Vdc (thp hn 0,6 vn i vi diode Silic v cao hn 0,2 vi diode Ge). K hiu ca diode v bn dn Schottky cho hnh 3-10. 35

Bng 3-3. Bng trng thi ca cng 3 trng thi.

e. H TTL c diode Schottky ( TTL + S )

te

ch

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Q5

Chng 3: Cng logic TTL v CMOS

C B E a) K hiu Diode Schottky b) Cu to bn dn Schottky B

E c) K hiu bn dn Schottky

Hnh 3-10. Cu to ca diode Schottky

R1 8,2k

R2 900

A B

Q1

Q2

Hnh 3-11. Mch in ca cng NAND 2 li vo h TTL+S

Nh s dng diode v bn dn Schottky m tn s cng tc ca h cng ny tng ng k. Thi gian tr truyn lan ca cng TTL+S khong 3 ns, cng sut tiu th khong 19 mW. Khi ch tiu thi gian tr khng cn cao th gi tr cc in tr phn cc c tng ln gim dng tiu th ca mi bn dn xung. H cng nh th c tn gi l TTL+LS (Transistor Transistor Logic + Lowpower Schottky Diode). Cng sut tiu th ca h cng ny ch khong 2 mW v thi gian tr truyn lan vn t khong 9,5 ns. Nu cn nng cao tn s cng tc, ngoi vic gim tr s cc in tr phn cc, ngi ta cn dng cc cch ni mch ci tin. H cng thu c c tn l TTL+AS.

36

Nu thay tt c diode v bn dn trong mch in ca h TTL tiu chun bng cc diode v bn dn Schottky, ta s c mch in h cng TTL+S. Hnh 3-11 l mt v d v cng NAND dng diode Schottky.

Mch in h cng TTL + S

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ch
Q4

D1

D2

.c
R5 500

om .v
+Vcc R3 50 Q3 R4 3,5k Q5 f Q6 R6 250

Mch in dng diode Schottky chng bo ho cho cc bn dn nh hnh 3-10b. n gin, ngi ta gi mch ny l bn dn Schottky v k hiu nh hnh 3-10c.

Chng 3: Cng logic TTL v CMOS 3.1.5. H MOS FET Bn dn trng (MOS FET) cng c dng rt ph bin xy dng mch in cc loi cng logic. c im chung v ni bt ca h ny l: Mch in ch bao gm cc MOS FET m khng c in tr Di in th cng tc rng, c th t +3 n +15 V tr thi gian ln, nhng cng sut tiu th rt b Tu theo loi MOS FET c s dng, h ny c chia ra cc tiu h sau.

Hnh 3-12 l s cng NOT v cng NOR loi PMOS. y MOSFET Q2, Q5 ng chc nng cc in tr.
VDD A
S

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A

G
D S

Q1 f=A Q2
D

ch
f

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VDD A
S

Mch in ca h cng ny ch dng MOSFET c knh dn loi P. Cng ngh PMOS cho php sn xut cc mch tch hp vi mt cao nht.

te

VSS

.4

a) Cng NOT

2. Loi NMOS

Hnh 3-12. Mch in ca cng NOT v NOR theo cng ngh PMOS.

VDD Q1 Q2 B

Q2 Q3

B a) Cng NAND

VSS

b) Cng NOR

Hnh 3-13. Mch in cng NAND v NOR theo cng ngh NMOS. 37

n
G
D

1. Loi PMOS

Q3
S

G
D S

Q4 f= A+B Q5
D

VSS b) Cng NOR

VDD Q1 f Q3

VSS

Chng 3: Cng logic TTL v CMOS Hnh 3-13 l s cng NAND v NOR dng NMOS. Du + trn cc li vo mun ch cc tnh ca tn hiu kch thch. Trong trng hp ny, Q1 cng ng chc nng l mt in tr. i vi cng NAND, ta nhn thy rng ch khi trn c hai li vo A v B u ly mc cao th u ra mi c mc thp. ng vi 3 t hp bin vo cn li, li ra f u c logic thp. Hot ng ca cng NOR cng c gii thch tng t. 3. Cng CMOS CMOS l vit tt cc t ting Anh Complementary MOS. Mch in ca h cng logic ny s dng c hai loi MOS FET knh dn P v knh dn N. Bi vy c hin tng b dng in trong mch. Chnh v th m cng sut tiu th ca h cng, c bit trong trng thi tnh l rt b. Hnh 3-14 l mch in ca cng NOT v NAND thuc h CMOS. im ni bt trong mch in ca h cng ny l khng tn ti vai tr cc in tr. Chc nng logic c thc hin bng cch thay i trng thi cc chuyn mch c cc tnh ngc nhau. Du tr v du cng trn cc ca cc MOSFET ch ra cc tnh iu khin chuyn mch. Nh c im cu trc mch, mc VRL, VRH t c gn nh l tng. minh ho, ta c th tm hiu hot ng ca cng NOT. T hnh 3-14a, d thy rng, nu tc ng ti li vo A logic thp th Q1 s thng, Q2 kho. Li ra f gn nh c ni tt ti VDD v cch ly hn vi t, ngha l VRH VDD. Ngc li, khi A ly mc cao, Q1 m v Q2 ng. Do , li ra f gn nh ni t v cch ly vi VDD. Ni khc i, VRL 0.

.c
S G

VDD
S G

ch
f A B

Q1
D D

te

A
G

.4

Q2

a) Cng NOT

Da trn cng ngh CMOS, ngi ta sn xut loi cng c th cho qua c tn hiu s ln tn hiu tng t. Bi vy cng c gi l cng truyn dn. S nguyn l v k hiu cng truyn dn nh hnh 3-15.

38

Hnh 3-14. Mch in ca h cng CMOS.

4. Cng truyn dn

om .v
VDD
S

Q1
D

G D D G S

b) Cng NAND

n
Q2 f Q3 Q4

Chng 3: Cng logic TTL v CMOS

G Q1 S Vo/Ra D D +5V S Q2 G a) Mch in b) K hiu iu khin Ra/Vo Vo/Rao Ra/Vo

H CMOS cng c cng D h v cng ba trng thi nh h TTL. 3.1.6- H ECL

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R5

ECL (Emitter Coupled Logic) l h cng logic c cc E ca mt s bn dn ni chung vi nhau. H mch ny cng s dng cng ngh TTL, nhng cu trc mch c nhng im khc hn vi h TTL. Ngoi vic s dng hi tip m trn in tr RE chng bo ho, mch in ca h ECL cn tn dng c u im ca mch khuch i vi sai, nn tn s cng tc h ny l cao nht trong cc h. Ngoi tr thi gian tr, tt c cc tham s cn li u km hn cc h khc.

te
R6

ch
R8
Q7 Q5 Q6

.c
Q8

Tnh dn in ca cng truyn dn ph thuc mnh vo tn s cng tc v gi tr ti. V s dng cng ngh CMOS nn tn s cng tc ca cng ch gii hn 6 MHz.

B A

Li vo

D C

Q4 Q2 Q3

Q1

-1,29
R4 RE R7

D1 D2 R9 -Vcc = - 5V - 1,75 V - 1,4 V - 1,2 V Vo b) th mc vo/ra

R1

R2

R3

a) Mch in nguyn l

Hnh 3-16. Cng OR/NOR thuc h ECL. Hnh 3-16 l mch in v th mc vo ra ca mt cng OR/NOR thuc h ECL. V in th trn hai cc collector ca Q4, Q5 l b nhau nn c th ly ra cc E ca Q7 chc nng OR v cc E ca Q8 chc nng NOR. mch hot ng theo logic mc m, +Vcc c ni t, 39

om .v
+Vcc Ra - 0,9 V
Li ra OR

Mch nguyn l ca cng truyn dn cng s dng hai MOSFET c knh dn ngc nhau. Tuy nhin cch iu khin trng thi cc chuyn mch li khc vi cng logic thng thng. Trong trng hp ny, ngi ta phn cc sao cho khi c tn hiu iu khin th c hai chuyn mch Q1 v Q2 cng dn in. Khi , mch tng ng nh mt dy dn. Cc cng o (trong s k hiu) m bo cc tnh iu khin ph hp cho c hai cc G ca mi MOSFET.

Li ra NOR

Hnh 3-15. Cng truyn dn.

Chng 3: Cng logic TTL v CMOS Vcc c ni ti m ngun. Mc logic trong mch c bin i t gi tr thp l -1,75 V n gi tr cao l - 0,9 V so vi in th t. Khi mun c mc logic ra dng cc cc E ni ti t.

3.2. GIAO TIP GIA CC CNG LOGIC C BN TTL-CMOS V CMOS-TTL

Trong nhiu ng dng, yu cu chuyn i cc tn hiu gia cc mc logic khc nhau nh t TTL sang CMOS hoc ngc li. Cc cng logic collector h hoc cc mch khuch i transistor n gin thng c s dng trong cc mch chuyn i ny. 3.2.1. Giao tip gia TTL v CMOS.

Trong trng hp ny in p ra ca TTL nh hn so vi in p vo ca CMOS. Do vy ta phi dng mch b sung tng hp hai loi IC khc nhau. Gii php tiu chun l dng in tr ko ln gia iu khin TTL v ti CMOS nh hnh 3-17.
+ 5V

Rp iu khin TTL

b. Khc in p cung cp.

Khi li ra ca TTL mc H th li ra ca cc C h tng ln mt cch th ng n +12V. Trong trng no th cc li ra ca TTL cng u tng hp vi cc trng thi li vo ca CMOS.

40

in p cung cp dng cho IC CMOS thch hp nht l t +9V n +12V. Mt cch dng in p cung cp ln l s dng IC TTL h mch Collector nh hnh 3-18, v tng ra ca TTL h cc C ch gm transistor nhn dng vi cc C th ni. hnh ny cc C h c ni vi ngun cung cp +12V qua in tr ko ln 6,8k. Khi li ra ca h TTL mc L th dng ca n l: Inhn dng =

12V = 1, 76mA 6,8k

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Hnh 3-17. iu khin TTL v ti CMOS

ch

.c
Ti CMOS

om .v

a. Cng in p cung cp +5V.

to c giao tip gia TTL v CMOS th ta phi n ngun cung cp ca 2 h. H TTL cn in p cung cp l + 5V, h CMOS c th dng in p cung cp t +3V n +15V.

Chng 3: Cng logic TTL v CMOS

+ 5V 6,8k + 12V

TTL h mch Collector

Ti CMOS

Hnh 3-18. iu khin TTL h mch Collector v ti CMOS

Trong hnh 3-19, IC TTL tiu chun iu khin b chuyn mc ngun, n ko IC TTL ln t nht l +2,4V. in tr ko ln tip tc a in p ln cao n mc +5V, mc ny m bo chc chn li vo mc H. Li ra ca b chuyn mc ni vi ngun +12V.
+ 5V 3,3k + 12V

iu khin TTL

ch
B chuyn mc 40109

.c
Ti CMOS

3.2.2. Giao tip gia CMOS v TTL to ra c giao tip gia h CMOS v TTL th ta phi quan tm n vn chuyn mc in p cho ti khi trng thi li ra ca CMOS ph hp vi li vo ca TTL. Ta phi m bo chc chn li ra trng thi L ca CMOS lun lun nh hn 0,8 V(y l in p li vo ln nht trng thi L ca h TTL). in p li ra trng thi H ca CMOS lun lun ln hn 2 V(y l in p li vo nh nht trng thi H ca h TTL).

Theo s liu k thut ca IC 74Cxx th trng hp xu nht dng li ra ca CMOS iu khin TTL l: IOL MAX = 360A ; IOH MAX = - 360A

iu ny c ngha l iu khin CMOS c th cho nhn dng l 360 A khi trng thi L, l dng vo i vi IC TTL loi Schottky cng sut thp. Mt khc, iu khin CMOS c th cho dng ngun 360 A, n ln hn mc cn thit iu khin dng vo trng thi H. Nh vy h s ghp ti gia CMOS v 74LS l bng 1.

a. Cng in p cung cp +5V.

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Hnh 3-19. B chuyn mc CMOS cho php s dng hai loi ngun +5V v +12V.

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Hnh 3-19 l b chuyn mc CMOS 40109. Tng li vo ca IC dng in p cung cp +5V trong khi tng li ra dng +12V.

c. B chuyn mc ngun dng CMOS.

41

Chng 3: Cng logic TTL v CMOS i vi loi IC TTL cng sut thp th c dng li vo l 180 A th h s ghp ti gia CMOS v 74L l bng 2. IC CMOS khng th iu khin trc tip IC TTL tiu chun, v dng li vo trng thi L yu cu l 1,6 mA, m transistor nhn dng ca IC CMOS c in tr xp x 1,11k (trng hp xu nht). Nn in p li ra ca IC CMOS bng 1,6 mA x 1,11k = 1,78 V. in p ny qu ln i vi li vo trng thi L ca IC TTL. - Dng tng m bng CMOS.
Tng m CMOS iu khin CMOS + 5V

Hnh 3-20. Tng m CMOS c th iu khin ti TTL tiu chun

IOH MAX = 800A

Hnh 5-23 l mch iu khin CMOS dng in p cung cp +12V, trong khi tng m CMOS c in p cung cp l +5V.
+ 12V Tng m CMOS + 5V

Cc tng m CMOS nh 74C902 c th dng in p cung cp t +3V n +15V v in p li vo t -0,3 V n +15V> in p li vo c th ln hn in p cung cp m khng lm hng loi IC dng lm tng m ny. V d ta c th dng in p li vo trng thi H l +12V ngay khi in p cung cp ch bng 5V.

b. Khc in p cung cp.

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iu khin CMOS

Cc IC khc c dng lm tng m nh hnh 5-19 l IC CD4049A, 4050: o; CD405CA: khng o, 74C901: o

te

V ti TTL tiu chun c dng li vo trng thi L bng 1,6mA v dng li vo trng thi H l 48 A, IC 74C902 c th iu khin hai ti TTL tiu chun.

ch

IOL MAX = 3.60mA

.c

Hnh 3-20 l mch iu khin IC CMOS vi h s ti qua tng m. Tng m c dng ra ln. V d IC 74C902 c 6 tng m CMOS, mi tng m c dng li ra trong trng hp xu nht l:

Hnh 3-21. iu khin CMOS hot ng thch hp nht vi ngun cung cp +12V. 42

om .v
Ti TTL

Ti TTL

Chng 3: Cng logic TTL v CMOS c. Giao din ca h cc mng. Ta bit IC TTL h mch Collector, tng li ra ca transistor nhn dng vi cc C th ni. Tng t nh vy i vi IC CMOS cng c h cc mng. V d: IC 74C906 c 6 tng m h cc mng.
+ 12V 3,3k Tng m CMOS h cc mng + 5V

Hnh 3-22. Tng m CMOS h cc mng lm tng dng nhn. Hnh 3-22 l mch dng tng m CMOS h cc mng lm giao din iu khin CMOS v ti TTL. in p cung cp cho hu ht cc tng m l +12V. Tuy vy c th ni tng m h cc mng vi ngun cung cp +5V qua mt in tr ko ln (pull up) c gi tr 3,3k. Cch ni ny c u im l c iu khin CMOS v tng m CMOS u c cung cp ngun +12V, khng k li ra h cc mng giao din vi TTL

ng thi trong chng 3 cng a ra vn giao tip gia cc h cng vi nhau.

CU HI N TP

1. Chc nng ca mch logic RTL c s nh hnh v sau:

a. NOR
43

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C 2 loi vi mch s ph bin nht : TTL v MOS. TTL l cng ngh in hnh trong nhm cng ngh transistor bao gm TTL, HTL, ECL, MOS l cng ngh vi mch s dng MOSFET, trong in hnh l MOS

te

Chng 3 trnh by cu trc, nguyn l v c im ca cng thng dng. Xut pht t thc t mch in vi mch ho, nn trng tm ch nghin cu ca chng ta l cc cng c vi mch ho.

ch

TM TT

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iu khin CMOS

Ti TTL

Chng 3: Cng logic TTL v CMOS

b. OR c. AND d. NAND
2. Vi mch c s nh trong cu hi 1, nhng in p logic li vo tng ng vi cc mc logic cao v thp ln lt l 10 V v 0 V th chc nng ca mch l g?

a. NOR b. OR d. NAND c. AND

3. Cho mch c s nh s sau, in p logic li v tng ng vi cc mc logic cao v thp ln lt l 1 V v 0 V, nu chc nng ca mch?

a. NOR b. OR c. AND

d. NAND

4. Chc nng ca diode D3 trong s sau l g?

44

a. Cch ly transistor Q3 v Q4 b. Dch mc in p lm cho Q3 v Q4 khng bao gi cng ng hoc cng m

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Chng 3: Cng logic TTL v CMOS

c. Chng nhiu li ra d. Cch ly Q4 khi mch ngoi ni vo u ra f

5. Chc nng ca mch biu din trong s nh cu hi 4 s thay i th no nu diode D3 chuyn ti chn base ca transistor Q3 (cathode D3 ni vi base Q3 cn anode ni vi collector Q2)?

a. Q3 lun cm b. Q3 lun m c. Chc nng ca mch khng thay i d. Li ra lun trng thi treo a. Li ra c ni ln ngun thng qua mt tr gnh b. Li ra c ni ln ngun thng qua mt t gnh c. Li ra ni xung t thng qua mt tr d. Li ra ni xung t thng qua mt t
6. Cng collector h s hot ng bnh thng nh cc cng logic bnh thng nu :

7. Tc dng ca trng thi tr khng li ra cao trong cng ba trng thi l :

a. a ra mc logic th 3 l trung bnh ca hai mc cao v thp b. Cch ly gia cc li ra ca cc cng logic khi chng cng c ni vo mt li c. C mc logic thp nhng tr khng cao d. C mc logic cao nhng tr khng cao
8. Mch in c biu din trong s sau c cn hot ng nh bnh thng khng nu nh diode D1 b ni tt ?

a. Mch tr thnh cng NAND vi hai trng thi li ra nh cc cng NAND thng b. Mch tr thnh cng NOR
45

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Chng 3: Cng logic TTL v CMOS

c. Trng thi li ra khng theo logic c bn no d. Vn hot ng bnh thng l cng NAND 3 trng thi
9. Mch in nh trong cu hi 8 c cn hot ng nh bnh thng khng nu nh in tr R4 c gi tr bng 10 k?

a. N s hot ng nh mch NOR b. N s hot ng nh mch XOR c. Vn hot ng bnh thng

10. Vi mch in TTL nh s trong cu hi 4, hin tng g s xy ra khi mt trong hai li vo lng?

a. Li vo ny c tnh logic 0 b. Li vo ny c tnh logic 1 c. Mch khng hot ng d. C ba cch tr li trn u sai
11. So snh cng NOT h MOS v CMOS ta thy :

a. Cng sut tiu th ca MOS cao hn CMOS b. Cng sut tiu th ca CMOS cao hn MOS c. Cng sut tiu th ca hai h nh nhau d. C ba cch tr li trn u sai

a. c- C th coi l mc 1

46

13. Cng truyn dn l cng

b. c- Phi coi l mc 0 c. Khng c- mch hot ng bnh thng th u vo khng dng phi ni
vi mc logic 0 vi mc logic 1

d. Khng c- mch hot ng bnh thng th u vo khng dng phi ni

a. Ch cho php tn hiu s i qua theo mt chiu nht nh b. Ch cho php tn hiu s i qua theo hai chiu c. Ch cho php tn hiu tng t i qua theo mt chiu nht nh d. Cho php tn hiu tng t i qua theo hai chiu

12. C cho php u vo ca mch CMOS l lng khng? C th ni u vo lng tng ng vi mc cao khng?

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d. C ba cch tr li trn u sai

Chng 3: Cng logic TTL v CMOS 14. u im ca cc cng logic h ECL l

a. Tn s cng tc nhanh b. in p ngun nui thp c. Cng sut tiu th thp d. chng nhiu cao

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Chng 4: Mch logic t hp

CHNG 4: MCH LOGIC T HP

GII THIU CHUNG
Cc hm logic c thc hin nh cc h vt l gi l cc h logic hay l cc mch logic. Trong chng 4 chng ta cp n cc mch logic t hp, tc l cc mch m tn hiu u ra ch ph thuc vo tn hiu u vo ca mch ti thi im ang xt. Ni cch khc, cc tn hiu ra khng ph thuc vo "lch s " ca tn hiu vo trc , ngha l cc h ny lm vic theo nguyn tc khng c nh. Hot ng ca cc mch t hp c m t bng cc bng trng thi hoc bng cc hm chuyn mch logic c trng cho quan h gia cc i lng vo v ra ca h thng. V mt cu trc, cc mch t hp khng cha mt thit b hoc mt phn t nh thng tin no c. Trong chng ny cp n cc mch in c th thc hin cc chc nng khc nhau ca h thng s. Cc mch in ny c thit k da trn cc cng logic t hp. Cc cng logic ny c tch hp trong mt IC c va (MSI) c cha khong vi chc ti vi trm cc cc cng logic c s c xt n chng 4. Nhng linh kin ny c ch to nhm thc hin mt s cc hot ng thu nhn, truyn ti, bin i cc d liu thng qua tn hiu nh phn, x l chng theo mt phng thc no . Phn u ca chng gii thiu cch phn tch v thit k cc mch logic t hp n gin. Phn tip theo gii thiu v Hazard trong mch logic t hp. y l phn rt quan trng khi thit k mch. Nu khng n hin tng ny c th dn n s lm vic sai lch ca c h thng. Phn tch v nhn dng Hazard c ngha rt quan trng khng nhng trong tng hp cc h logic m c trong t ng chn on trng thi lm vic ca chng. Phn tip theo gii thiu mt s mch t hp thng dng trong cc h thng s: - M ho v gii m cc lung d liu nh phn.

48

- Cc mch cng, tr. - Cc php so snh s nh gi nh tnh v nh lng trng s ca cc s nh phn.

- Mch to v kim tra tnh chn l. - n v s hc v logic (ALU).

- Hp knh v phn knh chn hoc chia tch cc lung s nh phn theo nhng yu cu nht nh nh tuyn cho chng trong vic truyn dn thng tin,

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Chng 4: Mch logic t hp

NI DUNG
4.1 KHI NIM CHUNG
Cn c vo c im v chc nng logic, cc mch s c chia thnh 2 loi chnh: mch t hp v mch tun t (mch tun t c trnh by chng sau). 1) c im c bn ca mch t hp Trong mch s, mch t hp l mch m tr s n nh ca tn hiu u ra thi im ang xt ch ph thuc vo t hp cc gi tr tn hiu u vo. c im cu trc mch t hp l c cu trc nn t cc cng logic. Vy cc mch in cng chng 2 v cc mch logic chng 3 u l cc mch t hp. 2) Phng php biu din chc nng logic

Cc phng php thng dng biu din chc nng logic ca mch t hp l hm s logic, bng trng thi, s dng logic, bng Cac n (Karnaugh), cng c khi biu th bng th thi gian dng xung. i vi vi mch c nh (SSI) thng biu din bng hm logic. i vi vi mch c va (MSI) thng biu din bng bng trng thi. S khi tng qut ca mch logic t hp c trnh by hnh 4-1.
x0 x1

Nh vy, mch logic t hp c th c n li vo v m li ra. Mi li ra l mt hm ca cc bin vo. Quan h vo, ra ny c th hin bng h phng trnh tng qut sau: Y0 = f1(x0,x1,...,xn-1); Y1 = f2(x0,x1,...,xn-1); Ym-1 = fm-1(x0,x1,...,xn-1). T , ta thy rng c im ni bt ca mch logic t hp l hm ra ch ph thuc cc bin vo m khng ph thuc vo trng thi ca mch. Cng chnh v th, trng thi ra ch tn ti trong thi gian c tc ng vo. Th loi ca mch logic t hp rt phong ph. Phm vi ng dng ca chng cng rt rng.

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xn-1

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Mch logic t hp

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Hnh 4-1 S khi tng qut ca mch logic t hp.

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Chng 4: Mch logic t hp

4.2 PHN TCH MCH LOGIC T HP

Phn tch mch logic t hp l nh gi, ph phn mt mch . Trn c s , c th rt gn, chuyn i dng thc hin ca mch in c c li gii ti u theo mt ngha no y. Mch t hp c th bao gm hai hay nhiu tng, mc phc tp ca ca mch cng rt khc nhau. Nu mch n gin th ta tin hnh lp bng trng thi, vit biu thc, rt gn, ti u (nu cn) v cui cng v li mch in. Nu mch phc tp th ta tin hnh phn on mch vit biu thc, sau rt gn, ti u (nu cn) v cui cng v li mch in.

Thit k l bi ton ngc vi bi ton phn tch. Ni dung thit k c th hin theo tun t sau: 1- Phn tch bi ton cho gn hm v bin, xc lp mi quan h logic gia hm v cc bin ;

4- T bng trng thi c th vit trc tip biu thc u ra hoc thit lp bng Cac n tng 4- Dng phng php thch hp rt gn, a hm v dng ti gin hoc ti u theo mong mun; 5- V mch in th hin.

+ Nu k hiu hai cng tc l hai bin A, B. Khi tng 1 ta bt n v ln tng 2 th tt n i v ngc li. Nh vy n ch c th sng ng vi hai t hp chuyn mch v tr ngc nhau. Cn n tt khi v tr ging nhau. H thng chiu sng trong c s nh hnh 4-2.
1 1

Bng trng thi m t hot ng ca h nh ch bng 4-1. Biu thc ca hm l: f = A B + A B = A B hoc

Li gii:

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V d : Mt ngi nh hai tng. Ngi ta lp hai chuyn mch hai chiu ti hai tng, sao cho tng no cng c th bt hoc tt n. Hy thit k mt mch logic m phng h thng ?

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A

ng;

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0

2- Lp bng trng thi tng ng;

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4.3 THIT K MCH LOGIC T HP

f = AB A AB B

VAC Hnh 4-2 Mch in ca h thng chiu sng

y l hm cng XOR quen thuc cc chng trc. Hm ny c th c th hin bng nhiu kiu mch khc nhau. Hnh 4-3 l mt dng s th hin hm f.

50

n
B 0

Chng 4: Mch logic t hp

A 0 0 1 1 B 0 1 0 1 f 0 1 1 0

A B

Bng 4-1. Bng trng thi m t hot ng ca h chiu sng

Hnh 4-3. S logic th hin hm f

4.4 HAZARD TRONG MCH T HP

4.4.1. Khi nim.

- Hazard ch xut hin mt ln v khng bao gi gp li na. no).

Nh ta bit, mt trong cc c tnh quan trng nht ca mch in khi hot ng l qun tnh, linh ng hay s chm tr ca mch. Chnh s chm tr ny lm cho tn hiu t u vo khng th truyn ngay tc khc ti u ra ca mch in, iu ny lm cho cc thit b iu khin pha sau khng th c phn ng tc khc i vi tn hiu a vo. Do tt c cc mch in u c thi gian tr nht nh, ngay c cc mch vi in t cng c thi gian tr. S thay i nhit mi trng cng lm cho thi gian tr thay i, dn n s sai lch khi iu khin ca mch logic, chnh l hazard. 4.4.2. Bn cht ca Hazard hiu c nguyn nhn xut hin hazard trong mch logic t hp, hazard ch xut hin trong mch t hp m khng xut hin bt k h thng in t no khc. Ta xt v d sau:

Gi s tn hiu vo l X = (x1, x2, x3, x4) thay i gi tr t (0 0 0 1) n (1 1 1 1), tc l (X) thay i t QP. Nhn vo bng Cac n (hnh 4-4) ta thy p ng ra ca mch logic t hp khi tn hiu vo b thay i c gi tr: f(Q) = f(0001) = 1 f(P) = f(1111)= 1 51

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- Hazard c th do chnh chc nng ca mch in gy ra. y l trng hp kh gii quyt nht khi thit k.

te

- Hazard c th xut hin nhiu ln (theo mt chu k no hoc khng theo mt chu k

ch

Hazard cn c gi l s "sai nhm", hot ng lc c lc khng ca mch logic. S "sai nhm" ny c th xy ra trong mt mch in hon ton khng c hng hc linh kin. Tc l trong mch, cc linh kin hon ton tt nhng iu khin chc nng lc c lc khng. Ni chung l mch hot ng khng c s tin cy. Hin tng ca Hazard trong mch t hp c th gp l:

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Vic thit k cc mch logic nhn chung khng phc tp, v cn c biu thc ton l ta c th v ra c mch in v lp rp thnh h thng iu khin. Trn thc t, khng phi mch no cng c th hot ng tt c, nguyn nhn l do cu trc ca mch t hp gy ra, hin tng hot ng khng n nh xy ra trong mch t hp c gi l hazard.

Chng 4: Mch logic t hp

t0 x 3x 4 x 1x 2 00 t'0 01 11 10 00 1 0 1 0 01 1 0 1 0 11 1 0 1 1 10 0 1 0 1 t1

x1 x2 x3 x4

Mch logic

f(x)

Hnh 4-4. Mch chc nng logic

(X) t0
'

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(x1 x2 x3 x4 ) 0 0 0 0 1 1 1 1 1 1 0 1

V c s "chy ua" gia ba tn hiu vo (x1, x2, x3) (x4 khng thay i nn khng ua), gi s x2 chy nhanh hn (c thi gian tr nh hn) x1, x2 (gi s thi gian tr ca hai tn hiu ny bng nhau). Mi quan h ny ta c th biu din nh sau: p ng ra f(Q) = 1 f(0101) = 0 f(P) = 1

Do x2 "chy" nhanh hn x1 v x3 nn gi tr ca x2 chuyn t 0 sang 1 trc gi tr ca x1 v x3. Sau mt thi gian th (x1, x3) mi chuyn t 0 sang 1. Quan h "chy ua" gia ba tn hiu vo c minh ho bng biu sau: Do x2 "chy nhanh" hn (x1, x3) nn trong khong thi gian t xut hin mt xung zr nht thi. Nh vy trong thi gian tr ca mch tn hiu ra thay i t 101 (ng ra l khng c thay i), to ra mt xung kim nht thi. Hin tng xut hin mt xung zr u ra ca mch c gi l hin tng hazard v y l hazard nht thi, n ch xut hin trong thi gian tr sau li mt ngay. Nh vy ta c th ni rng s "chy ua" ca tn hiu vo gy ra 52

t0 t1

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Trong trng hp ny, cc tn hiu vo (x1, x2, x3) c gi tr logic b thay i khi ta thay i b tn hiu vo, v chng s c mt thi gian tr nht nh (c th rt nh, c s hay ns). Mt khc, thi gian tr ca mi ng tn hiu vo (xi) li khc nhau, d cng mt chng loi IC. Nh vy nu (x1, x2, x3) c thay i ng thi v chng c thi gian tr khc nhau th vn xy ra hin tng "chy ua" ca tn hiu vo ti u ra ca mch in.

ch

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Nhng thc t c th khng c nh vy v khi tn hiu vo thay i t Q = (0001) n P = (1111), ta thy tn hiu x1, x2, x3 b thay i cn gi tr x4 khng b thay i. Mch in no cng xut hin thi gian tr l () v s thay i gi tr (01 hay 10) ca tn hiu u c thi gian tr nht nh.

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Nh vy tn hiu vo (X) thay i gi tr t Q = (0001) n P = (1111) lm cho p ng ra ca mch b thay i gi tr t 1 sang 1 , s thay i iu khin u ra ca mch theo s thay i tn hiu vo (X) iu ny hon ton chnh xc, khi hazard khng xut hin v khng xy ra iu khin b sai nhm.

Chng 4: Mch logic t hp hazard, hay thi gian tr ca mch s lm xut hin hazard, l tn hiu iu khin khng mong mun u ra. Xung Hazard l mt xung kim xut hin u ra ca mch logic t hp, v thi gian xut hin (t) nh hn thi gian tr ca mch () nn xung hazard c th xut hin nhng khng gy nguy him, khng gy ra s iu khin sai nhm. V xung hazard qu hp nn nng lng ca n khng ln c th kch nhm hay kch c cc mch in tip theo, do d c xung hazard nhng mch in vn hot ng tt. Xung hazard ch tht s nguy him khi rng t ln th n c nng lng lt chuyn mch in tip theo gy ra hin tng iu khin nhm.
x1, x3

thi gian tr

0 x2

0 Q f(x) 1 0

t P

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Hnh 4-5. Hin tng hazard

4.4.3. Phn loi.

Q = (q1, q2, ....qk, qk+1,...qn )

nh ngha 1: Nu tp tn hiu vo (X) thay i t Q sang P th c gi l c s chuyn i t Q sang P (Q P). nh ngha 2: Hazard nht thi xut hin trong mch logic t hp l hin tng tn hiu ra mt hoc nhiu u ra ca mch xut hin khc vi cc gi tr quy nh cho chng theo hm Boole trong thi gian chuyn i t Q P.

nh ngha 3: Hazard nht thi xut hin trong mch logic t hp trong thi gian chuyn i t Q P gi l hazard tnh nu v ch nu f(Q) = f(P). y f(X) l hm logic c thc hin bi cc mch cho. nh ngha 4: Hazard nht thi xut hin trong mch logic t hp trong thi gian chuyn

i t Q P gi l hazard ng nu v ch nu f(Q) = f(P) . Nh vy khi c hazard nht thi

53

y P v Q l tp tn hiu vo ca mch, nhng yu cu gia P v Q cn c s lng v tr thay i gi tr logic 2, v ch khi tp tn hiu vo thay i gi tr logic ng thi vi t nht 2 v tr (2 bin s) th mi xut hin hin tng "chy ua" tn hiu vo, v khi hazard mi c kh nng xut hin. Cn nu tn hiu vo ch thay i gi tr ln lt trn tng u vo mt th s khng c hin tng chy ua tn hiu v hazard khng th xut hin c.

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P = ( q1 , q 2 ...q k , q k +1 ,...q n )

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u tin ta cp n mt s nh ngha tn gi khi ni v hazard nh sau:

ch

Nh vy c th thy vi b tn hiu vo thay i kiu khc vi t hp trn th c th khng xut hin xung hazard. Hay vi mt chc nng khc d c hin tng "chy ua" tn hiu vo gia (x1,x3 v x2) nh v d trn nhng c f(0101) = 1 th hazard cng khng th xut hin do xung zr nht thi khng c.Do vy ta thy hin tng hazard xut hin rt ngu nhin cho d mch in cha ton cc linh kin tt.

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Chng 4: Mch logic t hp ng th tn hiu u ra thay i t nht ba ln, v d 1010, ngha l c t nht hai xung nhiu xut hin. Loi hazard ny thng xy ra trong cc mch t hp. nh ngha 5: Hazard nht thi gi l hazard hm s trong thi gian chuyn i t QP nu: - f(Q)=f(P) - Hm f(X) ly c hai gi tr 1 v 0 trong thi gian chuyn i t QP nh ngha 6: Hazard nht thi gi l hazard logic trong thi gian chuyn i t QP nu: - f(Q)=f(P) - Hm f(X) ch nhn mt gi tr nh nhau (hoc 0 hoc 1)

- Trong thi gian chuyn i t QP xut hin mt xung hazard u ra.

4.4.3.1. Hazard tnh trong mch logic.

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x1, x4 0 x2 0

Nhng hazard tnh nguy him ch: n c th gy ra "sai nhm" cho iu khin ca h thng logic khi gi tr rng hazard (t) ln, iu ny s xy ra khi s "chy ua" ca tn hiu vo qu chnh lch, ngha l c tn hiu vo "chy" qu nhanh cn tn hiu khc li "chy" qu chm, hin tng ny c minh ho hnh 4-6.

te
Q t t0 t'0 t1

ch
P

Hazard nht thi cng chnh l hazard tnh, tc l loi hazard ch xut hin nh mt xung khng theo quy nh ca hm logic. Hin tng ny khng nguy him, v rng ca xung hazard tnh t lun nh hn thi gian tr ca mch, nn mch logic vn hot ng bnh thng d c xut hin hazard.

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Do c hin tng "chy ua" gia cc tn hiu vo vi nhau trong thi gian chuyn t QP m xut hin hazard. Nu f(Q) = f(P) tc l c s thay i ca tn hiu vo nhng s iu khin u ra ca mch logic vn khng i d l 0 hay 1, nhng xut hin hazard, khi s lng tn hiu chy ua khng nhiu, chnh l hazard tnh.

f(x)

0 Hnh 4-6. Chy ua hazard tnh

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t t t

Chng 4: Mch logic t hp Ta thy x2 trong qu trnh "chy ua" (thay i gi tr logic) "chy" nhanh hn so vi tn hiu x1, x4, th hin hnh v dc xung x2 ln hn, iu lm cho t ca xung hazard tng theo, khi xung hazard tr nn "nguy him" hn v n c th kch lt chuyn mt mch in tip sau h thng mch logic, gy hin tng iu khin "sai nhm" trong mch logic.
4.4.3.2. Hazard ng trong mch logic.

Trong thc t khi thay i tn hiu vo ca mch logic ng vi qu trnh chuyn i (QP) c th c rt nhiu tn hiu vo cng thay i khi c s chy ua ca cc tn hiu vo ti u ra ca mch. V d trng hp Q = (0000); P = (1101), d dng nhn thy c s chy ua (X) t0 t'0 t0 t1
"

0 0 1 1

0 1 1 1

0 0 0 0

0 0 0 1

f(Q) = 1 f(X') = 0 f(X") = 1 f(P) = 0

Hazard ng t c kh nng gy ra iu khin "sai nhm" trong mch logic t hp.

Do c nhiu tn hiu vo ng thi thay i gi tr logic t 0 sang 1 v t 1 v 0 m mi tn hiu vo c tc "chy" khc nhau nn v tnh lm cho gi tr hm f(X) u ra thay i nh hnh bn. Hin tng tn hiu ra f(X) thay i gi tr t 1010 c gi l hazard ng, tc l xut hin nhiu xung khng cn thit trong khong thi gian tr ca mch (). Nh vy trong thi gian rt nh xut hin rt nhiu xung hazard nh hn th ta c th hiu l xung hazard ng khng c g nguy him c, v mt xung b chia ra nhiu xung con th nng lng cn rt nh v rng xung qu b nn khng kch mch khc c. Hin tng ny ta c th hiu l khi n dang sng ta cho tn hiu thay i n tt nhng do c hin tng chy ua nn sau khi n tt th li hi sng ln ri mi tt hn.

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(X) 0 f(x) Q 0

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Hnh 4-7. Hazard ng

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(x1 x2

x3

x4)

Chng 4: Mch logic t hp

4.4.3.3. Hazard hm s trong mch logic.

Hazard c th xut hin do chc nng ca mch trong c hai trng hp l hm f(X) ly gi tr logic l 0 hoc 1. Hazard nht thi gi l hazard hm s trong thi gian chuyn i t QP nu: - f(Q)=f(P) - Hm f(X) ly c hai gi tr 1 v 0 trong thi gian chuyn i t QP iu ny c ngha l trong thi gian chuyn i QP th hm logic khng thay i gi tr (f(Q)=f(P)), nhng nu ly f(Q)=f(P) = 0 th th hazard vn xut hin hoc ly f(Q)=f(P)=1 th hazard vn xy ra. Hin tng ny c gi l hazard hm s. Trn thc t c nhng hm s hazard nht thi ch xut hin khi iu khin logic l 1 (f(X) = 1) cn iu khin logic u ra l 0 th khng c hazard nht thi xut hin v ngc li c th iu khin ra khng b hazard. nguy him ca hazard hm s cng ging nh hazard tnh, nhng n nguy him hn mt mc na v bt k qu trnh iu khin no (0 hay 1) u c kh nng xut hin hazard, tc l iu c kh nng gy ra "sai nhm" khi iu khin mch.
4.4.3.4. Hazard logic trong mch logic.

Bn cht ca loi hazard ny nh sau:

(X) t0 t0
" '

(x1 0

.4
x2 0 x3 0 1 1 1 1 0 0 0 0 x4 0 0 0 1 1 1 0 0 1

te
x5)
0

Khi tp tn hiu vo ca hm logic thay i ng thi nhiu bin trong thi gian chuyn i Q P, m mi mt ln tn hiu vo c thi gian tr khc nhau, trong qu trnh "chy ua" ny gp phi trng hp Q = (00000), P = (11101) f(Q) = 1 0 0 1 1 f(X') = 0 f(X") = 0 f(X"') = 0 f(P) = 1

56

t0

t"'0 t1

ch

y l loi hazard nguy him nht, hay gy ra iu khin "sai nhm" nhiu nht trong cc h thng mch t hp iu khin.

.c

om .v

Chng 4: Mch logic t hp Hin tng hazard logic c m t trn hnh 4-8: Hazard nht thi gi l hazard logic trong thi gian chuyn i t QP nu: - f(Q)=f(P) - Hm f(X) ch nhn mt gi tr nh nhau (hoc 0 hoc 1) - Trong thi gian chuyn i t QP xut hin mt xung hazard c rng t ln u ra, khi qu trnh chy ua ngu nhin ca cc tn hiu vo to ra hm f(X) c cng mt gi tr logic.
0 0 f(x) Q t t t0 t'0 t"0 t"'0 t1 P

(X)

Tm li, mi mt mch iu khin c th xut hin nhiu loi hazard, c mch logic c s lng bin s "chy ua" rt ln nhng hazard li khng xut hin, nhng c mch rt n gin th hazard li xut hin v gy ra iu khin "sai nhm". V vy mun khc phc c hazard th phi cn c vo mch in c th ca n, ri dng k thut phn tch pht hin kh nng xut hin hazard, sau tm cch khc phc hazard. Sau y l mt vi bin php khc phc v hn ch s xut hin hazard trong h thng logic diu khin.

4.4.4. Cc bin php khc phc Hazard.

Trn thc t qu trnh chuyn i t Q P trong mch logic t hp rt phc tp, rt t khi gp tng loi hazard ring bit m gp s t hp hn lon cc loi hazard trn. Hin tng ny c minh ho bng hnh 4-9.

te

Nh vy trong qu trnh chuyn i t Q P ca tp tn hiu vo, c nhiu tn hiu cng thay i gi tr v hm logic v tnh hay ngu nhin xy ra trng hp c cng mt gi tr logic hazard u ra f(X) ca mch. iu to nn mt xung hazard u ra ca ca mch rng t ln ln rt nhiu, khi t ln lm cho xung (X) hazard c nng lng ln kh nng kch chuyn mt mch tip theo sau mch iu khin, iu gy ra hin tng iu khin t "sai nhm" trong h thng logic t hp. y 0 l iu v cng nguy him i vi cc h Q P f(x) thng t hp c ln c nhiu u vo.

ch

.c

om .v
0 t0 t1 x1 2 1 x2 x3 1 2

Hnh 4-8. Hazard logic

n
t 3 Hnh 4-10. Phng php khc phc Hazard

.4

Hnh 4-9. Hin tng tng qut xut hin Hazard

Nh phn tch trn, hazard xut hin do c s chy ua tn hiu vo trong h logic t hp, ni cch khc hazard xut hin l do s khc nhau v thi gian tr truyn lan t u vo n u ra ca mch, t ta c nhng bin php khc phc hazard nh sau:

57

Chng 4: Mch logic t hp - Bin php n gin nht lm bin mt hazard l khng xut hin qu trnh chy ua ca cc tn hiu vo trong mch logic, ngha l ch thay i gi tr logic trn mt u vo tn hiu. Khi ch c mt tn hiu vo "chy" trong mch logic th s khng cn "ua" tn hiu na v chc chn hazard khng th xut hin. Nhng nh vy cng c ngha l tng tn hiu vo thay i gi tr logic s lm cho mch hot ng chm chp, v khng phi qu trnh iu khin no cng cho php lm nh vy, thng thng c s thay i nhiu tn hiu vo cng mt lc. - Tip theo khi phi chp nhn qu trnh chuyn i t QP c nhiu tn hiu thay i hay c nhiu bin (X) chy ua. Cch khc phc l chn gi tr linh kin hay IC c thi gian tr nh. V ta bit hazard ch xut hin trong thi gian tr ca mch, cng nh ngha l xung hazard c rng t nh, v nh vy n khng c nng lng kch chuyn mch tip theo.Nhng khi chn linh kin lp rp h thng hay chon IC c nh tc l phi chn linh kin, IC c cht lng cao, ngha l gi thnh ca h iu hnh tng, y cng l vn cn quan tm khi thit mch. - Khi ta chp nhn c s chy ua tn hiu vo (X) trong qu trnh chuyn i t QP, ng thi khng dng linh kin c cht lng cao gim gi thnh v mch vn hot ng tt ng thi khng c hazard xut hin, th ta c th dng phng php khc phc hazard bng cch thm cc mch tr trn ng truyn tn hiu, m bo cho thi gian chy ua ca cc tn hiu l tng ng nhau. Phng php ny c minh ho hnh 4-10: Ta bit tn hiu x2 chy nhanh ti u ra, nn trn ng truyn ca x2 ta cho thm hai cng o c thi gian tr l 1 v 2 cho tn hiu trn x2 xut hin ng thi vi x1 v x3, khi hazard s khng xut hin hoc s lm gim bt hazard . Phng php ny c gy ra hazard nu ng tr thm vo li lm cho x2 chy qu chm v li pht sinh hin tng chy ua tn hiu vo. trnh xy ra hin tng chy ua tn hiu vo, cn bit chnh xc thi gian tr 1 v 2, sau phi to ra c cng o c thi gian tr bng ng gi tr 1 v 2. - mc cao hn khi ta phi chp nhn c s chy ua tn hiu vo trong qu trnh chuyn i Q P, khng mun dng linh kin c cht lng cao, ng thi thm cc mch tr (khng nh hng ti chc nng ca mch logic) nhng vn khng th khc phc ht hazard th khi ta dng xung ng b, tc l ta bt chp c s chy ua ca tn hiu vo, v gia cc ng truyn tn hiu t u vo ti u ra c thi gian tr khc nhau. Nhng tn hiu truyn lan trong h logic d nhanh, d chm, n trc hay n sau th chng ch c lan truyn khi c s cho php ca xung ng b. Xung ng b thng thng "ch" theo ng tn hiu chy chm nht, khi cc xung n sm phi "ch" cho y cc tn hiu khc khi xung ng b mi cho php truyn tip. Nu cho thm vo mch iu khin xung ng b th cng c th gim ng k nh hng ca hazard. - Trong trng hp cc phng php nu trn u c p dng nhng hin tng hazard vn xut hin th ta buc phi thay i chc nng iu khin, tc l thay i chc nng ca hm logic ca h thng iu khin tc l phi xy dng mch in khc. Nh vy c c mt mch iu khin tt, cht lng cao th phn cng xy dng nn mch in mang tnh quyt nh. Ngi thit k phi hiu rt k v su sc h thng k thut m mnh thit k th mi c th khc phc c hazard trong mch in, cng nh phi bit thm hay bt cc mch in ph nh th no m khng lm thay i chc nng ca h thng. T lm 58

.4

te

ch

.c

om .v

Chng 4: Mch logic t hp cho mch c cht lng cao hn, gi tr kinh t cng cao hn. iu ny cung d hiu l cc mch in c cng chc nng iu khin nhng mi hng sn xut li a ra mt mch khc nhau v gi tr kinh t ca chng cng khc nhau, tu thuc vo trnh v s quan tm n vic tng tin cy, tng cht lng iu khin mch ca hng. Nhng bn cht vn ch l lm gim ti a kh nng xut hin hazard trong mch.

4.5. MCH M HO V GII M

4.5.1. Mt s loi m thng dng. 4.5.1.1. M BCD v m d 3.

4.5.1.2. M Gray.

M Gray cn c gi l m cch 1, l loi m m cc t hp m k nhau ch khc nhau duy nht 1 bit. Loi m ny khng c tnh trng s. Do , gi tr thp phn c m ha ch c gii m thng qua bng m m khng th tnh theo tng trng s nh i vi m BCD. M Gray c th c t chc theo nhiu bit. Bi vy, c th m theo m Gray. Cng tng t nh m BCD, ngoi m Gray chnh cn c m Gray d-3.

.4

te

Thp phn BCD 8421 M d 3 0011 0000 0 0100 0001 1 0101 0010 2 0110 0011 3 0111 0100 4 1000 0101 5 1001 0110 6 1010 0111 7 1011 1000 8 1100 1001 9 Bng 4-2. M BCD 8421 v m d 3

ch

V vy, ngi ta s dng m D-3 c hnh thnh t m NBCD bng cch cng thm 3 vo mi t hp m. Nh vy, m khng bao gm t hp ton Zero. M D-3 ch yu c dng truyn dn tn hiu m khng dng cho vic tnh ton trc tip.

.c

Do trng s nh phn ca mi v tr biu din thp phn l t nhin nn my c th thc hin trc tip cc php tnh cng, tr, nhn, chia theo m NBCD. Tuy nhin nhc im chnh ca m l tn ti t hp ton Zero, gy kh khn trong vic ng b khi truyn dn tn hiu.

om .v

M BCD (Binary Coded Decimal) l m c cu to bng cch dng t nh phn 4 bit m ha 10 k hiu thp phn, nhng cch biu din vn theo thp phn. V d i vi m NBCD, cc ch s thp phn c nh phn ho theo trng s nh nhau 23, 22, 21, 20 nn c 6 t hp d, ng vi cc s thp phn 10,11,12,13,14 v 15. S xut hin cc t hp ny trong bn tin c gi l li d.

59

Chng 4: Mch logic t hp

Thp phn

Gray

Gray d 3

4.5.2. Mch m ho.

m.
4.5.1.1. Mch m ho t thp phn sang BCD 8421

S khi tng qut ca mch M ho nh hnh 4-7. Mch gm 9 li vo (bin) ng Vi cc ch s thp phn t 1 n 9. Li vo zero l khng cn thit, v khi tt c cc li vo khc bng 0 th li ra cng bng 0. Bn li ra A, B, C, D (hm) th hin t hp m tng ng vi mi ch s thp phn trn li vo theo trng s 8421. Bng trng thi ca mch nh bng 4-5. 60

BCD 8421 BCD 8421chn BCD 8421l PC PL 0000 1 0000 0 0000 0001 0 0001 1 0001 0010 0 0010 1 0010 0011 1 0011 0 0011 0100 0 0100 1 0100 0101 1 0101 0 0101 0110 1 0110 0 0110 0111 0 0111 1 0111 1000 0 1000 1 1000 1001 1 1001 0 1001 Bng 4-4. M BCD 8421 chn / l

Mch in thc hin vic chuyn tin tc sang m, c gi l mch m ho hay mch ghi

.4

te

ch

M chn v m l l hai loi m c kh nng pht hin li hay dng nht. thit lp loi m ny ta ch cn thm mt bit chn/ l (bit parity) vo t hp m cho, nu tng s bit 1 trong t m (bit tin tc + bit chn/l) l chn th ta c m chn v ngc li ta c m l.

.c

4.5.1.3. M chn, l.

om .v

0010 0000 0 0110 0001 1 0111 0011 2 0101 0010 3 0100 0110 4 1100 0111 5 1101 0101 6 1111 0100 7 1110 1100 8 1010 1101 9 1011 1111 10 1001 1110 11 1000 1010 12 0000 1011 13 0001 1001 14 0011 1000 15 Bng 4-3. M Gray v Gray d 3

Chng 4: Mch logic t hp

Vo thp phn 0 1 2 3 4 5 6 7 8 9 Ra BCD 8 4 2 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1

Vo Thp phn

1 2 3 4 Mch 5 m ho 6 7 8 9

A 8 B 4 C 2 D 1 Ra BCD 8421

T bng trng thi ta vit c cc hm ra nh sau: A = 8 +9 B=4+5+6+7 = (8,9) = ( 4,5,6,7)

om .v
R4 R3 R2

n
+5V R1

Hnh 4-11 S khi ca mch m ho

Bng 4-5. Bng trng thi ca mch m ho.

D = 1 + 3 + 5 + 7 + 9 = (1,3,5,7,9)

Cn c h phng trnh, ta xy dng c mch in ca b m ho. Hoc dng ma trn diode (cng OR) xy dng

ch

.4

Hoc c th c vit li nh sau (dng nh l DeMorgan) v dng ma trn diode (cng AND) xy dng mch:

te

B = 4+5+ 6+ 7 = 4 . 5 . 6 . 7

A = 8+9 = 8 . 9

.c
3 5 6 7 8 9 4

C = 2 + 3 + 6 + 7 = (2,3,6,7)

4.5.1.2. Mch m ho u tin

Trong b m ho va xt trn, tn hiu vo tn ti c lp, (khng c trng hp c 2 t hp tr ln ng thi tc ng). B m ho u tin ra i gii quyt trng hp c nhiu u vo tc ng ng thi. i vi cc trng hp ny th b m ho u tin ch tin hnh m ho tn hiu vo no c cp u tin cao nht thi im xt. Vic xc nh cp u tin cho mi tn hiu vo l do ngi thit k mch. By gi ta xt nguyn tc hot ng v qu trnh thit k ca b m ho u tin 9 li vo, 4 li ra.

C = 2 + 3+ 6 + 7 = 2 . 3 . 6 . 7 D = 1+ 3 + 5 + 7 + 9 = 1 . 3 . 5 . 7 . 9

Hnh 4-12 Mch in ca b m ho dng diode.

61

Chng 4: Mch logic t hp

Theo bi, s m ho thc hin theo mc u tin t L1 n L9, khi cc tn hiu cng tc ng th cc tn hiu c mc u tin thp khng tc dng, ngha l bt k mc logic ca n l 0 hay 1 u khng nh hng n li ra nn gi n l iu kin tu chn, k hiu l "x".

T bng trng thi ta c th vit c biu thc li ra nh sau: D = 1 ti cc li: + L1 v bng 0 ti cc li L2, L4, L6, L8 + L3 v bng 0 ti cc li L4, L6, L8

+ L7 v bng 0 ti cc li L8

Nn ta vit c hm D:

D = L1. L 2 . L 4 . L 6 . L 8 + L 3 . L 4 . L 6 . L 8 + L 5 . L 4 . L 6 . L 8 + L 7 . L 8 + L 9 Tng t nh vy ta vit c hm ca B, C v A nh sau:

Mt vi IC thng dng: 74147 l b m ho u tin NBCD 4 bit, 74148 l b m ho u tin NBCD 3 bit.
4.5.2. B gii m.

62

C = L 2 . L 4 . L 5 . L8 . L 9 + L 3 . L 4 . L 5 . L8 . L 9 + L 6 . L8 . L 9 + L 7 . L8 . L 9 B = L 4 . L8 . L 9 + L 5 . L8 . L 9 + L 6 . L8 . L 9 + L 7 . L8 . L 9 A = L 8 .L 9

Mch in thc hin vic chuyn t m sang tin tc c gi l mch gii m ho.

.4
+ L9

te

+ L5 v bng 0 ti cc li L6, L8

ch

.c

Bng trng thi phn nh yu cu thit k, m ho theo cp u tin.

om .v

Vo Ra Thp phn A B C D L1L2L3L4L5L6L7L8L9 8 4 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 x 1 0 0 0 0 0 0 0 0 0 1 1 x x 1 0 0 0 0 0 0 0 1 0 0 x x x 1 0 0 0 0 0 0 1 0 1 x x x x 1 0 0 0 0 0 1 1 0 xx x x x 1 0 0 0 0 1 1 1 x x x x x x 1 0 0 1 0 0 0 x x x x x x x 1 0 1 0 0 1 x x x x x x x x 1 Bng 4-6. Bng trng thi ca b m ho u tin

Chng 4: Mch logic t hp

4.5.2.1. B gii m nh phn

B gii m nh phn cn c tn l b gii m "1 t n", b gii m a ch hoc b chn a ch nh phn. Chc nng ca n l la chn duy nht mt li ra (ly gi tr 1 hoc 0), khi tc ng ti u vo mt s nh phn. Nh vy, nu s nh phn l n bit (n li vo) s nhn din c 2n a ch khc nhau (trn 2n li ra). Ni khc i, mch chn a ch nh phn l mt mch logic t hp c n li vo v 2n li ra, nu tc ng ti u vo mt s nh phn th ch duy nht mt li ra c la chn, ly gi tr 1 (tch cc cao) hoc 0 (tch cc thp), cc li ra cn li u khng c la chn, ly gi tr 0 hoc 1. S khi tng qut ca b chn a ch nh phn nh ch hnh 4-13.
A0 A1 An-1 D0 D1

B gii m nh phn

om .v
74154
Vo A A0 A1 A2 A3

Hnh 4-13. S khi ca b gii m nh phn D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12

ch

Ta c th m rng dung lng b chn a ch nh phn bng cch ghp cc IC c dung lng nh li vi nhau.

.c

IC 74154 l mt b chn a ch nh phn 4 vo 16 ra. K hiu logic ca n c ch ra hnh 4-14. Cc li vo E1, E2, hot ng theo tch cc thp thng c s dng m rng dung lng hoc thay i chc nng logic ca b chn a ch.

n
Vo iu khin a f e g d D C B A

D2n- 1

Li ra

E1 E2

te

4.5.2.2. Mch gii m 7 on a) Dng c 7 on

hin th ch s ca mt h m phn bt k, ta c th dng dng c 7 on. Cu to ca n nh ch hnh 4-15. Cc on c hnh thnh bng nhiu loi vt liu khc nhau, nhng phi c kh nng hin th c trong cc iu kin nh sng khc nhau v tc chuyn mch phi ln. Trong k thut s, cc on thng c dng l LED hoc tinh th lng (LCD).

.4

Hnh 4-14. K hiu logic ca IC 74154

b c

i vi LED, mi on l mt Diode pht quang v khi c dng in i qua ln (5 n 30 mA) th on tng ng s sng. Ngoi 7 on sng chnh, mi LED cng c thm Diode hin th du phn s khi cn thit. LED c hai loi chnh: LED Ant chung v Ktt chung. Do , logic ca tn hiu iu khin hai loi ny l ngc nhau.

Hnh 4-15 Cu to dng c 7 on sng

a b c d e f g

b) Mch gii m 7 on

1 gii m 2 7 on 4 8

Mch

Nhim v ca ta l phi thit k mt mch logic lin hp vi 4 li vo v 7 li ra chuyn m NBCD thnh m 7 on. S khi tng qut ca b gii m nh hnh 4-16. T hnh 4-15 d

Hnh 4-16 S khi ca mch gii m 7 on sng

63

Chng 4: Mch logic t hp nhn thy rng, on a s sng khi hin th ch s : 0 hoc 2, hoc 3, hoc 5, hoc 7, hoc 8, hoc 9. Do , ta c th vit: a = (0,2,3,5,6,7,8,9). Tng t, ta c: b = (0,1,2,3,4,7,8,9), c = (0,1,3,4,5,6,7,8,9), d = (0,2,3,5,6,8,9), e = (0,2,6,8),

IC 7447, 74247 (Ant chung), 7448 (K chung ), 4511 (CMOS) l cc IC gii m t NBCD sang thp phn theo phng php hin th 7 on.

4.6 B HP KNH V PHN KNH

4.6.1 B hp knh (MUX-Multiplexer)

nh ngha: B hp knh l mch c 2n li vo d liu, n li vo iu khin, 1 li vo chn mch v 1 li ra.

Tu theo gi tr ca n li vo iu khin m li ra s bng mt trong nhng gi tr li vo (Xj). Nu gi tr thp phn ca n li vo iu khin bng j th Y = Xj.

Phng trnh tn hiu ra l:

Y = X 0 (A n 1 A n 2 ...A i ...A 0 ) + X1 (A n 1 A n 2 ...A i ...A 0 )

+ ... + X 2n 1 (A n 1A n 2 ...A i ...A1A 0 )

En

X0 X1 Xj

.4
MUX 2n 1

te
Y- Li ra

S khi ca MUX 2n 1 (2n li vo, 1 li ra) c biu din hnh 4-17a.

ch
X0 X1 Xj X2n-1

.c

X2n-1

An-1 An-2 A0 n li vo iu khin (a) S khi

(b). MUX l mt chuyn mch in t

Hnh 4-17. B hp knh MUX 2n 1

64

om .v
Y

g = (2,3,4,5,6,8,9).

f = (0,4,5,6,8,9),

Chng 4: Mch logic t hp Thc cht, MUX l chuyn mch in t dng cc tn hiu iu khin (An-1An-2A0) iu khin s ni mch ca li ra vi 1 trong s 2n li vo (hnh 4-17b). Hin nay, b MUX c dng nh mt phn t vn nng xy dng nhng mch t hp khc. IC 74151 l b MUX 8 li vo d liu - 1 li ra. Hnh 4-18 l k hiu logic ca IC 74151.
4.6.2 B phn knh (DEMUX-DeMultiplexer) nh ngha: B phn knh l mch c 1 li vo d liu, n li vo iu khin, 1 li vo chn mch v 2n li ra.
A0 A1 A2 D0

74151
Vo iu khin Vo d liu

S khi ca b DEMUX 1 li vo 2n li ra c biu din hnh 4-19.

.c
X Li vo A0 A1 A2 D

om .v
E1 E2 E1 E2

Tu theo gi tr ca n li vo iu khin m li ra th i (Yi) s bng gi tr ca li vo. C th nu gi n li vo iu khin l An-1An-2A0 th Yi = X khi (An-1An-2A1A0)2 = (i)10.

En Chn mch Li vo X

ch
Yj Y2n-1

MUX 2n 1

Y0 Y1

te

Phng trnh tn hiu ra ca DEMUX 1 2n :

.4

(b). DEMUX l mt chuyn mch in t

An-1 An-2 A0 n li vo iu khin (a) S khi

Hnh 4-19. B phn knh DEMUX 1 2n

Y0 = X.A n 1 A n 2 ...A i ...A 0 Y1 = X.A n 1 A n 2 ...A i ...A1A 0

n
D7 Vo cho php Hnh 4-18. K hiu logic ca IC 74151 Y0 Y1 Yj Y2n-1

74138
Vo iu khin Vo d liu Y0

.............. Y2n 1 = X.A n 1.A n 2 ...A i ...A 0

B phn knh cn c gi l b gii m 1 trong 2n. Ti mt thi im ch c 1 trong s 2n li ra mc tch cc. IC 74138 l b DEMUX 1 li vo d liu - 8 li ra. Hnh 420 l k hiu logic ca IC 74138.

Y7

Vo cho php

Hnh 4-20. K hiu logic ca IC 74138

65

Chng 4: Mch logic t hp

4.7. MCH CNG.

4.7.1. Mch ton tng.

Mch cng hay (b cng) l mch s hc nh phn quan trng, v trong x l nh phn phn ln cc php tnh c thc hin thng qua php cng. Mch logic thc hin php cng hai s nh phn 1 bit c li nh u vo c gi l mch ton tng. S khi tng qut ca mt mch ton tng c biu din hnh 4-21. Theo hnh 4-21 v nguyn l cng hai s nh phn mt bit c trng s bt k, ta c th lp bng trng thi cho mch ton tng. Cc hm ra Si , Ci s c dng: Si = ai bi Ci-1
C i = a i b i C i1 + a i b i C i1 + a i b i C i 1
Ci-1 0 0 0 0 1 1 1 1

om .v
ai 0 0 1 1 0 0 1 1 bi 0 1 0 1 0 1 0 1 Si Pi TT Ci Gi ai bi Ci-1 B ton tng CV2 CR1 CV1 CR0 B ton tng b1 a1 b0 a0

hay

Ci = aibi + (ai bi) Ci - 1

Ci-1 ai bi Si

.c
G i Pi a) Mch in

.4

4.7.2 Mch cng nh phn song song

Ta c th ghp nhiu b cng hai s nh mt bit li vi nhau thc hin php cng hai s nh phn nhiu bit. S khi ca b cng c trnh by hnh 4-22 v c gi l b cng song song. S0 Si S2 S1
B ton tng CRi CVi B ton tng

Mch logic thc hin biu thc li ra tng v li ra nh c trnh by hnh 4-21a v k hiu ca n l hnh 4-21b.

te

ch
CR2 b2 a2

Ci

Bng 4-7. Bng trng thi ca mch ton tng.

b) K hiu Hnh 4-21 a, b Mch ton tng v k hiu

bi

ai

Hnh 4-22 S khi ca b cng nh phn song song

66

n
Si 0 1 1 0 1 0 0 1 Ci 0 0 0 1 0 1 1 1 CV0

Chng 4: Mch logic t hp gim bt mc phc tp ca mch, trong thc t ngi ta thng sn xut b tng 4 bit. Mun cng nhiu bit, c th hp ni tip mt vi b tng mt bit theo phng php nu trn. Mt trong nhng b cng thng dng hin nay l 7483. IC ny c sn xut theo hai loi: 7483 v 7483A vi logic vo, ra khc nhau.

4.8. MCH SO SNH.

Trong cc h thng s, c bit l trong my tnh, thng thc hin vic so snh hai s. Hai s cn so snh c th l cc s nh phn, c th l cc k t m ho nh phn. Mch so snh c th hot ng theo kiu ni tip hoc theo kiu song song. Trong phn ny ta s nghin cu b so snh theo kiu song song.

4.8.1.1. B so snh bng nhau 1 bit.

Xt 2 bit ai v bi, gi gi l kt qu so snh. T l c bng trng thi 4-8.

gi = a i . bi + a i . bi = a i bi

om .v
ai 0 0 1 1 bi 0 1 0 1

4.8.1. B so snh bng nhau.

4.8.1.2. B so snh bng nhau 4 bit.

So snh hai s nh phn 4 bit A = a3a2a1a0 vi B = b3b2b1b0. Vy hai s A v B bng nhau khi a3 = b3, a2 = b2, a1 = b1, a0 = b0. Biu thc u ra tng ng l:

4.8.2. B so snh. 4.8.2.1. B so snh 1 bit.

f < = a i . bi

G = g3. g2. g1. g0

vi

g3 = a 3 b3 g2 = a 2 b2 g1 = a 1 b1 g0 = a 0 b0

.4

te

Hnh 4-23. S logic hm ra ca b so snh bng 1 bit

ch
f = = a i bi f > = a i . bi

ai bi

.c
gi

Bng 4-8. Bng trng thi ca mch so snh bng.

T bng trng thi 4-9 ta c biu thc ra:

n
gi 1 0 0 1

67

Chng 4: Mch logic t hp

ai bi ai 0 0 1 1 bi 0 1 0 1 f< 0 1 0 0 f= 1 0 0 1 f> 0 0 1 0

f< f= f>

Bng 4-9. Bng trng thi ca mch so snh.

4.8.2.2. B so snh 4 bit (So snh ln hn).

Hnh 4-24. Mch in ca b so snh 1 bit

a3 > b3 hoc a3 = b3 v a2 > b2 hoc a3 = b3 v a2 = b2 v a1 > b1 hoc a3 = b3 v a2 = b2 v a1 = b1 v a0 >b0. T ta c biu thc hm ra l:

f > = a 3 . b 3 + a 3 b 3 . a 2 . b 2 + a 3 b3 . a 2 b 2 . a1 . b1 + a 3 b 3 . a 2 b 2 . a1 b1 . a 0 . b 0
a3 b3

.4

te
f> Hnh 4-26. Mch in ca b so snh ln hn 4 bit

a2 b2

a1 b1 a0 b0

bit.

4.9. MCH TO V KIM TRA CHN L.

C nhiu phng php m ho d liu pht hin li v sa li khi truyn d liu t ni ny sang ni khc. Phng php n gin nht l thm mt bit vo d liu c truyn i sao cho s ch s 1 trong d liu lun l chn hoc l. Bit thm vo c gi l bit chn/l. thc hin c vic truyn d liu theo kiu a thm bit chn, l vo d liu chng ta phi: Xy dng s to c bit chn, l thm vo n bit d liu.

68

Mt trong nhng b so snh thng dng hin nay l 7485. IC ny so snh 2 s nh phn 4

ch

.c

om .v

So snh hai s nh phn 4 bit A = a3a2a1a0 vi B = b3b2b1b0. S A ln hn s B khi:

Chng 4: Mch logic t hp Xy dng s kim tra h xem l h chn hay l vi (n + 1) bit u vo (n bit d liu, 1 bit chn/l).

4.9.1. Mch to bit chn/l.

Gi 3 bit ca d liu l d1, d2, d3 v Xe, Xo l 2 bit chn, l thm vo d liu. T lp c bng trng thi 4-10:
d1 0 0 0 0 1 1 1 1 Vo d2 0 0 1 1 0 0 1 1 d3 0 1 0 1 0 1 0 1 Ra Xe Xo 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 n bit d liu

To bit chn/l

Xo Xe

Bng 4-10. Bng trng thi ca mch to bit chn l

V biu thc ca Xo v Xe l Xo = d1 d2 d3

X o = X e = d1 d 2 d 3
4.9.2. Mch kim tra chn/l.

te
Kim tra h chn/l

n bit d liu Bit chn l (Xo, Xe)

.4
Fe 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 Ra Fo 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

d1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Vo d2 d3 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Bng trng thi ca mch kim tra tnh chn/l ca h c cho bng 4-11. T bng trng thi ta thy: Fe = 1 nu h l chn (Fe ch ra tnh chn ca h). Fo = 1 nu h l l (Fo ch ra tnh l ca h).

Hai hm ny lun l ph nh ca nhau. Mt khc do tnh cht ca hm cng XOR, ta c: Fo = d1 d2 d3 X

ch
Fo Fe

Fo = Fe
69

Bng 4-11. Bng trng thi ca mch kim tra chn /l

.c
Hnh 4-28. S khi ca mch kim tra chn/l

T bng trng thi ta thy X o = X e hay X e = X o .

om .v

Hnh 4-27. S khi ca mch to bit chn/l

Chng 4: Mch logic t hp

4.10. N V S HC V LOGIC (ALU).

n v s hc v logic (Arithmetic Logic Unit) l mt thnh phn c bn khng th thiu c trong cc my tnh. N bao gm 2 khi chnh l khi logic v khi s hc v mt khi ghp knh. Khi logic: Thc hin cc php tnh logic nh l AND, OR, NOT, XOR. Khi s hc: Thc hin cc php tnh s hc nh l: cng, tr, tng 1, gim 1.

Thanh ghi A

TM TT

Mch t hp rt phong ph, ta khng th xem xt ht trong chng 4. Trng tm ca chng ta l nm vng c im mch t hp v phng php chung khi thit k, phn tch mch t hp. V vy, chng ta gii thiu mt cch chn lc b m ho, b gii m, b hp knh, phn knh, mch cng, tr, mch so snhtrong qu trnh , ta xem xt phng php phn tch v thit k mch t hp. Khi phn tch mch t hp cho, ta c th vit ra hm logic u ra cho tng cp ca s , ri tin hnh ti thiu ho hm logic biu th r mi quan h gia u ra vi u vo. Cn lu thm rng phi xem xt n hin tng Hazard- l hin tng chy ua trong mch logic v cch khc phc hin tng ny.

70

Trong chng ny, chng ta gii thiu mch logic t hp. Mch t hp do cc phn t logic c bn cu trc nn. c im ca mch t hp l tn hiu u ra thi im bt k no cng ch ph thuc vo tn hiu u vo thi im m khng lin quan n trng thi vn c ca mch.

.4

te

4 4 M l li vo chn Cin php tnh s hc hay logic. M (Mode) ALU F0, F1 l hai li vo chn F0 Chn chc nng chc nng. Sau khi mt F1 (Php tnh) php tnh s hc hay logic 4 4 c thc hin th kt qu Ghi trng thi s c ghi ln 1 thanh ghi, v d thanh ghi A. Kt qu ny c th c s dng Hnh 4-29. S khi ca ALU 4 bit thc hin php tnh sau. B ALU cn to ra cc bit trng thi chuyn i thanh ghi. V d: Carry out: nu c nh; Zero: nu kt qu php tnh bng 0.

ch

.c

om .v
Thanh ghi B

S khi ca 1 n v s hc logic ALU 4 bit c m t hnh 4-29:

Chng 4: Mch logic t hp Vic ti thiu ho hm logic rt quan trng. V vic ny lm cho mch logic n gin, kinh t. Chng ta mong mun mch in cng t linh kin cng tt, s u vo ca mch cng cng khng th qu nhiu

CU HI N TP
1. Mch logic t hp l mch: a. C tn hiu u ra ch ph thuc vo tn hiu u vo ca mch ti thi im ang xt. b. Khng nhng tn hiu u ra ph thuc vo tn hiu u vo m cn ph thuc vo trng thi trong ca mch ti thi im ang xt.

d. Khng c phng n no ng. 2.

Loi Hazard c trong mch lgic t hp c th l loi:

a. Hazard ch xut hin 1 ln v khng bao gi gp na. b. Hazard c th xut hin nhiu ln.

c. Hazard c th do chc nng ca mch in gy ra.

3.

Loi Hazard no trong mch logic t hp l loi nguy him nht? a. Hazard tnh. b. Hazard ng.

d. Khng c phng n no ng.

5.

6.

4.

B m ho u tin l b m ho cho php m ho khi:

a. Ch c mt tn hiu tc ng vo. b. Ch hai tn hiu tc ng vo. c. C hai tn hiu tr ln ng thi tc ng vo.

d. C 3 phng n trn u ng. B gii m BCD sang thp phn lm nhim v bin i: a. u vo nh phn thnh u ra thp lc phn (h hexa). b. u vo thp phn thnh m BCD 8-4-2-1. c. u vo BCD 8-4-2-1 thnh u ra thp phn tng ng. d. Khng c phng n no ng. Dng c hin th 7-on: a. ch c th ch th cc k t t 0 n 9. 71

.4

c. Hazard logic.

te

ch

d. C 3 phng n trn u ng.

.c

om .v

c. C hai phng n trn u ng.

Chng 4: Mch logic t hp b. ch c th ch th cc k t t A n F. c. ch c th ch th cc k t t 0 n 9 v t A n F. d. c th c cu to ch th cc k hiu s, ch ci hoc cc k hiu c bit khc. 7. Dng c hin th 7-on Ant chung: a. c biu din bng mt Ant n bn trong. b. c biu din bng by n LED ring l. c. c biu din bng mt catt n bn trong. d. khng c phng n no ng. 8. B hp knh c kh nng:

a. ni mt li vo mch vi mt li ra trong mt nhm cc li ra.

b. ni ng thi mt li vo mch vi mt hoc nhiu li ra ca mt nhm cc li ra. c. ni mt li vo trong mt nhm cc li vo vi mt li ra.

9.

B phn knh c kh nng:

c. ni mt li vo trong mt nhm cc li vo vi mt li ra.

10.

Mch minh ho trong hnh 4-29 l:

b. cp m ho (a)/ gii m (b). c. cp hp knh (a)/phn knh (b). d. cp phn knh (a)/hp knh (b).

a. cp gii m (a)/ m ha (b).

.4

d. ni ng thi mt hoc nhiu li vo vi mt li ra.

te

b. ni ng thi mt li vo mch vi mt hoc nhiu li ra trong mt nhm cc li ra.

ch
Hnh 4-29.

a. ni mt li vo mch vi mt li ra trong mt nhm cc li ra.

.c
(b)

d. ni ng thi mt hoc nhiu li vo vi mt li ra.

U VO D LIU

(a)

72

om .v

n
U RA D LIU

Chng 4: Mch logic t hp

11.

IC trong hnh 4-29(a) c gi l: a. b hp knh 8 vo - 1 ra. b. b phn knh 8 vo 1 ra. c. b hp knh 1vo 8 ra. d. b phn knh 1vo 8 ra.

12.

IC trong hnh 4-29(b) c gi l:

b. b phn knh 8 vo 1 ra. c. b hp knh 1 vo 8 ra. d. b phn knh 1 vo 8 ra. 13. Thut ng parity (tnh chn l):

a. dng ch kch thc ng d liu ca h thng.

c. lin quan n qu trnh kim tra li. d. dng cho thanh ghi dch. 14.

Nu b to bit chn l nhn mt bit kim tra parity chn, n yu cu nhn: a. d liu parity chn. b. d liu parity l.

c. mt trong hai trng hp trn.

15.

16.

17.

d. Khng phi hai trng hp trn. Khi ghp b cng 2 s nh phn 4 bit c th :

a. Cng thnh cc s 8 bit.

b. Cng thnh cc s 4 bit. c. To ra mt tng 8 bit. d. To ra mt s 8 bit khc. Li ra ca tng tng ca b cng c c l do thc hin cng : a. Tt c 4 bit ca tng s nh phn. b. tng cp bit mt. c. Bit nh. d. 1 vi bit trc . Nu li ra A>B ca b so snh c kch hot, th: 73

.4

te

ch

.c

b. ch c th dng cho cc h thng 8-bit.

om .v

a. b hp knh 8 vo 1 ra.

Chng 4: Mch logic t hp a. Gi tr ca s A ln hn gi tr ca s B. b. C hai s li vo u c gi tr ging nhau. c. Gi tr ca s A nh hn gi tr ca s B. d. Gi tr ca s B ln hn gi tr ca s A. 18. Nu li ra A=B ca b so snh c kch hot, th: a. Gi tr ca s A ln hn gi tr ca s B. b. C hai s li vo u c gi tr ging nhau.

d. Gi tr ca s B ln hn gi tr ca s A. 19. Nu li ra A<B ca b so snh c kch hot, th: a. Gi tr ca s A ln hn gi tr ca s B.

b. C hai s li vo u c gi tr ging nhau. c. Gi tr ca s A nh hn gi tr ca s B.

20.

Mt ALU c cha: a. Mt khi s hc. b. Mt khi logic. c. Mt khi so snh.

d. Mt khi s hc v mt khi logic.

74

.4

te

ch

.c

d. Gi tr ca s B nh hn gi tr ca s A.

om .v

c. Gi tr ca s A nh hn gi tr ca s B.

Chng 5: Mch logic tun t

CHNG 5: MCH LOGIC TUN T

GII THIU.
Chng ta nghin cu v php phn tch v thit k cc mch logic t hp. Mc d rt qua trng nhng n ch l mt phn ca cc h thng k thut s. Mt phn qua trng ca cc h thng k thut s khc l phn tch v thit k mch tun t. Tuy nhin vic thit k cc mch tun t li ph thuc vo vic thit k mch t hp c cp chng 4.

Nhng ng dng ny yu cu u ra khng ch ph thuc vo cc iu kin u vo hin c m cn ph thuc vo lch s ca cc u vo. Lch s c cung cp bng cch phn hi t u ra v li u vo. Mch logic tun t khng nhng ph thuc vo trng thi cc li vo v cn ph thuc vo trng thi trong ca n. Mch tun t c chia lm hai loi chnh l mch tun t khng ng b v mch tun t ng b.

5.1. KHI NIM CHUNG V M HNH TON HC

5.1.1. Khi nim chung

Trong chng ny, chng ta s ni n h thng s c gi l mch logic tun t (hay cn gi l mch dy - Sequential Circuit). Hot ng ca h ny c tnh cht k tip nhau, tc l trng thi hot ng ca mch in khng nhng ph thuc trc tip li vo m cn ph thuc vo trng thi bn trong trc ca chnh n. Ni cch khc cc h thng ny lm vic theo nguyn tc c nh.

.4

te

NI DUNG

ch
x1 x2

Trong phn ny chng ta s gii thiu v cc phn t nh ca mch tun t. Cch phn tch v thit k mch tun t n gin v phc tp.

.c

om .v
Mch t hp Ql Mch nh

C nhiu ng dng m u ra s phi c to ph hp vi tun t nhn c cc tn hiu vo. Yu cu ny khng th c tho mn bng vic s dng h thng logic t hp.

5.1.2. M hnh ton hc

z1 z2 zj W1 Wk

Mch tun t l mch bao gm mch x i logic t hp v mch nh. Mch nh l cc trig. i vi mch tun t, p ng ra ca h thng mch in khng ch ph thuc trc Q1 tip vo tn hiu vo (X) m cn ph thuc vo trng thi ni (Q) ca n. C th m t s khi tng qut ca mch tun t.

Hnh 5-1. S khi ca mch tun t.

75

Chng 5: Mch logic tun t y: X - tp tn hiu vo. Q - tp trng thi trong trc ca mch. W - hm kch. Z - cc hm ra Hot ng ca mch tun t c m t bng mi quan h ton hc sau: Z = f(Q, X) Trong phng trnh ton hc ca mch tun t ta thy c hai thng tin. l thng tin v trng thi tip theo ca mch tun t v thng tin v tn hiu ra ca mch. Hai thng tin ny cng ph thuc ng thi vo trng thi bn trong trc ca mch (Q) v tn hiu tc ng vo (X) ca n. Ta c th vit li biu thc trn nh sau: Z = f (Q(n), X). Q (n +1) = f (Q(n), X) Trong :
k

Q(n +1): l trng thi tip theo ca mch.

5.2.1. Cc loi Trig

nh ngha: Trig l phn t c kh nng lu tr (nh) mt trong hai trng thi 0 v 1.

Trig c t 1 n mt vi li iu khin, c hai li ra lun lun ngc nhau

.4

te
PR Q Cc li vo iu khin Clock TRIG

5.2. PHN T NH CA MCH TUN T

thm cc li vo lp (PRESET) v li vo xo (CLEAR). Ngoi ra, trig cn c li vo ng b (CLOCK). Hnh 5-2 l s khi tng qut ca trig. Phn loi:

l Q v Q . Tu tng loi trig c th c

ch

hiu r hn v mch tun t ta i xt cc phn t c trong mch. Nh ta bit mch logic t hp c xt chng 4. By gi ta s tm hiu v mch nh, m phn t nh chnh l cc trig.

.c

Q(n): l trng thi bn trong trc . tin cho vic nghin cu ta s k hiu Q(n +1) l Q , Q(n) l Q.

CLR Hnh 5-2. S tng qut ca mt Trig

Theo chc nng lm vic ca ca cc li vo iu khin: hin nay thng s dng loi trig 1 li vo nh trig D, T; loi hai li vo nh trig RS, trig JK. Theo phng thc hot ng thi ta c hai loi: trig ng b v trig khng ng b. Trong loi trig ng b li c chia lm hai loi: trig thng v trig chnh - ph (Master- Slave).

S khi ca s phn loi trig c cho hnh 5-3.

76

om .v
Q

Chng 5: Mch logic tun t

TRIG

TRIG D

TRIG T

TRIG RS

TRIG JK

KHNG NG

NG B

Hnh 5-3.

LOI THNG

CHNH - PH

5 2.1.1. Trig RS

Q Clock

a) b) Hnh 5-4. S k hiu ca trig RS

0 0 1 1

0 1 0 1

Q 0 1

te

Qk

ch
Q S Q R S Q Q

Hnh 5-4 l k hiu ca trig RS trong cc s logic (hnh a l s ca trig RS khng ng b, hnh b l s ca trig RS ng b). Hnh 5-5 l s nguyn l ca trig RS v RS ng b. Trng thi u ra ca Q ph thuc vo cc tn hiu logic hai li vo iu khin S, R theo bng trng thi 5-1 v 5-2 : Mod hot ng Nh Xo Lp C 0 1 1 1 1 S x 0 0 1 1 R x 0 1 0 1 Qk Q Q 0 1 x Mod hot ng Nh Nh Xo Lp Cm

Bng 5-1. Bng trng thi ca trig RS

.4
Cm
R

Bng 5-2. Bng trng thi ca trig RS ng b cng NAND

Trong bng, k hiu Qk l gi tr li ra Q thi im k tip, Q l gi tr ti thi im hin ti.

Q

.c

S C R

om .v
S Q >C R
Q

Hnh 5-5. S nguyn l ca trig RS v RS ng b

n
Q

Trig RS l loi c hai li vo iu khin S, R. Chn S gi l li vo "lp" (SET) v R c gi l li vo "xo" (RESET).

77

Chng 5: Mch logic tun t Ta thy khi S = 1, R = 0 th Qk = 1; khi S = 0, R = 1 th Qk = 0. y chnh l hai iu kin iu khin li vo khin cho li ra ca trig c th lt trng thi. S v R l cc li vo iu khin. Trng hp S = 0, R = 0 th Qk = Q, iu ny c ngha l khi khng c tn hiu iu khin th trig vn gi nguyn trng thi vn c ca n. Cui cng khi S = R = 1 th li ra Qk v Q k c gi tr bng nhau (c th l 1, c th l 0) nn ta ni trng thi ca trig l khng xc nh hay gi l trng thi cm. Vy, khng bao gi c s dng trng hp ny.
5 2.1.2. Trig JK

S hot ng ca trig JK c trnh by bng bng trng thi 5-2 C 0 1 Ck Ck Ck Ck J x x 0 0 1 1 K x x 0 1 0 1 Qk Q Q Q 0 1 Mod hot ng

Nh (i vi loi trig JK dng cng NAND)

Nh Xo Lp

J C K

.4

Bng 5-3. Bng trng thi ca trig JK ng b

Q J C Q K Q K Q J C Q Q

5 2.1.3. Trig D
D Q C Q D C Q Q

S nguyn l v s k hiu ca trig JK c trnh by hnh 5-6.

78

Hnh 5-6. S nguyn l v k hiu ca trig JK ng b

Hnh 5-7. S nguyn l v k hiu ca trig D ng b

te
Q

ch
Thay i trng thi theo mi xung nhp

.c

Nh (i vi loi trig JK dng cng NOR)

om .v

Trig JK l loi trig c hai li vo iu khin J, K. Trig ny c u im hn trig RS l khng cn tn ti t hp cm bng cc ng hi tip t Q v chn R v t Q v S. Tuy nhin, im c bit l trig JK cn c thm u vo ng b C. Trig c th lp hay xo trong khong thi gian ng vi sn m hoc sn dng ca xung ng b C. Ta ni, trig RS thuc loi ng b.

Chng 5: Mch logic tun t Trig D l loi trig c mt li vo iu khin D. Tn hiu li vo iu khin s truyn ti li ra Q (Qk = D) mi khi xut hin xung nhp C. Trig D thng c dng lm b ghi dch d liu hay b cht d liu. S nguyn l v s k hiu ca trig D c biu din hnh 5-7.
5 2.1.4. Trig T

Trig T l loi trig c mt li vo iu khin T. Mi khi c xung ti li vo T th li ra Q s thay i trng thi. K

T 0 1 Q Q

Bng 5-3 l bng trng thi ca trig T S nguyn l v k hiu ca trig T c biu din hnh 5-8.
T Qk T

Q Q

Hnh 5-8. S nguyn l v k hiu ca trig T

5 2.1.5. Cc loi trig Chnh- Ph (MS-Master- Slave).

Do cc loi trig ng b trn u hot ng ti sn dng hay sn m ca xung nhp nn khi lm vic tn s cao th li ra Q khng p ng kp vi s thay i ca xung nhp, dn n mch hot ng tnh trng khng c tin cy. Loi trig MS khc phc c nhc im ny. Li ra ca trig MS thay i ti sn dng v sn m ca xung nhp, nn cu trc ca n gm 2 trig ging nhau nhng cc tnh iu khin ca xung Clock th ngc nhau m bo sao cho ti mi sn ca xung s c mt trig hot ng. V nguyn tc hot ng ca loi trig MS (RS-MS, JK-MS, D-MS, T-MS) hon ton ging nh cc loi trig thng thng (RS, JK, D, T).

Cu trc chung ca mt trig MS c minh ho hnh 5-9.

> TRIG
M

.4

Nhn xt: T cc bng trng thi ca cc trig trn ta thy rng: Cc trig D v RS c th lm vic c ch khng ng b v mi tp tn hiu vo iu khin D, RS lun lun tn ti t nht 1 trong 2 trng thi n nh. Trng thi n nh l trng thi tho mn iu kin Qk = Q. Cn trig T v trig JK khng th lm vic c ch khng ng b v mch s ri vo trng thi dao ng nu nh tp tn hiu vo l 11 i vi trig JK hoc l 1 i vi trig T. Nh vy, trig D, trig RS c th lm vic c hai ch : ng b v khng ng b cn trig T v trig JK ch c th lm vic ch ng b.

te

Hnh 5-9. Cu trc ca trig MS

ch
> TRIG
S

.c

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C Q

Bng 5-4. Bng trng thi ca trig T

79

Chng 5: Mch logic tun t

5.2.2. Chuyn i gia cc loi trig.

C 4 loi trig c gii thiu l trig RS, JK, D v T. Trn thc t c khi trig loi ny li c s dng nh trig loi khc. Ni dung phn ny l xy dng cc trig yu cu t cc trig cho trc. Vi 4 loi trig trn th c 12 kh nng chuyn i sang nhau.
D

JK

RS

Hnh 5-10. Cc kh nng chuyn i gia cc loi trig.

Y = f (X, Q)

thc hin chuyn i trig loi Y sang loi X cn thc hin cc bc sau:

Ti thiu ho cc hm ny v xy dng cc s .

Xc nh h hm Y = f (X, Q) theo bng hm kch.

.4
Mch logic t hp

te
Y

Cc li vo X l cc li vo ca trig loi X cn thit k. Li ra ca mch logic l cc li vo ca trig Y cho trc. Nh vy, bi ton chuyn i t trig loi Y sang trig loi X l xy dng mch t hp c cc u vo l X v Q; cc li ra l Y biu din bi h hm:

ch
Trig loi Y

Mt trong cc phng php xy dng trig loi X t loi Y cho trc c cho s khi hnh 5-11.

.c
Q

5.2.2.1. Phng php chuyn i gia cc loi trig.

Bng hm kch ca cc loi trig c cho bng 5-5.

80

om .v
Hnh 5-11. S khi ca trig loi X

Chng 5: Mch logic tun t

Q 0 0 1 1

Qk 0 1 0 1

RS X0 01 10 0X

JK 0X 1X X1 X0

D 0 1 0 1

T 0 1 1 0

Bng 5-5. Bng hm kch ca cc loi trig

V d: Chuyn i t trig RS sang trig JK. Ta cn phi thit k mch logic t hp ca cc hm logic: R = f1 (Q, J, K) S = f2 (Q, J, K)

te
Bng 5-6. Bng tnh S v R
R S

ch

JK Q 0 1

00 0 X

01 0 0 S = JQ

11 1 0

10 1 X

.c
JK Q 0 1 00 X 0
Q

T bng hm kch thch trn ta thu c bng Karnaugh (bng 5-6) cho S v R vi cc bin vo l Q, J, K.
01 X 1 11 0 1 10 0 0

Mch thc hin chuyn i c cho hnh 5-12.

.4
K J

Tng t nh vy ta cng c th lm nh vy i vi cc chuyn i khc.

5.3. PHNG PHP M T MCH TUN T.

Thit b c thit k phi c m t bng li hay mt s hnh thc khc. Cng vic u tin ca ngi thit k l phi phin dch cc d kin thnh 1 hnh thc m t hot ng ca thit b cn phi thit k mt cch trung thc v duy nht. Ni cch khc l phi hnh thc ho dc liu ban u. C hai cch hnh thc ho thng dng l dng bng v hnh trng thi. 81

om .v
R = KQ

Hnh 5-12. Trig JK xy dng t trig RS

Sau y ta xt mt s v d xy dng cc trig t cc trig cho trc thng hay c s dng trong thc t.

Chng 5: Mch logic tun t

5.3.1. Bng 5.3.1.1. Bng chuyn i trng thi.

Bng chuyn i trng thi bao gm cc hng v cc ct, cc hng ghi cc trng thi trong, cc ct ghi cc gi tr ca tn hiu vo. Cc ghi gi tr cc trng thi trong k tip m mch s chuyn n ng vi cc gi tr hng v ct. Bng chuyn i trng thi c m t bng 5-6. Tn hiu vo
V S S1 S2 : : Sn 5.3.1.2. Bng tn hiu ra. V1 V2 . Vn

Bng 5-6. Bng chuyn i trng thi

te

V S

V1

ch
Tn hiu vo
V2

Cc hng ca bng ghi cc trng thi trong, cc ct ghi cc tn hiu vo. Cc ghi gi tr ca tn hiu ra tng ng. Bng tn hiu ra c m t bng 5-7. Tn hiu vo V2 .
Vn

.c
.

C th gp hai bng chuyn i trng thi v bng tn hiu ra thnh mt bng chung gi l bng chuyn i trng thi / ra. Lc trn cc ghi cc gi tr ca trng thi k tip v tn hiu ra (Sk / R) tng ng vi trng thi hin ti v tn hiu vo. Bng chuyn i trng thi v tn hiu ra c m t bng 5-8.

.4

Trng thi trong

S1 S2 : : Sn

Bng 5-7. Bng tn hiu ra

V S 5.3.2. hnh trng thi.

V1

Trng thi trong

82

S1 S2 : : Sn Bng 5-8. Bng chuyn i trng thi v tn hiu ra

om .v
Tn hiu ra - R
Vn

Trng thi trong

Trng thi k tip Qk

Trng thi k tip Sk v Tn hiu ra R

Chng 5: Mch logic tun t hnh trng thi l hnh v phn nh quy lut chuyn i trng thi v tnh trng cc gi tr li vo v li ra tng ng ca mch tun t. hnh trng thi l mt hnh c hng gm hai tp: M - Tp cc nh v K - Tp cc cung c hng.
a). i vi m hnh Mealy thc hin nh x.

Tp cc trng thi trong l tp cc nh M; Tp cc tn hiu vo / ra l tp cc cung K. Trn cung c hng i t trng thi trong Si n trng thi trong Sj ghi tn hiu vo/ra tng ng.
b). i vi m hnh Moore.

V tn hiu ra ch ph thuc vo trng thi trong ca mch m khng ph thuc vo tn hiu vo cho nn thc hin nh x: Tp cc trng thi trong, tn hiu ra l tp cc nh M. Tp cc tn hiu vo l tp cc cung K.

Qu trnh thit k mch tun t c m t theo lu sau

Bi ton ban u: Nhim v thit k c m t bng ngn ng hoc bng lu thut ton. Hnh thc ho: T cc d kin bi cho m ta m t hot ng ca mch bng cch hnh thc ho d kin ban u dng bng trng thi, bng ra hay hnh trng thi. Sau rt gn cc trng thi ca mch c c s trng thi trong t nht.

.c

5.4. CC BC THIT K MCH TUN T.

ch

.4

te

M ho trng thi: M ho tn hiu vo ra, trng thi trong nhn c m nh phn (hoc c th l cc loi m khc) c tp tn hiu vo l X, tp tn hiu ra l Y, tp cc trng thi trong l Q.

H hm ca mch: Xc nh h phng trnh logic ca mch v ti thiu ho cc phng trnh ny. Nu S mch tun t khi thit k cn dng cc trig v mch t hp th tu theo yu cu m ta vit h phng trnh Hnh 5-13. Cc bc thit cho cc li vo kch cho tng loi trig .
k mch tun t

Xy dng s : T h phng trnh ca mch vit c ta xy dng mch in thc hin.

5.4.1. Thit k mch tun t t hnh trng thi. Gi thit: Cho hnh trng thi ca mch c tp tn hiu vo V, tp tn hiu ra R, tp trng thi trong S (cha m ho nh phn).

om .v

n
Bi ton ban u Hnh thc ho M ho trng thi H hm ca mch

83

Chng 5: Mch logic tun t

Xc nh: H phng trnh nh phn ca mch ( ti thiu ho). Trn c s v mch

in.
5.4.1.1. Cc bc thit k

M ho tn hiu vo V, tn hiu ra R, trng thi trong S chuyn thnh mch dng nh phn c cc tp tn hiu vo X, tn hiu ra Y, trng thi trong Q. Xc nh h phng trnh tn hiu ra: Yi = fi (X, Q). Phng trnh ny c xc nh trn cc cung vi m hnh kiu Mealy, trn cc nh vi m hnh kiu Moore. Ti thiu cc hm ny.

i vi trig Qi bt k s thay i trng thi t Qi n Qki ch c th c 4 kh nng nh hnh 5-16.

Qi = 0 0 2 3 Qi = 1 1

Hnh 5-14. Cc cung biu din s thay i trng thi t Qi n Qki ca trig Qi

a.Thut ton xc nh phng trnh li vo kch cho trig Qi loi D.

84

Ti thiu ho hm Di va tm c rt ra phng trnh li vo kch cho trig loi D.

b.Thut ton xc nh phng trnh li vo kch cho trig T

Phng trnh c trng ca trig T: Qki = Ti Qi Ti = Qi Qki = Q'i Trong Q'I bng 1 khi Qi thay i trng thi t 0 1 hoc t 1 0, ta lm nh sau: - in s thay i gi tr ca Qi vo cc cung. - Ti = Q'I = cc cung c Qi thay i (cung loi 2, loi 3) = (2) v (3). Ti thiu ho hm Ti va tm c rt ra phng trnh kch cho trig T.

Phng trnh c trng ca trig D : Qki = Di. T ta rt ra Di = Qki = tuyn tt c cc cung i ti nh c Qi = 1. = cc cung loi (2), k c khuyn ti nh tc l cung loi 1

= (1) v (2)

.4

T quy c c thut ton sau:

te

Trong cc cung biu din s thay i t Qi n Qki c k hiu nh sau: 0 0 l (0), 1 1 (l 1), 0 1 l (2), 1 0 l (3).

ch

.c

om .v

Sau y gii thiu thut ton xc nh phng trnh li vo kch cho cc trig t hnh trng thi.

Xc nh h phng trnh hm kch cho cc trig v ti thiu ho n.

Chng 5: Mch logic tun t

c.Thut ton xc nh phng trnh li vo kch cho trig JK

Phng trnh c trng ca trig JK: Q ik = J Q i + K Q i Xc nh: Ton = cc cung m Qi c bt (Qi thay i t 0 1 - cung loi 2) = (2). a phng trnh ca Ton v dng: Ton = ( T* ) Q i rt ra J = T*. Toff = cc cung m Qi c tt (Qi thay i t 1 0 - cung loi 3) = (3). a phng trnh ca Toff v dng: Toff = ( T** ) Q i rt ra K = T**.

d.Thut ton xc nh phng trnh li vo kch cho trig RS

Phng trnh li vo S ca trig RS c xc nh nh sau: S = Ton + [Cc cung loi (1)]

5.4.1.2. V d

minh ho,xt v d sau: Thit k b m ng b c M = 5 vi hnh trng thi v m ho trng thi nh hnh 5-17 , dng
Q2Q3 Q1 00 0 0 1 4

.4
01 1 x 11 3 x 10 2 x

te

Cc cung loi (1), cc cung loi (0) trong du [ ] biu thc ca S, R c ly gi tr khng xc nh. Nhng gi tr ny v nhng trng thi khng c s dng s c dng ti thiu ho sao cho biu thc nhn c l ti gin nht.

ch
100 Q'1Q'2Q'3 011

R = Toff + [Cc cung loi (0)]

.c
0 Q'1 4 Q'3 1 001 000 Q'2Q'3 3 Q'3 2 010 a). hnh trng thi

b). Bng m ho trng thi

Hnh 5-15.

a) Trig D v cc mch AND. b) Trig T v cc mch AND. 85

om .v

Chng 5: Mch logic tun t c) Trig JK v cc mch AND. d) Trig RS v cc mch AND. B m M =5 nn c 5 trng thi 0, 1, 2, 3, 4. n gin, trn hnh ta khng ghi cc tn hiu vo m v tn hiu ra. Tn hiu ra ca b m ch xut hin khi b m ang trng thi 4 v c tn hiu vo m, lc b m quay tr v trng thi ban u 0 v cho ra tn hiu ra. Mch c 5 trng thi v do vy c m ho t nht bng 3 bin nh phn tng ng vi 3 trig: Q1, Q2 Q3 nh trn bng m ho trng thi hnh 5-17b. in m tng ng vo cc trng thi trn hnh 5-17a. T ta vit c phng trnh cho tn hiu ra Y: Y = Q1 Q 2 Q 3 . X .

S dng cc trng thi tu chn ti thiu ho, t ta nhn c kt qu Y = Q1 X

By gi ta xc nh cc phng trnh kch cho cc trig :

a) Trig D.

D2 = Cc cung i n nh (2), (3) = (1) + (2) = Q1 Q 2 Q 3 + Q1 Q 2 Q 3 . D3 = Cc cung i n nh (1), (3) = (0) + (2) = Q1 Q 2 Q 3 + Q1 Q 2 Q 3 .

.4
01 x 11 1 x 10 x Q2Q3 Q1 00 0 1 1 x x 01 11

Q2Q3 Q1 00 0 1

te

ch
Q2Q3 Q1 00 0 1 10 1 x

D1 = Cc cung i n nh (4) = (3) = Q1 Q 2 Q 3 .

.c
01 1 x

Nhn vo hnh trng thi ta thy: Q1 = 1 ti nh (4), Q2 = 1 ti nh (2), (3), Q2 = 1 ti nh (1), (3).

D1 = Q2Q3

D2 = Q 2 Q 3 + Q 2 Q 3 = Q 2 Q 3

Bng 5-9. Bng tm hm kch

Dng bng Karnaugh 5-9 ta thu c kt qu D1 = Q2Q3 D2 = Q 2 Q 3 + Q 2 Q 3 = Q 2 Q 3 86

om .v
11 x 10 1 x

D3 = Q1 Q 3

Chng 5: Mch logic tun t

D3 = Q1 Q 3
b) Xc nh phng trnh kch cho Trig T.

in s thay i gi tr ca Qi (Qi) vo cc cung. Khi mch m t trng thi (0) (1) (ngha l t 000 001) th Q3 thay i t 0 1 nn ta ghi Q3 ln cung . Khi mch chuyn t trng thi (1) (2) (tng ng t 001 010): Q1 khng thay i trng thi (= 0), Q2 thay i t 0 1 v Q3 thay i t 1 0, nn ta ghi Q2Q3 ln cung t (1) (2). Tng t nh vy ta c: T1 = Q1 = cc cung c Q1 thay i = (3) + (4) = Q1 Q 2 Q 3 + Q1 Q 2 Q 3

Q1 Q 2 Q 3 + Q1 Q 2 Q 3 + Q1 Q 2 Q 3 + Q1 Q 2 Q 3
Q2Q3 Q1 0 1 1 x 00 01 11 1 x x 10

.c
01 1 x 11 1 x 10 1 x

T1 = Q1 + Q2Q3 Q2Q3 Q1 0 1

ch
00 1 T3 =

.4

Ch khi vit cc biu thc Ton, Toff ca trig th I ta cn phi n gin cc biu thc v a v dng: Ton = ( T* ) Q i rt ra Ji = T*. Toff = ( T** ) Q i rt ra Ki = T**. Vit cc biu thc Ton, Toff cho cc trig v t xc nh phng trnh kch cho cc trig nh sau:

T1 = Q1 + Q2Q3

T2 = Q3

T3 = Q1

c) Xc nh phng trnh kch cho Trig JK.

Lp bng Karnaugh 5-10 cho cc hm trn ta thu c kt qu:

te

Q1

om .v
Q2Q3 Q1 0 1 00 01 1 x 11 1 x 10 x T2 = Q3 Bng 5-10.

T3 = Q3 = cc cung c Q3 thay i = (0) + (1) + (2) + (3) =

T2 = Q2 = cc cung c Q2 thay i = (1) + (3) = Q1 Q 2 Q 3 + Q1 Q 2 Q 3

87

Chng 5: Mch logic tun t

Ton1 = Cc cung m Q1 c bt (Chuyn t 0 1) = (3) = Q1 Q 2 Q 3 Toff1 = Cc cung m Q1 tt (Chuyn t 1 0) = (4) = Q1 Q 2 Q 3 Ton2 = Cc cung m Q2 c bt (Chuyn t 0 1) = (1) = Q1 Q 2 Q 3 Toff2 = Cc cung m Q2 tt (Chuyn t 1 0) = (3) = Q1 Q 2 Q 3 Ton3 = Cc cung m Q3 c bt (Chuyn t 0 1) = (0) + (2) = Q1 Q 3

Q2Q3 Q1 0 1 x x J1 = Q2Q3 Q2Q3 Q1 0 1 00 01 1 x 00 01 11 1 x x 10

Q2Q3 Q1 0 1

.c
x 1 x x K1 = 1 01 x x K 2 = Q3 Q2Q3 Q2Q3 Q1 0 1 00 x x Q1 0 1 00 x x 01 1 x K3 = 1 Bng 5-11. Bng tm hm kch

te
11 x x 10 x 11 x x 10 1 x

ch
J1 = Q2Q3; K1 = 1 J2 = Q3; J3 = Q1 ; K2 = Q3 K3 = 1

Q2Q3 Q1 0 1

J2 = Q 3

00 1

.4
01 x x

J3 = Q1

Ta thu c kt qu t bng 5-11 nh sau:

d) Xc nh phng trnh kch cho Trig RS.

88

om .v
00 01 11 x x 10 x x 11 1 x x 10 11 1 x 10 x x

Biu din cc hm ny trn bng Karnaugh, s dng cc trng thi tu chn ti thiu ho . Cc trng thi tu chn bao gm 3 s khng nm trong phm vi m 5, 6, 7. Ngoi ra cn mt s trng thi khc tu vo tng bng. V d, i vi bng tnh J1 gi tr tu chn ngoi 3 s trn cn thm c gi tr Q1 = 1, bng tnh K1 c thm cc c gi tr Q1 = 0, tng t nh vy vi cc bng cn li.

Toff3 = Cc cung m Q3 tt (Chuyn t 1 0) = (1) + (3) = Q1 Q 3

Chng 5: Mch logic tun t S1 = Ton1 + [Cc cung loi (1)] = (3) + [] R1 = Toff1 + [Cc cung loi (0)] = (4) + [(0), (1), (2)] S2 = Ton2 + [Cc cung loi (1)] = (1) + [(2)] R2 = Toff2 + [Cc cung loi (0)] = (3) + [(0), (4)] S3 = Ton3 + [Cc cung loi (1)] = (0) + (2) + [] R3 = Toff3 + [Cc cung loi (0)] = (1) + (3) + [(4)] Biu din cc hm ny trn bng Karnaugh v ti thiu ho chng.
Q1 0 1 x S1 = Q2Q3 Q 2Q 3 Q1 0 1 00 01 1 x S2 = Q 2 Q 3 Q2Q3 Q1 0 1 00 1 x 11 10 x x 00 01 11 1 x x 10

.c
0 1 x x Q2Q3 Q1 0 1 x 00

ch
11 x 10 1 x Bng 5-12. Bng tm hm kch

te
01 x

.4

S3 = Q1 Q 3

5.4.2. Thit k mch tun t t bng. Gi thit: Cho bng chuyn i trng thi, bng ra ca mch (cha m ho nh phn). Xc nh: H phng trnh nh phn ca mch vo gm h hm ra, h hm kch cho cc trig. Trn c s v s mch.

Sau khi rt gn t bng 5-12 ta thu c kt qu sau: S1 = Q2Q3 ; R1 = Q1 hoc R1 = Q 2 hoc R1 = Q 3

S2 = Q 2 Q3 ; R2 = Q2 Q3 S3 = Q1 Q 3 ; R3 = Q 2 Q3

Cc bc thc hin: 89

om .v
0 1 x 1 x x x x x R1 = Q1 hoc R1 = Q 2 hoc R1 = Q 3 Q2Q3 Q1 00 01 x 11 1 x x 10 R2 = Q2 Q3 01 1 x 11 1 x x 10 R3 = Q 2 Q3

Q1

00

01

n
11 10

Q2Q3

Q2Q3

Chng 5: Mch logic tun t M ho tn hiu vo V, tn hiu ra R, trng thi trong ca mch S chuyn mch ban u thnh mch nh phn c tp tn hiu vo X, tp tn hiu ra Y, tp trng thi trong Q. Lp bng chuyn i trng thi, bng ra ca mch nh phn ng vi s m ho trn. Da vo bng cc li vo kch ca cc trig xc nh cc li vo kch cho cc trig ng vi s chuyn i trong bng trng thi. Vit phng trnh li vo kch cho tng Qi ca trig v cc hm ra ri ti thiu cc hm ny. Trn c s xy dng mch in.

S 0 1 2 3 4

Sk 1 2 3 4 0

Q2Q3 Q1 0 1 00 0 4 01 1 x 11 3 x 10 2 x

.c
1 1 T2 T3 R1S1 R2S2

a) Bng chuyn i trng thi

b) Bng m ho trng thi

Q1

Q2

Q3

Qk 1

Qk2

Qk3

te
D1 D2 D3 T1

ch
1 1 0 X X X 0 0 1 1 X X X 0 0 1 0 X X X 1 1 1 1 0 0 0 0 1

om .v
Q 0 0 1 Qk 0 1 0 D 0 1 0 1 T 0 1 0 1 RS X0 01 10 JK 0X 1X X1 X0 0X

V d: Thit k b m c K = 5, hnh trng thi cho hnh 5- 15a. T lp bng chuyn i trng thi nh hnh 5- 16a, m ho trng thi nh hnh 5-16b. Da vo hai bng ny v cn c vo bng hm kch thch cho trig hnh 5- 16c ta lp c bng nh hnh 516d. T xc nh c cc phng trnh cc li vo kch cho cc loi trig. Bng Karnaugh v kt qu ti gin ging nh mc 5.4.1.2.

c) Bng hm kch cho cc trig

R2S3

0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

0 0 0 1

1 1 0 0

.4

1 1 0

0 0 0

0 1 0

X0 X0 X0 01 10

X0 01 0X 10 X0

01 10 01 10 X0

0 0

0 1

1 0

X X X

X X X

X X X

X X X

X X X

X XX XX XX XX XX XX X XX XX XX XX XX XX X XX XX XX XX XX XX

d) Bng trng thi nh phn v u vo kch cho cc loi trig

Hnh 5-16. (a), (b), (c), (d) : Cc bc thit k mch tun t

5.5 MCH TUN T NG B

Phn ny trnh by phng php c bn phn tch v thit k mch tun t ng b. Mch tun t ng b l mt mch s bao gm cc mch t hp v cc phn t nh (trig), hot ng ca mch c ng b bi xung nhp C. Trn thc t gim nh cng sut tiu th, thi gian tr v cho cc mch thc hin n gin, ngi ta thng thit k s s dng cc trig JK v cc mch NAND. 90

n
J1K1 J2K2 J3K3

0X 0X 0X 1X X1

0X 1X X0 X1 0X

1X X1 1X X1 0X

Chng 5: Mch logic tun t nm vng cc vn thit k mch tun t ng b, trc ht ta s i phn tch mch tun t.
5.5.1. Phn tch mch tun t ng b. 5.5.1. 1. Cc bc phn tch mch tun t ng b.

Bi ton phn tch l bi ton xc nh chc nng ca mt mch cho trc. Khi tin hnh phn tch cn tun theo cc bc sau: - S mch: T s cho trc cn xc nh chc nng tng phn t c bn ca s , mi quan h gia cc phn t . - Xc nh cc u vo v ra, s trng thi trong ca mch: Coi mch nh mt hp en cn phi xc nh cc u vo v ra ca mch, c im ca cc u vo, u ra. xc nh c s trng thi trong ca mch cn phi xc nh xem mch c xy dng t bao nhiu phn t nh (trig JK) t xc nh c s trng thi trong c th c ca mch. Gi s trig l n th s trng thi c th c ca mch l 2n.

- Xc nh phng trnh hm ra, phng trnh hm kch ca cc trig.

- hnh trng thi: T bng trng thi xy dng hnh trng thi v tn hiu ra ca - Chc nng ca mch: Da vo hnh trng thi xc nh c chc nng ca mch
5.5.1.2. V d.

Phn tch mch tun t ng b c s c biu din nh hnh 5- 17a.

.4
Q1

te

mch.

ch
Q0
X
Q0

Da vo phng trnh c trng ca trig xc nh c trng thi k tip v tn hiu ra tng ng vi tn hiu vo v trng thi hin ti ca mch.

.c
J1 Q 1 > K1 Q1

- Lp bng trng thi, bng ra nh phn l bng biu din mi quan h trng thi k tip, tn hiu ra nh phn vi trng thi hin ti v cc tn hiu vo tng ng .

om .v
Q0 Q1

J0 Q 0 >

1 Clock

K0 Q 0

Hnh 5-17a)

Bc 1. S trn c hai u vo l tn hiu X v xung nhp Clock. C mt tn hiu Z ra, mch s dng hai phn t nh l hai trig JK (Q0 v Q1). Bc 2: Xc nh u vo, u ra v s trng thi trong ca mch. Mch ny c th c biu din bng mt hp en c hai u vo v mt u ra. Do mch c cu to bng hai trig nn s trng thi c th c ca mch l 4. C th l: Q1Q0 = 00. 01, 10 v 11. 91

n
Z

Chng 5: Mch logic tun t Bc 3: Xc nh phng trnh hm ra v hm kch cho trig. T s trn ta tm c: + Phng trnh hm ra: Z = C Q1 Q0 + Phng trnh hm kch J0 = Q1; K0 = 1 J 1 = Q 0 ; K1 = X Q 0 = X + Q 0

Phng trnh chuyn i trng thi:

k Q0 = J 0 Q0 + K 0 Q0 = Q1 Q0

k Q1 = J1 Q1 + K1 Q1 = Q0 Q1 + X + Q0 Q1 = Q0 Q1 + X Q0 Q1

ch
X=0 Q0Q1 01 10 00 00 X=1 Q0Q1 01 11 00 00

Trng thi hin ti Q0Q1 00 01 11 10

Trng thi k tip

.c
X

T cc phng trnh trn ta lp c bng chuyn i trng thi

Bc 5: hnh trng thi. T bng chuyn i trng thi trn ta xy dng c hnh trng thi nh hnh 5-17 c) (m hnh Mealy). hnh gm 4 trng thi trong S0, S1, S2, S3. Cc trig JK hot ng ti sn m ca xung nhp. Nhn vo hnh trng thi ta thy trng thi trong S2 (Q0Q1 = 11) khi c xung nhp C th mch s a ra tn hiu Z = 1.

.4

S0 S1 S2 S3

te

Hnh 5-17 b). Bng chuyn i trng thi

00

Bc 6: Chc nng ca mch:Trn 11 S2 S3 10 hnh trng thi ta thy c hai ng chuyn i Z=1 trng thi l S0 S1 S2 S0 v S0 S1 Hnh 5-17 c). hnh trng thi S3 S0. Theo ng S0 S1 S2 S0 th tn hiu ra Z = 1 s c a ra cng thi im c xung nhp th 3. Theo ng S0 S1 S3 S0 th khng c tn hiu ra (Z = 0). Do vy ta s phn tch theo con ng th nht S0 S1 S2 S0 : S chuyn i trng thi u tin t S0 S1 ch nh tc ng ca xung nhp m khng ph 92

om .v
Tn hiu ra X=1 Z 0 0 1 0 X=0 Z 0 0 1 0
S0 S1 01 X

Phng trnh c trng ca trig JK l Q k = J Q + K Q

Bc 4. Bng chuyn i trng thi.

Chng 5: Mch logic tun t thuc vo trng thi ca X. Chuyn i trng thi th hai t S1S2 nh tc ng ca xung nhp v s tc ng ca tn hiu vo X = 1. Cn s chuyn i trng thi th ba t S2 S0 ch nh tc ng ca xung nhp m khng ph thuc vo tn hiu vo. Nh vy, mch ch a ra tn hiu ra Z = 1 khi ng chuyn i i qua S2 tc l mch ch a ra tn hiu ra Z = 1 khi dy tn hiu vo X c dng 010, 011, 110 v 111. C th biu din dy tn hiu vo mch c tn hiu ra Z = 1 nh sau:
0 1

011

011

X Clock Z = C Q1 Q0 Z = Q1 Q0

0 1

1 2

1 3

5.5.2. Thit k mch tun t ng b.

Vic ti thiu ho trng thi ch yu da vo khi nim trng thi tng ng. Cc trng thi tng ng vi nhau c th c thay bng mt trng thi chung i din cho chng. Bc 4: M ho trng thi.

S bin nh phn dng m ho cc trng thi trong ca mch ph thuc vo s lng trng thi trong ca mch. Nu s lng trng thi trong l N, s bin nh phn cn dng l n th n phi tho mn iu kin: n log2N. C rt nhiu cch m ho khc nhau, mi cch cho mt s thc hin mch khc nhau. Vn l phi m ho sao cho s mch thc hin l n gin nht. Bc 5: Xc nh h phng trnh ca mch. C hai cch xc nh: 93

Bc 1: Xc nh bi ton, gn hm v bin, tm hiu mi quan h gia chng.

Bc 2: Xy dng hnh trng thi, bng chuyn i trng thi v hm ra. Bc 3: Rt gn trng thi (ti thiu ho trng thi).

5.5.2.1. Cc bc thit k mch tun t ng b.

.4

te

Hnh 5-17 a, b, c, d . Phn tch mch tun t ng b

ch

Hnh 5-17d) Dng xung ra ca mch

.c

om .v
0 0 1 1 1 0 1 2 3 1 2 3

Tm li, mch cho s trn c chc nng kim tra dy tn hiu vo X dng chui c di bng 3. Nu chui tn hiu vo c dng l 1 trong 4 dy: 010, 011, 110 v 111 mch s cho tn hiu ra Z = 1 ti thi im c xung nhp th 3. rng ca tn hiu ra Z bng rng xung nhp (Z = C Q1 Q0).

Chng 5: Mch logic tun t + Lp bng chuyn i trng thi v tn hiu ra, t xc nh cc phng trnh kch cho cc trig. + Da trc tip vo hnh trng thi, vit h phng trnh Ton, Toff ca cc trig v phng trnh hm ra. Bc 6: V s thc hin.
5.5.2.2. V d.

Mch phi thit k l mch ng b, nn s c cc li vo l X- tn hiu vo, Ck- xung nhp iu khin, Z tn hiu ra. Bc 2: Xy dng hnh trng thi, bng chuyn i trng thi

Tng t nh vy. Khi mch trng thi S1 th khi c tn hiu X. Ck mch chuyn n

te
X S1 X

trng thi S3 v chuyn n trng thi S4 khi c tn hiu X . Ck. Tng t ta xy dng c hnh sau 5-18 a.

.4 w

ch
S0 S3 Z=1 X

Khi tn hiu vo l X. Ck th mch s chuyn ti trng thi S1. Khi tn hiu vo l X . Ck mch s chuyn n trng thi S2.

.c
X X
S6

Gi s trng thi ban u l S0:

om .v
S2 X S5 X

Bc 1: Xc nh bi ton. Mch c thit k c nhim v pht hin tn hiu vo. Khi nhn c 1 trong cc dy tn hiu trn th mch s bo rng nhn c.

S4

Hnh 5-18 a). hnh trng thi

Nu mch 1 trong 4 trng thi S3, S4, S5, S6: khi c tn hiu vo X. Ck hoc X . Ck th mch s chuyn v trng thi ban u S0. Khi dy tn hiu vo l 110 hoc 111 (ng vi ng chuyn i trng thi l S0 S1 S3 S0) hay khi dy tn hiu vo l 010 hoc 011 (ng vi ng chuyn i trng thi l S0 S3 S5 S0) th mch s cho tn hiu ra Z = 1 ti thi im xung th 3. Vi cc ng chuyn i khc Z = 0. T hnh trng thi ta xy dng c bng chuyn i trng thi nh sau: 94

n
X

Thit k mch tun t thc hin nhim v kim tra dy tn hiu vo dng nh phn c di bng 3 c a vo lin tip trn u vo X. Nu dy tn hiu vo c dng l 010 hoc 011 hoc 110 hoc 111 th Z = 1. Cc trng hp khc Z = 0.

Z=1

Chng 5: Mch logic tun t

S X=0 S0 S1 S2 S3 S4 S5 S6 S2 S4 S6 S0 S0 S0 S0

Sk X=1 S1 S3 S5 S0 S0 S0 S0 X=0 0 0 0 1 0 1 0

Z X=1 0 0 0 1 0 1 0

Bc 3: Ti thiu ho trng thi. c c s mch n gin ta phi ti thiu ho cc trng thi. Trong phn ny s gii thiu phng php ti thiu ho Caldwell. C s l thuyt ca vic ti thiu ho l da vo khi nim cc trng thi tng ng.
nh ngha cc trng thi tng ng:

Nhng hng (tng ng vi trng thi trong) ca bng chuyn i trng thi v tn hiu ra s c kt hp vi nhau v c biu din bng mt hng chung - c trng (trng thi c trng) cho chng nu nh chng tho mn hai iu kin sau: 1. Cc hng tng ng trong ma trn ra ging nhau. 2. Trong ma trn ra, cc hng tng ng phi tho mn 1 trong 3 iu sau: Cc hng trong ma trn trng thi ging nhau. Cc trng thi trong cng mt ct nm trong nhm trng thi c xt. Cc trng thi trong cng mt ct l cc trng thi tng ng.

Sau khi thay th cc trng thi tng ng bng mt trng thi chung c trng cho chng, lp li cc cng vic tm cc trng thi tng ng khc cho n khi khng th tm c 95

Quy tc Caldwell:

Nhm cc trng thi tng ng phi c nhng hng trong bng trng thi cng mt ct (ng vi cng mt t hp tn hiu vo) l tng ng. Ngha l ng vi cng mt t hp tn hiu vo cc trng thi k tip ca chng l tng ng.

.4

Nhm cc trng thi tng ng phi c nhng hng trong bng tn hiu ra ging nhau.

te

Nu c nhiu trng thi tng ng vi nhau tng i mt th chng tng ng vi nhau (tnh cht bc cu). kim tra mt nhm cc trng thi xem chng c tng ng vi nhau khng, c th s dng bng trng thi v tn hiu ra nh sau:

ch

Trng thi Si c gi l trng thi tng ng vi trng thi Sj (Si Sj) khi v ch khi: nu ly Si v Sj l hai trng thi ban u th vi mi dy tn hiu vo c th chng lun cho dy tn hiu ra ging nhau.

.c

om .v

Hnh 5-18b). Bng chuyn i trng thi

Chng 5: Mch logic tun t cc trng thi tng ng no na th dng li. S trng thi trong bng chuyn i trng thi l ti thiu. Nhc im ca phng php ny l khi s trng thi qu ln th cng vic ti thiu ho mt nhiu thi gian. p dng quy tc Caldwell cho bi ton trn ta thy trng thi S4 tng ng vi trng thi S6 (S4 S6), S3 tng ng vi S5 (S3 S5). Thay th cc trng thi tng ng bng mt trng thi chung c trng cho chng. V d thay th S4, S6 bng S46, thay th S3, S5 bng S35. T lp c bng chuyn i trng thi 5-18c) v 5-18 d):
X S S0 S1 S2 S35 S46 S2 Z=0 S46 Z=0 S46 Z=0 S0 Z=1 S0 Z=0 S0 Z=0 S0 Z=1 S35 Z=0 S35 Z=0 S1 Z=0 0 1 S S0 S12 S46 S0 S0 Z=0 Z=0 Z=1 Z=0 X 0 S12 S35 S0 S0 1

.c
X
S46

Bc 4: Sau khi gp hai trng thi S1 v S2 thnh trng thi chung S12 th mch ch cn 4 trng thi S0, S12, S35, S46. M ho 4 trng thi ny bng hai bin nh phn Q1 v Q0.
Q0 0 0 1 1

Q1 0 1 1 0

.4

M ho S S0 S0 S12 S35 S46 S12

te
00 01 X 11 10 S35 Z=1

Hnh 5-18c) Bng chuyn i trng thi sau khi gp S3 v S5, S4 v S6

mch. C hai cch xc nh h phng trnh ny. Cch 1:

Bc 5: Xc nh h phng trnh ca

Hnh 5-18 e) Bng m ho trng thi

Da vo bng chuyn i trng thi ta lp bng hm kch 5-13 cho hai trig Q0 v Q1. 96

ch

Hnh 5-18d) Bng chuyn i trng thi sau khi gp S1 v S2

Hnh 5-18f). hnh trng thi ti gin

om .v
Z=0 Z=0 Z=1 Z=0 S12 S35 S46

Chng 5: Mch logic tun t Dng bng Karnaugh 5-14 rt gn, ta thu c kt qu sau: J0 =Q1 ; K0 = 1 J1 = Q0 ; K1 = X + Q0 Z = X Q0Q1
Trng thi hin ti Q0Q1 00 01 11 10 Trng thi k tip X=0 Q0Q1 01 Z=0 10 Z=0 00 Z=1 00 Z=0 X=1 Q0Q1 01 Z=0 11 Z=0 00 Z=1 00 Z=0 X 1 X 1 X X 1 X 1 X=0 J0 0 K0 X 0 Cc u vo ca trig

X=1 J0 K0 X 1

X=0 J1 K1 X 1 1 1

X=1

.c
1 0
Q0Q1 X 0 1 Q0Q1 X 0 1 00 01 11 1 1 Z = X Q0Q1 10

Bng 5-13. Bng hm kch thch

te

Q0Q1 X 0 1 00

ch
10 x x 10 Q0Q1 X 0 1

om .v
X 1 X X X X 0 X
00 x x 01 x x 11 1 1 K0 = 1 00 x x K1 = X + Q 0 01 1 11 1 1

01 1

11 x x

.4

J0 =Q1

Q0Q1 X 0 1

00 1 1

01 x x

11 x x

J1 = Q 0

Bng 5-14. Bng tnh hm kch

n
J1 K1 X 0 1 X
10 x x 10 x x

97

Chng 5: Mch logic tun t Cch 2: Da trc tip vo hnh trng thi vit phng trnh Ton, Toff ca tng trig v phng trnh tn hiu ra. i vi trig JK nu: Ton Q = T* Q JQ = T*

ToffQ = T** Q KQ = T** i vi trng hp ny ta c:

TonQ0 = S12 X + S12 X = S12 = Q0 Q1 ToffQ0 = S35 + S46 = Q0 Q1 + Q0 Q1 = Q0 TonQ1 = S0 X = Q0 Q1

Phng trnh hm ra Z = Q0Q1Ck Bc 6: S mch in:
Q1 J0 Q 0 > 1 Clock K0 Q 0 X
Q0

J 0 = Q1 J1 = Q0

ToffQ1 = S12 X + S35 = Q0 Q1 X + Q0 Q1 = Q1 (Q0 X + Q0 )

.c ch
> K1 Q1

Q0

Hnh 5-18 a, b, c, d, e, f. Thit k mch tun t

Vic thit k mch tun t khng ng b dng cc trig loi khng ng b khc hon ton tng t.
5.6.1. Cc bc thit k mch tun t khng ng b

98

Mch tun t khng ng b c th thit k: - Ch dng nhng mch NAND. - Dng trig RS khng ng b v cc mch NAND.

Bc 1: Xc nh bi ton, gn hm v bin, tm hiu mi quan h gia chng. Bc 2: Xy dng hnh trng thi, bng chuyn i trng thi v hm ra. Bc 3: Rt gn trng thi (ti thiu ho trng thi).

Phn 5.6 nghin cu cc mch tun t ng b, hot ng ca chng c iu khin bi cc xung nhp. Nhng trn thc t c nhiu mch li c iu khin bi cc s kin m khng tun theo mt quy lut no c. V d mt h thng chng trm s ch hot ng khi c trm. Nhng mch tun t hot ng theo kiu nh vy gi l mch tun t khng ng b.

.4

5.6. MCH TUN T KHNG NG B

te

om .v
J1 Q1
Q0 Q1

K1 = Q 0 X + Q 0 = X + Q 0

n
Z

K 0 =1

Chng 5: Mch logic tun t Vic ti thiu ho trng thi ch yu da vo khi nim trng thi tng ng. Cc trng thi tng ng vi nhau c th c thay bng mt trng thi chung i din cho chng. Bc 4: M ho trng thi. S bin nh phn dng m ho cc trng thi trong ca mch ph thuc vo s lng trng thi trong ca mch. Nu s lng trng thi trong l N, s bin nh phn cn dng l n th n phi tho mn iu kin: n log2N. C rt nhiu cch m ho khc nhau, mi cch cho mt s thc hin mch khc nhau. Vn l phi m ho sao cho s mch thc hin l n gin nht. Do mch khng ng b hot ng khng c s tc ng ca xung nhp cho nn trong mch thng c cc hin tng chy ua lm cho hot ng ca mch b sai, v vy khi m ho trng thi phi trnh hin tng ny. Bc 5: Xc nh h phng trnh ca mch. C hai cch xc nh:

+ Lp bng chuyn i trng thi v tn hiu ra, t xc nh cc phng trnh kch cho cc trig. + Da trc tip vo hnh trng thi, vit h phng trnh Ton, Toff ca cc trig v phng trnh hm ra. C hai cch ny u c hai loi phng trnh: -

Phng trnh ca mch ch dng NAND. Phng trnh ca mch dng trig RS khng ng b v cc mch NAND

Sau y l ni dung ca tng phng php.

Cch 1: Da vo bng chuyn i trng thi.

a) Ch dng cc mch NAND

K hiu : A, B, N l cc bin nh phn dng m ho cc trng thi trong ca mch.

Da vo bng chuyn i trng thi xc nh h phng trnh: Ak = fA (A, B, N , X1, X2Xm ) Bk = fB (A, B, N , X1, X2Xm ) Nk = fN (A, B, N , X1, X2Xm ) Z1 = g1 (A, B, N , X1, X2Xm ) Z2 = g2 (A, B, N , X1, X2Xm ) 99

X1, X2Xm l cc tn hiu vo c m ho nh phn. Z1, Z2Zm l cc tn hiu ra c m ho nh phn.

.4

te

Bc 6: V s thc hin.

ch

.c

om .v

Chng 5: Mch logic tun t Zn = gn (A, B, N , X1, X2Xm ) Ti thiu ho h hm v vit phng trnh dng ch dng NAND. b) Mch dng trig RS v cc mch NAND Trong bng trng thi cn c vo s thay i trng thi ca tng trig: A Ak, B Bk,, N Nk, xc nh c gi tr tng ng ca u vo kch R, S cho tng trig, t vit c h phng trnh: RA = 1 (A , N , X1, X2Xm )

Ti thiu ho cc hm v vit phng trnh dng ch dng NAND. Tng t vi B, C,N cng nh vy. Ta xc nh tn hiu ra : Z = (A , N , X1, X2Xm )

Ti thiu ho v vit phng trnh dng ch dng NAND.

Cch 2: Da trc tip vo hnh trng thi

Ta c phng trnh u vo kch (R, S) ca trig A l: SA = tp hp bt ca A + [(1)] RA = tp hp tt ca A + [(0)]

a) Ch dng mch NAND

Ta c phng trnh c trng ca trig RS

100

b) Dng cc trig RS khng ng b v cc mch NAND RA = 1A (A , N , X1, X2Xm )

Sau ta phi ti thiu ho phng trnh v vit di dng ch dng NAND. i vi cc trig khc cng lm nh vy.

SA = 2A (A , N , X1, X2Xm )

RN = 1N (A , N , X1, X2Xm ) SN = 2N (A , N , X1, X2Xm ) Z1 = 1 (A , N , X1, X2Xm ) Z2 = 2 (A , N , X1, X2Xm )

Qk = S + R Q

.4
Ak = S A + R A A

te

Lm tng t vi cc trig khc.

ch

.c

om .v

SA = 2 (A , N , X1, X2Xm )

Chng 5: Mch logic tun t Zn = n (A , N , X1, X2Xm ) Ti thiu ho h phng trnh.

5.6.2. V d

Mt mch tun t khng ng b c thit k m s ngi vo thm mt vin bo tng. Mch gm hai n X1, X2 c b tr cch nhau 10 mt. Mch c thit k sao cho mi ln ch m c mt ngi.
10 m Li vo Li ra

Hnh 5-19 a) B tr cc n ca vo vin bo tng

X1 X2 Mch logic Z

Hnh 5-19 b) S khi ca mch

Ta quy c: n b chn = X; ngc li th = X . hnh trng thi c m t hnh 5-19c.

S1

.4
X1 X 2
X1 X 2

te
S0

Hai li vo ca mch l X1 X2. u ra Z c a ti li vo ca b gii m.

ch
Trng thi tnh

Khi c mt ngi i vo th hai n s b chn lin tip. u tin X1 b chn, tip n c X1 v X2 cng b chn, sau n X2 b chn. Khi mch cho ra tn hiu Z = 1. Khi mt ngi ra th s ngc li. u tin n X2 s b chn, sau c X1 v X2 cng b chn v cui cng ch c X1 b chn. S khi ca mch to tn hiu m Z c m t bi hnh 5-19b.

.c
X1 X 2 X1 X 2 X1 X 2

X1 X 2

X1X2

X1 X 2
Z=1 S2

ng vo ng ra Hnh 5-19 c) hnh trng thi

S0 l trng thi ban u ca mch. Nu mt ngi i vo th s chuyn i ca mch s l S0 S1 S2 S3 S0. Nu mt ngi i ra th qu trnh chuyn i trng thi ca mch l S0 S3 S4 S1 S0. Khi c mt ngi ngp ngng sau li quay ra ban u chn n X1 sau quay ra th mch s chuyn i trng thi S0 S1 S0 , lc mch s khng thc hin m. 101

om .v
S3 X 1X 2

X1

X2

S4

n
X1 X 2

Chng 5: Mch logic tun t Tng ng vi hnh trng thi trn ta lp c bng chuyn i trng thi hnh 5-19d:

Trng thi hin ti X1 0 S0 S1 S2 S3 S4 S0 S0

Trng thi k tip v tn hiu ra X2 0 Z=0 S0 Z=0 S3 Z=0 S3 Z=0 S3 Z=0 Z=0 X1 0 S3 Z=0 S2 Z=0 Z=1 Z=0 Z=0 S2 S4 S4 S1 Z=0 Z=0 S1 X2 1 X1 1 X2 1 X1 1 S1 Z=0 X2 0

C th gn trng thi k tip v tn hiu ra vo cc trng sao cho hng c trng c th kt hp vi cc hng khc. bng chuyn i trng thi cc hng S0, S1, S2, v S3, S4 c cc trng thi k tip v tn hiu ra tng ng l ging nhau nu nh ta gn: - trng ca hng u tin (ng vi S0) l S2 / Z = 1, - trng ca hng th hai l S3 / Z = 0, - trng ca hng th t l S1 / Z = 0, - trng ca hng th ba v th nm l S0 / Z = 0, 102

Tin hnh ti thiu ho:

Trn bng c nhng trng. Nhng ny tng ng vi cc t hp tn hiu khng xut hin u vo. Nhng ny c th in gi tr tu chn ti thiu ho h phng trnh ca mch.

Trong bng chuyn i trng thi, nhng c khoanh trn l nhng c trng thi k tip bng trng thi hin ti. Nhng trng thi l nhng trng thi n nh. iu kin cho trng thi n nh l Sk = S.

.4

te

Bng c 5 hng ng vi 5 trng thi hin ti c th xut hin v 4 ct, mi ct ng vi mt t hp gi tr c th ca X1, X2. Mi ca bng biu din trng thi k tip v tn hiu ra tng ng vi trng thi hin ti v gi tr ca tn hiu vo X1, X2.

ch

Hnh 5-19 d) Bng chuyn i trng thi v hm ra

.c

om .v
S1 Z=0

Chng 5: Mch logic tun t Khi bng chuyn i trng thi c rt gn li nh sau:

Trng thi hin ti S012 S34

Trng thi k tip v tn hiu ra X1 X2 0 0 S012 Z=0 S012 Z=0 X1 0 S34 X1 X2 1 1 S012 Z=0 Z=0 S34 S34 Z=0 Z=0 X2 1 X2 X1 1 0 S012 Z=0 S012 Z=0

Hnh 5-19 e) Bng chuyn i trng thi v hm ra rt gn

S012 Z = X1X2 A=0

X1 X 2

Hnh 5-19 f) hnh trng thi sau khi rt gn Mch ch c hai trng thi nn m ho ta ch cn s dng mt bin nh phn A. m ho trng thi S012 th A = 0, S34 th A = 1. Tn hiu ra Z = 1 trng thi S012 khi X1 X2 = 11.

Ta c phng trnh u vo kch (R, S) ca trig l: S = tp hp bt ca Q + [(1)] ; Tp hp bt ca Q (Ton) l cc Cung Q Qk R S 0 0 0 X 0 cung m Q chuyn t 0 1. Ton 0 1 0 1 S A = A X1 X 2 + A X1 X 2 = X1 X 2 Toff 1 0 1 0 1 1 1 0 X R = tp hp tt ca Q + [(0)] ; Tp hp tt ca Q (Toff) l cc Bng 5-15.Bng hm kch cung m Q chuyn t 1 0.

RA = A X 2 + A X 1 X 2 + A X 1 X 2 = X 2

Cc cung [(0)], [(1)] c ly gi tr khng xc nh (x) v c dng ti thiu ho.

Phng trnh c trng ca trig RS

.4

Thay gi tr ca RA, SA vo biu thc thu c kt qu:

Phng trnh ra: 103

te

Ta dng trig RS thit k (da vo bng hm kch ca trig RS-bng 5-15 ).

Ak = X 1 X 2 + X 2 A = X 1 X 2 + X 2 A = X 1 X 2 . X 2 A

ch

.c
Q k = S A + RA QA

X2

om .v
S34 A=1

Chng 5: Mch logic tun t

X2 X1 A X2

Z k= A X 1 X 2 A
A X1 X2

Hnh 5-19 g) S mch ch dng NAND

X2 X1

X2

Hnh 5-19 h) S mch ch dng trig RS Hnh 5-19 a, b, c, d, e, f, g, h. Thit k mch tun t.

Nu thit k mch dng trig RS v cc mch NAND ta c:

V mch c biu din hnh 5-19 g, h.

5.7. HIN TNG CHU K V CHY UA TRONG MCH KHNG NG B

i vi mch tun t ng b, vic m ho trng thi l lm sao cho s thc hin mch l n gin nht. i vi mch tun t khng ng b, trong mch thng xy ra cc hin tng hoc l chu k hoc l chy ua. Nhng hin tng ny lm cho mch hot ng sai lch i so vi chc nng ca n. V vy, khi m ho trng thi ca mch tun t khng ng b ta phi trnh cc trng hp .
5.7.1. Hin tng chu k trong mch tun t khng ng b. nh ngha:

Hin tng chu k l hin tng ti mt t hp tn hiu vo no , mch lin tc chuyn t trng thi ny sang trng thi khc theo mt chu k kn. Ngha l trong qu trnh khng c trng thi no n nh. Do vy, khi thay i tn hiu vo khng xc nh c mch ang trng thi no trong dy trng thi ni trn.

V d: ng vi mt t hp tn hiu vo qu trnh chuyn i trng thi theo chu trnh sau:

Si1 Si2 Si3 Sin

Trn bng trng thi hin tng chu k c th hin ch: ct ng vi t hp tn hiu vo khng c trng thi no c khoanh trn (khng c trng thi no n nh).

104

.4

te

ch

.c

S A = X1 X 2

RA = X 2

om .v

Chng 5: Mch logic tun t V d: hnh trng thi ca mt mch tun t khng ng b c biu din trn hnh 520a. Vic m ho trng thi s dng bin nh phn A v B l tu chn. T hnh trng thi ta lp bng chuyn i trng thi 5-20b. Gi thit ban u mch trng thi S3 (AB = 10) v X = 0. Sau tn hiu vo X thay i t 0 n 1 th mch s chuyn trng thi t S3 sang S0. Nu X vn bng 1 th mch s ln lt chuyn n cc trng thi tip theo l S1, S2, S0. Khi X = 1 chu trnh chuyn i trng thi nh hnh 5-21: X S0 S1 X S 0 1 X
S1 S2 S3 S2 S3 S3 S2 S3 S0

S3

X+X

S2

Hnh 5-20a) hnh trng thi

Hnh 5-20 a,b. Bng trng thi hin tng chu k

S3

Hnh 5-21. Chu trnh chuyn i trng thi Khi mch khng c trng thi n nh.

nh ngha:

Nu trng thi cui cng ca nhng con ng l n nh v duy nht th chy ua khng nguy him. Ngc li, chy ua nguy him l nhng cch chuyn bin trng thi khc nhau cui cng dn n cc trng thi n nh khc nhau, c th ti trng thi kho v khng thot ra c.

V d: Chy ua khng nguy him: Mt mch tun t khng ng b c bng trng thi m t hnh 5-22 . Nhn vo bng ta thy nu mch ang trng thi S0 (AB = 00) tn hiu vo X thay i t 0 1 mch s chuyn trc tip ti trng thi S2 (AB = 01) v nu X vn bng 0 trng thi tip theo ca mch s l S3, n s l trng thi n nh cui cng ca mch nu nh X vn bng 0. Mch c th thay i trng thi theo nhng con ng khc nhau tu thuc vo th t thay i (hay thi gian qu ) ca A v B

Hin tng chy ua trong mch khng ng b l hin tng: do tnh khng ng nht ca cc phn t nh phn dng m ho trng thi, v mch hot ng khng ng b, khi mch chuyn trng thi t Si Sj mch c th chuyn bin trng thi theo nhng con ng khc nhau.

.4

te

5.7.2. Hin tng chy ua trong mch tun t khng ng b.

ch

.c

S0

S1

om .v
Hnh 5-20b) Bng chuyn i trng thi
S2

n
105

X+X

S0

S2

S1

Chng 5: Mch logic tun t

X AB S 0 S2 S2 S3 S3 1 S1 S2 S3 S0 00 S0 01 S1 11 S2 10 S3

A thay i trc B

B thay i trc A A, B cng thay i

Nu A v B thay i ng thi mch s chuyn trng thi sang S2 ri mi sang S3. Nu B thay i trc A th mch s ln lt chuyn qua S1, S2 ri mi sang S3. Nu A thay i trc B mch s chuyn i t S0 S3.

Chy ua nguy him: hnh trng thi ca mch khng ng b m t hnh 5- 23a.

te
S1 X 11

ch
X S AB S0 S2 S1 S3 00 01 11 10

Khi mch ang trng thi n nh (trng thi c khoang trn), n ch thay i trng thi khi tn hiu vo thay i.

.c
0 S0 S0 S2 S3

Ta thy rng c ba con ng u dn n cng mt trng thi n nh S3. Vy hin tng chy ua ny khng nguy him.

S0

X AB

.4

10

X 01

S3

S2

Gi thit trng thi ban u ca mch l S0 (AB = 00) v tn hiu vo X = 0. Nu X thay i t 0 1 th mch s chuyn i trng thi nh sau: - Nu A, B thay i ng thi th mch s chuyn n trng thi S1. - Nu B thay i trc A th mch s chuyn n trng thi S2. - Nu A thay i trc B th mch s chuyn n trng thi S3. y trng thi S3 l trng thi kho. Nh vy khi A thay i trc B th mch s ri vo trng thi kho v khng thot ra c. 106

Hnh 5-23b) Bng chuyn i trng thi

Hnh 5-23a) hnh trng thi

Hnh 5-23. Hin tng chy ua nguy him trong mch khng ng b

om .v
1 S1 S2 S1 S3

n
B thay i trc A, B thay i ng thi A thay i trc

Hnh 5-22. Hin tng chy ua khng nguy him trong mch tun t khng ng b

Chng 5: Mch logic tun t Chy ua ny l chy ua nguy him.

5.7.3. Ti thiu ho v m ho trng thi trong mch tun t khng ng b. 5.7.3.1. Ti thiu ho trng thi

Ti thiu ho trng thi l gim bt s trng thi (nu c th) mch thit k l n gin v do vy tin cy hn. i vi cc trng trong bng chuyn i trng thi (nhng ny ng vi t hp tn hiu vo khng xut hin) c th ly gi tr tu chn kt qu ti thiu ho l ti gin.

trnh c hin tng chu k th khi c mi tn hiu vo nhng mch phi lun c mt trng thi n nh. trnh hin tng chy ua, phi m ho trng thi sao cho vi tt c cc chuyn i trng thi c th c ca mch ch c duy nht mt bin thay i. V d. hnh trng thi ca mch tun t khng ng b c m t nh hnh 5-24:

.c
AB 00 10

ch
01 11

AB 00

S0

S1

te

.4

S2

a) hnh trng thi ban u

Cn hai bin nh phn A v B m ho 3 trng thi ny. Gi s chn cch m ho nh hnh 5-24a.

Vi cch m ho ny khi thay i t S2 S0 c hai bin A v B u thay i. iu ny dn n hin tng chy ua trong mch. Do vy, trnh hin tng chy ua a thm mt trng thi gi S3 cho thay i t S2 S0 thng qua trng thi gi ny bo m qu trnh thay i trng thi lun ch c mt bin thay i. hnh ny trnh c hin tng chy ua. Khi s dng cc trng thi gi m ho cho mch cn lu tm cch cho mch thot khi cc trng thi gi . Phn ln cc trng hp ta cho mch thot khi cc trng thi gi v iu kin. 107

Hnh 5-24. Trnh chy ua trong mch khng ng b

om .v
S0 X S1 01 X 11

S dng cc bin nh phn m ho cc trng thi trong ca mch. i vi mch tun t khng ng b phi m ho trng thi trnh c hin tng chu k v chy ua.

S3

b) hnh trng thi v m ho trnh chy ua

n
X
S2

5.7.3.2. M ho trng thi

Chng 5: Mch logic tun t

5.8. MT S MCH TUN T THNG DNG

5.8.1. B m.

B m l mch tun t n gin, n c xy dng t cc phn t nh l cc trig v cc mch logic t hp. Cc b m l thnh phn c bn ca cc h thng s, chng c s dng m thi gian, chia tn s, iu khin cc mch khcB m c s dng rt nhiu trong my tnh, trong thng tin. xy dng b m, ngi ta c th dng m nh phn hoc cc loi m khc nh m Gray, m NBCD, m vng m.
5.8.1.1. nh ngha v phn loi b m 1. nh ngha.

ch
X / 0 2 X / 1

S khi c m t nh hnh 5- 25.

hnh trng thi ca b m c h s m bng M c m t hnh 5-26. Xd / 0 Xd / 0 Xd /0 Xd /0 Xd /0

2. hnh trng thi tng qut ca b m.

.4
X / 0 1

Hnh 5- 25 S khi ca b m

te

B m H s m = M

.c
Y

B m l mt mch tun t tun hon c mt li vo m v mt li ra, mch c s trng thi trong bng chnh h s m (k hiu l M). Di tc dng ca tn hiu vo m, mch s chuyn t trng thi trong ny n mt trng thi trong khc theo mt th t nht nh. C sau M tn hiu vo m mch li tr v trng thi xut pht ban u.

X / 0

Hnh 5-26. hnh trng thi ca b m M

Khi khng c tn hiu vo m (X) mch gi nguyn trng thi c, khi c tn hiu m th mch s chuyn n trng thi k tip. Tnh cht tun hon ca b m th hin ch: sau M tn hiu vo X th mch li quay tr v trng thi xut pht ban u. Tn hiu ra ca b m ch xut hin (Y = 1) duy nht trong trng hp: b m ang trng thi M - 1 v c tn hiu vo X. Khi b m s chuyn v trng thi 0. 108

om .v
X / 0 M-2 M-1

Phn ny s a ra nhng c im c bn nht ca b m v cc phng php thit k b

Chng 5: Mch logic tun t Trong trng hp cn hin th trng thi ca b m th phi dng thm mch gii m.
2. Phn loi b m.

C nhiu cch phn loi b m. Hnh 5-27 l cch phn loi in hnh ca b m. ng b Phn theo cch hot ng Khng ng b m tin Phn theo hng m m li M = 2N Phn theo h s m

B m

Phn theo cc to M

.c ch
Phn theo m S
Hnh 5-28. Cc bc thit k b m

te

Hnh 5-27. S phn loi b m 5.8.1.2. Cc bc thit k b m

Hnh 5-28 l lu thit k b m.

.4

V hnh trng thi

Xc nh s trig ca b m (n) M ho trng thi theo m cho

Xc nh h phng trnh hm ra, hm kch ca cc trig v ti thiu ho

om .v
M 2N Khng lp trnh Lp trnh M nh phn M NBCD M Gray M Johnson M vng 109

Chng 5: Mch logic tun t

A. B m ng b. A.1. B m nh phn

Thit k b m nh phn ng b c M = 4. Do M = 4 nn lp c hnh trng thi hnh 5-29.

Q 1Q 0 S0 00 S1 01 S2 10 S3 11 Hnh 5-29

n +1

Trig Q1

Q1 Q0 Qk1 Qk0 R1 S1 J1 K1 T1 R0 S0 J0 K0 T0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 X 0 0 1 0 1 X 0 0 1 X X 0 1 0 0 1 1 X 1

X X

.c
0 1 0 1 1 0
R1 Q1 > S1 Q 1 '1' T0 Q0 >
Q0

ch
Bng 5-16
Clock

Clock

'1'

.4

te
R0 Q0 > S0 Q 0 J1 Q 1 > K1 Q 1

Ti thiu ho hm kch ca cc trig, nhn c kt qu:

J0 Q 0

> K0 Q 0 Clock

Hnh 5-30. B m Mod 4 dng trig RS, JK, T.

i vi trig Q0: R0 = Q0; S0 = Q 0 110

om .v
Trig Q0 1 1 0 X 1 X 1 1 1 1 X 1
T1 Q1 >
Q1

T xc nh c s trig cn dng thit k b m (n = 2) v m ho cc trng thi . Hai trig cn m ho cc thi l Q1 v Q0. Dng bng hm kch 5-16 xc nh cc li vo kch cho cc trig.

Chng 5: Mch logic tun t J0 = K0 = 1; T0 = 1; i vi trig Q1: R1 = Q1Q0; S1 = Q1 Q0 J1 = K1 = Q0; T1 = Q0; S mch in nh hnh 5-30.

Do M = 5 nn lp c hnh trng thi nh hnh 5-31.

Q2 Q1Q0 S0 000 S1 0 01 S2 010 S3

Hnh 5-31. hnh trng thi ca b m Mod 5

n 0 0 0 0 1 0

te
n+1 Qk1 0 1 1 0 0 Qk2 0 0 1 0

Q2 Q1 Q0 0 0 1 1 0

ch
Qk0 J2 0 0 0 1 X 1 0 1 0 0

T xc nh c s trig cn dng thit k b m (n = 3) v m ho cc trng thi . Ba trig cn m ho cc thi l Q2, Q1 v Q0. Dng bng hm kch 5-17 xc nh cc li vo kch cho cc trig.
Trig Q2 Trig Q1 Trig Q0 K2 X X X X 1 J1 0 1 X X 0 K1 X X 0 1 X J0 1 X 1 X 0 K0 X 1 X 1 X

Ti thiu ho hm kch ca cc trig, nhn c kt qu: J0 = Q 2 ; K0 = 1;

J1 = K1 = Q0; J2 = Q1Q0 ; K2 = 1; Kim tra kh nng t khi ng bng bng 5-18. Nhn vo bng trng thi 5-18, ta thy cc trng thi d sau 1 s xung nhp u quay tr li vng m nn ta ni b m ny t khi ng.

.4
0 1 0 1 0

Bng 5-17. Bng hm kch cho trig

.c

om .v
S4 011 100

Thit k b m ng b c M = 5.

n
111

A. 2. B m c mod m bt k

Chng 5: Mch logic tun t

n Q2 1 1 1 Q1 0 1 1 Q0 1 0 1 Qk2 0 0 0

n+1 Qk1 1 1 0 Qk0 0 0 0

Bng 5-18. Kim tra kh nng t khi ng S mch in hnh 5-32:

> '1' Clock K0 Q 0

> K1 Q1

B. B m khng ng b. B. 1. B m nh phn

- Ch dng mt loi trig T hoc JK. Nu dng trig T th li vo T lun c ni vi mc logic '1', nu dng trig JK th J v K c ni vi nhau v ni vi mc '1'. - u ra ca trig trc c ni vi li vo xung nhp ca trig sau k tip. Khi m tin ). th ly u ra Q, khi m li th ly u ra Q (vi gi thit xung Clock tch cc ti sn m - Tn hiu vo X lun c a ti li vo xung nhp ca trig c trng s nh nht.

S ca b m nh phn khng ng b 3 bit (M = 8 - m tin) dng trig JK c cho hnh 5-33

'1' Clock '1' J0 Q 0 > K0 Q 0 '1' '1' J1 Q 1 > K1 Q1 '1' '1' J2 Q 2 > K2 Q 2

V d i vi b m nh phn khng ng b M = 2n dng cc trig Q0, Q1 Qn-1 vi Q0 l bit c trng s nh nht, Qn-1 l bit c trng s ln nht, ta c: - Khi m tin: CQo = X; CQ1 = Q0CQn-1 = CQn-2.

- Khi m li: CQo = X; CQ1 = Q 0 CQn-1 = C Qn 2

112

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Hnh 5-33. B m nh phn khng ng b 3 bit

te

Cc b m ny c s rt n gin vi c im:

ch

.c

Hnh 5-32. B m Mod 5 ng b

om .v
> '1' K2 Q 2

J0 Q 0

J1 Q 1

J2 Q 2

Chng 5: Mch logic tun t

B. 2. B m c mod m bt k.

V d: Thit k b m M = 5 khng ng b. T yu cu bi ton ta xy dng s khi v hnh trng thi nh hnh 5-34.
C Xung m M = 5 Li ra S0 S1 S2 S3 S4

a) S khi ca b m Mod 5

b) hnh trng thi ban u

Hnh 5-34. M hnh thit k b m

S0 = 000; S1 = 001; S2 = 010; S3 = 011; S4 = 100. - Chn xung ng h t gin xung 5-35.
C Q0 Q1 Q2 1 2 3 4 5

C1 = C ; C2 = Q0 ; C3 = C;

.4

- Tm h phng trnh:
Q1Q0 Q2 0 1

te
Q1Q0 Q2 0 1 00 1 0 01 0 x 11 0 x 10 1 x 11 x 10 x 100 011 Qk0 = Q 2 Q 0 Q1Q0 01 1 x 11 0 x 10 x x Q2 0 1 00 0 0 01 0 x 11 1 x 10 0 x Qk2 = Q 2 Q1 Q0

00

01 x

001 000

010

Q1Q0 Q2 0 1 00 x x Qk1 = Q1

Bng 5-19. Bng tnh hm kch ca b m

ch

.c

om .v
Hnh 5-35. Gin xung ca b m Mod 5

C 5 trng thi nn s trig bng 3, chn trig JK. Chn m BCD8421.

n
113

- Chn la m ho trng thi

Chng 5: Mch logic tun t Sau khi ti thiu ho bng bng 5-19 ta nhn c h phng trnh: Qk0 = Q 2 Q 0 Qk1 = Q1 Qk2 = Q 2 Q1 Q0 Kim tra kh nng t khi ng bng bng 5-20:
n Q2 1 1 1 Q1 0 1 1 Q0 1 0 1 Qk2 0 0 0 n+1 Qk1 1 1 0 Qk0 0 0 0

Bng 5-20. Kim tra kh nng t khi ng

T ta tm c phng trnh hm kch: J0 = Q 2 ; K0 = 1; J1 = K1 = 1; J2 = Q1Q0 ; K2 = 1;

.4
J0 Q 0 > '1' K0 Q 0

T ta v c mch in ca b m Mod 5 khng ng b nh hnh 5-36.

te
'1' > '1'

ch
J1 Q 1 '1' J2 Q 2 > K2 Q 2 K1 Q1

5.8.2. B ghi dch.

B ghi dch c kh nng ghi gi v dch thng tin.

5.8.2.1. Cu to v phn loi a) Cu to:

B ghi dch gm mt dy cc phn t n bit mc lin tip v ng trn cng mt chip. Cc trig s dng trong b ghi dch thng l trig D hoc cc loi trig khc mc theo kiu D. 114

Clock

Hnh 5-36. S mch in ca b m Mod 5 ng b

.c

Nhn vo bng 5-20, ta thy cc trng thi d sau 1 s xung nhp u quay tr li vng m nn ta ni b m ny t khi ng.

om .v

Chng 5: Mch logic tun t ghi n bit thng tin, ngi ta s dng n trig, u ra ca trig ny mc ti u vo ca trig k tip. B ghi dch ghi c n bit thng tin c gi l b ghi dch n bit. Hnh 5- 37 l s ca mt b ghi dch 4 bit dng trig D
Li vo D0 Q0 > D1 Q1 > D2 Q2 > D2 Q2 >

Q0
Clock

Q1

Q2

Q3

b) Phn loi:

- Phn theo cch a tn hiu vo v ly tn hiu ra:

Vo song song, ra song song: thng tin c a vo v ly ra ng thi n trig. Vo ni tip, ra ni tip: thng tin c a vo v ly ra tun t tng bit mt. Vo song song, ra ni tip: thng tin c a vo ng thi c n trig, ly ra tun t tng bit mt di s iu khin ca xung nhp.

- Phn theo hng dch:

Dch phi, dch tri, dch hai hng, dch vng

- Phn theo u vo:

B ghi dch c s dng rng ri nh d liu, chuyn d liu t song song thnh ni tip v ngc li. B ghi dch l thnh phn khng th thiu c trong CPU ca cc h vi x l, trong cc cng vo/ra c kh nng lp trnh. 115

- Phn theo u ra: u ra n: mi trig trong b ghi dch ch c mt u ra Qi (hay Q i ) c a ra chn ca vi mch. u ra i: c hai u ra ca trig Qi v Q i u c a ra chn ca vi mch.

c) ng dng ca b ghi dch

u vo n: mi trig trong b ghi dch ch s dng mt u vo iu khin, v d nh trig D hay cc trig khc mc theo kiu D. u vo i: cc trig trong b ghi dch s dng c hai uvo iu khin , v d hai li vo iu khin ca trig JK hay trig RS.

.4

te

ch

.c

Vo ni tip, ra song song: thng tin c a vo thanh ghi dch tun t tng bit mt, s liu c a ra ng thi tc l tt c n trig ca thanh ghi c c cng mt lc.

om .v

Thng tin c np vo b ghi dch tng bit mt v c ng b vi xung nhp C.

Hnh 5-37. B ghi dch 4 bit dch phi

Chng 5: Mch logic tun t B ghi dch cn c dng thit k b m, to dy tn hiu nh phn tun hon
5.8.2.2. Hot ng c bn ca b ghi dch

Trong phn ny ta gii thiu b ghi dch 4 bit np vo ni tip hoc song song, ra ni tip v song song, dch phi. S b ghi dch ny c trnh by trn hnh 5- 37. B ghi dch ny c th np thng tin vo ni tip hoc song song. u ra ni tip c ly ra trig cui cng, u ra song song c ly ra ng thi trn c 4 trig. Vic np thng tin vo song song c thc hin bi mt trong hai u vo Preset 1 v Preset 2 (y l 2 li vo ph). Trc khi lm vic cn phi xo tt c cc trig v trng thi '0' nh li vo Clear. Thng tin trong b ghi dch ny c dch phi.

TM TT

Khc vi mch logic t hp, mch logic tun t c tn hiu u ra ph thuc khng nhng tn hiu u vo thi im xt m c vo trng thi mch in sn c thi im . y l c im chc nng logic ca mch tun t. nh trng thi mch in, mch tun t phi c phn t nh - l cc trig. 1Tnh cht c bn ca Trig

2-

Quan h gia chc nng logic v hnh thc cu trc ca trig

Mch tun t c th c rt nhiu chng loi. Chng ny ch gii thiu mt s loi 3mch tun t in hnh: b m, b ghi dchng thi vi vic nm vng cu trc, nguyn l cng tc v c im ca cc mch tun t , chng ta cng phi nm vng c c im chung ca mch tun t v phng php chung khi phn tch v thit k mch tun t.

CU HI N TP CHNG 5
1. Cho cc trig c bn loi RS, JK, D v T. Loi trig no trong s cc loi ny c th thc hin c m khng cn tn hiu ng b. a. Trig RS v trig D. 116

Mt trig c chc nng logic xc nh c th thc hin bng cc hnh thc cu trc khc nhau. V d, cc trig cu trc loi chnh ph v loi thng u c th thc hin chc nng ca mt trig khc. Ngha l cng mt cu trc c th m trch nhng chc nng khc nhau.

Chc nng logic v hnh thc cu trc ca trig l hai khi nim khc nhau. Chc nng logic l quan h gia trng thi tip theo ca u ra vi trng thi hin ti ca u ra v cc tn hiu u vo. Do chc nng logic khc nhau m trig c phn thnh cc loi RS, D, T, JK. Cn do hnh thc cu trc khc nhau m trig li c phn thnh loi trig thng v loi trig chnh ph.

.4

te

Trig l linh kin logic c bn ca mch s. Trig c hai trng thi n nh, di tc dng ca tn hiu bn ngoi c th chuyn i t trng thi n nh ny sang trng thi n nh kia, nu khng c tc dng tn hiu bn ngoi th n duy tr mi trng thi n nh vn c. V th, trig c th c dng lm phn t nh ca s nh phn.

ch

.c

om .v

Chng 5: Mch logic tun t b. Trig JK v trig T. c. Trig RS v trig T. d. Trig JK v trig D 2. Trong cc loi trig sau, trig no cn tn ti t hp cm: a. Trig D. b. Trig T c. Trig RS.

3. Cn bao nhiu cng NAND thc hin to ra mt trig RS ng b: a. 2. b. 3. c. 4. d. 5.

a. thay i trng thi ca n mt cch tc thi

b. s thay i sau khi c xung nhp clock u vo . c. s thay i sau khi c 2 xung nhp clock u vo . d. s khng thay khi c xung nhp tip theo.

a. 2000 hz. b. 1000 hz. c. 100 hz. d. 500 hz.

6. M hnh Mealy l m hnh: a. c hm ra ph thuc vo tn hiu vo v trng thi trong ca mch. b. c hm ra ph thuc vo tn hiu vo. c. c hm ra ph thuc vo trng thi trong ca mch. d. khng c phng n no ng. 7. M hnh Moore l m hnh: a. c hm ra ph thuc vo tn hiu vo v trng thi trong ca mch. b. c hm ra ph thuc vo tn hiu vo. 117

.4

5. Mt trig JK c ch lt. Nu tn s Clock ca n l 1000 hz th tn s ti li ra l:

te

ch

.c

4. Nu u vo D ca trig thay i t cao n thp th u ra

om .v

d. Trig JK.

Chng 5: Mch logic tun t c. c hm ra ph thuc vo trng thi trong ca mch. d. khng c phng n no ng. 8. Cc phng php m t mch tun t: a. Bng chuyn i trng thi. b. Bng tn hiu ra. c. hnh trng thi. d. C ba phng n trn u ng.

a. Trig D. b. Trig RS. c. Trig JK.

d. Bt k loi trig no nhng phi a v dng trig D.

10. Cn bao nhiu trig thc hin to ra mt b ghi dch 4 bit:

b. 3. c. 4. d. 5.

11. Bng cch no to ra c mt Trig Chnh - ph (MS): a. T hai trig cng loi ng b. b. T hai trig cng loi.

d. T 4 trig cng loi. 12. B m m Johnson l:

118

13. Mt b m nh phn 4 bit th tn s ti li ra ca bit c trng s ln nht so vi tn s xung nhp: a. nh hn 2 ln. b. nh hn 4 ln. c. nh hn 8 ln.

a. B m vng. b. B m vng xon. c. B m nh phn.

d. C ba phng n trn u ng.

c. T ba trig cng loi.

.4

te

ch

.c

a. 2.

om .v

9. Cc phn t nh ca b ghi dch l:

Chng 5: Mch logic tun t d. nh hn 16 ln. 14. Trn b m ng b, cc li vo Clock a. phi c ni vi tng LSB ca b m. b. phi c ni vi tng MSB ca b m. c. l chung cho mi tng ca b m. d. phi l dng xung c pht theo kiu n bc.

CC LI VO PHT XUNG HOT NG MC CAO

CC LI RA HOT NG MC THP

CC LI VO D LIU

HOT NG MC CAO HOT NG MC THP

15. Vi IC xut hin trn hnh 1, chn CLEAR a. xo tt c 6 li ra ca IC.

b. lp tt c 6 li ra ca IC. c.

Ch xo cc li ra t QD n QA.

d. Ch xo cc li ra CARRY v BORROW. 16. Nu cc li vo ca LS 193 c gi tr l 1010, th cc li ra ca b m s l:

17. Cc li ra CARRY v BORROW ca b m LS 193: a. bnh thng mc thp v s pht ra mt xung hot ng mc cao. b. c th c a ln mc cao bng cch kch hot chc nng LOAD. c. c th c a xung mc thp bng cch kch hot chc nng CLEAR. d. bnh thng mc cao v s pht ra mt xung hot ng mc thp.

18. Trn b m LS 193, b m thc hin m tin: a. nu chn DOWN c cp xung v chn UP ni ln VCC. 119

a. hin th gi tr 1010 sau khi chc nng LOAD c kch hot.

b. hin th gi tr 0101 l gi tr o ca 1010 sau khi chc nng LOAD c kch hot.

c. hin th gi tr 1010 sau mt xung clock. d. s tng ln nhng khng th gim xung.

.4

te

ch

.c

Hnh 1

om .v

CC LI RA D LIU HOT NG MC THP

Chng 5: Mch logic tun t b. nu chn UP c cp xung v chn DOWN ni ln VCC. c. chn UP v DOWN c cp xung ng thi. d. chn UP v DOWN u c ni ln VCC. 19. Trn b m LS 193, b m thc hin m li: a. nu chn DOWN c cp xung v chn UP ni ln VCC. b. nu chn UP c cp xung v chn DOWN ni ln VCC. c. chn UP v DOWN c cp xung ng thi.

a. 32. b. 16. c. 8. d. Khng c trng hp no trn.

21. Vi b m khng ng b, qua mi trig th li ra ca n chia tn s u vo ra lm :

b. 2. c. 10. d. 16.

120

23. Khi tn s xung nhp ca b m khng ng b tng th : a. Cc u vo xo (CLEAR) v lp (SET) khng iu khin tt c cc trig ca b m. b. Chc nng ca cc u vo xo (CLEAR) v lp (SET) khng b nh hng g. c. Tng kh nng m ln nht ca n. d. Gim kh nng m ln nht ca n. 24. Mt xung clock vo : a. Cho php mt b m khng ng b chy trong ch khng ng b.

b. 50 KHz.

c. 12,5 KHz.

d. 6, 25 KHz.

a. 100 KHz.

.4

22. Tn s u vo ca mt b m khng ng b 4 bit l 100KHz. Vy tn s ti u ra ti li ra c trng s ln nht (MSB) l bao nhiu ?

te

ch

a. 4.

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20. Mt b m khng ng b 5 bit th cung cp h s chia tn hay h s chia s m l bao nhiu :

d. chn UP v DOWN u c ni ln VCC.

Chng 5: Mch logic tun t b. Xc nh s m ln nht ca b m khng ng b. c. Thay i ln lt cc ch hot ng ca b m khng ng b. d. Chuyn mt b m khng ng b thnh mt b m ni tip. 25. Khi pht xung vo b m khng ng b th xung clock l : a. Tn hiu iu khin tt c cc u vo. b. Tn hiu iu khin tng LSB ca b m. c. Tn hiu iu khin tng MSB ca b m.

a. Khng tip nhn xung xo bi v xung CLOCK chy t do.

b. Tip nhn xung xo, lc ny tt c cc u ra khng o c t c nh mc thp.

d. Dao ng gia gi tr m ln nht v gi tr nh nht. 27. Khi chn SET (lp) ca b m khng ng b c a xung mc thp th b m: a. Khng tip nhn xung lp bi v xung CLOCK chy t do. b. Tip nhn xung lp, lc ny tt c cc u ra khng o c t c nh mc cao. c. Tip nhn xung lp, lc ny tt c cc u ra khng o c t tm thi mc cao.

28. Mt b m khng ng b c coi nh l mt b m ni tip l bi v : a. Tt c cc u ra thay i ng thi. b. Mt tn hiu xung nhp iu khin tt c cc trig.

29. H s chia tn s cho mt b m khng ng b 4 bit l : a. 1, 2, 4 v 8. b. 1, 2, 4 v 16. c. 2, 4, 8 v 16. d. Tt c cc trng hp trn, ph thuc vo tn s xung clock. 121

d. Dao ng gia gi tr m ln nht v gi tr nh nht.

c. Tt c cc u ra l o.

d. Cc trig trong b m hot ng theo phng php chui cnh hoa (daisy-chaind). (iu ny c ngha l li ra ca trig trc s iu khin li vo ca trig sau).

.4

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c. Tip nhn xung xo, lc ny tt c cc u ra khng o c t tm thi mc thp.

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26. Khi chn CLEAR (xo) ca b m khng ng b c a xung mc thp th b m :

d. Trng thi tnh.

Chng 5: Mch logic tun t 30. Nu mt b m khng ng b 4 bit c cc li ra o th chng a. m t 15 0. b. m t 0 15. c. Lun l 0. d. Lun l 15. 31. Cn bao nhiu chu k xung clock u vo pht ra mt chu k hon chnh ti li ra c trng s ln nht (MSB) ca b m khng ng b 4 bit. a. 32. b. 16. c. 8. d. Khng c trng hp no trn.

32. Cc Trig JK s dng trong b m khng ng b c xy dng bng cch:

a. Ni li vo J v K vi VCC v v hiu ho cc li vo CLR (xo) v PR (lp).

c. Ni tt c cc li vo J, K, CLR v PR vi VCC. d. S dng bt k cu trc no trn.

33. Cho b m hnh 2. Cho bit y l b m Mod my?

te
J1 Q 1 > K1 '1' J1 Q 1 > '1' K1 Q1

.4
> K0 Q J0 Q 0 > '1' K0 Q 0

J0 Q 0

ch
'1'

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J2 Q 2 > K2 Q Hnh 2 J2 Q 2 > K2 Q 2 Hnh 3

b. Cu trc mch Trig JK ging nh mt mch Trig T.

122

34. Cho b m hnh 3. Cho bit y l b m Mod my?

Clock

a. Mod 5.

b. Mod 6. c. Mod 7. d. Mod 8.

Clock

'1'

om .v

Chng 5: Mch logic tun t

a. Mod 5. b. Mod 6. c. Mod 7. d. Mod 8.

J0 Q 0 > '1' K0 Q

J1 Q 1 > K1

Clock

a. Mod 5. b. Mod 6. c. Mod 7. d. Mod 8.

36. Thit k b m Mod 9 ng b.

37. Thit k b m Mod 9 khng ng b.

38. B ghi dch ca bn c reset. Sau 4 sn dng ca xung clock tt c 4 li ra u mc cao. Kt lun ca bn v cc li vo d liu l: a. c t mc thp. Ln lt thay i gia hai trng thi cao v thp. Ln lt thay i gia hai trng thi thp v cao. c t mc cao.

39. Nu mch ca bn c thit k dch tri d liu vo ni tip, sau lung bit d liu chuyn ng t: a. Tri qua phi. b. T phi qua tri. 123

b. c. d.

.4

te

ch

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J2 Q 2 > Hnh 4 K2 Q

35. Cho b m hnh 4. Cho bit y l b m Mod my?

Chng 5: Mch logic tun t c. Mt trong hai trng hp trn. d. Khng c trng hp no trn. 40. Nu mch ca bn c nh hnh dch phi d liu vo ni tip, sau lung bit d liu chuyn ng t: a. Tri qua phi. b. T phi qua tri. c. Mt trong hai trng hp trn. d. Khng c trng hp no trn.

124

.4

te

ch

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om .v

Chng 6: Mch pht xung v to dng xung

CHNG 6: MCH PHT XUNG V TO DNG XUNG

GII THIU
Hu ht cc h thng k thut s u yu cu mt vi loi dng sng nh thi, v d mt ngun xung ca b dao ng cn thit cho tt c cc h thng tun t nh thi. Trong cc h thng k thut s, mt dng sng xung vung thng c s dng nht. S to ra cc dng sng xung vung c gi l b a hi. C ba loi b a hi: B dao ng a hi (chy t do). B a hi n n (mt nhp).

B a hi hai trng thi n nh (trig).

V d, mt b vi x l c th pht tn hiu cho mt thit b bn ngoi in mt ni dung no bng cch truyn qua mt xung. Thit b u ra ni chung c tc chm hn b vi x l, do n yu cu mt xung tn hiu trong mt khong thi gian lu hn. iu ny t c bng mt mch giao tip c cha b a hi n n. Mt mch a hi trong c hai trng thi u n nh th c gi l mch a hi hai trng thi n nh hay trig. Mch ny thc hin vic chuyn tip t mt trng thi n nh ny sang mt trng thi n nh khc ch lc xung kch khi c p vo. Mch ny thng c dng lm cc thnh phn trong b nh trong cc h thng k thut s v c tho lun chng 5. Chng ny tp trung vo s , nguyn tc hot ng, ng dng ca cc mch dao ng a hi, mch dao ng a hi i, trig Schmitt da trn cc cng TTL, CMOS v IC nh thi 555. Sau chng ny c gi c th t thit k cc mch dao ng theo cc yu cu c bn cho cc ng dng khc nhau. 125

Mt b a hi n n ch c mt trng thi n nh, tc l trong iu kin trng thi n nh th u ra ca n c nh. u ra ny trng thi LOW hoc trng thi HIGH. Mch ny cn mt xung kch khi t bn ngoi cho mch chuyn sang trng thi khc. Mch ny vn gi nguyn trng thi c trong mt khong thi gian, khong thi gian ny ph thuc vo cc thnh phn c dng trong mch. Trng thi ca mch ny c xem l trng thi n nh bi v n phc hi tr v trng thi n nh m khng cn bt k xung kch hot no t bn ngoi. rng ca xung kch khi rt nh, rng ca xung u ra ch ph thuc vo khong thi gian m mch gi li trng thi n nh. Mch ny c gi l mch mt nhp (one-shot) bi v mt xung kch khi ch to c mt xung nhng rng xung li khc. Mch ny rt hu dng bi v n c th to ra mt xung tng i di (hng chc mili giy) t mt xung hp, do n cn c gi l b gim xung (pulse stretcher).

.4

te

ch

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Mt b dao ng a hi ch l mt b dao ng to ra dng xung. N c hai trng thi chun m khng yu cu s kch hot t bn ngoi. B ny thng c dng lm xung iu khin cho cc mch tun t.

om .v

Chng 6: Mch pht xung v to dng xung

NI DUNG
6.1. MCH PHT XUNG
6.1.1. Mch dao ng a hi c bn cng NAND TTL

Cng NAND khi lm vic trong vng chuyn tip c th khuch i mnh tn hiu u vo. Nu 2 cng NAND c ghp in dung thnh mch vng nh hnh 6-1 ta c b dao ng a hi.VK l u vo iu khin, khi mc cao mch pht xung, v khi mc thp mch ngng pht.

Hnh 6-1. B dao ng a hi cu trc bng cng NAND

Kt qu qu trnh ny l: cng I nhanh chng ngt cn cng II thng bo ho, mch in bc vo trang thi tm n nh mi. Lc ny C2 np in cn C1 phng cho n khi Vi1 bng ngng thng VT lm xut hin qu trnh phn hi dng a mch v trng thi n nh ban u. Mch khng ngng dao ng, khi b qua in tr u ra ca cc cng NAND, da vo hnh 6-2 gin xung ca mch c th hin trn hnh 6-3.

126

.4

Khi , cng I nhanh chng tr thnh thng bo ho, cng II nhanh chng ngt, mch bc vo trng thi tm n nh. Lc ny, C1 np in v C2 phng in theo mch n gin ho c th hin trong hnh 6-2. C1 np n khi Vi2 tng n ngng thng VT, trong mch xut hin qu trnh phn hi dng nh sau:

te

ch

.c

Nu cc cng I v II thit lp im cng tc tnh trong vng chuyn tip v VK = 1, th mch s pht xung khi c ni ngun. Nguyn tc lm vic ca mch nh sau: Gi s do tc ng ca nhiu lm cho Vi1 tng mt cht, lp tc xut hin qu trnh phn hi dng sau:

om .v

Chng 6: Mch pht xung v to dng xung

EC R1 V i2 C1 V L1 C1
+ + -

V H2

EC

V H2 R f2

R f2 V L1
+

R1 V i2

C2
-

V H2 V H2 V L1 V L1 C2
+

R f1 V i1

V i1

Hnh 6-2. Mch vng np phng in ca t C1, C2

V thi gian np in nhanh hn thi gian phng, nn thi gian duy tr trng thi n nh tm thi ph thuc vo thi gian np in ca hai tu in C1 v C2. T hnh 6-2 ta c thi gian np in ca tu C1 l 1 = (Rf2 // R1) C1, thi gian Vi2 np in n VT l:

Hnh 6-3. Dng sng gn ng ca in p ti cc im trn mch b dao ng a hi.

.4
t M 2 = (R f 2 // R 1 )C1 ln 2VOH (VT + VOL ) VOH VT
Nu Rf1=Rf2=Rf, C1=C2=C, VOH=3 V, VOL=0,35 V, VT = 1,4 V th ta c:

T l chu k ca tn hiu a hi li ra.

te
T 2(R f // R 1 )C

ch

.c
127

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R f1

Chng 6: Mch pht xung v to dng xung

6.1.2. Mch dao ng a hi vng RC

Hnh 6-4. B dao ng vng v dng sng

Hnh 6-5. B dao ng a hi c mch RC

6.1.4. Mch dao ng a hi CMOS

Hnh 6-7a l mch dao ng a hi c bn s dng hai cng NOR CMOS v cc linh kin nh thi tr v t. Gin xung ca mch c th hin trn hnh 6-7b. Chu k dao ng ca mch c tnh gn ng nh sau:

128

c cc tn hiu ng h c tn s chnh xc v c n nh cao, cc mch a hi trnh by trn y khng p ng c. Tinh th thch anh thng c s dng trong cc trng hp ny. Thch anh c tnh n nh tn s tt, h s phm cht rt cao dn n tnh chn lc tn s rt cao. Hnh 6-6 l mt mch dao ng a hi in hnh s dng tinh th thch anh. Tn s ca mch dao ng ch ph thuc vo tinh th thch anh m khng ph thuc vo gi tr cc t in v in tr trong mch.

.4

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6.1.3. Mch dao ng a hi thch anh

Hnh 6-6. Mch dao ng a hi thch anh

ch

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B dao ng vng c cu trc gm 3 cng NAND mc ni tip nh hnh 6-4. Phn hi dng t Vo n Vi1 lm cho mch ny khng c trng thi n nh. Tn s ca tn hiu li ra ph thuc vo thi gian tr ca cng NAND, v khng th iu chnh c tn s ny. Tn s ca mch pht s iu chnh c khi mt mch tr RC c mc thm vo mch nh hnh 6-5. Tn s dao ng ca mch iu chnh c thng qua gi tr ca t in C v in tr R.

Chng 6: Mch pht xung v to dng xung

Nu gi thit VT = ED/2 th T1 = T2, khi T = RCln4 1,4RC.

6.2. TRIG SCHMIT

ch
T2
P

R1 Vi
A

R2 R4

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R5 D3 R6
u Ra

D1

te
D0
u vo

T1

.4

R3

Mch Schmit

Hnh 6-8 l s nguyn l ca trig schmitt, hay cn c gi l b o pha trig schmit. N gm 3 phn: mch u vo, mch schmit v tng cng sut li ra. Nguyn tc lm vic ca mch nh sau: Nu VB1 mc thp th T1 ngt, T2 thng bo ho v ngc li nu VB1 mc cao th T1 thng bo ho, T2 ngt. Khi VB1 tng t mc thp ln mc cao n tr s VBE1 = VB1 - ILR3 = 0,5 V th T1 bt u chuyn t trng thi ngt vo trng thi khuch i. Do VB1 tip tc tng nn VCE1 = VBE2 gim xung. Sau khi T2 ri khi trng thi bo ho m VB1 tip tc tng th xy ra qu trnh phn hi dng sau:

Hnh 6-8. S nguyn l ca trig Schmit

om .v
EC R7 T4 T 3 D4 T5 Vo
Z

ED ED T = T1 + T2 = RC ln E V + V D T T

n
129

Hnh 6-7. B dao ng a hi dng cng NOR CMOS v gin xung

Chng 6: Mch pht xung v to dng xung Nh phn hi dng mch in nhanh chng chuyn sang trng thi T1 thng bo ho, T2 ngt. Nu VB1 sau khi tng n cc i th bt u gim; khi VB1 gim n mc lm T1 ra khi vng bo ho, T2 ra khi vng ngt th mch in li xy ra qu trnh phn hi dng sau:

6.3. MCH A HI I

6.3.1. Mch a hi i CMOS 1. Mch a hi i kiu vi phn

ED Vo1 VI
C R

Mch a hi i c mt trng thi n nh v mt trng thi tm n nh. Khi c tc dng ca xung ngoi, mch c th chuyn i t trng thi n nh sang trng thi tm n nh. Sau khi duy tr mt thi gian, mch s t ng quay li trng thi n nh. Thi gian tm n nh ph thuc vo cc thng s ca mch m khng ph thuc vo xung kch. Mch a hi c ng dng trong cc mach nh thi, to dng xung, tr v.v..

.4

Trig schmit thc cht l mt b so snh hai ngng nn n c dng ng dng khc nhau nh: Cc mch dao ng, cc mch so snh, lc nhiu v.v..

te

Hnh 6-9. Dng sng u vo VI v u ra VO ca trig schmit

ch
V i2

.c
Vo

Hnh 6-10. a hi i kiu vi phn dng cng NOR CMOS

130

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Kt qu mch in nhanh chng lt sang trng thi T1 ngt, T2 thng bo ho. Chng ta gi gi tr in p u vo VI trong qu trnh tng ln ca n t n ngng lm lt mch schmit u ra t mc cao xung mc thp l ngng trn VT+ v gi tr ngc li l ngng di ca trig schmit VT-(hnh 6- 9). Hiu in p tng ng vi ngng trn v ngng di c gi l chnh lch in p chuyn mch V = VT+ - VT-.

Chng 6: Mch pht xung v to dng xung

ED VI

ED VO1

ED

ED

VO2

Hnh 6-11. Dng song ca mch a hi i kiu vi phn

rng xung ti u ra ca mch c xc nh bng cng thc sau:

te

ch

Hnh 6-10 l s nguyn l ca mach a hi i kiu vi phn. Ti trng thi n nh, VI=0 th VO1=ED, VI2=ED, VO2=0. Khi c mt xung kch thch li vo lm cho cng 1 nhanh chng cm v li ra bng 0, xem gin 6-11. Mch in RC s np in cho t in C. Trong qu trnh np, in p VI2 tng dn n ngng VT v lm cng 2 ng, in p VO2=0. Khi , cng 1 nhanh chng chuyn v trng thi cm v lm cho mch a hi i tr v trng thi n nh.

2. Mch a hi i kiu tch phn

trong R0 l in tr u ra ca cng 1, nu VT=ED/2 th TW = 0, 7 ( R + R0 ) C

.4

TW = ( R + R0 ) C ln

Hnh 6-12. a hi i kiu tch phn dng cng NOR CMOS

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TW

ED ED VT

n
131

VI2

VT

Chng 6: Mch pht xung v to dng xung

ED VI

VO1

VI2

VT

TW

Hnh 6-13. Dng sng ca mch a hi i kiu tch phn

rng xung li ra ca mch a hi i c tnh theo cng thc:

D vo c tnh so snh ca trig Schmitt, mch nguyn l ch ra trn hnh 6-14 l b a hi i. rng xung li ra ph thuc vo ngng trn ca trig Schmitt v gi tr ca t in C v in tr R theo cng thc sau:

3. Mch a hi i dng trig Schmitt

.4
ED
R

trong R0 l in tr u ra ca cng 1, nu VT=ED/2 th TW = 0, 7 ( R + R0 ) C

te
C V

TW = ( R + R0 ) C ln

nu VT=ED/2 th TW = 0, 7 RC
VI

ch
TW = RC ln
Vo

Hnh 6-12 biu din s nguyn l ca mch a hi i kiu tch phn. Ti trng thi n nh, VI=1 th VO1=0, VI2=0, VO2=0. Khi li vo VI chuyn t 1 xung 0 li ra VO2 nhy t trng thi 0 ln 1 v ng thi mch RC bt u tch in cho t in C, khi in p VI2 = VT in p li ra VO2 chuyn xung trng thi 0. Sau khi khi ht xung li vo t in phng in thng qua tr R v mch tr v trng thi n nh.

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ED ED VT ED ED VT+
V

VI

132

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+ VT

VO

Vo
TW

Chng 6: Mch pht xung v to dng xung

Hnh 6-14. S nguyn l v gin thi gian ca mch a hi dng trig Schmitt 6.3.2. Mch a hi i TTL

Hnh 6-15 l s nguyn l mch a hi i h TTL, trong cc cng 1, 2, 3 cu trc ln mch flip-flop, cng 4,5 l mch to dng xung. Cc cng ny thuc h TTL nn c mc logic 1 l 3,6 V v logic 0 l 0,3 V. u vo V2 biu th s dng mch o. Mch o ny thng bo ho th V2 ~ 0,7 V, cn ngng thng ca n c 0,6 V. Ti trng thi n nh P = P = 0. Mch o u vo V2 l b khuch i transistor emitter chung trng thi bo ho v khi V2 = 0,7 V, V3 = 0 , V1 = 1, Q = 0, Q = 1. Khi c xung dng tc ng u vo th P = 1, P = 1, V1 = 0, Q = 1, Q = 0, mch th mch b cch ly khi xung P.

P'

ch

.c
V1
V2 V3

.4

V in p trn t C khng tng t bin nn khi V1 t mc cao 3,6 V t bin xung 0,3 V th V2 t mc 0,7 V t bin xung -2,6 V. Bt u qu trnh np in ca t in C. V2 tng dn ln. Khi V2 Tng ln n ngng thng 0,6 V th sinh ra qu trnh phn hi dng sau:

0, Q = 1. Tip t in C phng in, V2 dn dn hi phc v 0,7 V. Hnh 6-16 ch ra gin

xung ca mch a hi i h TTL vi gi thit thi gian tr truyn t ca cc cng v b o pha u bng tpd. rng xung ra c tnh theo cng thc TW = 0, 7 RC . Mch dao ng a hi i c

thit k sn trong mt s h IC TTL nh 74LS121, 74LS123 bng cch thay i cc gi tr t v tr mc ngoi s cho cc xung li ra mong mun.

Qu trnh ny lm mch nhanh chng tr v trng thi n nh ban u V3 = 0 , V1 = 1, Q =

te

Hnh 6-15. S nguyn l mch a hi i h TTL

V2 V3 V1 Q

om .v
E C =5V
Q Q

trng thi tm n nh. Do Q = 0 kho cng 4, nn sau khi b kch thch bi sn dng xung P

133

Chng 6: Mch pht xung v to dng xung

V1

V3

.c
6.4. IC NH THI

B nh thi 555 c s dng rt rng ri trong cc b dao ng a hi, a hi i, v cc b so snh v.v Hnh 6-17 l s khi nguyn l ca IC nh thi ny, trong chc nng ca cc chn c ch ra trong bng sau:
Chn 1 2 3 4 Chc nng Chn 5 6 7 8 Chc nng in p iu khin Chn ngng u phng in Ngun - Vcc

Bng chc nng ca IC 555 TH X 2 > EC 3 2 < EC 3 X 134

.4

t - GND u ra Xo - Reset

Chn kch thch

te
R L
H H H OUT L L H

Hnh 6-16. Gin xung ca mch dao ng a hi i TTL vi gi thit tr ca cc cng l tpd.

TRIG X 1 > EC 3 1 > EC 3 1 > EC 3

ch
DIS

Thng Thng

Khng i Khng i Ngt

om .v
t (t pd )

V2

Chng 6: Mch pht xung v to dng xung

8
5K

5 6
5K

4 +
B iu khin Trig

So snh 1

+ 2 5K

Hnh 6-17. S khi nguyn l ca IC nh thi 555 Mt vi ng dng ca IC nh thi 555 1) Trig Schmitt

Hnh 6-18 l s nguyn l ca trig schmitt dng IC 555. Vi s ny ngng trn VT + = 2 EC1 v ngng di VT = 1 EC1 . chnh lch in p 3 3 V = VT + VT = 1 EC1 . Nu a in p vo u vo C-V th c th iu chnh c VT+, 3 VT- v V.

.4

te
R1

ch
E C1
E C2
R4

.c

VI
R3

R2

Hnh 6-18. Mch trig Schmitt dng IC 555

om .v
VO2
VO1
135

Tng cng sut li ra

So snh 2

Chng 6: Mch pht xung v to dng xung

2) Mch a hi i

Hnh 6-19 l s nguyn l v gin thi gian ca mch a hi i dng IC 555, trong RC l mch nh thi. ko di xung li ra c xc nh bng cng thc TW RC ln 3 1,1RC . Mch dao ng a hi i ny yu cu rng xung li vo nh hn rng xung li ra, nu n ln hn th yu cu dng thm mch vi phn li vo.

VI
VC

EC
2E C / 3

VO

TW

Hnh 6-19. Mch a hi i dng IC 555 v dng sng 3) Mch a hi

EC R1

VC

te
R2 VC

0,01 F

ch
2E C / 3 EC
0

VO

.c
TM1

2E C / 3

.4
1, 43 ( R1 + 2 R2 )C

VO

Nh ta thy xung li ra c lp y ph thuc vo c in tr R1 v R2 v khng th to ra xung vung vi lp y bng 50% thng qua vic thay i gi tr R1 v R2. c c xung vung vi lp y bng 50%, ngi ta s dng mch c thm 2 diode khi tr phng v 136

Hnh 6-20 l s mch a hi v dng sng, in tr R1, R2 v t in C ng vai tr l mch nh thi. Chu k ao ng ca tn hiu li ra c xc nh thng qua thi gian phng v np ca t in C nh sau:

TM 1 = ( R1 + R2 ) C ln 2 = 0, 7 ( R1 + R2 ) C

TM 2 = R2C ln 2 = 0, 7 R2C
T = TM 1 + TM 2 = 0, 7 ( R1 + 2 R2 ) C

f = 1/ T =

Hnh 6-20. Mch a hi dng IC 555 v dng sng

om .v
TM2

EC

Chng 6: Mch pht xung v to dng xung np in cho T c th thay i c lp v to ra xung mong mun. Hnh 6-21 l s nguyn l ca mch a hi dng IC 555 m lp y c th thay i c.

EC
8 5 4 7

R1 R2
VC
C

0,01 F
3

555
VO
1

6 2

Hnh 6-21. Mch a hi iu chnh c lp y xung dng IC 555

TM TT

CU HI N TP

Cch mch pht xung v to dng xung trn y, ngoi dng lm xung ng h ra cn c ng dng vo cng rng ri trong cc h thng xung - s. B dao ng a hi thng dng lm b to xung chun thi gian v chun tn s. Mch n n thng dng nh thi v lm tr xung. Trig Schmit ngoi ng dng to dng xung cn ng dng so snh mc v gim st mc

1. Trong mch dao ng a hi c bn dng cng NAND h TTL, hnh 6-1, nu gi tr tr in tr Rf1 = 5*Rf2 = 10 k, gi tr C1 = C2 = 1 F th mch c hot ng khng? ng tn hiu tng i li ra s nh th no?

.4

Hnh 6-1. B dao ng a hi cu trc bng cng NAND

te

Mch to dng xung khng t ng pht xung nhng c th bin tn hiu u vo hnh dng khc thnh xung vung theo yu cu ca mch s. Trong s mch to dng xung, chng ta tm hiu: trig Schmit v n n.

ch

Trong chng ny chng ta tm hiu cc mch to xung. Mch dao ng xung t kch khng cn tn hiu ngoi a vo; sau khi c cp ngun mt chiu mch t ng sinh ra xung vun. Thuc loi dao ng t kch ny c cc mch: b dao ng a hi c bn cng NAND h TTL, b dao ng vng, b dao ng thch anh, b dao ng a hi c bn CMOS.

.c

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n
137

Chng 6: Mch pht xung v to dng xung

a. Li ra lun mc logic thp b. Li ra lun mc logic cao c. Tn hiu li ra l xung vung vi lp y nh hn 50% d. Tn hiu li ra l xung vung c lp y ln hn 50%
2. Vi cu hi nh cu 1 v gi thit R1= 3 k, tnh tn s dao ng ca mch v v dng sng li ra.

a. f = 28 Hz b. f=28 Hz

v dng sng li ra c dng : v dng sng li ra c dng :

c. f=28 Hz v dng sng li ra c dng :

d. f=0 Hz

v dng sng li ra c dng :

a. Bin tn hiu li ra n nh b. Tn s tn hiu li ra n nh

c. Bin li ra c th iu chnh c d. Tn s li ra c th iu chnh c

a. Khng dao ng li ra lun thp b. Khng dao ng li ra lun cao c. C xung li ra nhng tn s thay i d. Tn s xung li ra khng thay i
5. c im quan trng nht ca trig Schmitt l g? 138

.4

4. Trong mch dao ng a hi dng thch anh nh hnh 6-6, nu khng c t C1, li ra ca thch anh c ni trc tip vi du vo ca cng NAND th hai th mch:

te

Hnh 6-6. Mch dao ng a hi thch anh

ch

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3. c im ni bt nht ca mch dao ng a hi dng thch anh l g?

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Chng 6: Mch pht xung v to dng xung

a. Tn s hot ng cao b. Tnh chng nhiu cao v n hot ng nh b so snh hai ngng c. Cng sut tiu th thp d. L b so snh mt ngng
6. Mch c s nguyn l nh hnh sau c chc nng nh th no?

a. B so snh mt ngng b. Trig Schmitt c. Mch dao ng a hi d. Mch dao ng a hi i

Vi

V+ Opam +

Hnh a.

te

ch

7. Vi mch in nh cu hi 6, nu tn hiu li vo c dng tn hiu nh hnh sau, tn hiu li ra nm hnh no. +V +V/2

+V +V/2 -V/2 -V

.4

+V +V/2 -V/2 -V

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-V/2 -V

Hnh c

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R R

+V +V/2 -V/2 -V
Hnh b +V +V/2

-V/2 -V
Hnh d

n
V-

Vo

139

Chng 6: Mch pht xung v to dng xung

a. Hnh a. b. Hnh b. c. Hnh c. d. Hnh d.

8. Chc nng ca mch a hi i l g?

a. L mch pht xung vung c. L mch dao ng a hi c mt trng thi n nh v mt trng thi tm n nh d. L mch pht xung iu ho
9. Trong mch a hi i kiu vi phn nh hnh 6-10, nu xung iu khin c rng ln hn xung a hi i li ra th :

a. Mch vn hot ng bnh thng b. Tn hiu li ra lun bng 0 c. Tn hiu li ra lun bng 1 d. Xung li ra bng xung li vo

a. Mch vn pht xung v tn s li ra ch ph thuc vo gi tr ca R1 v C c. Mch vn pht xung nhng tn s rt cao d. Khng c tn hiu li ra

140

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b. Xung li ra l xung vung c lp y l 50%

te

10. Trong mch a hi hnh 6-20, nu in tr R2 b ni tt th:

ch

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b. L mch dao ng a hi c chn iu khin

Chng 7: B nh bn dn

CHNG 7: B NH BN DN
GII THIU
B nh bn dn thay th cc loi b nh bng vt liu t. Cc tin b mi ca cng ngh bn dn trong thi gian gn y cung cp nhiu mch nh loi MSI v LSI c tn cy cao v gi thnh h. Vo u thp k 60 ca th k 20, gi thnh thng phm ca mt bit nh vo khong 2 USD. n nay (nhng nm u th k 21), gi thng phm ca 128 Mbyte vo khong 20 USD. Nh vy gi thnh thng phm ca mt bit nh sau khong 40 nm gim i khong 105.106 ln. B nh bn dn in hnh c cc t bo nh sp xp theo hnh ch nht, gn trong khi hp nh bng nha dng DIP (Dual in line package). T bo nh c bn l mt mch trig, transistor hay mch c kh nng tch tr in tch, t bo nh ny dng lu tr mt bit tin. Trong phn ny gii thiu mt s b nh bn dn c bn.

NI DUNG
7.1. KHI NIM CHUNG
7.1.1. Khi nim

7.1.2. Nhng c trng chnh ca b nh

Dung lng b nh l s bit thng tin ti a c th lu gi trong n. Dung lng cng c th biu th bng s t nh n bit. T nh n bit l s bit (n) thng tin m ta c th c hoc ghi ng thi vo b nh. V d: Mt b nh c dung lng l 256 bit; nu n c cu trc c th truy cp cng mt lcc 8 bit thng tin, th ta cng c th biu th dung lng b nh l 32 t nh x 8 bit = 32 byte.

7.1.2.2. Cch truy cp thng tin.

Truy cp trc tip, hay cn gi l truy cp ngu nhin (random access). cch ny, khng gian b nh c chia thnh nhiu nh. Mi nh cha c 1 t nh n bit v c mt a ch xc nh, m ho bng s nh phn k bit. Nh vy, ngi s dng c th truy cp trc tip thng tin nh c a ch no trong b nh. Mi b nh c k bit a ch s c 2k nh v c th ghi c 2k t nh n bit.

Cc b nh c th c mt trong hai cch truy cp thng tin.

7.1.2.1. Dung lng ca b nh.

.4

te

B nh l mt thit b c kh nng lu tr thng tin (nh phn). Mun s dng b nh, trc tin ta phi ghi d liu v cc thng tin cn thit vo n, sau lc cn thit phi ly d liu ghi trc s dng. Th tc ghi vo v c ra phi c kim sot cht ch, trnh nhm ln nh nh v chnh xc tng v tr nh v ni dung ca n theo mt m a ch duy nht.

ch

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141

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Chng 7: B nh bn dn
Truy cp lin tip (serial access) hay cn gi l kiu truy cp tun t. Cc a t, bng t, trng t, thanh ghi dchc kiu truy cp ny. Cc bit thng tin c a vo v ly ra mt cch tun t. 7.1.2.3. Tc truy cp thng tin.

y l thng s rt quan trng ca b nh. N c c trng bi thi gian cn thit truy cp thng tin. Thi gian truy cp thng tin cc b nh truy cp kiu trc tip gm thi gian tm a ch ca nh v thi gian c/vit thng tin trn . Thi gian truy cp thng tin ph thuc ch yu vo cng ngh ch to. Vi cng ngh MOS th thi gian truy cp khong 30 n vi trm ns.

7.1.3. Phn loi

B NH BN DN

B nh c nh ROM

ch
B nh bn c nh

.c
B nh c/vit EEPROM SRAM DRAM

MROM

PROM

B nh c th c/ vit nhiu ln c gi l RAM (Random Access Memory) gm hai loi: b nh RAM tnh-SRAM (Static RAM) thng c xy dng trn cc mch in t trig v RAM ng-DRAM (Dynamic RAM) c xy dng trn c s nh cc in tch t in; b nh ny phi c hi phc ni dung u n, nu khng ni dung s mt i theo s r in tch trn t. Gia ROM v RAM c mt lp cc b nh c gi l EPROM (Erasable PROM), d liu trong c th xo c bng tia cc tm v ghi li c, EEPROM (Electric EPROM) c th xo c bng dng in. Cc loi ny cn c gi l b nh bn c nh. Cc b nh DRAM thng tho mn nhng yu cu khi cn b nh c dung lng ln; trong khi khi cn c tc truy xut ln th phi dng cc b nh SRAM c gi thnh t hn. Nhng c hai loi ny u c nhc im l thuc loi bay hi (volatile), thng tin s b mt i khi ngun nui b 142

Da trn thi gian vit v cch vit, c th chia thnh b nh c nh, b nh bn c nh v b nh c/vit c. B nh c ni dung c vit sn mt ln khi ch to c gi l b nh c nh v c k hiu l ROM (Read Only Memory). Sau khi c vit (bng mt n-mask) t nh my th ROM loi ny khng vit li c na chnh l MROM. PROM l mt dng khc, cc bit c th c vit bng thit b ghi ca ngi s dng trong mt ln (Programmable ROM).

.4

te
EPROM

om .v

cc b nh truy cp kiu tun t, thi gian truy cp ph thuc vo v tr ca thng tin cn truy cp trong tp tin (file). i vi cc bng t, a t thi gian truy cp ca n c nh ngha l thi gian trung bnh hoc cc i truy cp mt thng tin v nm trong khong vi msec n nhiu sec.

Chng 7: B nh bn dn ngt. Do vy cc chng trnh dng cho vic khi ng PC nh BIOS thng phi np trn cc b nh ROM.
7.1.4. T chc ca b nh

B nh thng c t chc gm nhiu vi mch nh c ghp li c di t v tng s t cn thit. Nhng chip nh c thit k sao cho c y mt s chc nng ca b nh nh: Mt ma trn nh gm cc nh, mi nh ng vi mt bit nh. Mch logic gii m a ch nh. Mch logic cho php c ni dung nh. Mch logic cho php vit ni dung nh.

Cc b m vo, b m ra v b m rng a ch.

Ma trn nh l 128 x 128, nh vy c 128 = 27 t vt l. Mt t vt l c chn bi 7 ng a ch t A0 n A6. B gii m hng chn 1 hng t 128 hng. Mt t vt l c chia thnh 128/8 = 16 nhm 8 bit. Nhm th nht cha nhng bit c trng s cao nht ca 16 t logic. Nhm th hai cha cc bit cao tip theo ca 16 t logicNhm cui cng cha nhng bit thp nht ca 16 t logic, do S = 16. Nh vy, nhng b gii m ct gm 8 b hp knh mt ng t 16 ng cung cp mt t locgic ra 8 bit. Nhng a ch t A7 n A10 iu khin cc b gii m ct. Trng hp c bit khi s phn t trong mt t vt l bng sos bit trong mt t vt l th l b nh t chc theo bit c ngha l mi t logic c di 1 bit.

V d s ROM dung lng 2048 x 8 (2048 t, mi t cha 8 bit) t chc gii m hai bc nh hnh 7- 1.

.4

Kch thc ca phn gii m a ch s gim i khi t chc ma trn nh v phn logic chn t cho php gii m hai bc. Ma trn nh s dng gii m hai bc ng vi t vt l v t logic. T vt l bao gm s lng bit trong mt hng ca ma trn. T logic bao gm s lng bit tng ng vi mt t logic c nhn bit v gi ra cng mt lc. Cn hai b gii m: mt b gii m hng chn mt t vt l v mt b gii m ct gm c mt vi mch hp knh chn mt t logic t mt t vt l chn. Mt t vt l c chia thnh S t logic. B gii m hng l b gii m chn 1 t W m B = W/S v b chn ct cha B b hp knh mt ng t S.

te

ch

.c

Cch t chc n gin nht l t chc theo t (word organized) vi s chn tuyn tnh. Mt ma trn nh nh vy c di ca ct bng s lng t W v di ca hng bng s lng bit B trong mt t. B chn t phi gii m 1 t W, ngha l gii m c mt u ra duy nht cho mt t trong b nh. Phng php ny c thi gian truy nhp ngn nhng cn mt b gii m ln khi tng s t ln, do lm tng gi thnh sn phm.

om .v

n
143

Chng 7: B nh bn dn

7 A0-A6

m vo

Gii m hng 1 t 128

128

Ma trn ROM 128 x 128 bit 128

4 A7-A10

8 b gii m ct 1 t 16 8

CS

m ra 8 07,,,00

Hnh 7-1. Mt v d v gii m hai bc cho ma trn ROM 128 x 128

Cc b m ra m bo cc mc logic mong mun v cung cp dng in, ngoi ra n cn c u ra collector h hoc 3 trng thi cho php ni chung u ra ca mt vi chip vi nhau. B m ra c iu khin bi mt hay nhiu u vo nh chn mch CS (Chip Select), cho php m CE (Chip Enable) hay cho php m u ba trng thi OE (Output Enable).

7.2. DRAM
7.2.1. Cu to ca DRAM

Mt nh ca DRAM gm c mt transistor trng MOS c tr li vo rt ln v mt t in C l linh kin lu tr mt bit thng tin tng ng vi hai trng thi c hoc khng c in tch trn t.

Nu CAS mc tch cc thp th DRAM nhn c a ch t vo n v s dng nh a ch ct.

Nu RAS mc tch cc thp th DRAM nhn c a ch t vo n v s dng nh a ch hng.

T in in cc Lp xit n- Ngun Vng lu gi in tch

.4
Ca

Cc nh c xp xp theo hng v ct trong mt ma trn nh. a ch nh c chia thnh hai phn: a ch hng v ct. Hai a ch ny c c vo b m mt cch ln lt. X l kiu ny c gi l hp knh, l do l gim kch thc b gii m, tc l gim kch thc v gi thnh vi mch. Qu trnh dn knh a ch ny c iu khin bi cc tn hiu RAS (Row Access Strobe) v CAS (Column Access Strobe).

te
Transistor

ch
n- Mng

.c
Lp xit Tra C bn dn loi p WL BL BL

Hnh 7-2. Cu to mt nh ca DRAM

144

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Chng 7: B nh bn dn Transistor hot ng nh mt cng tc, cho php np hay phng in tch ca t khi thc hin php c hay vit. Cc ca (Gate) ca transistor c ni vi dy hng (cn gi l dy tWL-Word Line) v cc mng (Drain) c ni vi dy ct (cn c gi l dy bit BL hoc BL Bit Line), cc ngun (Source) c ni vi t in. in p np trn t tng i nh, v th cn s dng khuch i nhy trong mch nh. Do dng r ca transistor nn nh cn c np li trc khi in p trn t thp hn mt ngng no . Qu trnh ny c thc hin nh mt chu k lm ti (refresh), khi in p trn t c xc nh ( trng thi 0 hay 1) v mc in p logic ny c vit li vo nh. Mt s loi chip DRAM thng gp l: TMS 4116: c dung lng 16k x 1 bit; 41256 c dung lng 256k x 1 bit. Thi gian truy cp thng tin khong 150 nsec, cng sut tiu th khong 280 mW khi lm vic (khi ch = 28 mW)

7.3. SRAM

Mt nh ca SRAM gi thng tin bi trng thi ca mch trig. Thut ng tnh ch ra rng khi ngun nui cha b ct th thng tin ca nh vn c gi nguyn. Khc vi nh DRAM, y nh trig cung cp mt tn hiu s mch hn nhiu v c cc transistor trong cc nh, chng c kh nng khuch i tn hiu v do c th cp trc tip cho cc ng bit. Trong DRAM, s khuch i tn hiu trong cc b khuch i cn nhiu thi gian v do thi gian truy nhp di hn. Khi nh a ch trong cc trig SRAM, cc transistor b sung cho cc trig, cc b gii m a chcng c i hi nh DRAM.

.4
Tra

te
VCC
Tra
Trs Trs

ch
BL

Hnh 7-3 l v ca IC 41256 dung lng 256k x 1 bit. Mch cn 18 bit a ch m ho cho cc a ch hng v ct; nhng trn v ch c Hnh 7-3. IC 41256 9 ng a ch t A0 n A8. Hai chn RAS, CAS hot ng mc cao, dng iu khin 9 bit a ch trn chip ti b gii m a ch hng hay ct.

.c
WL

WL
BL

Hnh 7-4. Cu to mt nh ca SRAM v DRAM

Nh trong DRAM, cc ca ca transistor c ni vi ng t v cc mng ni vi cp ng bit. Nu s liu c c t nh, khi b gii m hng kch hot ng dy t WL tng ng. Hai transistor T dn v ni trig nh vi cp dy bit. Nh vy hai li ra Q v Q c 145

om .v
Tra C BL BL

Chng 7: B nh bn dn ni vi cc ng bit v cc tn hiu c truyn ti b khuch i cui ng dy ny. V in th chnh lch ln nn x l khuch i nh vy s nhanh hn trong DRAM (c 10 ns hoc ngn hn), do chip SRAM cn a ch ct sm hn nu thi gian truy nhp khng c gim. Nh vy SRAM khng cn thc hin phn knh cc a ch hng v ct. Sau khi s liu n nh, b gii m ct chn ct ph hp v cho ra tn hiu s liu ti b m s liu ra v ti mch ra. Vit s liu c thc hin theo cch ngc li. Qua b m vo v b gii m ct, s liu vit c t vo b khuch i ph hp. Cng lc b gii m hng kch hot ng dy t v lm transistor T dn. Trig a s liu c lu tr vo cp dy bit. Tuy vy, b khuch i nhy hn cc transistor nn n s cp cho cc ng bit mt tn hiu ph hp vi s liu vit. Do , trig s chuyn trng thi ph hp vi s liu mi hoc gi gi tr c lu tr ph thuc vo vic s liu vit trng vi s liu lu tr hay khng. Mt s IC DRAM thng gp l 2148, 2114-2 ca hng Intel. Dung lng 1k x 4 bit. Thi gian truy cp thng tin khong 200 ns, cng sut tiu th 525 mW. IC TMS 4016 dung lng 2k x 8 bit. IC HM 6116, h CMOS, dung lng 2kbyte, thi gian truy cp l 120 nsec, cng sut tiu th khi lm vic l P = 180 mW (khi ch W). Hnh 7-5 gii thiu IC 6264, dung lng 8 kbyte, v bng iu kin thao tc ca n.

te
CS
H L L L

Phng thc hot ng

.4

ch
Hnh 7-5. S chn ca SRAM 6264

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CS
X H H H

Khng c chn

c nhng khng xut d liu

Ghi

7.3. B NH C NH - ROM
Cc chip RAM khng thch hp cho cc chng trnh khi ng do cc thng tin trn b mt khi tt ngun. Do vy phi dng n ROM, trong cc s liu cn lu tr c vit mt ln theo cch khng bay hi nhm gi c mi.
7.3.1. MROM

146

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WE
X H H L

OE
X L H L

Chng 7: B nh bn dn ROM lp trnh theo kiu mt n c gi l MROM. N c ch to trn mt phin silic theo mt s bc x l nh quang khc v khch tn to ra nhng tip gip bn dn c tnh dn in theo mt chiu (nh diode, transistor trng). Ngi thit k nh r chng trnh mun ghi vo ROM, thng tin ny c s dng iu khin qu trnh lm mt n. Hnh 7-6 l mt v d n gin v s MROM dng diode.

Cc dy hng (i

Cc dy bit

7.3.2. PROM

7.4. B NH BN C NH
7.4.1. EPROM (Erasable PROM)

S liu vo c th c vit vo bng xung in nhng c lu gi theo kiu khng bay hi. l loi ROM c th lp trnh c v xa c. Hnh 7- 7 ch ra cu trc ca mt transistor dng lm mt nh gi l FAMOST (Floating gate avalanche injection MOS transistor).

Trong nh dng transistor ny, cc ca c ni vi ng t, cc mng c ni vi ng bit v cc ngun c ni vi ngun chun c coi l ngun cho mc logic 1. Khc vi transistor MOS bnh thng, transistor loi ny cn c thm mt ca gi l ca ni (floating gate); l mt vng vt liu c thm vo vo gia lp cch in cao nh hnh 7-7. Nu ca ni khng c in tch th n khng nh hng g n cc ca iu khin v transistor hot ng nh bnh thng. Tc l khi dy t c kch hot (cc ca c in th dng) th transtor dn, cc mng v ngun c ni vi nhau qua knh dn v dy bit c mc logic 1. Nu ca ni c cc in t trong vi in tch m th chng s ngn trng iu khin ca ca ca v d dy 147

PROM cng gm c cc diode nh MROM nhng chng c mt y to cc v tr giao nhau gia dy t v dy bit. Mi diode c ni vi mt cu ch. Bnh thng khi cha lp trnh, cc cu ch cn nguyn vn, ni dung ca PROM s ton l 0. Khi nh v n mt bit bng cch t mt xung in li ra tng ng, cu ch s b t v bit ny s bng 1. Bng cch ta c th lp trnh ton b cc bit trong PROM. Nh vy, vic lp trnh c th c thc hin bi ngi s dng ch mt ln duy nht, khng th sa i c.

.4

te

ch

C hai cng ngh MOS v lng cc c dng ch to MROM. Thi gian truy nhp ca b nh lng cc khong t 50 90 ns, b nh MOS lu hn khong 10 ln. Do ROM lng cc nhanh hn v c kh nng kch hot tt hn trong khi mch nh MOS cng dung lng c kch thc nh hn v tiu th nng lng t hn.

.c

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Ch giao nhau gia cc dy t (hng) v cc Hnh 7-6. MROM diode dy bit (ct) to nn mt phn t nh ( nh). Mt diode c t ti (hnh v) s cho php lu tr s liu 0. Ngc li nhng v tr khng c diode th s cho php lu tr s liu 1. Khi c mt t s liu th i ca ROM, b gii m s t dy t xung mc logic thp, cc dy cn li mc cao. Do vy ch nhng diode ni vi dy ny c phn cc thun, do n s dn lm cho in th li ra trn cc dy bit tng ng mc logic thp, cc dy bit cn li s gi mc cao.

Chng 7: B nh bn dn t c kch hot th cng khng th pht ra trng u mnh vi cc ca iu khin lm thng transistor. Lc ny ng bit khng c ni vi ngun chun v nh coi nh c gi gi tr 0.
Ngun Ca Mng

hv

hv

ID
0 1 Xo Lp xit n- Mng

Ca iu khin Lp xit n- Ngun Ca ni

- - - - -

Lp trnh

Hnh 7-7. Cu trc ca mt EPROM

7.4.2. EEPROM (Electrically Erasable PROM)

Vic np cc in t cho ca ni c thc hin nh cch EPROM. Bng mt xung in tng i di, cc in tch mang nng lng cao c pht ra trong s thm qua lp ca xit v tch t trong ca ni. xo EEPROM, mt lp knh mng mng xit gia vng ca ni tri xung di v cc mng gi vai tr quan trng. Cc lp cch in khng th l l tng c, cc in tch c th thm qua lp phn cch vi mt xc sut thp. Xc sut ny tng ln khi b dy ca lp gim i v in th gia hai in cc hai mt lp cch in tng ln. Mun phng cc in tch trong vng ca ni mt in th (-20 V) c t vo cc ca iu khin v cc mng. Lc ny cc in t m trong ca ni c chy v cc mng qua knh mng mng xit v s liu lu gi c xo i. iu lu l phi lm sao cho dng in tch ny chy khng qu lu v nu khng vng ca ni ny li tr nn tch in dng lm cho hot ng ca transistor khng c trng thi bnh thng (mc nh 1).

148

Ca s thch anh c gi thnh kh t v khng tin li nn nhng nm gn y xut hin cc chip PROM c th xo s liu bng phng php in. Cu trc ca nh ging nh hnh 78.

.4

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xo cc thng tin, tc l lm mt cc in tch in t trong vng ca ni, phi chiu nh sng t ngoi UV vo chp nh. Lc ny, nhng in t hp th nng lng v s nhy ln cc mc nng lng cao v ri khi ca ni ging nh cch m chng thm nhp vo. Trong chip EPROM c mt ca s lm bng thu tinh thch anh ch cho nh sng t ngoi i qua khi cn xo s liu trong b nh.

ch

.c

Vic np cc in t vo vng ca ni, tc l to ra cc nh mang gi tr 0 c thc hin bi xung in c di c 50 ms v ln + 20 V t gia cc ca va cc mng. Lc nhng in tch mang nng lng ln s i qua lp cch in gia v ca ni. Chng tch t trong vng ca ni v c gi y sau khi xung lp trnh tt. l do ca ni c cch in cao vi xung quanh v cc in t khng cn nng lng sau khi lnh i, c th vt ra ngoi lp cch in na. Chng s c gi y trong mt thi gian rt di (t nht l 10 nm).

om .v

bn dn loi p

v0

n
v1

vGS

Chng 7: B nh bn dn

Hnh 7-8. Cu trc ca EEPROM

Cc chip ROM hin nay c thi gian truy nhp t 120 ns n 150 ns di hn nhiu thi gian trong cc chip nh RAM.
7.4.3. a cng silicon- B nh FLASH

Phn chnh l mng nh bao gm cc nh FAMOST nh c m t mc trn. Ging nh SRAM, b nh flash khng dn phn knh a ch. Cc b gii m hng v ct chn mt ng t v mt hoc nhiu cp ng bit. S liu c c a ra ngoi b m s liu I/O hoc c vit vo nh c nh a ch bi b m ny qua cng I/O. X l c c thc hin vi in th MOS thng thng l 5V. lp trnh mt nh, n v iu khin flash t mt xung in th ngn c 10 s v 12 V gy nn mt s chc thng thc l vo transistor nh np vo ca ni. Mt chip nh flash 1 Mb c th c lp trnh trong khong 2 sec, nhng khc vi EEPROM vic xo c thc hin tng chip mt. Thi gian xo cho ton b b nh flash khong 1 sec. X l c, lp trnh v xo c iu khin bi cc lnh c di 2 byte c b x l vit vo cc thanh ghi lnh ca mch iu khin flash.

.4

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Trong nhng nm gn y, mt loi b nh khng bay hi mi xut hin trn th trng, thng c s dng thay th cho cc a mm v cng trong nhng my tnh. l b nh flash. Cu trc ca chng c bn nh EEPROM, ch c lp knh xit cc nh mng hn. Do vy ch cn in th c 12 V l c th cho php thc hin 10 000 chu trnh xo v lp trnh. B nh flash c th hot ng gn mm do nh DRAM v SRAM nhng li khng b mt s liu khi b ct in. Hnh 7- 9 ch ra s khi ca n.

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n
149

Chng 7: B nh bn dn

VPP
iu khin

WE CE
OE

Chuyn mch in th xo

Thanh ghi lnh B nh thi Chuyn mch in th chng trnh

Gii m ct

D liu vo

Vi cc my tnh c tc nhanh (trn 33MHz), cn phi xen cc trng thi i khi truy xut d liu ti cc DRAM r tin nhng c thi gian thm nhp chm (60-120ns). iu ny lm gim hiu sut ca my. C th gii quyt bng cch dng cc SRAM c thi gian thm nhp ngn hn (20-25 ns, thm ch 12 ns) nhng gi thnh li rt t. B nh Cache kt hp c cc li im nhanh ca SRAM v r ca DRAM. Gia CPU v b nh chnh bng DRAM, ngi ta xen vo mt b nh SRAM nhanh c dung lng nh bng 1/10 hoc 1/100 ln b nh chnh gi l cache; di s iu khin ca mch iu khin cache, b nh ny s lu tr tm thi cc s liu thng c gi v cung cp n cho CPU trong thi gian ngn. Cache cha cc thng tin mi va c CPU s dng gn y nht. Khi CPU c s liu n s a ra mt a ch ti b iu khin cache. Sau mt trong hai qu trnh sau s xy ra: 150

7.4.3. B nh CACHE

Nhc im ca b nh flash l ch c th xo theo kiu ln lt tng chip hoc ln lt tng trang.

Mc ch s dng chnh ca b nh flash l thay th cho cc a mm v a cng dung lng nh. Do n l mch tch hp nn c u im l kch thc nh v tiu th nng lng thp, khng b nh hng ca va p. Cc a cng cht rn da trn c s cc b nh flash c li th v cng sut tiu th cng nh gi thnh c dung lng ti vi Mbyte. Cc card nh loi ny c u im l khng gp phi vn mt thng tin nh trng hp RAM CMOS khi pin Ni-Cd b hng. Thi gian lu tr thng tin trong b nh flash t nht l 10 nm, thng thng l 100 nm, vi khong thi gian ny th cc a mm v cng b hng ri.

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Hnh 7-9. S b nh FLASH

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Ma trn t bo nh Ca vo ra m vo ra d liu

a ch

m a ch

Gii m hng

Chng 7: B nh bn dn Cache hit: nu a ch c sn trong RAM cache. Cache miss: ngc li, nu a ch khng c sn trong RAM cache.

Nh vy, cache hit t l vi truy xut thng tin c sn trong b nh cache SRAM, cn cache miss li t l vi truy xut thng tin c trong b nh chnh l cc DRAM.

SRAM Cache

B iu khin CACHE

Hnh 7-10. Nguyn l ca Cache

7.5. M RNG DUNG LNG B NH

Tng di nh, nhng khng lm tng s lng t nh. Tng s lng t nh nhng khng lm tng di t nh.

7.5.1 M rng di t

Trn mt chp nh, c th c c 1 n mt s hu hn li ra, thng l 4 hoc 8 bit. Mun c di t ln hn, chng hn t 4 ln 8 A0 hoc 16 bit, ta tin hnh ghp nhiu chp nh nh BUS a ch ch hnh 7-10 i vi RAM. i vi ROM cch An-1 lm cng tng t, ch khc trong trng hp ny, c th khng c li vo R/W.

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Tng c s lng v di t nh.

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Cc vi mch nh bn dn ch c dung lng xc nh. Mun c b nh c dung lng ln hn, ta tm cch ghp nhiu vi mch nh nhm mt trong ba mc ch sau:

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R/W CS

om .v
RAM

CPU

DRAM trong b nh chnh

7.5.2 M rng dung lng

Mun m rng dung lng, ta cng ghp CS nhiu chp li vi nhau. Nh bit, dung lng c lin quan n s li vo a ch (C = 2N x di t, vi N l s li vo a ch). C tng 1 chp th cn c thm mt li vo a ch. Khc vi trng hp m rng di t, khi m rng dung lng cc li vo/ra d liu D v

D0 BUS d liu Dn-1 BUS d liu

Hnh 7-10. S m rng di t.

n
R/W CS

RAM

II

151

Chng 7: B nh bn dn R/ w c ni song song. Mt phn dung lng c tr vo mi chp. S phn chia ny da trn c s t hp a ch vo v li vo iu khin. Hnh 7-11 l mt s v d.
A0 A11 A0 IC 1 A1 2k
CS 1

A0 IC 2 A1 2k

A0 IC 3 A1 2k

A0 IC 4 A1 2k

A12 A13

CS2

B gii m vo 2 ra 4

CS3

CS4

Hnh 7-11. Phng php m rng dung lng.

thc hin php m rng ta phi s dng mt s li vo a ch dnh ring cho b gii m (thng l cc a ch c trng s cao). s trn ta chn 2 a ch A12 v A13 gii m. Do ta c th nhn c 4 gi tr ra tng ng. Cc gi tr ny tc ng ln cc li vo CS m tun t cc IC nh. Cc IC nh ny c th lm ROM hoc RAM hoc c hai l ty chn. Tun t m cc IC theo A12, A13 nh ch ra bng hot ng sau.

0 1 1

1 0 1

te

Cc chip RAM khng thch hp cho cc chng trnh khi ng do cc thng tin trn b mt khi tt ngun. Do vy phi dng n ROM, trong cc s liu cn lu tr c vit mt ln theo cch khng bay hi nhm gi c mi. Trong nhng nm gn y, mt loi b nh khng bay hi mi xut hin trn th trng, thng c s dng thay th cho cc a mm v cng trong nhng my tnh. l b nh flash. Cu trc ca chng c bn nh EEPROM, ch c lp knh xit cc nh mng hn. Vi cc my tnh c tc nhanh (trn 33MHz), cn phi xen cc trng thi i khi truy xut d liu ti cc DRAM r tin nhng c thi gian thm nhp chm (60-120ns). iu ny lm gim hiu sut ca my. C th gii quyt bng cch dng cc SRAM c thi gian thm nhp 152

Trong chng ny chng ta trnh by nguyn l cu to, cc tnh nng c bn ca cc loi b nh bn dn: ROM, PROM, EPROM, EEPROM, SRAM, DRAM, FLASH, CACHE.

TM TT

K thut ny thng c ng dng trong cc h thng vi x l, ph bin nht l cc my vi tnh. Phng php ny khng ch cho php m rng dung lng, m cn to ra s phn vng nh. Ch cn ba a ch gii m c th to ra c 8 vng nh vi dung lng ty thuc cc chp thnh phn.

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ch
IC II IC III IC IV

CS1 CS2 CS3 CS4

IC I

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A13

A12

CS

IC m

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Khong a ch 000016 - 0FFF16 100016 - 1FFF16 200016 - 2FFF16 300016 - 3FFF16

Chng 7: B nh bn dn ngn hn (20-25 ns, thm ch 12 ns) nhng gi thnh li rt t. B nh Cache kt hp c cc li im nhanh ca SRAM v r ca DRAM. Trong chng ny cn gii thiu cch m rng dung lng v di t ca b nh bn dn.

CU HI N TP
1. B nh ROM l b nh: a. b. c. d. Ch c th c. Ch c th vit.

2. B nh RAM l b nh: a. b. c. d. Ch c th c. Ch c th vit. C th va c va vit. Khng c phng n no ng.

3. Linh kin lu gi bit thng tin ca DRAM l: a. b. c. d. Transistor. Trig. T in. Diode.

4. Linh kin lu gi bit thng tin ca SRAM l:

b. c.

d.

5. MROM c ch to bi cng ngh : a. b. c. d. Lng cc. MOS. Lng cc v MOS. Khng c phng n no ng.

6. PROM l loi ROM c th: a. b. Ch lp trnh c mt ln. Lp trnh c nhiu ln. 153

a.

Transistor. Trig.

T in. Diode.

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Khng c phng n no ng.

C th va c va vit.

Chng 7: B nh bn dn c. d. Lp trnh c v xo c. Khng c phng n no ng.

7. Linh kin lu gi bit thng tin ca EPROM l: a. b. c. d. Transistor lng cc. Transistor trng. T in. Diode.

a. b. c. d.

To cc nh mang gi tr 0. To cc nh mang gi tr 1. To cc nh mang gi tr 0 v 1. Khng c phng n no ng.

9. EEPROM l loi ROM c th: a. b. c. d. Ch lp trnh c mt ln.

Lp trnh c v xo c mt ln.

Lp trnh c v xo c nhiu ln. Khng c phng n no ng.

10. Mun xo d liu trong EEPROM th cn: a. b. c. d. Chiu tia t ngoi vo.

Cn t vo cc ca iu khin v cc mng mt in th c gi tr 20V.

C phng n trn u ng.

11. B nh FLASH l loi b nh:

154

a.

b. c.

d.

12. B nh FLASH l loi b nh c th thay th cho: a. b. c. d. a mm. a cng. mm v cng c dung lng nh. Khng c phng n no ng.

Mt d liu khi mt ngun nui. Khng mt d liu khi mt ngun nui. B mt dn d liu ngay c khi c ngun nui. Khng c phng n no ng.

Cn t vo cc ca iu khin v cc mng mt in th c gi tr - 20V.

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8. Trong EPROM, vic np cc in tch vo vng ca ni c ngha l:

Chng 8: Logic lp trnh (PLD)

CHNG 8: LOGIC LP TRNH (PLD)

GII THIU
Cc mch k thut s t hp v tun t c cp cc chng trc. Cc IC s rt a dng t thc hin cc php tnh k thut s cn bn n cc chc nng phc tp khc nh: b hp knh, phn knh, b cng, so snh, b m ho, gii m, b m Chng l cc IC s c chc nng c nh, tc l mi IC thc hin mt ch nng chuyn bit. Nhng linh kin ny c sn xut mt s lng ln p ng nhu cu ng dng phong ph. thit k mt mch, nh thit k c th chn t cc IC c sn ph hp nht cho mch in. Phn thit k ny c th c chnh sa p ng cc yu cu chuyn bit ca nhng linh kin ny. u im ca phng php ny l: 1. Chi ph pht trin thp.

2. Vn hnh nhanh xung quanh bn thit k.

Nhc im:

1. Cc yu cu v kch thc trong bng mch ln. 2. Yu cu v in ln.

khc phc nhng nhc im ca thit k bng cch s dng cc IC chc nng c nh, cc mch tch hp chuyn bit ng dng (ASIC-Aplication Specific IC) c pht trin. Cc ASIC c thit k p ng cc yu cu chuyn bit ca mt mch v c gii thiu bi mt nh sn xut IC. Cc thit k ny qu phc tp khng th thc hin bng cch s dng cc IC chc nng c nh c.

u im ca phng php ny l: 1. Gim thiu c kch thc thng qua vic s dng mc tch hp cao. 2. Gim thiu c yu cu v in. 3. Nu c sn xut theo mt quy m ln th chi ph gim ng k. 4. Vic thit k c thc thi di dng ny th hon ton khng th sao chp c.

Nhc im: 1. Chi ph pht trin ban u c th cc k ln. 155

4. Cc yu cu v chi ph b sung, khong trng, incn thit chnh sa bn thit k hoc trnh by cc tnh nng khc.

.4

3. Thiu tnh bo mt. (Cc bng mch c th b sao chp).

te

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3. Tng i d th nghim cc mch

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Chng 8: Logic lp trnh (PLD)

2. Cc phng php th nghim phi c pht trin v iu ny lm gia tng chi ph v cng sc. C mt phng php khc c cc u im ca hai phng php trn l s dng cc thit b logic c th lp trnh c (PLD). Mt thit b logic c th lp trnh l mt IC m ngi dng c th cu hnh chng c kh nng thc thi cc chc nng logic nh mong mun. y l mt chip LSI c cha mt cu trc bnh thng v cho php nh thit k to tu bin cho n dng cho bt k ng dng c bit no, tc l n c th c ngi dng lp trnh thc hin mt chc nng cn thit cho ng dng ca h. Cc PLD c cc u im sau:

3. Gim thiu c yu cu khong trng trn bng mch. 4. Gim thiu c yu cu v in. 5. Bo m tnh bo mt ca thit k. 6. Mch c kt cht li. 7. Tc o mch nhanh hn. 8. Mt tch hp cao.

9. Chi ph sn xut s lng ln thp.

NI DUNG

8.1. GII THIU CHUNG V LOGIC KH TRNH (PLD)

Vi mch lp trnh, vit tt l PLD (Programmable Logic Device), l loi cu kin in t c nhiu u im v hin nay ang c pht trin rt mnh. V nguyn l, chng c cu to rt ging vi PROM. Vic lp trnh cho PLD c th c thc hin bng cc cng ngh khc nhau, da trn c s b cu ch hoc chuyn mch. Tuy nhin, ng dng ca PLD li rt khc vi PROM. Mt PLD, c to thnh bng mt s cng AND, OR, XOR hoc c cc trig, c th thc hin nhiu hm Boole khc nhau.

156

Vi nhiu u im nh vy nn hin nay c mt s lng ln cc PLD c cc nh sn xut IC to ra vi nhiu tnh nng a dng v nhiu tu chn c sn nh thit k mch c th s dng mt cch ph bin. Cu trc v cc tnh nng a dng khc ca cc PLD nh ROM, cc mng logic lp trnh (PLA). Logic mng c th lp trnh (PAL), thit b logic c th lp trnh n gin (SPLD), v cc mng cng c th lp trnh trng (FPGA) s c cp y. Cng dng ca nhng thit b ny yu cu phi c thay i thit k truyn thng, mc du cc khi nim c bn vn c gi li khng i.

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PLD cng cho php nh thit k c nhiu phng tin linh ng hn th nghim vi cc bn thit k bi v chng c th c lp trnh li trong vi giy.

ch

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2. Chi ph pht trin thp.

1. Chu k thit k ngn.

Chng 8: Logic lp trnh (PLD)

8.2 SPLD
SPLD - cu kin logic kh trnh n gin. y l loi cu kin s c nhiu u im v cng c pht trin rt mnh. V nguyn l, chng c cu to rt ging vi PROM. Vic lp trnh cho SPLD c th c thc hin bng cc cng ngh khc nhau, da trn c s thc hin cc kt ni bng cch s dng cu ch hoc chuyn mch. Mt SPLD, c to thnh bng mt s mng cng AND, OR, XOR hoc c cc triger, c th thc hin nhiu hm Boole khc nhau. Cc SPLD u c cu to da trn mt trong hai dng cu trc chnh: mng logic kh trnh PLA (Programmable Logic Array) v logic mng kh trnh PAL (Programmable Array Logic).

u vo

PAL

u vo

u ra

Cng ngh PLD xut hin t rt sm vi cc cng ty nh Xilinx sn xut vi mch CMOS cng sut cc thp da trn cng ngh Flash. PLD da trn cng ngh Flash cho php lp trnh v xo vi mch nhiu ln bng in, nh tit kim c thi gian so vi xo vi mch bng tia cc tm.

8.3. CPLD (Complex PLD)

Cu trc PLA to ra s t hp ty gia cc cng AND v OR, cho mt logic cao nhng tc chm, s lng cu ch ln. V vy, sau ny ngi ta a ra mt kiu kin trc khc l logic mng kh trnh PAL (Programmable Aray Logic).

.4

Thnh phn c bn ca PLA l mt mng AND v mt mng OR lp trnh c. Mi mng AND, OR gm cc hng v cc ct lin kt vi nhau. Ti mi im giao gia hng v ct, c mt cu ch. Khi cu ch ng, ti im c kt ni gia hng v ct, khi cu ch ngt, ti khng c kt ni. Vic ng ngt cu ch c thc hin bng phn mm (do lp trnh vin hoc s dng cng c In- System Programming (ISP) lp trnh trn h thng).

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Hnh 8.1 - So snh gia PAL v PLA

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u ra

n
PLA

157

Chng 8: Logic lp trnh (PLD)

IO/Registers/Logic Interconnect IO/Registers/Logic

Thit b logic kh trnh phc hp (CPLD) c mt logic cao hn so vi cc PLD n gin nh xt trn (PLA v PAL). CPLD bao gm nhiu mch logic, mi mch c th coi l mt SPLD. Trong mt mch n ch thc hin cc chc nng logic n gin. Cc chc nng logic phc tp hn cn s lng khi nhiu hn, s dng ma trn lin kt chung gia cc khi to kt ni. CPLD thng dng iu khin ghp cng phc hp tc rt cao (5ns, tng ng vi 200 MHz). Kin trc c bn ca CPLD c minh ho trong hnh v 8.2. CPLD c cu trc ng nht gm nhiu khi chc nng "Function Block" c kt ni vi nhau thng qua mt ma trn kt ni trung tm "Interconnect Array". Mi khi function block gm c mt khi logic - gm cc hng tch AND v OR sp xp ging PLA hoc PAL, cho php thc hin cc hm logic t hp- v nhiu khi MC (Macrocell) c cha ti nguyn l cc Trig cho php xy dng cc thanh ghi v mch tun t. Phn li bn trong ca CPLD c ni ra bn ngoi thng qua cc khi vo ra I/O cho php thit lp chc nng cho cc chn ca IC c chc 158

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Hnh v 8.2 - Kin trc ca CPLD

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Chng 8: Logic lp trnh (PLD)

nng vo hoc ra hoc va l chn vo va l chn ra, ngoi ra cn c th thit lp cc chn I/O ny lm vic cc mc logic khc nhau, c in tr pull-up hoc pull-down ... Vi cu trc ng nht, gi thnh r, tnh nng kh mnh, d s dng CPLD v ang c s dng rt rng ri trong thc t, gip cho nh sn xut pht trin nhanh sn phm ca mnh vi gi thnh r. c bit hin nay cc hng pht trin cc h CPLD vi tnh nng rt mnh, cng sut tiu th thp, chng ang c s dng rt nhiu pht trin cc sn phm in t, vin thng, cng ngh thng tin, nht l trong cc thit b cm tay, di ng Trong thc t rt c nhiu loi CPLD khc nhau, ca cc hng khc nhau, v c pht trin vi nhiu chng loi, th h CPLD khc nhau. Cu to, dung lng, tnh nng, c im, ng dng ca mi loi CPLD cng rt khc nhau. Trong gio trnh ny khng i su trnh by cu to c th ca cc h CPLD, m ch trnh by kin trc chung n gin nht ca CPLD. Khi s dng c th loi CPLD no, ngi hc nn tham kho cc ti liu khc, nht l tham kho cc ti liu k thut c cung cp km theo cu kin do cc hng a ra. Cc hng in t ni ting trn th gii ang s hu, pht trin, cung cp cc loi cu kin CPLD l Xilinx, Altera

8.4. FPGA

Cu trc FPGA n gin gm cc t bo logic (Logic Cell), cc khi cch u nhau, lin kt nh cc ng kt ni c th thay i c theo yu cu ca ngi thit k. Ngha l ngi thit k c quyn thit k, lp trnh v thay i mch in. Hin nay, FPGA c mt kh cao, ln ti hng trm t cng v cu trc cng a dng, phc tp hn. Nhiu chc nng phc tp c tch hp sn tng hiu qu s dng FPGA. V d nh ngoi nhng khi t bo logic, nhiu h FPGA c tch hp thm cc khi chc nng nh cc b nhn cng, khi nh, PLL, thm ch c mt b vi x l mnh C hai loi FPGA c bn: loi lp trnh li c, da trn cng ngh SRAM v loi lp trnh mt ln. 159

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Hnh 8-3. Kin trc chung ca FPGA

te

ch

FPGA (Field Programmable Gate Array - Ma trn cng lp trnh c theo trng): c cu trc v hot ng phc tp hn CPLD. N c th thc hin nhng chc nng phc tp u vit hn CPLD. Nm 1985, cng ty Xilinx a ra tng hon ton mi, l kt hp thi gian hon thnh sn phm v kh nng iu khin c ca PLD vi mt v u th v chi ph ca GateArray. T , FPGA ra i. Hin nay, Xilinx vn l nh sn xut chip FPGA s mt trn th gii.

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Chng 8: Logic lp trnh (PLD)

Loi lp trnh li c (da trn SRAM):

-

SRAM xc nh cc kt ni SRAM nh ngha cc hm logic trong bng nh x (LUT- Look Up Table)

Loi lp trnh mt ln:

-

Kt ni dng b cu ch S dng cc cng logic truyn thng

nh iu khin b chn knh u ra

u vo

Bng LUT 4 u vo

Dng FPGA quan trng hn v c dng ph bin hn c l dng lp trnh li c, da trn SRAM. Trn thc t, FPGA SRAM c lp trnh li mi khi bt ngun, v FPGA l dng chip nh tm thi. Do , mi chip FPGA u cn c mt b nh PROM ni tip hoc mt b nh h thng. Trong t bo logic SRAM, thay v cc cng thng thng, ngi ta s dng bng nh x (LUT). Bng ny xc nh cc gi tr u ra da trn cc gi tr u vo, s dng xy dng cc hm logic t hp. Trong s T bo logic SRAM minh ho hnh v 8-3, 16 t hp khc nhau ca 4 u vo s xc nh gi tr ca u ra). Cc cc nh SRAM cng c s dng iu khin kt ni . 160

Chip FPGA lp trnh mt ln s dng phng php b cu ch (kt ni c to ra bng cch ng cu ch) to kt ni tm thi trong chip, do khng cn SPROM hoc cc phng tin khc np chng trnh vo FPGA. Tuy nhin, mi ln thay i thit k, phi b hon ton chip c i. T bo logic OTP tng t nh PLD vi cc cng v cc trig nh trc.

Hai dng ny khc nhau v quy trnh thc hin t bo logic v c ch c s dng to kt ni trong thit b.

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Hnh 8.4 - Cu trc ca logic cell n gin

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im kt ni

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nh iu khin im kt ni

Chng 8: Logic lp trnh (PLD)

8.5. SO SNH GIA CPLD V FPGA

CPLD FPGA

- Cu trc theo mng cc hng tch - Mng kt ni trung tm - Mt tch hp trung bnh - T l s chn I/O trn microcell ln

- Cu trc da vo LUT - Ma trn kt ni 2 chiu X-Y - Mt tch hp cao - T l s chn I/O trn microcell nh

- Cu trc ng nht

Cu trc khng ng nht

Nhiu ti nguyn: DLL (Delay_Locked Loop: Vng kho pha tr ), b nh, cc b nhn ng dng: m ho v gii m logic, cc my trng thi hay cc giao din bus chun (SPI, I2C, SMBus...), u im ni bt khi thit k cc mch logic nhiu u vo. - ng dng: PCI (Peripheral Component Interface), giao tip ni tip tc cao v cc b vi x l nhng ...., u th ni bt khi thit k phc tp, cn nhiu ti nguyn.

8.6. QUY TRNH THIT K CHO CPLD/FPGA

Trong thc t c rt nhiu hng in t trn th gii cung cp cc sn phm PLD v b cng c phn mm thit k i km. Mi h CPLD, FPGA ca cc hng c nhng quy trnh thit k khc nhau dnh cho chng, tuy nhin v c bn chng vn c quy trnh thit k chung nht inh. Khng mt tnh tng qut, ngi hc tip cn d dng hn, trong ti liu ny vic trnh by quy trnh thit k cho CPLD/FPGA c ly v d, c th ho cho CPLD/FPGA ca hng Xilinx Mt hng cung cp cc sn phm PLD s 1 th gii hin nay s dng b cng c phn mm thit k ISE.
8.6.1. Yu cu chung khi thit k vi CPLD/FPGA

8.6.1.1 Chn vi mch CPLD hoc FPGA ph hp

Khi pht trin cc h thng s s dng CPLD/FPGA bc u tin cn c thc hin l phn tch bi ton, la chn vi mch CPLD hoc FPGA ph hp. Vic chn c vi mch, cng ngh ph hp nht cho cc tiu chun thit k, c tin hnh theo cc yu cu sau:
Mt : l mt logic d tnh ca linh kin, c trng bi khi nim "s lng cng". S lng thanh ghi: Phi tnh c s thanh ghi cn cho b m, my trng thi, thanh ghi v b cht. S lng macrocell trong vi mch ti thiu phi bng s thanh ghi cn c.

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S lng chn vo/ra: phi xc nh vi mch thit k cn bao nhiu u vo, bao nhiu u

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- Cu hnh c lu li khi mt in, v - Cu hnh np vo SRAM, khi mt in s khng khng i trong qu trnh hot ng cn, cn c b nh cu hnh PROM, cu hnh c th c np ng trong qu trnh hot ng.

Chng 8: Logic lp trnh (PLD)

Yu cu v tc : Tuyn t hp nhanh nht s xc nh tpd (tr truyn trong vi mch, tnh theo ns). Mch tun t nhanh nht s xc nh tn s ti a ca vi mch (fMax). ng v: Phi xc nh vi mch cn gn nht hay ch s dng dng QFP thng thng. Hoc vi mch thit k thuc dng c lp chn cm, trong trng hp ny l vi mch PLCC. Cng sut thp: Phi xc nh sn phm s s dng ngun pin hay nng lng mt tri, thit k c yu cu cng sut tiu th thp hay khng, vn tn hao nhit c quan trng hay khng? Chc nng cp h thng: Phi xc nh bo mch c bao gm nhiu vi mch a mc in p hay khng, gia cc vi mch c phi chuyn mc hay khng, c yu cu sa dng xung ng b hay khng, c yu cu giao tip gia b nh v b vi x l hay khng?

Lp trnh ngay trn h thng

Lp trnh bn ngoi

Cu hnh ca CPLD c np vo FLASH nn khi mt in cu hnh khng b mt i, trong khi cu hnh khi hot ng ca FPGA c ghi vo SRAM nn s mt i khi mt in, v vy cn s dng FPGA v kt hp vi PROM lu cu hnh ph hp, mi khi bt ngun, cu hnh s np t ng t PROM vo FPGA. C th s dng PROM ni tip hoc song song, tuy nhin th loi PROM ni tip hay c s dng hn c. Khi thit k cn chn loi PROM c dung lng ph hp vi mt ca cc loi FPGA khc nhau. Ngoi ra Xilinx cn cung cp cc gii php c thit k trc, d s dng cu hnh cho tt c CPLD v FPGA ca Xilinx, nht l khi thit k cc h thng phc tp. Tt c cc ni dung lin quan n cu hnh, PROM cho FPGA hay ISP cho CPLD, u c a ra. Cc gii php s

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Cc CPLD v FPGA ca Xilinx cng c th c lp trnh bn ngoi bi b lp trnh chip HW130 ca Xilinx cng nh cc b lp trnh ca cc nh pht trin khc. iu ny cng thun tin cho vic s dng cc chip c lp trnh trc trong thi gian sn xut.

+ Parallel Cable IV: Cp np s dng cng giao tip song song ca my tnh, c pht trin thay th cho chun cp np Parallel Cable III v cho php tng tc ln hn 10 ln v h tr cho tt cc cc vi mch s dng mc in p I/O t 5V xung 1,5V. Hin nay chun cp np ny c dng ph bin hn c.

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+ MultiLINX : Cp np da trn giao chun giao tip ni tip USB hoc RS232, cp np ny c tc truyn trong di rng v giao din c in p iu chnh c ph hp vi vic giao tip vi cc h thng v cc chn I/O hot ng cc mc in p khc nhau 5V; 3,3V; 2,5V. V c thit k h tr cho cc phn mm g ri phn cng trc kia, nay chng tr ln li thi khi c s ra i ca cng c g ri phn cng ChipScope ILA.

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Cc CPLD v FPGA ca cc hng ni chung, ca Xilinx ni ring c th c lp trnh ngay trn h thng (vi mch c hn vo mch ng dng) thng qua giao thc JTAG (Joint Test Advisory Group: Chun giao tip ) c tch hp sn trong IC. Ngi thit k s dng cp np np cu hnh cho CPLD hoc FPGA. Xilinx a ra mt chun cp np nh sau:

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8.6.1.2 Chn gii php cu hnh cho CPDL/FPGA

Chng 8: Logic lp trnh (PLD)

dng cng c 3rd part boundary scan, cc gii php phn mm km theo, cp ISP, thit b kim tra t ng ATE v h tr lp trnh cng nh cc thit b lu tr cu hnh. Gii php cu hnh hin i nht l nhm cu hnh System ACE. Vi gii php System ACE, ngi thit k c th d dng s dng giao din vi x l trong System ACE trc tip phi hp cu hnh FPGA theo cc yu cu ca h thng. Gii php u tin trong nhm ny l System ACE CF, cung cp cng ngh iu khin a Microdrive kch thc mt inch v CompactFlash cng nh b lu tr cu hnh c dung lng 8 gigabits. Ngoi ra, System ACE CF cng c thit k trc, cung cp cc c tnh hin i tn dng kh nng cu hnh li linh hot ca FPGA, bao gm:

- Nng cp cu hnh qua mng (IRL) - Hot-swapping

- Khi to trung tm x l v lu tr phn mm - M ha

Mt s c im ca gii php cu hnh System ACE:

- linh hot: Vi System ACE CF, c th s dng mt thit k cho nhiu ng dng khc nhau, nh gim ng k thi gian hon thnh sn phm. Thay v thit k vi bo mch tng t nhau ph hp vi cc chun khc nhau, gi y ngi thit k ch phi thit k mt bo mch duy nht vi nhiu cu hnh c lu tr trong b nh System ACE CF. Mi bo c th chn cc cu hnh ph hp vi cc chun khc nhau bng cch khi to gi tr mc nh tng ng c lu trong b nh ACE. H thng cn cho php lu nhiu cu hnh cho mt thit k trong mt System ACE CF n. V d nh trong qu trnh thit k mu, ngi thit k c th lu cc cu hnh hot ng, cu hnh kim tra v cu hnh g ri trong b nh ACE, ng thi c th chn cc cu hnh khc chy th bn thit k ca mnh.

h tr qun l nhiu bitstream v tch hp iu khin cu hnh FPGA vi hot ng ca h thng, System ACE c mt cng vi x l trong h thng. Cng ny cho php b x l ca h thng thay i cu hnh mc nh, cu hnh li trig, cu hnh li tng FPGA hoc mt nhm FPGA, truy nhp vo cc file khng cu hnh c lu trong khi CompactFlash, hoc dng khi CompactFlash lm b nh chung cho h thng. Vi cc FPGA c trung tm x l km theo, System ACE CF cung cp gii php 3 trong 1 qun l phn cng v phn mm. System ACE CF c th cu hnh khung FPGA, khi to trung tm vi x l, v cung cp cc ng dng phn mm cho trung tm ny nu cn m khng phi thm bt c thit b phn cng no.

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Vi System ACE CF, ngi thit k c th thc hin c gn nh ton b cc yu cu cu hnh cho FPGA. Cc kh nng b tr h thng ny cho php ngi thit k s dng FPGA tha mn cc yu cu nh trc v mt thit k v thi gian x l li. Ngoi ra, cc cng vi x l v cng kim tra JTAG cn cho php tch hp System ACE trong mi h thng.

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- Qun l bitstream a cu hnh

- Cu hnh multi-board t mt ngun duy nht

Chng 8: Logic lp trnh (PLD)

+ Mt : Vi mt logic cao cha tng thy (trn 8 Gb), mt System ACE CF c th cu hnh cho hng trm FPGA v c th thay th cho cc mng PROM cu hnh. Ngi thit k c th lu mt s lng ln cc thit k khc nhau cho mt mng FPGA trong cng mt khi nh. System ACE CF s dng h thng file FAT (File Allocation Table: bng sp xp file tiu chun), do ngi thit k c th lu c nhng file khng dng bitstream hoc s dng b nh tha lm b nh chun cho h thng. + Kh nng qun l tp trung: System ACE CF c thit k qun l cu hnh theo yu cu. Mt System ACE CF c th cu hnh cho mt hoc nhiu bo FPGA kt ni qua mt backplane. Kh nng tp trung cho php n gin ha qu trnh qun l v nng cp cu hnh. thay i hay nng cp cu hnh ca mt h thng, ngi thit k c th vo khi nh, thc hin cc thay i cn thit trn mn hnh my tnh, chnh li ni dung trong h thng qua cng vi x l; hoc ti cu hnh mi v qua mng, s dng IRL. 8.6.1.3 Chn cng c phn mm ph hp

+ ISE WebPACK - bn min ph c th dng thit k cho tt c cc h CPLD ca Xilinx

+ Gi phn mm Foundation: c th thit k cho tt c cc loi FPGA v CPLD ca Xilinx Ngoi ra Xilinx cn pht trin cc b cng c phn mm tin ch khc nh System Generator h tr cho cc thit k DSP (Digital Signal Processor: B x l tn hiu s), hay EDK (Embbleded Dvelopment Kit: B phn mm pht trin h thng) h tr cho cc thit k nhng.

8.6.2 Lu thit k cho CPLD ca Xilinx

Qu trnh thit k cho CPLD ch yu l thc hin trn cc cng c phn mm, lu thit k chung cho CPLD (V d s dng phn mm ISE) nh hnh v sau, bao gm cc bc nh sau: + Nhp thit k (Design Entry): y l bc u tin v quan trng nht ca qu trnh thit k cho CPLD. Cc cng c thit k cho php nhp thit k cho php nhp thit k theo cc cch sau:
- Nhp thit k theo s nguyn l Schematic, ngi thit k s dng cc modul c sn trong th vin Schematic ghp ni chng vi nhau to thnh bn thit k theo yu cu, cch ny c th thc hin thit k nhanh nhng s rt kh khn v khng ti u ti nguyn ca CPLD

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ISE c dng kt hp vi phn mm m phng ModelSim ca Mentor Graphics phin bn XE c pht trin ring h tr cho cc h CPLD/FPGA ca Xilinx.

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+ Gi phn mm c bn BASEX: c th thit k cho cc loi chp sau:

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Xilink cng cung cp ISE di dng cc gi phn mm c cu hnh khc nhau vi gi thnh khc nhau:

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Xilinx cung cp cc cng c thit k in t hon chnh, cho php thc hin thit k trn cc thit b logic kh trnh ca Xilinx. Cc cng c ny kt hp cng ngh tin tin vi giao din ha linh hot, d s dng ngi thit k c c thit k ti u. B cng c phn mm hin ang c s dng rng ri l ISE vi phin bn mi nht l 7.0 (nm 2005).

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Chng 8: Logic lp trnh (PLD)

khi thit k phc tp, v thit k khng th s dng sang cng c thit k CPLD ca cc hng khc. T s nguyn l thit k c cng c phn mm s chuyn i sang file ngn ng m t phn cng HDL, m ph bin l VHDL hoc Verilog. - Nhp thit k s dng ngn ng m t phn cng HDL (VHDL, Verilog, ABEL, AHDL...), Ngi thit k c th s dng chng trnh son tho thc hin vic m t ton b bn thit k ca mnh di dng ngn ng HDL no m cng c thit k c th tng hp c. C rt nhiu phng php m t, mc tru tng khc nhau khi thit k, mi cch m t khc nhau c th to ra mt cu trc mch khc nhau trong CPLD mc d chng c cng chc nng.
Design Entry Schematic ECS HDL Verilog/VHDLL

Design Verification

Functional Simulation ModelSim XE

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Design Synthesis

Xilinx Synthesis Tool XST

Design Implementation

Timing Simulation ModelSim XE

Download (iMPACTE)

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State Machines StateCad

Chng 8: Logic lp trnh (PLD)

Hnh 8.5- Lu thit k CPLD

Do ngi thit k cn thc hin phn tch bi ton, tm hiu ti nguyn, cu trc ca CPLD, yu cu v thi gian thit k s dng kiu m t. Mc tru tng trong khi m t ph hp va m bo yu cu v thi gian thit k va ti u c vic s dng ti nguyn ca CPLD. - Nhp thit k di dng s : Cng c thit k cn cho php nhp thit k vo di dng s m in hnh l hnh trng thi, sau chng cng c chuyn i sang HDL.

+ Kim tra, m phng thit k (Design Verification): Thc hin kim tra, m phng chc nng hot ng ca thit k HDL to ra trn. Cc cng c thit k u h tr vic m phng chc nng hot ng ca bn thit k HDL theo m hnh hot ng (Behavioral Model), mc m phng ny c lp vi loi CPLD c la chn. Bc ny c th khng cn phi thc hin trong khi thit k. + Tng hp thit k (Design Synthesis): Sau khi hon thnh m phng thit k, bc tng hp tip theo c nhim v chuyn thit k di dng file vn bn HDL thnh dng file netlist, thc hin m t mch thc mc thp di dng cng logic v kt ni gia chng vi nhau. C th s dng cc cng c tng hp ca cc hng khc nhau.

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Mi cng c c th to ra file netlist theo nh dng ring (v d ca XST ca Xilinx XNFXilinx Netlist Format) nhng c th t la chn to ra file netlist di dng nh dng chun EDIF (Electronic Digital Interchange Format) m tt c cc cng c c th hiu c.
U1A
U1A

U3A

U2A

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A B

U4A

U1A

U4B

U2A U3A

U4D

Ghp cc b m v/ra To Netlist

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Thc hin kt ni Component AND G1 Component OR G Component NOT G3 Net N1: A. G1:a. G3:a Net N2: B. G1:b. G2:a Net N3: G1:c. P Net N4: G3:b. G2:b Net N5: G2:c. Q ;

Vic nhp thit k rt linh hot, c th s dng c 3 cch trn thc hin cc phn khc nhau ca thit k.

Chng 8: Logic lp trnh (PLD)

Hnh 8.6- V d tng hp ra file netlist + Thc hin thit k (Design Implementation): Sau khi c file netlist, bc tip theo l thc hin thit k, ngha l xy dng cu hnh cho CPLD. Bc ny s dng file netlist v file rng buc "constraints File" (m t cc nguyn tc thit k, cc rng buc v vt l nh gn v tr cho cc u vo/ra trn chip, cc rng buc v tc , thi gian, tn s) to thit k s dng ti nguyn c sn ca CPLD. Bc ny bao gm cc bc: Translate (bin dch), Map (Phn b bn thit k vo chip), Place and Route (nh v v nh tuyn kt ni).
+ Translate (bin dch): Bc ny nhm thc hin kim tra thit k v m bo netlist ph hp vi kin trc chn, kim tra file rng buc "constraints File" ca ngi s dng pht hin cc li mu thun vi tham s ca chip chn. Bin dch thng bao gm cc qu trnh: ti u ho, bin dch thnh cc thnh phn vt l ca thit b; kim tra rng buc thit k. Khi kt thc bc bin dch, s c mt bn bo co v cc chng trnh c s dng, danh sch cc cng I/O v cc thit b c s dng trong thit k, nh ngi thit k s la chn c phng n thit k ti u. + Map: to bn phn b thit k ti cc ti nguyn c th trong CPLD. Nu thit k qu ln so vi thit b c chn, quy trnh ny khng th hon thnh nhim v ca mnh. Qu trnh Map c cc tham s rng buc ca thit k, v d nh tham s tc , thi gian ca thit k, v i khi quyt nh gn thm cc thnh phn logic p ng cc yu cu v thi gian. Map c kh nng thay i thit k xung quanh cc bng nh x to kh nng thc hin tt nht cho thit k. Quy trnh ny c thc hin hon ton t ng v cn rt t tc ng u vo t ngi s dng. Bc ny nhm a mch thit k vo mt thit b c th. Bc ny cng to ra bo co xc nhn cc ti nguyn c s dng trong chip, m t chnh xc cc phn trong thit k c t v tr no trong chip thc t. + Place and Route (PAR - nh v tr v nh tuyn kt ni) Place l qu trnh la chn v tr ph hp ca mi khi chc nng trong thit k v a cc cng logic ca phn vo cc khi logic hay cc modul c th trong CPLD trn c s ti u vic kt ni v m bo v cc rng buc v thi gian. Nhng phn logic hot ng tc cao s c xp cnh nhau gim di ng kt ni. Route l qu trnh to lin kt vt l gia cc khi logic. Hu ht cc nh sn xut cung cp cng c Place and Route t ng cho ngi s dng. Ngoi cng c t ng, ngi thit k c th t Place and Route trong khi thit k. Nh sn xut cng cung cp cc cng c, nh Floorplanner, nng cao hiu sut qu trnh Place and Route do ngi thit k thc hin so vi qu trnh t ng.

Place and Route l qu trnh phc tp, do n chim thi gian nhiu nht. Tuy nhin, bc ny ch c th hot ng tt nu chip chn p ng cc tuyn lin kt cho thit k. Nu khng, ngi thit k s phi chn chip c dung lng ln hn. Sau bc ny to ra c file cu hnh *.jed c th c np vo cho CPLD.
+ Timing Simulation (M phng c tham s thi gian): Sau bc Place and Route ngi thit k c th thc hin m phng thit k mc cng logic c nh v tr v nh tuyn trn CPLD, phn mm s dng file cu hnh c to ra v kt hp vi th vin v m hnh thi gian ca cc h CPLD (V d ISE ca Xilinx th dng th vin VITAL), thc hin m phng hot ng ca thit k m c tnh n cc tham s thi gian tr, thi gian thit lp ca cc cng logic trong CPLD. Bc ny rt quan trng vi nhng thit k phc tp, tc ln.

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Chng 8: Logic lp trnh (PLD)

+Configuration (Cu hnh): Gi chng trnh iu khin vic np cu hnh, thc kt ni thit b np (cp np) n CPLD v np file cu hnh cho CPLD. Vi CPLD ca hng Xilinx, qu trnh lp trnh c th thc hin ngay trong h thng nh cng c JTAG, hoc s dng b lp trnh thit b chuyn dng, v d nh cng c JTAG Data I/O, theo chun IEEE/ ANSI 1149.1_1190. Cng c JTAG l mt b cc nguyn tc thit k, h tr qu trnh kim tra, lp trnh cho thit b v g ri trn chip, trn bo mch v trn h thng. Kh nng lp trnh trn h thng l u im ca CPLD, cho php hn trc tip thit b ln PCB. Nu c thay i trong thit k, s khng phi tho thit b ra khi bo mch, m n gin ch phi lp trnh li trn h thng. 8.6.3 Lu thit k cho FPGA

TM TT

Trong chng ny trnh by cc khi nim c bn ca logic lp trnh. Vi s pht trin ca cc thit b logic lp trnh ta c th thit k cc h thng k thut s phc tp. Cc k thut thit k cp cao v cc cng c tr gip my tnh cn thit to nn chc nng thc thi PLD v FPGA hiu qu. Vic th nghim tnh thc thi ca PLD v FPGA cng yu cu phi c cc cng c th nghim v s tr gip ca my tnh.

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Lu thit k cho FPGA cng tng t nh lu thit k cho CPLD, ch khc bc cui cng - bc Cu hnh cho FPGA. bc ny, i vi FPGA c thm bc "Create Bit file" to ra file "bitstream" np vo b nh cu hnh trong FPGA thng l b nh tm thi nh SRAM. Dng bit c np mang tt c thng tin nh ngha cc hm logic v cc lin kt trong thit k. Mi thit k khc nhau c mt dng bit khc nhau. Cc thit b SRAM mt ton b thng tin mi khi ngt ngun, do khi cn thit phi np dng bit cu hnh ny vo trong PROM (thng s dng PROM ni tip). Mi khi thit b c bt ngun file cu hnh t PROM s c np t ng vo b nh SRAM ca FPGA, v FPGA hot ng theo cu hnh c np .

Chng 9: Ngn ng m t phn cng VHDL

CHNG 9: NGN NG M T PHN CNG VHDL

GII THIU
Trong ton b lu thit k cho CPLD hoc FPGA, bc nhp thit k l bc quan trng v tn nhiu cng sc nht, n quyt nh phn ln n kt qu ca cng vic thit k. Cc cng c thit k h tr nhiu phng php nhp thit k khc nhau, tuy nhin phng php nhp thit k dng ngn ng m t phn cng HDL l u vit hn c v c s dng ch yu trong qu trnh thit k s ni chung v thit k cho CPLD/FPGA ni ring. Hin nay c nhiu ngn ng HDL c s dng, tuy nhin trong phn ny ch gii thiu phng php thit k dng ngn ng VHDL v gii thiu nhng c im ca VHDL khin n c tr thnh mt ngn ng HDL ang c ging dy v s dng nhiu trng i hc trn th gii. Ngy nay, cc mch tch hp ngy cng thc hin c nhiu chc nng, do , vn thit k mch cng tr nn phc tp. Nhng phng php truyn thng nh dng phng php ti thiu ho hm Boolean hay dng s cc phn t khng cn p ng c cc yu cu t ra khi thit k. Nhc im ln nht ca cc phng php ny l chng ch m t c h thng di dng mng ni cc phn t vi nhau. Ngi thit k cn phi i qua hai bc thc hin hon ton th cng: l chuyn t cc yu cu v chc nng ca h thng sang biu din theo dng hm Boolean, sau cc bc ti thiu ho hm ny ta li phi chuyn t hm Boolean sang s mch ca h thng. Cng tng t khi phn tch mt h thng ngi phn tch cn phi phn tch s mch ca h thng, ri chuyn n thnh cc hm Boolean, sau mi lp li cc chc nng, hot ng ca h thng. Tt c cc bc ni trn hon ton phi thc hin th cng khng c bt k s tr gip no ca my tnh. Ngi thit k ch c th s dng my tnh lm cng c h tr trong vic v s mch ca h thng v chuyn t s mch sang cng c tng hp mch vt l dng cng c Synthesis. Mt nhc im khc na ca phng php thit k truyn thng l s gii hn v phc tp ca h thng c thit k. Phng php dng hm Boolean ch c th dng thit k h thng ln nht biu din bi vi trm hm. Cn phng php da trn s ch c th dng thit k h thng ln nht cha khong vi nghn phn t. Phng php thit k, th nghim, phn tch cc h thng s s dng cc ngn ng m t phn cng ni bt ln vi cc u im hn hn v s dn thay th cc phng php truyn thng. S ra i ca ngn ng m phng phn cng gii quyt c rt nhiu nhc im ln ca cc phng php thit k trc y: Nu cc phng php c i hi phi chuyn i t m t h thng (cc ch tiu v chc nng) sang tp hp cc hm logic bng tay th bc chuyn hon ton khng cn thit khi dng HDL. Hu ht cc cng c thit k dng ngn ng m phng phn cng u cho php s dng biu trng thi (finite-state-machine) cho cc h thng tun t cng nh cho php s dng bng chn l cho h thng tng hp. Vic chuyn i t cc biu trng thi v bng chn l sang m ngn ng m phng phn cng c thc hin hon ton t ng. Nh tnh d kim tra th nghim h thng trong sut qu trnh thit k m ngi thit k c th d dng pht hin cc li thit k ngay t nhng giai on u, giai on cha a vo sn xut th, do tit kim c lng chi ph ng k bi t thit k n to ra sn phm ng nh mong mun l mt vic rt kh trnh khi nhng kh khn, tht bi. 169

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Chng 9: Ngn ng m t phn cng VHDL Khi mi lnh vc ca khoa hc u pht trin khng ngng th s phc tp ca h thng in t cng ngy mt tng theo v gn nh khng th tin hnh thit k th cng m khng c s tr gip cu cc loi my tnh hin i. Ngy nay, ngn ng m t phn cng HDL c dng nhiu thit k cho cc thit b logic lp trnh c PLD t loi n gin n cc loi phc tp nh FPGA.

NI DUNG
9.1. GII THIU NGN NG M T PHN CNG VHDL
VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mt loi ngn ng m t phn cng c pht trin dng cho trng trnh VHSIC( Very High Speed Itergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho php th nghim cc h thng s nhanh hn cng nh cho php d dng a cc h thng vo ng dng trong thc t. Ngn ng VHDL c ba cng ty Intermetics, IBM v Texas Instruments bt u nghin cu pht trin vo thng 7 nm 1983. Phin bn u tin c cng b vo thng 8-1985. Sau VHDL c xut t chc IEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v VHDL( tiu chun IEEE-1076-1987). VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i v lp ti liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu m t. c th vn hnh bo tr sa cha mt h thng ta cn tm hiu k lng ti liu . Vi mt ngn ng m phng phn cng tt vic xem xt cc ti liu m t tr nn d dng hn v b ti liu c th c thc thi m phng hot ng ca h thng. Nh th ta c th xem xt ton b cc phn t ca h thng hot ng trong mt m hnh thng nht. VHDL c pht trin nh mt ngn ng c lp khng gn vi bt k mt phng php thit k, mt b m t hay cng ngh phn cng no. Ngi thit k c th t do la chn cng ngh, phng php thit k trong khi ch s dng mt ngn ng duy nht. V khi em so snh vi cc ngn ng m phng phn cng khc k ra trn ta thy VHDL c mt s u im hn hn cc ngn ng khc: + Th nht l tnh cng cng: VHDL c pht trin di s bo tr ca chnh ph M v hin nay l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng. + Th hai l kh nng h tr nhiu cng ngh v phng php thit k. VHDL cho php thit k bng nhiu phng php v d phng php thit k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh ng b hay khng ng b, s dng ma trn lp trnh c hay s dng mng ngu nhin. + Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng dng VHDL thit k mc cng c th c chuyn thnh cc bn tng hp mch khc nhau tu thuc cng ngh ch to phn cng mi ra i n c th c p dng ngay cho cc h thng thit k .

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Chng 9: Ngn ng m t phn cng VHDL + Th t l kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc h thng s cho n mc cng. VHDL c kh nng m t hot ng ca h thng trn nhiu mc nhng ch s dng mt c php cht ch thng nht cho mi mc. Nh th ta c th m phng mt bn thit k bao gm c cc h con c m t chi tit. + Th nm l kh nng trao i kt qu: V VHDL l mt tiu chun c chp nhn, nn mt m hnh VHDL c th chy trn mi b m t p ng c tiu chun VHDL. Cc kt qu m t h thng c th c trao i gia cc nh thit k s dng cng c thit k khc nhau nhng cng tun theo tiu chun VHDL. Cng nh mt nhm thit k c th trao i m t mc cao ca cc h thng con trong mt h thng ln (trong cc h con c thit k c lp). + Th su l kh nng h tr thit k mc ln v kh nng s dng li cc thit k: VHDL c pht trin nh mt ngn ng lp trnh bc cao, v vy n c th c s dng thit k mt h thng ln vi s tham gia ca mt nhm nhiu ngi. Bn trong ngn ng VHDL c nhiu tnh nng h tr vic qun l, th nghim v chia s thit k. V n cng cho php dng li cc phn c sn.

9.2. CU TRC NGN NG CA VHDL

M hnh hot ng (a Model of Behavior). M hnh thi gian (a Model of Time). M hnh cu trc (a Model of Structure).

thc hin m t cho mt h thng s no cn thc hin theo cc bc nh sau:

+ Phn tch h thng thnh nhng khi con.

Nh vy vic nm chc cu trc, c php, cc m hnh m t ca ngn ng l rt quan trng, quyt nh ch yu n thnh cng trong vic m t h thng s cn thit k. VHDL cng c nhiu im ging nh mt ngn ng lp trnh bc cao, c cu trc, c c php ring, c cch t chc chng trnh, c t kha, c phng php biu din s liu ring...

Ch : - Trong cc on m m t VHDL trong chng cc t kha u c in m.

+ Xc nh m hnh m t ph hp cho mi khi con hoc cho c h thng.

+ S dng ngn ng VHDL m t h thng s theo cc m hnh xc nh.

- Trong VHDL khng phn bit ch hoa, ch thng.

+ Phn tch yu cu ca h thng s cn phi thit k hoc cn phi m t.

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te

ch

VHDL l ngn ng cho php m t cc thit b phn cng s tru tng, n khng da vo cng ngh thit b phn cng s, phng php c s dng thit k thit b s, m nhng khi nim, m hnh tru tng ca thit b phn cng s c a ra nh l nn tng ca ngn ng. Do dng VHDL cho php m t c hu ht cc h thng phn cng s. Cc m hnh tru tng gm:

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Chng 9: Ngn ng m t phn cng VHDL

9.2.1 i tng trong VHDL

Trong ngn ng VHDL gm c 3 i tng l: tn hiu - signal, bin - variable, hng constant, mi i tng c khai bo da vo t kha tng ng v chng c mc ch s dng nh sau:
+ Tn hiu Signal: l i tng biu din ng kt ni cc gia cc cng vo/ra ca thc th, gia cc cng vo/ra ca cc khi thnh phn phn cng xut hin trong thc th Chng l phng tin truyn d liu ng gia cc thnh phn ca thc th.

Signal tn_tn_hiu {,tn_tn_hiu}:kiu_d_liu [:=gi_tr_khi_to]; V d: Signal a,b,c: Bit:=1; Signal y, reg: std_logic_vector(3 downto 0):=0000;

variable tn_bin {,tn_bin}: kiu_d_liu [:=gi_tr_khi_to]; variable Q: std_logic_vector(3 downto 0);

+ Hng constant: l i tng hng c gn cho cc gi tr c th ca mt kiu khi c to ra v khng i trong ton b qu trnh thc hin. Hng cng c tnh ton cc ging nh tn hiu v c th c khai bo trong package, entity, architecture, proceduce, process C php khai bo hng:
constant tn_hng {,tn_hng}: kiu_d_liu :=gi_tr_khi_to; V d: constant GND : std_logic:=0; constant PI: real:=3.1414;

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Bin chim t b nh hn trong khi tn hiu cn nhiu thng tin c th lp k hoch thc hin cng nh cha cc thuc tnh ca tn hiu.

S dng tn hiu yu cu c lnh wait thc hin ng b php gn tn hiu vi php lp thc hin theo cch s dng quen thuc.

Vic s dng bin hiu qu hn v gi tr ca bin c gn ngay lp tc trong process khi tn hin ch c lp k hoch thc hin v ch c cp nht ton b sau khi kt thc process.

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Nu khng c khi to gi tr ban u bin s nhn gi tr khi to ban u l gi tr thp nht trong cc gi tr thuc min xc nh ca kiu d liu. Tn hiu cng c th cha d liu nhng chng li khng c s dng v nhng l do sau:

te

V d: variable x : Bit:=1;

ch

+ Bin Variable: l i tng cc b c s dng cha cc kt qu trung gian. Bin ch c khai bo v s dng trong process v trong chng trnh con. C php khai bo ca bin cng tng t nh khai bo tn hiu:

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Tn hiu c tnh ton cc rt cao, chng c th c khai bo trong package (tn hiu ton cc, c s dng bi mt s thc th), khai bo trong thc th - Entity (tn hiu ni b dng trong thc th, c th c tham chiu bi bt k kin trc no ca thc th ), khai bo trong kin trc Architecture (tn hiu ni b dng trong kin trc, c th c s dng trong bt c cu trc lnh no trong kin trc). Cc tn hiu c th c s dng nhng khng c khai bo trong tin trnh process, trong chng trnh con. V tin trnh v chng trnh con l thnh phn c s ca m hnh v chng c coi nh cc hp en. C php khai bo tn hiu nh sau:

Chng 9: Ngn ng m t phn cng VHDL Tm li: Cc i tng trong VHDL c mc ch s dng, phm vi s dng khc nhau, nhng chng c c php khai bo chung nh sau:
i_tng tn_i_tng : kiu_d_liu {:=gi_tr_khi_to}

Cc i tng khi khai bo phi c xc nh kiu d liu tng ng. VDHL nh ngha nhiu kiu d liu khc nhau ph hp vi vic m t, thit k, m phng cc h thng s khc nhau trong thc t.
9.2.2 Kiu d liu trong VHDL

Trong VHDL c 4 dng d liu:

Kiu ghp: cc d liu di dng mt nhm cc thnh phn nh mng, bng ghi (record). Bit_logic_vector, std_logic_vector v String u l nhng dng d liu ghp c nh ngha sn. 2-D Arrays: cc d liu c dng mng 2 chiu, c to nn t 1 mng ca mt mng 1 chiu ( hay mt bn ghi).

Type Tn_kiu is gii_hn_gi_tr_ca_kiu

a. Kiu v hng

- Kiu Bit : Kiu lit k vi 2 gi tr 0 v 1. Kiu Bit c nh ngha nh sau: Type

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nh sau: Type Boolean is (false, true);

- Kiu Integer: Kiu s nguyn vi nhng gi tr dng hoc m, ln mc nh l 32 bit vi gii hn gi tr: t -2147483647 n +2147483647. Khi s dng c th gii hn min xc nh theo gii hn gim dn dng t kha downto hoc tng dn dng t kha to:
signal A : integer range 0 to 7; -- A s nguyn 3 bit variable B : integer range 15 downto 0; -- B s nguyn 4 bit signal B : integer range 15 downto -15; -- B s nguyn 5 bit

- Kiu Boolean: Kiu lit k vi 2 gi tr false v true. Kiu Boolean c nh ngha

Cc cch biu din s nguyn dng thp phn: + digit[underline]digit, v d : 0, 1, 123_456_789 , -123_5678 + digit(E)digit, v d: 987E6 (=987.106) Cc cch biu din di dng c s xc nh: 173

te

Cc kiu d liu c nh ngha trong gi Standard cha trong th vin chun Standard Library ca VHDL l: bit, boolean, integer, real, physical, character, std_logic and std_ulogic, Bit_logic_vector, std_logic_vector v String v mt s kiu d liu con. C php chung nh ngha kiu d liu nh sau:

ch

Bit is (0, 1);

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VHDL Subtypes: dng d liu con do ngi dng t nh ngha da trn nhng dng c sn.

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V hng : gm cc d liu c gi tr n nh bit, boolean, integer, real, physical, character, std_logic v std_ulogic, enumerated (kiu lit k)...

Chng 9: Ngn ng m t phn cng VHDL + base#based_integer#[exponent], v d: 2#1100_0100#, 16#C4#, 4#301#E1, (=196)
- Kiu Real: Kiu s thc c gii hn t -1.0E+38 n 1.0E+38, khc vi kiu integer kiu s thc khi s dng thng c nh ngha thnh kiu d liu ring v c gii hn min xc nh:
signal a: Real:=-123E-4; type CAPACITY is range -25.0 to 25.0 ; signal constant Sig_1 : CAPACITY := 3.0 ; P : PROBABILITY := 0.5 ; type PROBABILITY is range 1.0 downto 0.0;

+ Biu din di dng c s xc nh: base#based_integer[.based_integer ]#[exponent]

V d: 2#1.111_1111_111#E+11, 16#F.FF#E2 (=4095.0)

type units

Time is range <xc_nh gii hn>

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- Kiu Vt l Physical: c s dng biu din cc i lng vt l nh khong cch, in tr, dng in, thi gian Kiu vt l cung cp n vi c bn v cc n v k tip c nh ngha theo n v c bn, n v nh nht c th biu din c l n v c bn. Trong thc vic chun Time (kiu d liu thi gian) l kiu vt l duy nht c nh ngha.

fs; -- n v c bn

ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us;

- Kiu std_logic v std_ulogic: kiu d liu logic nhiu mc c nh ngha trong gi std_logic_1164, so vi kiu Bit th chng c th m t chnh xc v chi tit hn cho cc phn cng s, chng cn xc nh c cng khc nhau ca cc tn hiu.

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sec = 1000 ms; min = 60 sec; hr = 60 min;

End Units;

ch
...

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- Kiu Character: Kiu kiu k t, lit k vi min xc nh l tp hp cc k t ASCII. Biu din ca gi tr Character: A, a, *, , NUL, ESC

V d s dng: constant Tpd : time := 3ns ; Z <= A after Tpd ;

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+ Biu din di dng thp phn: integer[.integer][exponent], v d: 0.0, 0.5, 1.1234_5678, 12.4E-9

Cc cch biu din s thc:

Chng 9: Ngn ng m t phn cng VHDL

type X, 0, 1, Z, W, L, H, - ) ;

std_ulogic

is

type X, 0, 1, Z, W, L, H, - ) ;

std_logic

is

( U,

-- Uninitialize -- Forcing Unknown ------Forcing Zero Forcing One High Impedance Weak Zero Weak One Dont Care

( U,

-- Uninitialize -- Forcing Unknown ------Forcing Zero Forcing One High Impedance Weak Zero Weak One Dont Care

-- Weak Unknown

-- Weak Unknown

signal signal

A,B,C,Res_Out : std_logic ;

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A B C

Out_1 : std_ulogic ;

Out_1 <= A ; A Out_1 <= B ; Out_1 <= C ; B C Out_1

ch

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C li

- Kiu d liu lit k t nh ngha: Kiu d liu lit k, do ngi s dng t nh ngha, cho php m t rt sng sa, v linh hot cho cc m hnh phn cng s vi mc tru tng cao. Kiu d liu ny dng nhiu m t hnh trng thi, cc h thng phc tp

(K hiu <= dng trn l lnh gn tn hiu, lnh gn tn hiu thc hin c vi 2 d liu cng kiu, cng ln, gi tr ca tn hiu bn phi s c gn cho tn hiu bn tri).

V d: type My_State is( RST, LOAD, FETCH, STOR, SHIFT) ;

. . . signal STATE, NEXT_STATE : My_State ;

b. Kiu d liu ghp

Tng t cc ngn ng lp trnh, VHDL cng c cc kiu d liu ghp l nhm cc phn t d liu theo dng mng (array) hoc bng ghi (record).
+ Mng Array:

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Hai kiu d liu std_logic v std_ulogic tng t nhau, chng ch khc nhau ch l kiu std_ulogic khng c hm phn di (unresolved) hm quyt nh gi tr tn hiu, do s c li khi cc tn hiu kiu std_ulogic c ni chung vo 1 im. Th vin cng cung cp hm pht hin li ny ca cc tn hiu kiu std_ulogic.

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Res_Out

Res_Out <= A; Res_Out <= B; Res_Out <= C;

Thc hin c

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Chng 9: Ngn ng m t phn cng VHDL Mng l nhm nhiu phn t c cng kiu d liu vi nhau thnh i tng duy nht. Mi phn t ca mng c th c truy cp bng mt hoc nhiu ch s ca mng. C php nh ngha kiu d liu mng nh sau:
Type tn_mng is array (khong _ca _ch s) of kiu_ca_phn_t;

V d mt s cch khai bo v s dng d liu mng:

type WORD is array (3 downto 0) of std_logic ; signal B_bus : WORD ; type DATA is array (3 downto 0) of integer range 0 to 9 ;

signal C_bus : DATA ;

signal My_BusA, My_BusB: bit_vector (3 downto 0); signal My_BusC : bit_vector (0 to 3) ;

signal Data_Word : std_logic_vector (11 downto 0);

variable Warning2: string(1 to 30):= Unstable, Aborting Now ;

Mt s php ton thao tc vi phn t mng:

te
0

My_BusB <= My_BusA ;

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My_BusA My_BusB

- Php gn cho mng: 2 mng phi cng kiu, cng ln, php gn s thc hin gn theo tng phn t theo th t t tri sang phi:
My_BusC <= My_BusA ; 3 2 1 0

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My_BusA

My_BusB

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constant Warning3: string(1 to 20):= Entering FSM

Cch biu din s liu bit_vector v std_logic_vector: B|O|X gi_tr (dng du nhy kp). Trong B : Binary -Kiu nh phn, O: Octal - kiu bt phn, X: hexadecimal.
X1AF=B0001_1010_1111= B000_110_101_111=O0657

- Php gp ( ): cho php nhm c d liu v hng v d liu mng thun tin cho cc php gn cho mng:

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Data_Word <= 101001101111 ; Data_Word <= XA6F; Data_Word <= O5157; Data_Word <= B1010_0110_1111 ;

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State2; 2 ;

Cc kiu d liu mng c nh ngha trong th vin chun ca VHDL l: Bit_logic_vector (mng d liu kiu Bit), std_logic_vector (mng d liu kiu std_logic) v String (mng d liu kiu Chacracter). Mt s v d s dng cc kiu d liu ny nh sau:

Chng 9: Ngn ng m t phn cng VHDL

signal H_BYTE, L_BYTE: std_logic_vector ( 0 to 7); signal Q_Out : std_logic_vector (31 downto 0); signal A, B, C, D ... (A,B,C,D)<=WORD; : std_logic; signal WORD : std_logic_vector (3 downto 0);

Ch : Php gp v bn tri ch dng vi kiu d liu v hng.

WORD <= ( 2 => 1, 3 => D, others => 0 ) ; Q_Out <= (others => 0) ; H_Byte <= (7|6|0=>1, 2 to 5 => 0 ); WORD <= ( A, B, C, D ) ;

Ch : others c th c s dng khi gn mc nh, n c ngha l cc tt c cc phn t cn li c gn bng mt gi tr no ) . + Bng ghi Record:

Mi phn t ca bn ghi c truy nhp ti theo tn trng. Cc phn t ca bn ghi c th nhn mi kiu ca ngn ng VHDL k c mng v bng ghi.

type OPCODE is record PARITY : bit;

ADDRESS : std_logic_vector ( 0 to 3 ); DATA_BYTE : std_logic_vector ( 7 downto 0 );

end record ; . . . signal TX_PACKET, RX_PACKET : OPCODE;

NUM_VALUE : integer range 0 to 6; STOP_BITS : bit_vector (1 downto 0);

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ADDRESS

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V d nh ngha kiu d liu bng ghi nh sau:

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;

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DATA BYTE

Bng ghi l nhm nhiu phn t c kiu d liu khc nhau thnh i tng duy nht.

PARITY

Cch truy nhp v gn d liu cho cc trng ca bn ghi: Cc phn t ca bn ghi c truy nhp theo tn bn ghi v tn trng, 2 thnh phn ny c ngn cch bi du .
TX_PACKET <= ( 1,0011,11101010,5,10 ) ; TX_PACKET.ADDRESS <= (0011); TX_PACKET <= RX_PACKET;

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L_Byte <= (3=>1, 1 to 2 => 0, 4 to 7 => 1);

NUM VALUE STOP BIT

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Chng 9: Ngn ng m t phn cng VHDL

TX_PACKET.ADDRESS <= RX_PACKET.ADDRESS;

c. Kiu d liu mng 2 chiu (2-D Array)

Mng 2 chiu l kiu d liu mng ca cc phn t mng mt chiu hay bng ghi. Mt s v d nh ngha v khai bo kiu d liu mng 2 chiu nh sau:
type Mem_Array is array (0 to 3) of std_logic_vector (7 downto 0); type ... signal My_Mem:Mem_Array ; Data_Array is array ( 0 to 2 ) of OPCODE ;

V d ng dng dng mng 2 chiu khi to mt vng nh ROM

constant My_ROM : REM_Array := (0 => (others=>1), 1 => 10100010, 2 => 00001111,

Subtype Tn_kiu_d_liu_con is xc_nh_kiu_d_liu_con;

subtype My_Small_Int is My_Int range 5 to 30 ; subtype word is bit_vector(31 downto 0);

9.2.3 Cc php ton trong VHDL

Ton t logic: c s dng cho cc dng d liu l bit, boolean, bit_vector v std_logic_vector. Ton t logic gm c: and, or, nand, nor, xor, not, xnor.
A B

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F
Z

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H G

V d:

subtype My_Int is integer range 0 to 255 ;

ch

L mt tp hp con ca cc kiu d liu c nh ngha khc. Php khai bo kiu d liu con c th nm mi v tr cho php khai bo kiu d liu. C php khai bo chung:

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d. Kiu d liu con:

V d: Z <= A and B;

Y <= G or ( F and H ) ;

Ton t logic dng cho kiu d liu mng:

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3 => 11110000);
Y

signal My_Data:Data_Array ;

Chng 9: Ngn ng m t phn cng VHDL

signal ...

A_vec,

B_vec,

C_vec :

bit_vector(7 downto 0 ) ; C_vec <= A_vec and B_vec ;

A_vec (7) B_vec (7) A_vec (6) B_vec (6) A_vec (5) B_vec (5)

C_vec (7) C_vec (6) C_vec (5)

Nguyn tc thc hin php logic vi d liu mng: + Ch thc hin vi cc mng phi cng kiu, cng ln.

. . .
C_vec (0)

Ton t quan h: c s dng cho hu ht cc dng d liu, tt c cc ton t quan h u cho gi tr tr v di dng boolean. Ton t quan h gm c: =, /=, <, <=, >, >=.
V d: signal signal FLAG_BIT : boolean ; A, B : integer ;

FLAG_BIT<=(A > B);

+ Cc mng phi cng kiu, di c th khc nhau.

signal ...

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> B_vec ) State <= State <=

signal

A_vec : bit_vector

B_vec : bit_vector then

if ( A_vec else

end if;

Ton t s hc: c s dng cho s nguyn, s thc, v cc dng d liu vt l, std_logic. Std_logic_vector, Bit, Bit_vector. Cn ch rng khng phi tt c ton t s hc u c th s dng cho mng. Cc ton t s hc l: +, -, *, /, abs (tr tuyt i), ** (hm m). Ton t dch: mi ton t tc ng vo thnh phn bn tri ca mt ton hng hoc ton hng bn phi ca s nguyn to ra rt nhiu ton t dch v quay. S m ch ra cch hng khc c s dng. Mi ton t cho kt qa cng dng v kch thc vi ton hng ban u. Cc ton t dch trong VHDL l: sll (dch tri logic), srl (dch phi logic), sla (dch tri s hc), sra (dch phi s hc), rol (quay tri), ror (quay phi).
V d: signal A_vec : bit_vector (7 downto 0) := 11000110;

te
Normal; Code_Red;

+ Mng c di khc nhau th php quan h thc hin u tin phn t t tri sang phi v so snh theo gi tr ASCII.
( 7 downto 0 ) := 11000110 ; ( 5 downto 0 ) := 111001 ;

ch

- Nguyn tc thc hin php quan h vi d liu mng:

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+ Php ton logic thc hin vi tng phn t ca mng v A_vec (0) theo th t t tri sang phi. B_vec (0)

Chng 9: Ngn ng m t phn cng VHDL

signal D_vec : bit_vector (7 downto 0); D_vec <= A_vec sll D_vec <= A_vec sra D_vec <= A_vec ror D_vec <= A_vec srl 2; 2; 3; 2; D_vec =00011000 D_vec =11110001 D_vec =11011000 D_vec =00110001 D_vec =00011000

D_vec <= A_vec sra -2;

Ton t ghp ni: ton t & cho php ghp ni mt cch linh hot cc d liu n v d liu dng mng thnh cc mng ln hn.

V d: signal A_vector, B_vector: std_logic_vector (7 downto 0); signal Z_vector: std_logic_vector (15 downto 0); Z_vector <= A_vector & B_vector;

Ton t tch: cho php ta ly ra mt s thnh phn ca mng, chiu ch s ca php tch phi cng chiu nh ch s nh ngha cho mng.
V d: signal signal Z_vec: std_logic_vector (15 downto 0); B_vec: std_logic_vector (7 downto 0);

B_vec <= Z_vec (12 downto 5);

- Cc thuc tnh c nh ngha trc cho kiu d liu mng trong VHDL l:

+ high, low : tr li ch s ca phn t cao nht hoc thp nht ca kiu d liu mng.

+ event, stable : thuc tnh ch dng cho i tng l tn hiu, tr v gi tr boolean, ch ra rng trn ng tn hiu ang xt c xut hin s kin thay i hay gi tr trn ng tn hiu n nh ti thi im hin ti. Cc thuc tnh ny dng nhiu vi lnh wait v if. V d s dng ton t thuc tnh nh sau:

180

+ length : tr v s lng cc phn t ca mng.

signal a : std_logic:=0; ... PROCESS(a) TYPE bit4 IS ARRAY(0 TO 3) of BIT; TYPE bit_strange IS ARRAY(10 TO 20) OF BIT; VARIABLE len1, len2 : INTEGER; BEGIN If (aevent and a=1)then - s kin c xn dng ca a. len1 := bit4LENGTH; -- returns 4

+ range, reverse_range : xc nh khong ca ch s ca mng.

.4

+ left, right: tr li ch s ca phn t bn tri nht hoc bn phi nht ca d liu mng.

te

ch

Ton t thuc tnh: Xc nh thuc tnh d liu ca i tng bin v tn hiu. C php chung:

i_tngthuc_tnh

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL

len2 := bit_strangeLENGTH; -- returns 11 End if; END PROCESS;

9.2.4 Cc n v thit k trong VHDL:

VDHL s dng 6 n v thit k gm 2 loi: n v c bn v n v thit k th cp: - n v thit k c bn:

Library: Cho php to th vin trong VHDL

- n v thit k th cp (Ph thuc vo mt n v thit k c bn):

Architecture: M t hot ng bn trong ca mt Entity hay y chnh l phn m t hot ng ca khi mch s.

+ Entity - (Thc th) :

entity Tn_thc_th is generic(--Khai bo danh sch cc tham s generic Tn_tham_s : [Kiu_d_liu] [:=gi_tr_khi_to]; ... ); port(-- Khai bo danh sch i tng cc port vo ra Tn_cng : [mode] [Kiu_d_liu] [:=gi_tr_khi_to]; ... ); end Tn_thc_th;

Khai bo thc th trong VHDL phn nh ngha cc ch tiu pha ngoi ca mt phn t hay mt h thng. Thc cht ca vic khai bo thc th chnh l khai bo giao din ca h thng vi bn ngoi. Ta c th c tt c cc thng tin kt ni mch vo mch khc hot thit k tc nhn u vo phc v cho mc ch th nghim. Tuy nhin hot ng tht s ca mch khng nm phn khai bo ny. C php khai bo chung ca mt Entity nh sau:

.4

te

ch

Configuration: n v thit k cu hnh cho php gn cc phin bn ca thc th vo nhng kin trc khc nhau. Cu hnh cng c th c s dng thay th mt cch nhanh chng cc phn t ca thc th trong cc biu din cu trc ca thit k.

.c

Package Body: M t ch tit cho cc khai bo trong Package nh vit cc hm, cc th tc ...

om .v

Entity: (Thc th) - cho php khai bo cc giao din ca mt khi thit k s no : nh khai bo cc chn vo/ra, cc tham s ca khi mch...

Package: To cc gi gi liu trong Library, nh cc khai bo cc i tng, khai bo chng trnh con, hm...

181

Chng 9: Ngn ng m t phn cng VHDL

Trong khai bo trn: + Tham s khai bo trong phn generic dng kim sot cu trc, hot ng ca thc th, chng s c truyn gi tr hoc ly gi tr mc nh ban u khi thc th c khi to. + -- Du nh du dng ch thch (comment) trong m m t VHDL + [mode]: ch hng tn hiu ca cng c th l: (in, out, inout hoc buffer). Trong cng dng in ch dng c d liu. Cng dng out ch dng gn gi tr d liu. Cng inout cho php ng thi va c va gn gi tr d liu trong v ngoi chng trnh. Cng dng buffer cho php c 2 thao tc c v gn d liu t bn trong chng trnh, nhng ch cho php c d liu t ngoi chng trnh.
V d khai bo thc th cho mt cng logic AND: entity Logic_AND is port(A, B : in std_logic ; Y : out std_logic) ; end Logic_AND;

Cu trc ny cho php m t hot ng bn trong ca thc th. C php chung ca mt Architecture:
-- Thc hin cc khai bo cho kin trc Begin ...

Phn khai bo kin trc c th bao gm cc khai bo v cc i tng signal, constant, kiu d liu, khai bo cc phn t bn trong h thng (component), hay cc hm (function) v th tc (proceduce) s dng m t hot ng ca h thng. Tn ca kin trc l nhn c t tu theo ngi s dng VHDL cho php to ra nhiu m t Architecture cho mt thc th, cho php thc hin nhiu cch m t hot khc nhau cho mt thc th. Mi cch m t hot ng s ti u v mt thi gian thit k hay tin cy hay ti u v ti nguyn s dng khi tng hp C 3 cch chnh m t kin trc ca mt phn t (hoc h thng s) l m hnh hot ng (Behaviour), m t theo m hnh cu trc logic (Structure), v m hnh lung d liu. Tuy nhin m t cho mt h thng, trong mt kin trc c th kt hp s dng 2 hoc c 3 m hnh m t trn thc hin cho tng thnh phn con tng ng ca h thng s. Trong phn sau ca ti liu ny s trnh by chi tit hn cc phng php m t ny. 182

End Tn_kin_trc;

-- Vit cc m t hot ng bn trong cho thc th

.4

...

te

Architecture Tn_kin_trc of Tn_thc_th is

ch

+ Architecture (Kin trc) :

.c

om .v
A B PLD Logic_AND Y

Chng 9: Ngn ng m t phn cng VHDL

entity Half_Add is . . . end Half_Add; architecture . . . end BEH ;

-- V d cc cch m t hot ng khc nhau ca thc th Half_Add

BEH of

Half_Add

is

-- Kin trc m t theo m hnh hot ng

architecture . . . end RTL ;

RTL of

Half_Add

is

architecture . . .

XLX of

Half_Add

end XLX ; + Package v Package Body

.4

te

Package Body l n v thit k ph thuc c dng cha nhng m t ch tit cho cc khai bo trong n v thit k Package no , m t chi tit ni dung ca cc hm, cc th tc ... Package Body thng c vit ngay sau Package. C php chung cc n v thit k Package v Package Body :

ch

Package ( gi d liu) l n v thit k c bn dng cha nhng khai bo cho cc i tng, khai bo chng trnh con, hm, kiu d liu, component c th dng chung cho nhng thit k, project, cu trc.

.c

om .v
is

-- Kin trc m t theo m hnh cu trc logic

-- Kin trc m t theo m hnh lung d liu

183

Chng 9: Ngn ng m t phn cng VHDL

package My_Pack is constant. . . . . . function bv_to_integer (BV: bit_v.. return integer . . . component . . . . . . subtype. . . end package My_pack; package body My_Pack is

-- Cch s dng package trong file m t VHDL. library IEEE;-- Th vic chun use IEEE.std_logic_1164.all ; . . . -- Trong phn mm thit k ISE gi d liu do ngi s dng to ra thng c t chc mc nh trong th vin work use work.My_Pack.all; entity . . .

Package: cha nhng m t khai bo c dng chung. Entity: l nhng m t giao din thit k c dng chung. Architecture: nhng m t hot ng thit k c dng chung. Configuration: l nhng phin bn ca thc th c dng chung.

nh. Trong VHDL c th vin thit k c bit c tn l WORK. Khi ngi thit k bin dch mt chng trnh vit trn VHDL nhng khng ch r th vin ch, chng trnh ny s c bin dch v cha vo th vin WORK. V d cch gi v s dng th vin nh sau:

184

Cc n v th vin l cc cu trc VHDL c th c phn tch ring r theo trnh t nht

Phn tch VHDL l mt qu trnh kim tra cc n v thit k VHDL cho ng c php v ng ngha, cc n v thit k VHDL c lu vo th vin s dng sau ny. Th vin thit k cha cc nhng phn t th vin sau:

.4

Trong VHDL c cc th vin thit k chun, ngoi ra ngi thit k c th to cc th vin thit k ring. Trong mt thit k VHDL nhiu on chng trnh c th c gi t cc th vin khc nhau.

te

+ Library (th vin)

ch

end function; . . . end My_Pack ;

.c

function bv_to_integer (BV: bit_v.. return integer is variable ... begin for index in BV'range loop . . . .

om .v

Chng 9: Ngn ng m t phn cng VHDL

library My_Lib ; use My_Lib.Fast_Counters.all ; entity Mod1 is port ( . . .

+ Configuration (Cu hnh)

C php ca m t cu hnh nh sau:

Configuration tn_cu_hnh of tn_thc_th is -- cc phn t trong package v library. for c_t_ca_khi {mnh__use} end for;

-- Phn khai bo ca cu hnh (cho php s dng

{cc_phn_t_ca_cu_hnh}

V d:

9.2.5 Cu trc chung ca mt chng trnh m t VHDL

.4
for use end for use end for end end end

library ttl, work; configuration v4_27_87 of processor is use work.all; for structure_view a1:alu configuration ttl.sn74ls181; for; m1,m2,m3: mux entity multiplex4 (behavior); for; all: latch -- use defaults for; for; configuration v4_27_87;

te

ch

.c

om .v

Mt thc th c th c mt vi kin trc m t hot ng cho n. Trong qu trnh thit k c th phi th nghim mt vi bin th ca thit k bng cch s dng cc kin trc khc nhau. Cu hnh l thnh phn c bn ca n v thit k. Cu hnh cho php gn cc phin bn ca thc th vo nhng kin trc khc nhau. Cu hnh cng c th c s dng thay th mt cch nhanh chng cc phn t ca thc th trong cc biu din cu trc ca thit k.

185

Chng 9: Ngn ng m t phn cng VHDL M hnh cu trc m t phn cng s v phm vi s dng ca cc i tng trong VHDL c th c tng kt n gin nh trong hnh 9-1 di y:

CPLD/FPGA
entity architecture process Variables Input Ports Output Ports

Hnh 9-1. Cu trc m t phn cng v cc i tng trong VHDL.

Sau y l cu trc chung n gin ca mt chng trnh m t VHDL:

-- V d cu trc 1 file m t cho mt h thng phn cng s dng VHDL -- chun c xy dng). library IEEE;...

use IEEE.STD_LOGIC_1164.ALL;... -- Khai bo thc th Entity Tn_thc_th is

-- Khai bo cc tham s generic nu cn: Generic( -- khai bo danh sch cc tham s); Port(-- Khai bo danh sch cc cng vo/ra End Tn_thc_th; -- Bt u vit Architecture Tn_kin_trc of Tn_thc_th is {Khai bo:kiu d liu, cc component,cc i tng constant, signal} Begin { Vit cc m t dng cu trc lnh song song } ... Process(-- danh sch tn hiu kch thch nu cn) {Khai bo:kiu d liu, cc i tng bin constant, variable } Begin { Vit cc m t dng cu trc lnh tun t } End process;

186

);

.4

te

-- Khai bo gi d liu (package) trong th vin cn s dng:

ch

-- Khai bo th vin,(mc nh cn khai bo th vin IEEE (th vin

.c

om .v

Signals

Chng 9: Ngn ng m t phn cng VHDL

... { Vit cc m t dng cu trc lnh song song hay process khc } ... End Tn_kin_trc;

9.2.6 Mi trng kim tra testbench

Data Source (stimuli Generator

.4

te

ch
Testbench Entity Generics

Testbench c m t nh mt Entity khng c u vo u ra, ch c tn hiu bn trong c ghp ti khi DUT cn c kim tra theo kiu cu trc. Ngi thit k s m t cc tn hiu bn trong ny to ra tn hiu kch thch cho cc u vo ca DUT v c kt qu ra quan st...

DUT

Trong : DUT: (device under test) m hnh VHDL cn kim tra Observer: khi quan st kt qu Data source: ngun d liu (khi to ra cc tn hiu kch thch) Hnh 9.2. S tng qut chng trnh th Testbench

.c

Mi trng kim tra c th hiu nh mt mch kim tra o. Mi trng kim tra sinh ra cc tc ng ln bn thit k v cho php quan st hoc so snh kt qu hot ng ca bn m t thit k. Thng thng th cc bn m t u cung cp chng trnh th. Nhng ta cng c th t xy dng chng trnh th (testbench). Mch th thc cht l s kt hp ca tng hp nhiu thnh phn. N gm ba thnh phn. M hnh VHDL qua kim tra, ngun d liu v b quan st. Hot ng ca m hnh VHDL c kch thch bi cc ngun d liu v kim tra tnh ng n thng qua b quan st. Hnh 9-2 l s tng qut ca mt chng trnh th (Testbench).

om .v
Observer

Mt trong cc nhim v rt quan trng l kim tra bn m t thit k. Kim tra mt m hnh VHDL c thc hin bng cch quan st hot ng ca n trong khi m phng v cc gi tr thu c c th em so snh vi yu cu thit k.

187

Chng 9: Ngn ng m t phn cng VHDL Vit Testbench cho thc th Logic_AND m t phn trc: ; M t to kch thch
A B Test_bench

A B

DUT

Logic_AND

Quan st

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -- Khai bo thc th Test_bench; ENTITY Test_bench IS END Test_bench; -- M t kin trc ca Test_bench COMPONENT Logic_AND PORT(

ARCHITECTURE behavior OF Test_bench IS

B : IN std_logic;

SIGNAL A :

SIGNAL B : SIGNAL Y :

BEGIN

-- Ni chn cng vo ra ca DUT vi cc tn hiu ca Test_bench uut: Logic_AND PORT MAP( a => a, b => b, y => y ); tb : PROCESS BEGIN -- Vit m t to kch thch

188

END COMPONENT;

Y : OUT std_logic

);

.4
std_logic:='0'; std_logic:='0'; std_logic;

A : IN std_logic;

te

ch

.c

om .v

Thc th Test_bench khng c cc cng vo ra m ch khai bo cc tn hiu ni b A, B, Y ni ti khi DUT cn kim tra (Logic_AND). Trong phn kin trc m t hot ng ca Test_bench, coi khi Logic_AND nh mt component to thnh khi Test_bench. Ton b m m t cho Test_bench nh sau:

Chng 9: Ngn ng m t phn cng VHDL

A<= '1' after 10ns; B<= '1' after 20ns; ... END PROCESS; -- *** End Test Bench - User Defined Section ***

END; Trong cc phn mm thit k sau khi hon thnh cc m t cho Test_bench, ngi thit k s chy cng c m phng, cc tn hiu u ra ca DUT s c mc tnh c ra v cho php ngi thit k quan st d dng di dng gin thi gian, hay cc file s liu

9.2.7 Cc cu trc lnh song song

+ Cu trc process.

+ Lnh gn tn hiu song song. + Lnh gn c iu kin.

+ Khi.

a. Cu trc Process:

Cu trc Process c to thnh t mt tp hp cu trc lnh tun t (c trnh by chi tit phn sau). N l khi c bn ca vic m t hot ng ca thc th. Tt c cc

[ Khai bo:kiu d liu, cc i tng bin constant, variable ] Begin { Vit cc m t dng cu trc lnh tun t } End process;

Process trong mt thit k c thc hin song song. Tuy nhin, ti mt thi im xc nh ch c mt cu lnh tun t c thc hin trong mi cu trc Process. Cu trc tng qut: Trong cc phn t trong du [ ] c th c hoc khng. 189

[Nhn] Process [(Danh sch tn hiu kch thch)]

+ Php gi chng trnh con song song.

.4

+ Lnh gn tn hiu c la chn.

te

ch

Nh trnh by trong phn cu trc chung ca chng trnh m t VHDL, trong m t mt kin trc (Architecture) c cha nhiu cu trc lnh song song. Mi cu trc lnh song song s tng ng vi mt thnh phn phn cng no khi thc hin tng hp mch, mi cu trc song song c th vit bt k v tr no trong on m t Architecture m chc nng hot ng ca thc th khng thay i. Cc cu trc lnh song song c trong VHDL gm:

.c

om .v

Ngi thit k c th d dng vit cc m t kch thch to ra cc yu cu kim tra ty cho bn thit k ca mnh. Nhiu chc nng m phng, kim tra c h tr rt mnh bi cc phn mm thit k.

Chng 9: Ngn ng m t phn cng VHDL - Nhn_lnh: Tu thuc ngi thit k t tn. - Danh sch tn hiu kch thch: Danh sch cc yu t kch thch hot ng Nu Process cha (danh sch tn hiu kch thch) th lc Process s c thc hin khi c bt k s thay i no ca bt k tn hiu no trong danh sch tn hiu kch thch. iu ny tng ng vi Process khng cha danh sch tn hiu kch thch nhng li cha lnh wait v tr cu lnh cui cng trong qu trnh:
Wait on <danh sch tn hiu kch thch>

V d Process m t mch logic AND nh sau:

entity Logic_AND is Port ( A,B : in std_logic; C end Logic_AND; begin Process(A,B) begin end Process; end Behavioral; C<= A and B; : out std_logic);

.c

S hot ng ng thi ca mi Process v m hnh kt ni ca chng c m t nh hnh v 9-3, trong tn hiu s truyn gi tr gia nhng Process hot ng ng thi.:

190

Mt Process lin kt vi phn cn li ca thit k thng qua cc thao tc c cc gi tr t cc tn hiu vo, cc cng c khai bo ngoi Process v ghi gi tr vo cc tn hiu ra, cng ra. Ch khi thit k l mt tn hiu c th vo (c c ra) bi nhiu Process nhng ch nn c ghi ra bi mt Process.

.4

te

ch

architecture Behavioral of Logic_AND is

om .v
A B

Khi tng hp mch th mi Process s tng ng vi mt khi mch chc nng no . Cn khi thc hin m phng, vic thc hin mt Process bao gm vic thc hin lp li cc cu trc lnh tun t cha bn trong thn ca Process. Ging nh mt vng lp v hn v mi bc lp c thc hin mi khi c s thay i ca bt k tn hiu no trong danh Sch tn hiu kch thch.

n
C

Chng 9: Ngn ng m t phn cng VHDL

Process 1
A B G1 C G2
C<=A and B ...

Process 2
C C
If C = 1 then ...

Process 3
G3
process (C,..) begin

Process n
C<=A and B ...

Process n1
C C
If C = 1 then ...

Sig1 Sig2

om .v
Process n2

Process n4
process n

b. Cc php gn tn hiu song song

...

architecture Behavioral of logic1 is signal I1, I2, I3, I4, AND_out, OR_out: std_logic; begin ... AND_out<= I1 and I2 and I3 and I4; OR_out<= I1 or I2 or I3 or I4; ... end Behavioral;

Trong <tn_hiu_ch> nhn gi tr ca <biu_thc>, ch l lnh after ch dng cho m phng cn khi tng hp mch n s c b qua. Php gn song song tng ng mt Process cha 1 php gn tn hiu. V d m t mch AND v OR c cng 4 u vo nh sau:

.4

Php gn tn hiu song song s dng bn trong cc Architecture nhng bn ngoi Process. Dng n gin nht ca php gn tn hiu song song c c php nh sau: <tn_hiu_ch> <= <biu_thc> [after <biu_thc_thi_gian>];

te

Hnh 9-3. M hnh kt ni ca cc Process.

ch

.c

process (C,..) begin

n
Process n3
process (...

Rst

191

Chng 9: Ngn ng m t phn cng VHDL on chng trnh trn tng ng vi on chng trnh VHDL vi cc Process cha cc php gn tn hiu tun t sau:
... architecture Behavioral of logic1 is signal I1, I2, I3, I4, AND_out, OR_out: std_logic; begin ... process(I1, I2, I3, I4) begin end process; process(I1, I2, I3, I4) begin OR_out<= I1 or I2 or I3 or I4; end process; ... end Behavioral; AND_out<= I1 and I2 and I3 and I4;

c. Php gn tn hiu c iu kin

<tn_hiu_ch> <= <biu_thc>[after <biu_thc_thi_gian>] when <iu_kin> else <biu_thc>[after <biu_thc_thi_gian>] when <iu_kin> else ...

V d m t cu trc chn knh nh sau:

architecture ... begin Z <= A when Sel=00 else B when Sel=10 else C when Sel=11 else X ; end architecture;

Cu trc php gn tn hiu c iu kin c th coi l cu trc song song ca lnh tun t If c thay th tng ng vi Process cha lnh tun t if.

.4

<biu_thc>[after <biu_thc_thi_gian>];

d. Php gn tn hiu theo la chn

192

te

ch

Php gn tn hiu c iu kin l cu trc lch song song thc hin php gn gi tr ca cc biu thc cho mt tn hiu ch ty theo cc iu kin t ra. C php chung:

.c

architecture ... begin process(A,B,C, SEL ) begin case (SEL) is when 00 =>Z <= A; when 10 =>Z <= B; when 11 =>Z <= C; when others =>Z<= X; end case; end process;

om .v

Chng 9: Ngn ng m t phn cng VHDL Php gn tn hiu theo la chn thc hin gn cho mt tn hiu ch vi biu thc with. Cu trc ny c th coi nh l cu trc song song ca lnh tun t case, n c th thay th tng ng vi Process cha lnh tun t case. C php chung ca lnh with nh sau:
With <biu_thc_la_chn> select <tn_hiu_ch> <= <biu_thc> [after <biu_thc_thi_gian>] when <gi_tr_la _chn>, <biu_thc> [after <biu_thc_thi_gian>] when <gi_tr_la _chn>, ... <biu_thc> [after <biu_thc_thi_gian>] when others;

e. Khi (Block)

<phn_khai_bo> : xc nh cc i tng tn ti cc b trong khi v c th l cc khai bo sau:

-

Khai bo hng, kiu d liu, tn hiu. Thn chng trnh con. Khai bo b danh. Khai bo component. Lut use. 193

<nhn>: Block {<phn_khai_bo>} {<cu_lnh_song_song>} c trnh t bt k

begin

end block;

.4

Block bao gm tp hp cc cu trc lnh song song. Mt kin trc c th phn tch thnh mt s c cu trc logic. Mi khi biu din mt thnh phn ca m hnh v thng c s dng t chc mt tp hp cc cu trc song song phn cp. C php chung:

te

ch

.c

architecture... with SEL select Z<= A when 00, B when 10, C when 11 , X when others ; end architecture; 9.2.7 Cc cu trc lnh tun t

om .v

V d m t cu trc chn knh nh sau:

architecture ... begin process (A,B,C, SEL) begin case SEL is when 00 => Z <= A when 10 => Z <= B when 11 => Z <= C when others => Z <= end case; end process; end architecture;

n
; ; ; X;

Chng 9: Ngn ng m t phn cng VHDL

f. Gi chng trnh con song song

Php gi chng trnh con song song tng ng vi cc process bao gm cc php gi chng trnh con tun t tng ng. Mi php gi chng trnh con tng ng vi mt process khng cha dy danh sch cc tn hiu kch thch, phn khai bo rng v phn thn cha mt php gi chng trnh con, tip theo l mt cu lnh wait.
9.2.8 Cu trc lnh tun t

Cc cu trc lnh tun t c bn trong VHDL gm:

-

Cu lnh gn cho bin. Cu lnh gn cho tn hiu. Cu lnh if. Cu lnh case. Cu lnh rng Null. Cc lnh lp.

a. Php gn bin

.4

C php ca php gn bin nh sau:

...

process( Clk ) variable B, C, D : bit := 1 ; begin If (Clkevent and Clk =1) then B := A ; C := B ; D := C ; end if ; end process ;...

Php gn bin c thc hin vi thi gian m phng bng 0, v gi tr bin s c cp nht ngay gi tr ca biu thc. i tng <bin> ch c khai bo v s dng trong Process v chng trnh con, n c s dng lu tr cc kt qu trung gian. V d:

te
bin := biu_thc

ch
A D Clk

194

.c

om .v

Trong ngn ng VHDL mt cu trc ng thi quan trng l Process. Cu trc ny c s dng m t hnh vi hot ng ca mch s. Trong kin trc, tt c cc Process s c tng hp thnh mt khi mch chc nng v thc hin ng thi khi m phng. Mt Process n c xy dng t cc cu trc lnh tun t. Khi m phng cc lnh tun t c thc hin ln lt trong mt chu trnh v hn bt u t lnh th nht n lnh cui v c kch hot tr li thc hin lnh u mi khi c bt k s thay i no trong danh sch tn hiu kch thch hay trong danh sch tn hiu trong cu lnh wait.

Chng 9: Ngn ng m t phn cng VHDL

... process( Clk ) variable B, C, D : bit := 1; begin If ( Clkevent and Clk =1 ) then D := C; A C := B; B := A; end if; end process ;

Clk

b. Php gn tn hiu

C php ca php gn tn hiu nh sau:

Architecture Behavior of Triger is Begin

process( Clk ) begin If (Clkevent and Clk =1) then A B <= A ; C <= B ; D <= C ; Clk end if ; end process ;

.4

signal Clk, A, B, C, D

te

V d:

ch
:

Khc vi php gn bin, php gn tn hiu trong Process khng c cp nhp ngay tc th m php gn ch c t k hoch thc hin v kt qu ch c cp nhp sau khi kt thc Process.

.c

Tn_hiu_ch<= biu_thc [after gi_tr_thi_gian];

om .v
bit := 1;
B C

Ch trong 2 v d trn, gi tr cc bin c cp nhp tc th, v d th nht khi tng hp mch ch to ra mt triger D. Cn vi v d th 2 th t gn bin thay i, kt qu to ra 3 triger D. Trong v d 1, nu B,C,D l tn hiu th kt qu hon ton khc. Xem v d phn php gn tn hiu.

c. Lnh if

Lnh ny cho php cc php ton c thc hin trn mt iu kin no . C ba dng c bn l:
+ Dng 1: if (iu_kin) then <Cc_cu_lnh_tun_t>; end if; + Dng 2:

End Behavior;

195

Chng 9: Ngn ng m t phn cng VHDL

if (iu_kin) then <Cc_cu_lnh_tun_t>; else <Cc_cu_lnh_tun_t>; end if; + Dng 3: if (iu_kin_1) then <Cc_cu_lnh_tun_t>; elsif elsif else <Cc_cu_lnh_tun_t>; end if; (iu_kin_2) then <Cc_cu_lnh_tun_t>; (iu_kin_3) then <Cc_cu_lnh_tun_t>;

Trong lnh if/else, ta phi ch mt s iu sau:

+) iu kin ng u tin c tm thy s c thc hin. +) Cc iu kin c th chng lp ln nhau.

V d:

te
then

process (A, B, C, D, Sel) begin If (Sel = Z <= A ; elsif (Sel = Z <= B ; elsif (Sel = Z <= C ; elsif (Sel = Z <= D ; end if; end process ; 00) 01) 10) 11)

ch

+) iu kin u tin trong lnh if/else c u tin.

.c
A B C D Sel Z D C B Z A

d. Lnh case:

Lnh case c s dng trong trng hp c mt biu thc kim sot nhiu r nhnh trong chng trnh VHDL. Cc lnh tng ng vi mt trong cc la chn s c thc hiu nu biu thc kim sot c gi tr bng gi tr tng ng ca la chn . C hai dng c bn:
Dng 1: Case (biu_thc_kim_sot) is When <gi_tr_la_chn> => <Cc_cu_lnh_tun_t>; When <gi_tr_la_chn> =>

196

.4
then then then

om .v

Chng 9: Ngn ng m t phn cng VHDL

<Cc_cu_lnh_tun_t>; ... end case; Dng 2: Case (selector expression) is When <gi_tr_la_chn> => <Cc_cu_lnh_tun_t>; When <gi_tr_la_chn> => <Cc_cu_lnh_tun_t>; ... When others => <Cc_cu_lnh_tun_t>; end case;

Cc ch khi dng lnh case:

+) Tt c cc gi tr ca biu thc la chn phi c ch r. +) Khng c cc gi tr la chn b chng lp ln nhau.

ch
Z Z Z Z <= <= <= <= A B C D ; ; ; ;

process begin

(A, B, C, D, Sel )

.c
A B C D Sel Z
Null;

V d:

end case ; end process ;

e. Cu lnh rng Null

Trong VDHL khi chng trnh m phng gp cu lnh Null n s b qua lnh ny v thc hin lnh tip theo sau. Thng thng lnh Null dng ch trng hp khng thc hin ca lnh mt cch tng minh khi c cc iu kin tr li gi tr true. Do lnh Null thng c dng trong cc cu lnh case i vi nhng gi tr la chn khng cn thao tc. V d:

Cu lnh rng c c php nh sau:

.4

te

case Sel is when 00 when 01 when 10 when 11

=> => => =>

om .v
197

Chng 9: Ngn ng m t phn cng VHDL

process begin

(A, B, C, D, Sel )

A B C Sel Z

case Sel is when 00 => Z <= A ; when 01 => Z <= B ; when 10 => Z <= C ; when others => Null; end case ; end process ;

f. Cc lnh lp

Lnh lp loop cha thn vng lp bao gm dy cc cu lnh s c thc hin khng hoc nhiu ln. C php ca lnh lp nh sau:
[<nhn>:] [<s__lp>] loop {<lnh_tun_t>}| {next [<nhn>] [when <iu_kin>];}| {exit [<nhn>] [when <iu_kin>];} end loop [nhn];

Count_down: Process Begin

Variable Min,Sec: integer range 0 to 60; L1: loop

End loop L1; End process Count_down;

198

V d vng lp khng cha s lp:

L2: loop exit L2 when (Sec=0); wait until CLKevent and CLK=1; Sec:=Sec-1;

End loop L2; Exit L1 when (Min=0); Min:=Min-1; Sec:=60;

.4

Vi nhng vng lp khng cha [<s__lp>], cc lnh trong dy lnh tun t s c thc hin cho ti khi c ngt bi cu lnh exit. Trong cu lnh next cng c dng thay i trnh t thc hin thn ca vng lp.

te

- <s__lp>: vng lp vi s lp for hoc vng lp while, v vng lp khng cha cc s lp.

ch

- <nhn>: nhn ca vng lp v thng c dng xy dng nhng vng lp lng nhau, trong mi vng lp c kt thc bi t kha end loop.

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL V d vng lp cha <s__lp> dng for:
process ( A, B_bus ) begin for i in 7 downto 0 loop C_bus (i) <= A and B_bus (i); end loop ; end process; hoc: process ( A, B_bus ) begin for i in 0 to 7 loop C_bus (i) <= A and end loop ; end process;

A B_bus (7) A B_bus (6)

C_bus (7) C_bus (6)

. . .
C_bus (0)

A B_bus (0)

B_bus (i);

V d vng lp cha <s__lp> dng while nh sau:

process ( A, B_bus ) variable i:integer:=0; begin while (i<8) loop C_bus (i) <= A i:=i+1; end loop ; end process;

.c

ch
and B_bus (i);

te

.4

S dng VHDL cho php m t h thng phn cng s theo cc mc tru tng khc nhau. Hnh v 9-4 m t cc mc m t tru tng gim dn khi s dng VHDL. + Mc m t theo m hnh hnh vi (Behavioral): mc m t tru tng cao nht, kiu m t ny thng dng cho m hnh phn cng v m phng. + Mc m t theo m hnh lung d liu RTL (Register Tranfer Level): Kiu m t ny kh ti u v c cho kh nng tng hp cao, c lp vi cng ngh. + Mc m t theo m hnh cu trc logic: Kiu m t ny thng s dng cc cu trc logic c xy dng sn, hoc chn trong th vin ca nh cung cp ph hp vi loi cng ngh s dng. + Mc m t theo cu trc layout. Mc m t chi tit nht, m t chi tit ti cu trc bn trong nhng ti nguyn sn c trong cu kin, cch ny ti u cho vic tng hp trn loi cu kin, cng ngh s dng. 199

9.3. CC MC TRU TNG V PHNG PHP M T H THNG PHN CNG S

om .v
A A B_bus (6) B_bus (7) C_bus (7) C_bus (6)

A B_bus (0)

n
. . .
C_bus (0)

Chng 9: Ngn ng m t phn cng VHDL Vi h thng s thng thng c m t theo 3 mc: hnh vi, RTL v cu trc logic. Trong mt thit k c th ch s dng theo mt cch m t, hoc cng c th phi dng kt hp c 3 cch ty theo phc tp ca thit k, yu cu v thi gian thit k, yu cu v s ti u phn cng - t chi tit hn, tru tng hn. - Nhp thit k v m phng nhanh hn.

Behavioral

- M t chi tit hn v ti u vi cng ngh. - Nhp thit k v m phng chm hn

Logic

Layout

.c

Hnh 9-4. Cc mc m t h thng phn cng s.

9.3.1. Phng php m t theo m hnh cu trc logic

Trc khi c s dng trong kin trc ca c h thng, cc thnh phn phi c khai bo mt cch tng minh theo c php sau:
Component <tn_thnh_phn> Port(<khai_bo_danh_sch_cc_cng_cc_b;>) -- Tng t nh khai bo trong thc th End component;

Ch : Cc cng vo ra ca mi thnh phn con khng c kt ni trc tip vi nhau m phi kt ni thng qua tn hiu ni b c cng kiu, cng ln vi cc cng vo ra . C php m t mc ni gia cc thnh phn con nh sau:
<nhn_khi_to>:<tn_thnh_phn>

200

M hnh cu trc ca mt phn t (hoc h thng) c th bao gm nhiu cp cu trc bt u t mt cng logic n gin n xy dng m t cho mt h thng hon thin. Thc cht ca vic m t theo m hnh cu trc l m t cc phn t con bn trong h thng v s kt ni ca cc phn t con . Cch thc m t cu trc ca thnh phn con cng tng t nh cch thc m t thc th. Trc ht m t cu trc ca thnh phn con, chng ta phi xc nh r cc giao din ca thnh phn con. Cc giao din ny chnh l cc ng tn hiu vo v ra t thnh phn con.

.4

te

ch

om .v
DFF CLB_ R5C5 CLB_ R5C6

AND_OR2

RTL

Chng 9: Ngn ng m t phn cng VHDL

port map ([<tn_cng_cc_b> =>] <biu_thc> {[<tn_cng_cc_b>=>]<biu_thc>});

Cu trc port map nh x cc cng ca phn t vo cc tn hiu. nh x ny c th hiu nh vic kt ni cng tng ng ca phn t vo ng tn hiu. Cu trc port map t tng ng mi cng thc ca phin bn vi mt cng cc b thnh phn. Thc hin ni cc cng vo ra ca cc thnh phn con vi cc chn vo ra ca h thng hoc ni vi tn hiu ni b trong h thng kt ni ti cc cng vo ra ca cc thnh phn con khc. nh x c thc hin theo v tr theo tn: + Khi s dng nh x theo v tr, chng ta a ra danh sch cc tn hiu tun theo ng trt t m cng c khai bo.

<tn_cng_cc_b> => <tn_tn_hiu_thc>

V d m t m hnh cu trc mt thanh ghi 4 bt c xy dng t 4 triger D. C th m t triger D sau sau m t s mc ni cc phn t triger D to thnh thanh ghi. - M t triger D nh sau:

ch

entity DFF is port ( D, Clock : in std_logic ; Reset : in std_logic ; Q : out std_logic) ; end entity DFF ;

.c
D Q
Reset
201

architecture RTL of DFF is begin process (Clock, Reset) Clock begin If (Reset = 1 ) then Q <= 0 ; elsif (Clockevent and Clock = 1) then Q <= D ; end if; end process ; end architecture RTL;

.4

te

om .v

+ i vi trng hp nh x theo tn, chng ta s dng cu trc nh x tng minh t tng ng vi mi cng vi cc tn hiu thc:

Chng 9: Ngn ng m t phn cng VHDL - V d M t cu trc ca thanh ghi:

entity REG_4 is port (D_in: in std_logic_vector (3 downto 0); Clk, Rst: in std_logic; Q_out: out std_logic_vector (3 downto 0)); end REG_4; D_in(3) architecture Structural of REG_4 is component DFF port ( D,Clock : in std_logic; Reset : in std_logic; Q : out std_logic); end component; begin -- nh x theo v tr:

REG_4
DFF U3

Q_out(3)

D_in(2)

DFF U2

Q_out(2)

U3:DFF port map(D_in(3), Clk, Rst, Q_out(3)); D_in(0) U2:DFF port map(D_in(2), Clk, Rst, Q_out(2)); U1:DFF port map(D_in(1), Clk, Rst, Q_out(1)); Clk

Reset =>Rst,Q =>Q out(0));

9.3.2. Phng php m t theo m hnh hnh vi (Behavioral):

V d m t h thng cnh bo theo m hnh hnh vi. H thng gm c u vo t cc sensor (Front_Door, Rear_Door, Window), u vo t bn phm bm Keypad, tn hiu Clk, Reset v u ra iu khin ci bo ng Alarm_Siren . Chc nng hot ng ca h thng nh sau: Nu mi khi c mt sensor no c kch hot, th h thng kim tra m bn phm. Nu sau 20 giy m khng c m bn phm nhp ng nhp vo th ci bo ng s c bt ln.

202

y l mc m t tru tng nht, ch yu l m t theo chc nng ca h thng s theo yu cu u vo v p ng ra s dng cc cu trc lnh nh ca ngn ng lp trnh bc cao nh PROCESS , WAIT, IF, CASE, FOR-LOOP M t theo cch ny tnh ng ngha t nhin v gii thut rt cao, nhp thit k rt nhanh, nhng cu trc ca phn cng thng khng r. Tuy nhin vi nhng h thng phc tp, yu cu cn thit k nhanh, m khng cn yu cu v mc ti u phn cng cao thng dng cch m t ny. Ngi thit k ch m t chc nng, hnh vi c mong i ca thit k bng cch s dng m t dng vn bn v cc phn t th. Phng php m t ny thng dng cho m phng.

.4

te

ch

.c

-- nh x theo tn: U0:DFF port map(Clock =>Clk, D =>D_in(0),

om .v
DFF U0

D_in(1)

Rst

n
DFF U1

Q_out(1)

Q_out(0)

Chng 9: Ngn ng m t phn cng VHDL

Keypad Front_Door Rear_Door Window Clk Reset

Security_1
Alarm_Siren

9.3.3 Phng php m t theo m hnh lung d liu RTL

H thng c biu din theo m hnh RTL bao gm tp cc thanh ghi v cc php ton c thc hin trn d liu s nh phn c lu trong cc thanh ghi. Lung d liu v vic x l d liu thc hin trn s liu c cha trong cc thanh ghi c coi nh l hot ng chuyn i gia cc thanh ghi. V d m hnh RTL ny c s dng biu din cu trc b vi x l. H thng s c biu din theo m hnh RTL khi chng c xc nh bi 3 thnh phn nh sau:
-

Tp cc thanh ghi trong h thng. Cc php ton c thc hin trn d liu c lu trong cc thanh ghi. Nhng iu khin gim st chui tun t cc php ton trong h thng. 203

architecture Behavioral of Security_1 is constant Delay_Period : time := 20 s; begin process (Keypad,Front_Door,Rear_Door,Window) begin if (Front_Door or Rear_Door or Window ) then If (Keypad = 0011) then Alarm_siren <= false ; else Alarm_Siren <= true after Delay_Period ; end if ; end if ; end process ; end Behavioral;

.4

te

ch

.c

om .v

entity Security_1 is port (Clk, Reset : in std_logic ; Keypad : in std_logic_vector (3 downto 0) ; Front_Door, Rear_Door, Window: in boolean ; Alarm_Siren : out boolean ) ; end Security_1 ;

Chng 9: Ngn ng m t phn cng VHDL Thanh ghi gm nhm cc Trig cha d liu nh phn v c kh nng thc hin mt hoc nhiu php ton c bn. Mt thanh ghi c th np thng tin mi, dch thng tin Mt b m c coi nh l mt thanh ghi c kh nng tng, gim gi tr tun t. Mt Trig c th coi nh l thanh ghi 1 bit. Phn mch gm c cc Trig v cc cng lin quan trong bt c mch tun t no c th c gi l nhng thanh ghi. Cc php ton c thc hin trn d liu cha trong cc thanh ghi l nhng php ton c bn c th c thc hin song song trn chui bit trong mt chu k clock. Kt qu ca php ton c th thay th d liu trc ca thanh ghi, hoc kt qu c th c chuyn n thanh ghi khc. C 4 kiu php ton nh sau:

+ Php ton logic. + Php dch.

iu khin khi to chui cc php ton bao gm tn hiu nh thi cho php thc hin tun t cc php ton theo cch c m t trc. C th coi m hnh RTL l m hnh m t hnh vi theo tng xung clock ca h thng s. H thng s c m t bng VHDL theo m hnh RTL c kh nng tng hp rt cao v rt d dng trong vic trao i gia cc cng c tng hp, thit k, v c th tng hp trn cc cng ngh PLD khc nhau. Theo m hnh RTL, h thng s c m t bng cc tin trnh t hp (combinatorial process) v cc tin hot ng theo clock (clocked process)

ch
Z
begin Q <= 0; if end if ;

.c

V d tin trnh t hp nh sau:

Clocked process Mch logic t hp c th m t bng cc cu trc lnh song, tuy nhin thng dng cc process t hp. Trong cc process t hp tt c cc tn hiu vo ca mch t hp phi c a vo danh sch tn hiu kch thch.

.4

9.3.3.1. M t mch t hp

te

process(A,B) A begin B Z <= A or B ; end process;

process (D, En) -- gn mc nh u ra

om .v
D E n

+ Php ton s hc.

Combinatorial process

En = 1 then Q <= D ;

end process ;

Ch trong cc process t hp nn c php gn gi tr mc nh cho u ra trnh trng hp mch b bin thnh mch cht theo mc.

204

n
Q

+ Php chuyn i: truyn d liu t thanh ghi ny sang thanh ghi khc.

Chng 9: Ngn ng m t phn cng VHDL

process (D, En) begin if En = 1 then end if ; end process ;

D
Q <= D ;

En

9.3.3.2. M t mch tun t:

process ( Clk, reset ) begin if reset = 1 then Q <= 0 ; elsif (Clk`event and Q <= D ; end if ; end process ;

ch
Clk = 1) then Q <= 0 ;

V d m t hot ng ca Triger D lm vic theo sn dng vi cc tn hiu Reset khng ng b nh sau:

.c
then

Tin trnh hot ng theo clock c th c m t thnh tin trnh ng b (danh sch tn hiu kch thch ch c duy nht tn hiu clock, mi bin i ca mch c ng b theo sn clock) hoc thnh tin trnh khng ng b.

om .v
D Clk
D Clk Reset

Mi cu lnh tun t tr cc lnh wait, loop, if vi nhng tn hiu iu khin theo sn u c th dng m t cc mch t hp. Cc php ton s hc, logic, quan h u c th c s dng trong biu thc.

.4

te

V d m t hot ng ca Triger D lm vic theo sn dng vi cc tn hiu Reset ng b nh sau:

process ( Clk ) begin if (Clk`event if reset = elsif then end if ; end if ; process ;

and

Clk = 1) then

Q <= D ;

end

n
Reset
Q

Khi m t mch logic t hp cc bin v tn hiu trong mt process khng c nhn gi tr khi to trc bi v mch t hp khng cha cc phn t nh. Khi trong m hnh mch cc bin hoc tn hiu c khi to gi tr trc, chng trnh tng hp s to ra cc phn t nh lu tr cc gi tr khi to, mch tr thnh mch c nh.

205

Chng 9: Ngn ng m t phn cng VHDL

Tm li biu din h thng s theo m hnh RTL cn s dng cc cu trc thanh ghi (Registers) v mch t hp (combinational logic), v d t datapath theo m hnh RTL nh hnh v 9-5 sau:

Hnh 9-5. Mt m hnh RTL

M t VHDL cho m hnh trn c th thc hin theo 2 cch nh sau:

architecture SPLIT of DATAPATH is signal X1, Y1, X2, Y2 : ... begin REG : process (CLK) begin X1 <= Y0; X2 <= Y1; X3 <= Y2; end if; end process;

if (CLK'event and CLK = '1') then

te

ch
Registe rs

206

end SPLIT;

LOGIC : process (X1, X2) Y1 <= F(X1); Y2 <= G(X2);

begin

end process;

.4

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL

architecture COMBINED of DATAPATH is signal X1, X2 : ... begin

process (CLK)
begin if (CLK'event and CLK = '1') then X2 <= F(X1); X3 <= G(X2); X1 <= Y0; end if; end process;

-- Registers

Combinational Logic

9.3.4 Phng php m t theo m hnh hnh trng thi (my trng thi State Machine)

Hot ng ca mt h thng s tun t c th c m t di dng hnh trng thi Moore hoc Mealy. Dng VHDL c th m t c hnh chuyn i trng thi . Bng sau cho bit kh nng m t hnh trng thi dng VHDL:

1 2 3 4 5 6

- Trng thi logic hin ti

- Xc nh trng thi logic tip theo - Xc nh u ra

- nh gi mi trng thi

te
Clock

- t tn cho cc trng thi

- nh gi cc iu kin u vo

.4

Tng kt li cc kiu hnh trng thi nh sau:

- M hnh Moore: Kt qu u ra ch ph thuc vo trng thi hin ti.

Inputs

ch
Current State Register

.c
- Lnh Case - Lnh if/else

STT

Yu cu m t

- Process hot ng theo clock - Process t hp

- Process t hp - Kiu d liu lit k

Next State Logic

om .v
Output Logic

S dng cu trc trong VHDL

n
Outputs
207

Chng 9: Ngn ng m t phn cng VHDL

- M hnh Mealy: u ra ph thuc vo c trng thi hin ti v tn hiu vo.

Inputs

Next State Logic Clock

Current State Register

Output Logic

Outputs

- Cch s dng kiu d liu lit k t tn cho cc trng thi nh sau:

architecture RTL of FSM is

begin

- Cch s dng hng m ha cc trng theo nh mong mun:

subtype My_State is std_logic_vector( 0 to 5 ) ; constant Init constant Load constant Init signal Curr_State, . . . : My_State : My_State : My_State Next_State := 111000 ; := 101010 ; := 000011 ; : My_State ;

begin --architecture

208

signal Current_State, Next_State : My_State; . . .

. . . type My_State is ( Init, Load, Fetch, Stor_A, Stor_B) ;

.4

te

ch

Clock

.c

Inputs

Next State Logic

Current State Reg

Output Logic

om .v
Output Reg Moore Reg Outputs Moore Mealy Output Reg Mealy Reg Outputs

Trong thc t h thng s thng c m t bng vic kt hp c m hnh Moore v Mealy:

Chng 9: Ngn ng m t phn cng VHDL - m t qu trnh chuyn i trng thi v cp nht kt qu u ra ng vi mi trng thi thng thng s dng cch m t bng nhiu tin trnh + Tin trnh cp nhp trng thi mi ca h thng (tin trnh Sync).
Sync: process begin . . . ( CLK , RST)

end process Sync ;

+ Tin trnh kim tra iu kin chuyn i trng thi (tin trnh Comb).
Comb: process begin . . . ( Curr_State, In1, In2)

end process Comb ;

end process Outputs ;

- V d b m thp phn thun nghch ng b c hnh trng thi nh sau:

.4

te

Outputs: process begin . . .

ch

+ Tin trnh cp kt qu u ra ng vi mi trng thi (tin trnh Outputs).

( Curr_State, In1, In2)

.c

om .v
209

Chng 9: Ngn ng m t phn cng VHDL

RESET

S0 if UP='0' then Z='1' else Z='0' UP='0' UP='1'

UP='0' S1 Z='0' UP='1'

UP='0' S2 Z='0' UP='1' UP='1' UP='0'

S9 if UP='0' then Z='0' else Z='1' UP='1' S8 Z='0' UP='0' UP='1' UP='1' S7 Z='0' UP='0' S6 Z='0' UP='1'

S3 Z='0' UP='1' UP='0'

UP='0'

Z='0'

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY FSM IS

PORT (CLK,RESET,UP: IN std_logic; END;

ARCHITECTURE BEHAVIOR OF FSM IS

SIGNAL sreg : std_logic_vector (3 DOWNTO 0); SIGNAL next_sreg : std_logic_vector (3 DOWNTO 0); CONSTANT S1 : std_logic_vector (3 DOWNTO 0) :="0001"; CONSTANT S3 : std_logic_vector (3 DOWNTO 0) :="0011";

BEGIN Sync: PROCESS (CLK) BEGIN IF CLK='1' AND CLK'event THEN

210

CONSTANT S4 : std_logic_vector (3 DOWNTO 0) :="0100"; CONSTANT S5 : std_logic_vector (3 DOWNTO 0) :="0101"; CONSTANT S6 : std_logic_vector (3 DOWNTO 0) :="0110"; CONSTANT S7 : std_logic_vector (3 DOWNTO 0) :="0111"; CONSTANT S8 : std_logic_vector (3 DOWNTO 0) :="1000"; CONSTANT S9 : std_logic_vector (3 DOWNTO 0) :="1001"; SIGNAL next_Z : std_logic;

CONSTANT S2 : std_logic_vector (3 DOWNTO 0) :="0010";

CONSTANT S0 : std_logic_vector (3 DOWNTO 0) :="0000";

.4

te

Z : OUT std_logic);

ch

.c

M t VHDL cho hnh trng thi trn nh sau:

om .v
UP='0' UP='1' S5 Z='0' UP='0'

S4

Chng 9: Ngn ng m t phn cng VHDL

if RESET='1' then sreg<= S0; else sreg <= next_sreg; end if; END IF; END PROCESS; Comb: PROCESS (sreg,UP) CASE sreg IS WHEN S0 => IF ( UP='0' ) THEN ELSE END IF; WHEN S1 => IF ( UP='0' ) THEN ELSE END IF; WHEN S2 => ELSE

next_sreg<=S1;

IF ( UP='0' ) THEN END IF;

ch

WHEN S3 => ELSE

te
END IF; ELSE END IF; ELSE END IF; ELSE END IF; ELSE

.4 w
WHEN S4 =>

IF ( UP='0' ) THEN

IF ( UP='0' ) THEN

WHEN S5 => IF ( UP='0' ) THEN next_sreg<=S4; next_sreg<=S6;

WHEN S6 => IF ( UP='0' ) THEN next_sreg<=S5; next_sreg<=S7;

WHEN S7 => IF ( UP='0' ) THEN next_sreg<=S6; next_sreg<=S8;

.c

next_sreg<=S2;

next_sreg<=S3;

next_sreg<=S4;

next_sreg<=S5;

om .v
next_sreg<=S9; next_sreg<=S0; next_sreg<=S1; next_sreg<=S2; next_sreg<=S3;

n
211

BEGIN

Chng 9: Ngn ng m t phn cng VHDL

END IF; WHEN S8 => IF ( UP='0' ) THEN ELSE END IF; WHEN S9 => IF ( UP='0' ) THEN ELSE END IF; END CASE; END PROCESS; Outputs: PROCESS (sreg,UP) BEGIN IF UP='1' THEN if sreg=S9 then else end if; ELSE if sreg=S0 then else end if; END IF; END PROCESS; END BEHAVIOR; Z<= '1'; Z<= '0'; next_sreg<=S8; next_sreg<=S0; next_sreg<=S7; next_sreg<=S9;

Thit k vi s tr gip ca my tnh ca cc h thng k thut s c dng rng ri trong cng nghip. Do , ta cn phi hiu cc khi nim khc nhau trong qu trnh thit k. Ngn ng m t phn cng ph bin VHDL l loi ngn ng c trnh by trong chng ny. y l mt ch rt rng nn chng ti khng th trnh by chi tit ca VHDL. Tuy nhin cc khi nim c bn c trnh by y s gip cho chng ta hc nhng chi tit v ngn ng t nhng quyn sch vit v VHDL

212

TM TT

.4

te

ch
Z<= '0';

Z<= '1';

.c

om .v

WHEN OTHERS => next_sreg<=S0;

Chng 9: Ngn ng m t phn cng VHDL

CU HI N TP CHNG 8 V CHNG 9

1.

c im no di y l nhc im ca phng php thit k mch dng IC c chc nng c nh? A. B. C. D. Chi ph thit k thp Vn hnh nhanh xung quanh bn thit k Kh khn khi trin khai cc thit k phc tp Tng i d dng khi th nghim cc mch thit k

2.

c im no di y l u im ca phng php thit k mch dng IC c chc nng c nh? A. B. C. D. Yu cu cng sut in tiu th ln Thiu tnh bo mt Kh khn khi sa cha, nng cp thit k

A. B. C. D. 4.

CPLD FPGA Vi x l SPLD

c im no di y khng phi l u im ca PLD A. B. C. D.

5.

6.

Trong cu trc ca SPLD khng c phn t no Mng cc cng logic AND,OR. Ma trn kt ni B nh RAM Triger B. C. D.

A.

Khi no sau y khng c trong cu trc ca CPLD A. B. Khi logic gm ma trn hng tch AND, OR Khi Microcell cha ti nguyn v cc Triger, thanh ghi 213

Mt tch hp cao. Bo m tnh bo mt ca thit k Thi gian thit k ngn

Chi ph sn xut s lng ln cao

.4

te

ch

3.

Trong s cc loi cu kin logic sau, loi no khng thuc h PLD

.c

Tng i d dng khi th nghim mch thit k

om .v

Chng 9: Ngn ng m t phn cng VHDL

C. D. 7.

Ma trn kt ni trung tm Vi x l

thc hin hm logic t hp trong FPGA s dng A. B. C. D. Ma trn hng tch AND, OR. Cu trc bng tra LUT da vo SDRAM . Cc cu trc thanh ghi Cu trc vo/ra. FPGA c cu trc khng ng nht CPLD c cu trc ng nht Cu hnh ca CPLD c lu li khi mt in

8.

Xc nh pht biu sai trong s cc pht biu sau A. B. C. D.

Cu hnh trong FPGA da vo cng ngh SRAM c lu li khi mt in

9.

Trnh t thc hin trong lu thit k cho CPLD/FPGA l: A. B. C. D.

Nhp thit k, kim tra thit k, tng hp thit k, thc hin thit k, m phng nh thi, cu hnh.

10.

Kt qu ca bc tng hp thit k trong lu thit k cho CPLD/FPGA l: A. B. C. File m t VHDL File cu hnh File netlist

11.

12.

214

D.

Kt qu ca bc thc hin thit k trong lu thit k cho CPLD/FPGA l: File m t VHDL File cu hnh File netlist File s mch

A. B. C. D.

Trong bc thc hin thit k ca lu thit k cho CPLD/FPGA gm cc chc nng:

File s mch

.4

te

Nhp thit k, tng hp thit k, kim tra thit k, thc hin thit k, m phng nh thi, cu hnh.

ch

Nhp thit k, kim tra thit k, thc hin thit k, tng hp thit k, m phng nh thi, cu hnh.

.c

Nhp thit k, kim tra thit k, tng hp thit k,m phng nh thi, thc hin thit k, cu hnh.

om .v

Chng 9: Ngn ng m t phn cng VHDL

A. B. C. D. 13.

M phng chc nng, tng hp thit k. Bin dch, map, nh v tr v nh tuyn k ni. M phng nh thi, to cu hnh, bin dch. To file m t HDL, tng hp thit k, nh v tr v nh tuyn k ni.

VHDL l ngn ng: A. B. C. D. Lp trnh hp ng Lp trnh bc cao M t phn cng Lp trnh mng

14.

Trnh t sp xp theo mc m t tru tng tng dn dng VHDL l: A. B. C. D. Mc hnh vi, mc lung d liu RTL, mc logic, mc layout. Mc hnh vi, mc logic, mc lung d liu RTL, mc layout.

Mc layout, mc logic, mc lung d liu RTL, mc hnh vi.

15.

i tng tn hiu (signal) trong ngn ng VHDL : B. C. D. Biu din ng kt ni trong h thng phn cng s Biu din cng vo hoc ra ca thc th

16.

i tng bin (variable) trong ngn ng VHDL : A. C. Lu cc kt qu trung gian Lu nhng gi tr c nh A. Biu din ng kt ni trong h thng phn cng s Biu din cng vo hoc ra ca thc th

17.

D.

Cho khai bo ca cc i tng nh sau: signal A : in std_logic; Php gn no ng: A. B. C. D. A:=1; A<=1; A<=1; A<=true; 215

.4

Lu nhng gi tr c nh

te

A.

Lu cc kt qu trung gian

ch

.c

Mc layout, mc logic, mc hnh vi, mc lung d liu RTL.

om .v

Chng 9: Ngn ng m t phn cng VHDL

18.

Cho khai bo ca cc i tng nh sau: Variable A : in std_logic; Php gn no ng: A. B. C. D. A<=true; A:=1; A<=1; A:=1;

A.

D C

B.

te
D C Q

ch
C. D
C Q

library ieee; use ieee.std_logic_1164.all; entity flop is port(C, D : in std_logic; Q : out std_logic); end flop; architecture archi of flop is begin process (C) begin if (C'event and C='1') then Q <= D; end if; end process; end archi;

.c
D. C
D Q

216

.4

om .v

19.

M hnh phn cng no tng hp c ng vi on m t nh sau:

Chng 9: Ngn ng m t phn cng VHDL

20.

M hnh phn cng no tng hp c ng vi on m t nh sau:

entity flop is port(C, D, CLR : in std_logic; Q : out std_logic); end flop; architecture archi of flop is begin process (C, CLR) begin if (CLR = '1')then Q <= '0'; elsif (C'event and C='0')then Q <= D; end if; end process; end archi; Q Q B. D C. D A. D

om .v
Q

n
D.
D Q C CLR S

C CLR

C CLR

CLR

21.

M hnh phn cng no tng hp c ng vi on m t nh sau:

entity flop is port(C, D, S : in std_logic; Q : out std_logic); end flop; architecture archi of flop is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; else Q <= D; end if; end if; end process; end archi;

.4
B.

te
S

ch
D Q

.c
A.
D C S Q

C.

D C

D.
Q

D C

217

Chng 9: Ngn ng m t phn cng VHDL

22.

M hnh phn cng no tng hp c ng vi on m t nh sau:

entity flop is port(C, D, CE : in std_logic; Q : out std_logic); end flop; architecture archi of flop is begin process (C) begin if (C'event and C='1') then if (CE='0') then Q <= D; end if; end if; end process; end archi;

A.

B.

C.

23.

on m t VHDL no m t cho m hnh mch cht cng dng v xa khng ng b nh sau:

D G Data Input

te .4 w
A.
CLR Q

entity latch is port(G, D, CLR : in std_logic; Q : out std_logic); end latch; architecture archi of latch is begin process (CLR, D, G) begin if (CLR='1') then Q <= '1'; elsif (G='1') then Q <= D; end if; end process; end archi;

218

ch
B.

.c
Positive Gate Asynchronous Clear (active High) Data Output
entity latch is port(G, D, CLR : in std_logic; Q : out std_logic); end latch; architecture archi of latch is begin process (CLR, D, G) begin if (CLR='0') then Q <= '0'; elsif (G='1') then Q <= D; end if; end process; end archi;

om .v
D.

Chng 9: Ngn ng m t phn cng VHDL

C.
entity latch is port(G, D, CLR : in std_logic; Q : out std_logic); end latch; architecture archi of latch is begin process (CLR, D, G) begin if (CLR='1') then Q <= '0'; elsif (G='1') then Q <= D; end if; end process; end archi;

D.
entity latch is port(G, D, CLR : in std_logic; Q : out std_logic); end latch; architecture archi of latch is begin process (CLR, D, G) begin if (CLR='1') then Q <= '0'; elsif (G='0') then Q <= D; end if; end process; end archi;

24.

on m t kin trc no m t cho m hnh mch cht cng o v Preset khng ng b nh sau:

entity latch is port(D : in std_logic_vector(3 downto 0); G, PRE : in std_logic; Q : out std_logic_vector(3 downto 0)); end latch;

A.

.4

Trong m t thc th nh sau:

te

architecture archi of latch is begin process (PRE, G) begin if (Q='1') then Q <= "1111"; elsif (PRE='0') then Q <= D; end if; end process; end archi;

ch
PRE

.c
G Inverted Gate Asynchronous Preset (active High) Q[3:0] Data Output

D[3:0] Data Input

om .v
B.

architecture archi of latch is begin process (PRE, G) begin if (PRE='1') then Q <= "1111"; elsif (G='0') then Q <= D; end if; end process; end archi;

219

Chng 9: Ngn ng m t phn cng VHDL

C.
architecture archi of latch is begin process (PRE) begin if (PRE='1') then Q <= "1111"; elsif (G='0') then Q <= D; end if; end process; end archi;

D.
architecture archi of latch is begin process (PRE, G) begin if (PRE='1') then Q <= "1111"; elsif (G='1') then Q <= D; end if; end process; end archi;

25.

on m t kin trc no m t cho cng 3 trng thi sau:

A.

architecture archi of three_st is begin process (I, T) begin if (T='0') then O <= I; else O <= 'X'; end if; end process; end archi;

.4

C.
architecture archi of three_st is begin O <= I when T=1 else Z; end archi;

220

te

entity three_st is port( T, I : in std_logic; O : out std_logic); end three_st;

ch
B.
architecture archi of three_st is begin process (I, T) begin if (T='1') then O <= I; else O <= 'Z'; end if; end process; end archi;

Trong m t thc th nh sau:

.c
D.
architecture archi of three_st is begin O <= I when T=0 else Z; end archi;

om .v

Chng 9: Ngn ng m t phn cng VHDL

26.

on m t kin trc no m t hot ng ca b m tin 4 bit c xa khng ng b c m t thc th nh sau:

entity counter is port( Clk, CLR : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter;

A.
architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (Clk'event and Clk='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi;

B.
architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk) begin if (Clk'event and Clk='1')then if (CLR='1') then tmp <= "0000"; else tmp <= tmp + 1;

C.

architecture archi of counter is begin process (Clk, CLR) begin if (CLR='1') then Q <= "0000"; elsif(Clk'event and Clk='0')

te

then

.4

Q <= Q + 1; end if; end process; end archi;

ch
D.

.c

om .v
end if; end if; end process; Q <= tmp; end archi; end if; end if; end process; Q <= tmp; end archi;

architecture archi of counter is signal tmp: std_logic_vector(3

downto 0); begin process (Clk) begin if (Clk'event and Clk='0')then if (CLR='1') then tmp <= "0000"; else tmp <= tmp - 1;

221

Chng 9: Ngn ng m t phn cng VHDL

27.

M hnh mch s no c m t VHDL nh sau:

entity counter is port( Clk, S : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk) begin if (Clk'event and Clk='1') then if (S='1') then tmp <= "1111"; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;

222

.4

te

C. B m tin 4 bit ra Q[3:0], hot ng D. B m li 4 bit ra Q[3:0], hot ng sn dng ca clock CLK, tn hiu sn dng ca clock CLK, tn hiu thit lp S tch cc dng v ng b thit lp S tch cc dng v khng ng b.

ch

A. B m li 4 bit ra Q[3:0], hot ng B. B m li 4 bit ra Q[3:0], hot ng sn m ca clock CLK, tn hiu sn dng ca clock CLK, tn hiu thit lp S tch cc dng v ng b thit lp S tch cc dng v ng b.

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL

28.

on m t kin trc no m t hot ng ca b m tin 4 bit np khng ng b t tn hiu u vo, hot ng sn clock m v c m t thc th nh sau:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port( Clk, ALOAD : in std_logic; -- Clock v tn hiu np D : in std_logic_vector(3 downto 0); -- u vo b m Q : out std_logic_vector(3 downto 0)); -- u ra b m end counter;

A.
architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk,ALOAD, D) begin if (ALOAD='1') then tmp <= D; elsif (Clk'event and Clk='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi;

B.

C.

te

downto 0); begin process (Clk,ALOAD, D) begin if (ALOAD='1') then tmp <= D; elsif (Clk'event and Clk='0') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi;

.4

architecture archi of counter is signal tmp: std_logic_vector(3

ch
D.

.c

om .v
then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi; then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi;

architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk,D) begin if (ALOAD='1') then tmp <= D; elsif (Clk'event and Clk='0')

architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk) begin if (ALOAD='1') then tmp <= D; elsif (Clk'event and Clk='0')

223

Chng 9: Ngn ng m t phn cng VHDL

29.

M hnh mch s no c m t VHDL nh sau:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port( Clk, SLOAD : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk) begin if (Clk'event and Clk='1') then if (SLOAD='1') then tmp <= "1010"; else tmp <= tmp + 1; end if; end if; end process; Q <= tmp; end archi;

224

C. B m tin 4 bit ra Q[3:0], hot ng D. B m li 4 bit ra Q[3:0], hot ng sn dng ca clock CLK, np ng sn dng ca clock CLK, np b hng s 1010 (theo mc tch cc ng b hng s 1010 (theo mc tch cc dng). dng).

.4

te

A. B m tin 4 bit ra Q[3:0], hot B. B m tin 4 bit ra Q[3:0], hot ng ng sn m ca clock CLK, np sn dng ca clock CLK, np ng b hng s 1010 (theo mc khng ng b hng s 1010 (theo tch cc dng). mc tch cc dng).

ch

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL

30.

on m t kin trc no m t cho m hnh thanh ghi 4 bit hot ng sn dn ca clock, c tn hiu cht clock v thit lp khng ng b,
D[3:0] C PRE CE Q[3:0] u vo d liu 4 bit Clock sn dng Tn hiu thit lp khng ng b mc tch cc cao Tn hiu cht Clock mc tch cc cao u ra d liu 4 bit

M t thc th ca thanh ghi nh sau:

architecture archi of flop is begin process (C) begin if (PRE='1') then Q <= "1111"; elsif (C'event and C='1')then if (CE='1') then Q <= D; end if; end if; end process; end archi;

C.

.4

te

architecture archi of flop is begin process (C, PRE) begin if (PRE='1') then Q <= "1111"; elsif (C'event and C='1')then if (CE='1') then Q <= D; end if; end if; end process; end archi;

ch
D.

A.

.c
B.

library ieee; use ieee.std_logic_1164.all; entity flop is port( C, CE, PRE : in std_logic; D : in std_logic_vector (3 downto 0); Q : out std_logic_vector (3 downto 0)); end flop;

om .v
architecture archi of flop is begin process (C, PRE) begin if (PRE='1') then Q <= "1111"; elsif (C'event and C='1')then if (CE='0') then Q <= D; end if; end if; end process; end archi; architecture archi of flop is begin process (C, PRE) begin if (PRE='1') then Q <= "0000"; elsif (C'event and C='1')then if (CE='1') then Q <= D; end if; end if; end process; end archi;

n
225

Chng 9: Ngn ng m t phn cng VHDL

31.

M hnh mch s no c on m t VHDL nh sau:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port( Clk, SLOAD : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (Clk) begin if (Clk'event and Clk='1') then if (SLOAD='1') then tmp <= "1010"; else tmp <= tmp + 1; end if; end if; end process; Q <= tmp; end archi;

226

C. B m tin 4 bit u ra Q [3:0] hot D. B m tin 4 bit u ra Q [3:0] hot ng vi sn dng clock, np ng vi sn dng clock, np khng ng b gi tr c nh 1010 ng b gi tr c nh 1010 mc tch cc thp mc tch cc cao

.4

te

A. B m tin 4 bit u ra Q [3:0] hot B. B m tin 4 bit u ra Q [3:0] hot ng vi sn m clock, np ng b ng vi sn dng clock, np gi tr c nh 1010 mc tch cc ng b gi tr c nh 1010 mc cao tch cc cao

ch

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL

32.

on m t kin trc no m t cho m hnh b m thun/nghch 4 bit c xa khng ng b, c m t thc th nh sau:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port( C, CLR, up_down : in std_logic; -- C - clock Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (up_down='1') then tmp <= tmp + 1; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;

C.

.4

te

architecture archi of counter is begin process (C, CLR) begin if (CLR='1') then Q <= "0000"; elsif (C'event and C='1') then if (up_down='1') then Q <= Q + 1; else tmp <= tmp - 1; end if; end if; end process; end archi;

ch
D.

.c

om .v

architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (up_down='1') then tmp <= tmp + 1; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;

architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "1111"; elsif (C'event and C='1') then if (up_down='1') then tmp <= tmp + 1; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;

A.

B.

227

Chng 9: Ngn ng m t phn cng VHDL

33.

on m t no m t cho triger JK sau:

Clk

J > K

A.
entity JKFF is Port(J,K,Clk:in std_logic; Q, notQ:out std_logic); end JKFF; architecture Behavioral of JKFF is signal Qtemp: std_logic; signal JK:std_logic_vector(0 to 1); begin JK<=(J,K); process(Clk) begin

C.
Port(J,K,Clk:in std_logic; end JKFF;

architecture Behavioral of JKFF is signal Qtemp: std_logic; signal JK:std_logic_vector(0 to 1); begin JK<=(J,K); begin

when "00" when "01" when "10"

.4
=> Null;

case JK is

te

if(Clk'event and Clk='1') then

ch

.c
end if; Q<=Qtemp;

process(Clk)

if(Clk'event and Clk='0') then case JK is when "00" when "01" when "10" => Null; => Qtemp<='0'; => Qtemp<='1';

=> Qtemp<='0'; => Qtemp<='1';

when others=>Qtemp<=not Qtemp; end case;

when others=>Qtemp<=not Qtemp; end case; end process; notQ<=not Qtemp; end Behavioral;

228

end if;

end process; Q<=Qtemp; notQ<=not Qtemp;

end Behavioral;

om .v

Q, notQ:out std_logic);

entity JKFF is

Chng 9: Ngn ng m t phn cng VHDL

B.
entity JKFF is Port(J,K,Clk:in std_logic; Q, notQ:out std_logic); end JKFF; architecture Behavioral of JKFF is begin process(Clk) begin if(Clk'event and Clk='1') then Q<=J; notQ<=K; end if; end process; end Behavioral;

D.
entity JKFF is Port(J,K,Clk:in std_logic; Q, notQ:out std_logic); end JKFF; architecture Behavioral of JKFF is begin process(Clk) if(Clk'event and Clk='0') then Q<=J; notQ<=K; end if; begin

J0 Q 0 > '1' K0 Q 0

te
> K1 Q1

Clk

A.

architecture Behavioral of cau33 is begin notQ<=not Q; J(0)<=Q(1) nand Q(2); K(0)<='1'; J(1)<=Q(0); end Behavioral; K(1)<= notQ(0) nand notQ(2); J(2)<=Q(1) and Q(0); K(2)<=Q(1);

.4

ch
J1 Q 1

.c
J2 Q 2 > K2 Q 2

34.

on m t no m t ng cho mch sau theo m hnh RTL:

om .v
end process; end Behavioral;

n
229

Chng 9: Ngn ng m t phn cng VHDL

B.
architecture Behavioral of cau33 is signal Clk: std_logic; signal J,K,Q,notQ: std_logic_vector(0 to 2); signal JK0,JK1,JK2: std_logic_vector(0 to 1); begin JK0 <=(J(0),K(0));JK1 <=(J(1),K(1)); JK2 <=(J(2),K(2)); notQ<=not Q; J(1)<=Q(0); end Behavioral; K(1)<= notQ(0) nand notQ(2); J(0)<=Q(1) nand Q(2); K(0)<='1'; J(2)<=Q(1) and Q(0); K(2)<=Q(1);

C.
architecture Behavioral of cau33 is begin process(Clk) begin case JK0 is if(Clk'event and Clk='1') then when "00" when "01" when "10" end case; =>

when others => Q(0)<= not Q(0); end if;

end Behavioral;

230

end process;

.4

te

ch
Null;

=> Q(0)<='0'; => Q(0)<='1';

.c

om .v

Chng 9: Ngn ng m t phn cng VHDL

D.
architecture Behavioral of cau33 is signal Clk: std_logic; signal J,K,Q,notQ: std_logic_vector(0 to 2); signal JK0,JK1,JK2: std_logic_vector(0 to 1); begin JK0 <=(J(0),K(0));JK1 <=(J(1),K(1)); JK2 <=(J(2),K(2)); process(Clk) if(Clk'event and Clk='0') then case JK0 is when "00" when "01" when "10" end case; case JK1 is when "00" when "01" when "10" end case; => => Null; begin

=> Q(0)<='0'; => Q(0)<='1';

when others => Q(0)<= not Q(0);

when others => Q(1)<= not Q(1); case JK2 is

te
when "00" when "01" when "10"

.4 w
end case;

when others => Q(2)<= not Q(2);

end if;

end process; notQ<=not Q; J(0)<=Q(1) nand Q(2); K(0)<='1'; J(1)<=Q(0); K(1)<= notQ(0) nand notQ(2); J(2)<=Q(1) and Q(0); K(2)<=Q(1);

end Behavioral;

ch
=>

.c
Null; Null;

=> Q(1)<='0'; => Q(1)<='1';

=> Q(2)<='0'; => Q(2)<='1';

om .v
231

Chng 9: Ngn ng m t phn cng VHDL

35.

on m t no m t ng cho mch gii m BCD sang m 7 segment. A.

entity BCDto7seg is Port( BCD:in std_logic_vector(3 downto 0); Seg : out std_logic_vector(6 downto 0)); end BCDto7seg; architecture Beh of BCDto7seg is begin with BCD select --abcdefg" Seg<= "1111110" when x"0", "0110000" when x"1", "1101101" when x"2", "1111001" when x"3", "0110011" when x"4", "1011011" when x"5", "1011111" when x"6", "1110000" when x"7", "1111111" when x"8", "1111011" when x"9", 0)); end BCDto7seg; begin 0); Seg : out std_logic_vector(6 downto

C.
entity BCDto7seg is Port ( BCD:in std_logic_vector(3 downto

with BCD select

ch
end Beh;

te

"0000000" when others; end Beh;

.4

232

.c

om .v
--abcdefg" Seg<= "1111110" when "0110000" when x"1", "1101101" when x"2", "1111001" when x"3", "0110011" when x"4", "1011011" when x"5", "1011111" when x"6", "1111111" when x"7", "1111111" when x"8", "1111111" when x"9",

architecture Beh of BCDto7seg is

"0000000" when others;

n
x"0",

Chng 9: Ngn ng m t phn cng VHDL

B.
entity BCDto7seg is Port ( BCD:in std_logic_vector(3 downto 0); Seg : out std_logic_vector(6 downto 0)); end BCDto7seg; architecture Beh of BCDto7seg is begin with BCD select --abcdefg" Seg<= "1111110" when x"0", "0110000" when x"1", "1101101" when x"2", "1111001" when x"3", "0000000" when others; end Beh;

D.
entity BCDto7seg is Port ( BCD:in std_logic_vector(3 downto 0); Seg : out std_logic_vector(6 downto 0)); end BCDto7seg; architecture Beh of BCDto7seg is begin with BCD select Seg<=

.4

te

ch

.c
end Beh;

om .v
--abcdefg"

"1011111" when x"6",

"1110000" when x"7", "1111111" when x"8", "1111011" when x"9", "0000000" when others;

n
233

Chng 9: Ngn ng m t phn cng VHDL

36.

on m t no m t ng cho mch hp knh 8 vo 1 ra: A.

entity Mux is end Mux; architecture Behavioral of Mux is signal I : std_logic_vector(8 downto 0); signal SEL: std_logic_vector(4 downto 0); signal Y :std_logic; begin with SEL select --abcdefg" Y <= I(0) when "0000", I(1) when "0001", I(2) when "0010", I(3) when "0011", I(4) when "0100", I(5) when "0101", I(6) when others; end Behavioral; 0); begin 0); signal SEL: std_logic_vector(2 downto

C.
architecture Behavioral of Mux is signal I : std_logic_vector(7 downto

ch

te

.4 w w w
234

.c
Y<=I(1); Y<=I(2); Y<=I(3); Y<=I(4); Y<=I(5); Y<=I(6); Y<=I(7);

Y<=I(0);

end Behavioral;

om .v
process begin case SEL is when "000" => when "001" => when "010" => when "011" => when "100" => when "101" => when "110" => when others => end case; end process;

signal Y :std_logic;

Chng 9: Ngn ng m t phn cng VHDL

B.
entity Mux is end Mux; architecture Behavioral of Mux is signal I : std_logic_vector(7 downto 0); signal SEL: std_logic_vector(2 downto 0); signal Y :std_logic; begin with SEL select --abcdefg" Y <= I(0) when "000", I(1) when "001", I(2) when "010", I(3) when "011", I(4) when "100", I(5) when "101", I(6) when "110", end Behavioral;

D.
architecture Behavioral of Mux is signal I : std_logic_vector(7 downto 0); signal SEL: std_logic_vector(2 downto 0); signal Y : begin begin process(I) std_logic;

.c
Y<=I(2); Y<=I(3); Y<=I(4); Y<=I(5); Y<=I(6); Y<=I(7);

ch

te

I(7) when others;

.4 w w w

om .v
case SEL is when "000" => Y<=I(0); Y<=I(1); when "001" => when "010" => when "011" => when "100" => when "101" => when "110" => when others => end case; end process; end Behavioral;

n
235

p n v hng dn tr li

P N V HNG DN TR LI
CHNG 1
1. 2. 3. 4. 5. 6. Bit l s nh phn c mt ch s. 1byte = 8 bit. b c a d a

CHNG 2
Bi 1. 1. a 2. b Bi 2.2 1. c 2. b Bi 2.3 d Bi 2.4

d. Do u bng A+AB Bi 2.5

- Mc logic v phn tch

- Tr truyn lan v phn tch - Cng sut tiu th v phn tch

236

- H s ghp ti v phn tch - phng v nhiu v phn tch - Mt s tham s khc

Bi 2.6 c Bi 2.7 c Bi 2.8

- Nu c khi nim v ti u ho mch in cc h cng

.4

te

ch

.c

om .v

p n v hng dn tr li
- Cng c ti u ho - a ra v d v phn tch hiu qu k thut, kinh t ca vic ti u ho

Bi 2.10 a Bi 2.11 d Bi 2.12

1.d 3.d 5.c 7.b 9.d 11.a 13.d

.c ch

CHNG 4

te
1.a 3.c 5.c 7.b 9.a 11.a 13.c 15.b 17.a 19.c 1.a

.4 w w w
CHNG 5

om .v
2.a 4.b 6.a 8.c 10.b 12.d 14.a 2.d 4.c 6.d 8.c 10.c 12.d 14.a 16.b 18.b 20.d 2.c

CHNG 3

n
237

p n v hng dn tr li

3.c 5.d 7.c 9.d 11.a 13.d 15.c 17.d 19.a 21.b 23.b 25.b 27.c 29.c 31.b 33.c 35.c

4.b 6.a 8.d 10.c 12.b 14.c 16.a

ch

.4
39.b 1.c 3.b 5.b 7.c 9.a 1.a 3.c 5.c

37. Xem v d phn 5.4.1.2

te

CHNG 6

CHNG 7
2.c 4.b 6.a

238

.c
30.a 32.d 34.a 36. Xem v d phn 5.4.1.2 38.d 40.a 2.a 4.d 6.b 8.c 10.d

om .v
22.d 24.a 26.c 28.d

20.a

18.b

p n v hng dn tr li

7.b 9.c

8.a 10.c

CHNG 8 V CHNG 9
1.C 3.C 5.C 7.B 9.D 11.B 13.D 15.B 17.C 19.A 21.D 23.C 2.D 4.D 6.D 8.D 10.C 12.B

ch

te .4
25.D 27.B

29.C 31.B 33.C 35.A

.c

om .v
14.D 16.A 18.D 20.D 22.A 24.B 26.A 28.C 30.C 32.A 34.D 36.B

n
239

Mc lc

TI LIU THAM KHO

1. Gio trnh K thut s - Trn Vn Minh, NXB Bu in 2002. 2. C s k thut in t s, i hc Thanh Hoa, Bc Kinh, NXB Gio dc 1996 . 3. K thut s, Nguyn Thy Vn, NXB Khoa hc v k thut 1994.

6. Fundamentals of logic design, fourth edition, Charles H. Roth, Prentice Hall 1991. 7. Digital engineering design, Richard F.Tinder, Prentice Hall 1991 .

8. Digital design principles and practices, John F.Wakerly, Prentice Hall 1990. 9. VHDL for Programmable Logic by Kevin Skahill, Addison Wesley, 1996

10. The Designer's Guide to VHDL by Peter Ashenden, Morgan Kaufmann, 1996.

240

.4

te

ch

11. Analysis and Design of Digital Systems with VHDL by Dewey A., PWS Publishing, 1993.

.c

om .v

5. L thuyt mch logic v K thut s, Nguyn Xun Qunh - NXB Bu in - 1984

4. Ton logic v k thut s, Nguyn Nam Qun - Khoa HTC xut bn - 1974

Mc lc

MC LC
LI GII THIU ................................................................................................................................................. 1 CHNG 1: H M ......................................................................................................................................... 2 GII THIU ...................................................................................................................................................... 2 NI DUNG........................................................................................................................................................ 2 1.1. BIU DIN S....................................................................................................................................... 2 1.2. CHUYN I C S GIA CC H M ....................................................................................... 6

1.4. DU PHY NG............................................................................................................................... 9 TM TT.......................................................................................................................................................... 9 CU HI N TP.......................................................................................................................................... 10 CHNG 2: I S BOOLE V CC PHNG PHP BIU DIN HM............................................ 11 GII THIU CHUNG..................................................................................................................................... 11 NI DUNG...................................................................................................................................................... 12 2.1 I S BOOLE ........................................................................................................................................ 12 2.3 CC PHNG PHP RT GN HM.............................................................................................. 14 2.4 CNG LOGIC V CC THAM S CHNH ....................................................................................... 16 TM TT........................................................................................................................................................ 26 CU HI N TP.......................................................................................................................................... 26 GII THIU .................................................................................................................................................... 29 NI DUNG...................................................................................................................................................... 30 3.1. CC H CNG LOGIC ...................................................................................................................... 30 3.2. GIAO TIP GIA CC CNG LOGIC C BN TTL-CMOS V CMOS-TTL.............................. 40

CHNG 4: MCH LOGIC T HP ........................................................................................................... 48 GII THIU CHUNG..................................................................................................................................... 48 NI DUNG...................................................................................................................................................... 49 4.1 KHI NIM CHUNG............................................................................................................................ 49 4.2 PHN TCH MCH LOGIC T HP ................................................................................................. 50 4.3 THIT K MCH LOGIC T HP..................................................................................................... 50 4.4 HAZARD TRONG MCH T HP .................................................................................................... 51 4.5. MCH M HO V GII M .......................................................................................................... 59 4.6 B HP KNH V PHN KNH....................................................................................................... 64 4.7. MCH CNG....................................................................................................................................... 66

TM TT........................................................................................................................................................ 43 CU HI N TP.......................................................................................................................................... 43

.4

CHNG 3: CNG LOGIC TTL V CMOS................................................................................................ 29

te

ch

2.2 CC PHNG PHP BIU DIN HM BOOLE ............................................................................. 12

.c

om .v

1.3 S NH PHN C DU........................................................................................................................ 8

241

Mc lc
4.8. MCH SO SNH. ................................................................................................................................67 4.9. MCH TO V KIM TRA CHN L. ............................................................................................68 4.10. N V S HC V LOGIC (ALU). ...............................................................................................70 TM TT ........................................................................................................................................................70 CU HI N TP..........................................................................................................................................71 CHNG 5: MCH LOGIC TUN T..........................................................................................................75 GII THIU. ...................................................................................................................................................75 NI DUNG ......................................................................................................................................................75 5.1. KHI NIM CHUNG V M HNH TON HC ............................................................................75 5.2. PHN T NH CA MCH TUN T ...........................................................................................76 5.3. PHNG PHP M T MCH TUN T. .....................................................................................81 5.4. CC BC THIT K MCH TUN T. .......................................................................................83 5.5 MCH TUN T NG B...............................................................................................................90 5.6. MCH TUN T KHNG NG B ..............................................................................................98 5.7. HIN TNG CHU K V CHY UA TRONG MCH KHNG NG B ..........................104 5.8. MT S MCH TUN T THNG DNG ...................................................................................108 TM TT ......................................................................................................................................................116 CU HI N TP CHNG 5...................................................................................................................116 CHNG 6: MCH PHT XUNG V TO DNG XUNG.......................................................................125 GII THIU ..................................................................................................................................................125 NI DUNG ....................................................................................................................................................126 6.1. MCH PHT XUNG .........................................................................................................................126 6.2. TRIG SCHMIT.................................................................................................................................129 6.3. MCH A HI I ..........................................................................................................................130 6.4. IC NH THI....................................................................................................................................134 TM TT ......................................................................................................................................................137 CU HI N TP........................................................................................................................................137 GII THIU ..................................................................................................................................................141 NI DUNG ....................................................................................................................................................141 7.1. KHI NIM CHUNG.........................................................................................................................141 7.2. DRAM .................................................................................................................................................144 7.3. SRAM..................................................................................................................................................145 7.3. B NH C NH - ROM ................................................................................................................146 7.4. B NH BN C NH ...................................................................................................................147 7.5. M RNG DUNG LNG B NH...............................................................................................151 TM TT ......................................................................................................................................................152 CU HI N TP........................................................................................................................................153 CHNG 8: LOGIC LP TRNH (PLD)......................................................................................................155 GII THIU ..................................................................................................................................................155

242

CHNG 7: B NH BN DN...................................................................................................................141

.4

te

ch

.c

om .v

Mc lc
NI DUNG.................................................................................................................................................... 156 8.1. GII THIU CHUNG V LOGIC KH TRNH (PLD) ................................................................... 156 8.2 SPLD ................................................................................................................................................... 157 8.3. CPLD (Complex PLD)....................................................................................................................... 157 8.4. FPGA................................................................................................................................................... 159 8.5. SO SNH GIA CPLD V FPGA.................................................................................................... 161 8.6. QUY TRNH THIT K CHO CPLD/FPGA..................................................................................... 161 TM TT...................................................................................................................................................... 168 CHNG 9: NGN NG M T PHN CNG VHDL ........................................................................... 169 GII THIU .................................................................................................................................................. 169 NI DUNG.................................................................................................................................................... 170 9.1. GII THIU NGN NG M T PHN CNG VHDL ............................................................... 170 9.2. CU TRC NGN NG CA VHDL ............................................................................................. 171 9.3. CC MC TRU TNG V PHNG PHP M T H THNG PHN CNG S.... 199 TM TT...................................................................................................................................................... 212 CU HI N TP CHNG 8 V CHNG 9....................................................................................... 213 CHNG 1 ................................................................................................................................................... 236 CHNG 2 ................................................................................................................................................... 236 CHNG 3 ................................................................................................................................................... 237 CHNG 4 ................................................................................................................................................... 237 CHNG 5 ................................................................................................................................................... 237 CHNG 6 ................................................................................................................................................... 238 CHNG 7 ................................................................................................................................................... 238 CHNG 8 V CHNG 9 ....................................................................................................................... 239 TI LIU THAM KHO................................................................................................................................. 240

MC LC.......................................................................................................................................................... 241

.4

te

ch

.c

P N V HNG DN TR LI............................................................................................................ 236

om .v

243