EE3011 MULTILEVEL POWER CONVERTERS
UNIT-I
MULTILEVEL TOPOLOGIES
Introduction – Generalized Topology with a Common DC bus – Converters derived
from the generalized topology – symmetric topology without a common DC link –
Asymmetric topology.
Two Marks
1. What is a common DC bus and mention its advantages?
A common DC bus is a centralized DC link shared by multiple converters to distribute power
efficiently. It enables energy exchange between different converters, improving system efficiency.
2. Give one example where a common DC bus is used.
Used in renewable energy systems where multiple power sources and loads share the same DC
link. Rectifiers, inverters, and DC-DC converters can be connected to common dc-bus.
3. Why is a common DC bus beneficial in electric drives?
It allows regenerative braking energy to be reused instead of being wasted as heat.
4. What is a Voltage Source Inverter and current source inverter?
A VSI is an inverter that converts DC voltage into AC output with a fixed or variable frequency.
A CSI is an inverter that converts DC current into AC output while maintaining a controlled
current waveform.
5. What is the main advantage of multi-level converters?
MLI provide lower harmonic distortion and higher efficiency.
It connects different voltage levels efficiently in hybrid energy storage systems.
6. What is a symmetric topology without a common DC link and give an example?
It is a topology where converters operate independently without sharing a centralized DC link.
AC-coupled systems where inverters are directly connected to an AC grid.
7. Why is a symmetric topology without a common DC link more reliable?
It eliminates the need for a large DC-link capacitor, reducing failure points.
8. What is an asymmetric topology and give an example?
A system where power stages or control structures are different, leading to an unbalanced
configuration. Example: Asymmetric Cascaded H-Bridge (ACHB) Inverter.
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9. Why are asymmetric cascaded H-bridge inverters used?
Asymmetric Cascaded H-Bridge (ACHB) inverters are used because they allow operation at
different voltage levels, reducing switching losses and improving efficiency. They provide better
harmonic performance with fewer switches, making them ideal for medium and high-power
applications like renewable energy systems and electric drives.
10. What is a key difference between symmetric and asymmetric topologies?
Symmetric topology has balanced power stages, while asymmetric topology has unbalanced
stages.
11. Which type of topology is commonly used in electric vehicle charging stations
and why?
A generalized topology with a common DC bus is used in EV charging stations because it enables
efficient power distribution, reduces conversion losses, and supports multiple power sources like
the grid, solar panels, and battery storage. It also allows for fast DC charging, scalability, and
bidirectional power flow (V2G technology), making the charging infrastructure more flexible and
efficient.
12. Define Multilevel inverter.
Voltage source multilevel converters synthesizes the output voltage in small steps
nearer to sinusoidal using isolated dc sources or capacitors and have the capability to
work at medium-voltage levels without power transformers.
Advantages:
The blocking voltage of the power devices has limited the supply voltage of
transformer less power converters.
But this limit can be overcome if the number of voltage levels of the converter is
increased.
Moreover, the increment of voltage levels contributes to build a softer AC
voltage with the consequent reduction in harmonic distortion.
Also, the voltage variation rate (dv/dt) is reduced, diminishing the
electromagnetic interference (EMI) problems and other stresses on the power
switches.
13. Classification of MLI
The classic multilevel converters, like the diode-clamped (DCMC), flying capacitor
(FCMC), or cascade H-bridge (CCMC), present modular structures. So in all of them
it is simple to increase the voltage levels adding basic modules.
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14. Define redundant state.
The different combinations of ON and OFF states of the power switches of the
VSMC determine the “switching states” of the converter.
Each state defines one level of the output voltage and depending on the topology,
a given voltage level may be built with different switching states- redundant
states.
15. Define forbidden states.
In some topologies, like the DCMC, there exist some states for which the voltage
level is not determined by the converter, but depends on the sign of the load current.
These states are defined as forbidden states and should be avoided.
13 -Marks
1. Explain generalized with common dc-bus.
The one leg of a symmetric n-level VSMC with a common DC bus is shown in
Figure.
This is built with a specific array of power switching devices and capacitors.
It has a cellular structure in which the number of voltage levels is increased by
adding basic cells.
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The basic cell is the functional unit of the generalized topology, and it is built
with two complementary power switches and one capacitor.
An n-level converter has (n -1) stages.
Each stage is formed by a stack of basic cells.
This cellular structure allows us to increase the number of voltage levels by
implementing a symmetrical growth, in both vertical and horizontal directions.
2. Explain the operation of Basic Cell.
The basic cell is formed with two complementary power switches (Sj, Sj), which
can carry bipolar current, together with a power source (battery, solar panel, etc.)
or a power storage element (capacitor).
The complementary power switches are controlled with a switching function sj,
which has two possible states,
When the switching function equals 1, Sj is ON while Sj is OFF. On the other
hand, when the switching function equals 0, Sj is OFF while Sj is ON.
The output voltage of the cell is measured between nodes g and g-, and it is
defined by the switching function.
Assuming that the voltage variation on Cj is negligible compared to its average
value VC, the output voltage results:
The basic cell has two voltage levels determined by the switching function. State
0 defines a 0V output voltage and state 1 defines an output voltage equal to VC.
The basic cell is the most elementary topology of a voltage source converter. It
corresponds with one leg of a two-level topology.
In this way, the classic two-level voltage source inverter is included in the
generalized topology with the minimum number of voltage levels.
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3. Explain the characteristics of generalized topology.
One leg of an n-level generalized topology is formed by (n -1) cascaded stages.
Each stage employs one less cell than the previous one.
The first stage, near the DC source, has (n-1) vertically connected basic cells,
while the last one, near the load, has only one.
Every basic cell should have the same voltage (VC) in order to synthesize a
symmetric output voltage.
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The voltage level (VC) is fixed by the capacitor voltage divider of the first stage.
Assuming that all the capacitors have the same capacitance, then VC is
A constant and equal voltage source for each cell (VC) in every stage is
guaranteed when all the cells in one stage use the same switching function.
The mechanism to equalize the voltages in each cell of every stage is shown in
Figure.
The figure represents a portion of the first three stages of an n-level leg.
The power switches that are OFF are indicated in gray, while those that are ON
are drawn in black.
It is clearly seen that the switches (S1j) connect the capacitors (C2j) in parallel
with (C1j)(where j = 1, 2, … n – 1).
At the same time, capacitors (C3j) are connected in parallel with (C2(j+1)) through
the switches (S2j).
When switches (S1j) are turned OFF, the first stage changes its state and the
capacitors (C2j) are now connected in parallel with (C1(j+1)) .
A similar change can be observed in the other stages of the leg. In this way the
voltage (VC) is maintained in all the cells of the generalized topology.
It is important to remark that the voltage on every capacitor is preserved when all
the cells in the same stage commutated simultaneously with the same switching
function.
4. Explain the operation of three level generalized topology
The three-level generalized topology has three basic cells in each leg, forming
two stages.
The first one has two cells and is controlled by a switching function S1.
The other has only one cell and is controlled by a switching function S2.
The output voltage of each leg results in:
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The graphic representation of the states and voltages for the three-level topology
is shown in Figure.
Each switching function is located on each axis, so the corners of the square
represent each state and voltage level.
The circuits resulting for each state of the converter is shown in Figure and the
switches that are OFF are indicated in light gray.
State 00 occurs when the switches S1(1,2) and S2 are ON. Then, the output voltage
equals 0V and the capacitor C2 is connected in parallel with C12.
When the second stage changes and S2 is turned on, state 01 takes place.
The capacitor C2 is still in parallel with C12, and they apply the voltage across
them to the output, which equals VDC/2.
For state 11, the switches S1(1,2) and S2 are ON and the output voltage equals VDC.
In this case, the capacitor C2 is connected in parallel with C11.
State 10, the output voltage is defined by the voltage over capacitor C12 and
equals VDC/2.
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It is clear that there are two states, 01 and 10, that generate the same output
voltage. So, these are defined as redundant states.
The connection of capacitors is different in both states, so a careful usage of the
redundant states may serve to correct possible unbalances of the voltages on the
capacitors.
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Switching Table
S11 S11’ S12 S12’ S2 S2’ Output
0 1 0 1 0 1 0V
0 1 0 1 1 0 Vdc/2
1 0 1 0 1 0 Vdc
1 0 1 0 0 1 Vdc/2
0 1 0 1 0 1 0V
5. Explain the operation of diode clamped topology.
The three-level generalized topology shows that (C2) is always connected in
parallel with one of the capacitors of the first stage.
It is possible to eliminate (C2) without altering the voltage levels at the output.
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The converter without (C2) , which is called active neutral point clamping
(ANPC) is shown in above Figure.
A further reduction in semiconductor devices may be obtained by eliminating the
transistors from the switches (S12) and (S11) and leaving only the diodes (De and
De’).
In this case the voltages synthesized by states 00 and 11 are the same as before.
But the voltage generated in states 01 and 10 depends on the sign of the current
in node i.
The Figure shows the connections in these two states, where the switches being
OFF are indicated in light gray.
Analyzing state 01, when the current enters into node i, it finds its way through
the diodes of switches S2 and S1. So the resulting voltage (VIN) equals (VDC).
On the contrary, when the current goes out of node i, it finds its way through the
diodes of switches S2’ and S1’ and the resulting voltage is 0.
In the case of state 10, when the current enters in node i, it finds its way through
switch S2’ and diode De’, resulting in ViN = VDC/2.
On the contrary, when the current goes out of node i, it finds its way through the
diodes of switches S2’ and S1’, resulting in VIN = 0.
So this topology cannot generate the intermediate voltage levels and states 01 and
10, which are considered forbidden states.
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6. Explain the operation of 4- level flying capacitor topology.
A systematic approach to obtain an n-level FCMC from the generalized topology
consists in eliminating the switches from the internal cells while preserving only
their capacitors.
The average voltage on each capacitor equals VDC/3 and presents a three-stage
structure, where each stage is formed by two complementary switches and one or
more flying capacitors.
The 4L-FCMC has three switching functions and eight possible states.
The same as for the 4L-DCMC, the switching functions S1, S2, and S3 define a
cube whose corners represent the topology states.
The voltage levels are also indicated in each corner.
The blocking voltage for each open switch equals the voltage on each capacitor,
which is VDC/3.
There are three redundant states for VDC/3 and three redundant states for 2VDC/3.
These states are used to preserve the voltage on the capacitors of each stage,
similarly as it was analyzed for the 3L-FCMC.
The changes among states are carried out between adjacent states; this means that
they need to pass through state 000.
Beginning in state 001, the switches (S1’, S2’, and S3) are closed and the current
flows through (C3), reducing the charge.
In state 010, the current flows through (S1’, S2, S3’, C2, and C3).
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In this case (C2) loses charge and (C3) recovers the charge lost in state 001.
In state 100, the current flows through (S1, S2’, S3’, and C2).
In this case (C2) recovers the charge lost in state 010.
If the current is almost constant and the topology remains in the different states
for the same amount of time, the net charge and the voltage on the flying
capacitors are preserved.
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7. Explain the operation of symmetric topologies without common dc-link.
One leg of an n-level multilevel topology with independent and isolated power
sources is shown in Figure.
This topology does not have a common DC link for all the legs of the topology.
Each stage has two basic cells connected in parallel and sharing a common DC
source or capacitor.
The different stages are connected in series to obtain an n-level voltage at the
output.
This topology is known as n-level cascaded cell multilevel converter (CCMC).
The voltage of each stage is calculated as the voltage difference of each basic cell.
Then, each stage is controlled with two independent switching functions and the
stage voltage (vj) is calculated as
Where, S(2j–1) and S(2j) are the switching functions and (VC) is the DC voltage
source of the ( jth) stage.
Each stage offers three voltage levels, 0 and ±VC; a series connection of two
stages gives five levels: 0, ±VC, and ±2VC, and the 0 levels of each stage do not
sum a different level.
Continuing with this reasoning, (n-1)/2 stages are required to obtain an n-level
leg voltage (Vio).
Assuming that all stages have the same value of DC voltage source (VC), then
(Vio) is the sum of all the contributions of the (n-1)/2 stages, resulting in
In this topology the leg voltage is the same as the load voltage since the load is
connected between both terminals of the leg.
It is also the phase or line voltage of a multi phase topology, depending on a star
or triangle connection of the load.
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8. Summarise symmetric topologies without common dc-link.
9. Explain about asymmetric topologies.
An important characteristic of the symmetric topologies is their modular structure
and the easiness to increase the number of voltage levels.
The price for this is an important increment of extra components, passive or
active, which is more than proportional to the increment of voltage levels.
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The increment of components also implies a rise in mounting complexity, and
thus in the cost of the power converter.
It is important to look for a different alternative when more than four or five
voltage levels are required.
The hybrid multilevel converter (HMC) is a topology with a cascade of different
stages connected in series but with different values of DC voltages.
Each stage may be built with a different topology, which in turn generates a
different number of voltage levels.
This fact, together with the different values of the DC sources, generates
asymmetric topologies in which there are no equal stages.
The term hybrid is related to the modulation of each stage.
The asymmetry of the DC voltage sources also determines the power handled by
each stage.
The stages with higher DC voltage manage higher power than those with a lower
DC voltage.
It is possible to implement the power switches of the different stages with
different devices.
For example, the high-voltage stages may be implemented with Integrated Gate-
Commutated Thyristor (IGCT) switching at the network frequency.
The low-voltage stages may be implemented with Insulated Gate Bipolar
Transistor (IGBT) switching at high frequency with pulse width modulation
(PWM).
10. Explain about Hybrid asymmetric topologies.
Let us consider a cascade of H-bridges connected in series but with different
values of DC voltages.
Starting with a CCMC with a given number of stages and to increase the number
of voltage levels by adopting different DC voltage sources.
For example, a two-stage CCMC in which the DC voltage source of one stage
doubles the voltage source of the other generates a seven-level HMC (7L-HMC)
instead of the 5L-CCMC obtained with equal voltage sources.
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In a two-stage CCMC with equal DC voltage sources there exist some states in
which the voltage generated by one stage cancels the voltage generated by the
other.
It is not possible to find this situation when different DC voltage sources are used.
Moreover, there are new intermediate voltages generated on the phase voltage
VIN.
The phase voltage of a seven-level HMC can be calculated considering that each
stage is fed with a different voltage,
In a p-stage CCMC in which the DC voltages have a progression such that the
voltage of stage j equals [2(j-1).VC] (With j = 1, 2, …, p), the number of voltage
levels will be n = [2(p+1)-1].
Other commonly used HMCs is that in which the voltage of stage j equals [3(j–
.VC] (with j = 1, 2, …, p), and the resulting number of voltage levels is n = 3p.
1)
11. Explain about Cascaded asymmetric topologies.
There is a first stage built with two stacked basic cells and a second stage built
with a three-level FCMC.
This topology is named Cascade Asymmetric Multilevel Converter (CAMC).
It has two topologically different stages that are fed with different DC voltages,
preserving a common DC link.
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The High-Voltage (HV) stage is a two-cell stack similar to the generalized
topology; it is fed by the DC link voltage.
The Low-Voltage (LV) stage, connected between nodes (w-z) is fed with half the
DC link voltage and has the structure of a three-level flying capacitor cell.
The capacitors (C1 and C2) have the same capacitance and divide the DC link
voltage in two equal shares (VDC/2).
The switches (S1w and S1z) use the same switching function (S1) and the voltage
between nodes (w-z) is fixed to (VDC/2).
The LV stage is fed with half the voltage of the HV stage.
The first term corresponds to the HV stage contribution (0 and VDC/2), while the
second term corresponds to the LV stage contribution (0, VDC/4, and VDC/2).
Switching Table
S1 S2 S3 Vout
0 0 0 0V
0 0 1 VDC/4
0 1 1 VDC/2
1 0 1 3VDC/4
1 1 1 VDC
1 1 0 3VDC/4
1 0 0 VDC/2
0 1 0 VDC/4
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12. Write the necessity and Features of Multi-Level Inverters (MLI)
Necessity of Multi-Level Inverters (MLI):
Multi-Level Inverters (MLI) are required due to the following reasons:
Reduced Harmonics: MLIs generate output voltage with lower Total Harmonic
Distortion (THD), improving power quality.
Higher Voltage Operation: MLIs enable operation at higher voltages without
requiring bulky transformers, making them suitable for medium- and high-power
applications.
Improved Efficiency: By using multiple voltage levels, MLIs reduce switching
losses, enhancing system efficiency.
Lower dv/dt Stress: MLIs produce a staircase waveform, reducing voltage stress
on power electronics components and enhancing their lifespan.
Better Electromagnetic Compatibility (EMC): Lower harmonics reduce
electromagnetic interference, ensuring smooth operation in industrial and power
applications.
Renewable Energy Integration: Widely used in solar and wind energy systems
for efficient power conversion and grid integration.
Features of Multi-Level Inverters (MLI):
Multiple DC Voltage Levels: Uses multiple DC sources or capacitors to
generate stepped AC output.
Types of MLI: Diode-Clamped (Neutral Point Clamped, NPC) MLI, Flying
Capacitor MLI, Cascaded H-Bridge (CHB) MLI.
Modular and Scalable Design: Can be easily expanded by increasing the
number of levels.
Soft-Switching Capabilities: Supports pulse-width modulation (PWM)
techniques to minimize switching losses.
Wide Application Range: Used in high-voltage drives, FACTS devices, electric
vehicles (EVs), and HVDC transmission systems.
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13. Comparison of Symmetric and Asymmetric Multi-Level Inverter (MLI)
Topologies.
Feature Symmetric MLI Asymmetric MLI
All DC sources or voltage DC sources or voltage levels are
Definition
levels are equal. different.
DC Source Equal voltage sources (e.g., V, Unequal voltage sources (e.g., V,
Ratio V, V). 2V, 4V).
Number of More switches required for Fewer switches needed for the same
Switches higher levels. number of levels.
Harmonic Higher THD compared to Lower THD due to optimized
Distortion asymmetric MLI. voltage levels.
Fewer levels for the same Higher number of levels with fewer
Voltage Levels
number of components. components.
Lower efficiency due to more Higher efficiency with fewer
Efficiency
switching losses. components.
Control Simpler control due to equal More complex control due to
Complexity voltage levels. different voltage sources.
Higher cost due to more Lower cost for the same number of
Cost
components. levels.
Used in industrial motor Used in renewable energy, electric
Applications drives, HVDC and power vehicles and high-power
systems. applications.
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