1

DEVELOPMENT AND ANALYSIS OF A NOVEL MULTILEVEL

INVERTER TOPOLOGY WITH REDUCED DEVICE COUNT

Priyesh Bharti, Lipika Nanda

Abstract— A novel MLI structure has been proposed. First, 9-

Level basic MLI structure has been developed and analysed for
low and high frequency modulation techniques. Further, an
extended structure has been developed to generate more number
of output voltage level using lower components. The voltage
stress analysis, power losses analysis and an extensive
comparison study have been presented in detail. The proposed
structure uses lower number of components and sustains lower
TSV as compare to the other structures. Extensive simulation
and hardware studies of the basic 9-Levelstructure have been
presented for validating the merits and effectiveness of the
proposed structure.
Index Terms— dc-ac power conversation, symmetrical novel
topology, TSV, THD

Fig 1. The basic proposed topology

I. INTRODUCTION
Multilevel inverters (MLIs) become viable converter The top DC source (V1, V2) and the lowest DC source (V3,
topologies in the different field of applications such as V4) are associated with two unidirectional switches each. The
renewable energy system, motor drive system, UPS, FACTS, switches S1 and S2are across V2and switches S3 and S4 are
active filtering etc. MLIs can produce staircase output voltage connected across V4 source. A bidirectional switch (S9) is
waveform with better harmonic spectrum and can handle high connected at O point which is the midpoint of the DC sources
power level using medium rated switching devices as as shown in Figure 1. An H-Bridge circuit consisting of 4
compared to classical 2-Level inverters. However, the unidirectional switches (S5, S6, S7, S8) is connected which is
conventional MLI topology namely Diode clamped, Flying responsible for producing the positive and negative voltage
capacitor and cascaded H – Bridge inverters suffer from large levels across the load. The load is connected across XY
number of components such as switching devices, drivers and terminals and the bidirectional switch (S9) is connected
DC sources as the output voltage level increases. This between O and X. The structure can produce 9 output voltage
limitation further increases the size, cost and complexity of the levels by arranging the switches with a specified switching
converter structure. To mitigate this limitation of conventional strategy.
MLIs, a number of innovative MLI structures known as B. General structure of proposed topology
reduced device count MLI (RDC MLIs) have been proposed
in recent years. However, it is very difficult to find a specific The general structure of the proposed multilevel inverter is
topology which has all the advantages. Hence, there has a shown in Fig. 2. It is possible to connect mnumber of basic
scope to develop novel MLI structures which use lower units in series.Table1shows a number of “voltage-levels,-
number of components and sustain lower total standing semiconductor-components,-dc-sources,-and-drivers-based-
voltage (TSV) as compare to the other MLI structures. on-the-number-of-module-units-(m)-and-a-number-of-desired-
levels-(NL).
TABLE I
II. PROPOSED TOPOLOGY EQUATION OF PROPOSED MLI
Based on number of Based on number of
A. Basic structure of proposed topology
module units desired levels
The-basic-unit-of-the-proposed-topology-is-symmetrical-in- Levels (4m+9) NL
nature-so all the DC source are equal in magnitude and-can- Number of (4m+9) NL
produce-9-levels-using-9-power-switches-and-4 non isolated- switches
input-DC-source. Number of (4m+13) (NL+4)
diodes
Drivers (4m+9) NL
Number of DC (2m+4) ½(NL-1)
link
TSV 13{(4m+8)/4}-4 13{(NL-1)/4}-4
The number of level in the form of 4m+9 (where, m = 0, 1, 2…….).
 2

TABLE II
LIST OF ON SWITCHES CORRESPONDING TO EACH OUTPUT VOLTAGE LEVEL OF
PROPOSED 13 LEVEL MLI
Switches States
S S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13
t Vo
a
t
e
1 OFF ON OFF ON OFF ON OFF ON OFF OFF ON ON OFF 6Vdc
2 OFF ON OFF ON OFF ON ON OFF OFF OFF ON ON OFF 5Vdc
3 OFF ON OFF ON ON OFF ON OFF OFF OFF ON ON OFF 4Vdc

4 OFF ON OFF ON OFF OFF OFF OFF OFF OFF ON OFF ON 3Vdc
5 OFF OFF ON ON OFF OFF OFF OFF OFF OFF ON OFF ON 2Vdc
6 ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON Vdc

7 OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF 0
8 OFF OFF OFF OFF ON OFF ON OFF OFF ON OFF OFF ON -Vdc
9 OFF OFF OFF OFF OFF ON ON OFF OFF ON OFF OFF ON -2Vdc

10 OFF OFF OFF OFF OFF ON OFF ON OFF ON OFF OFF ON -3Vdc
11 ON OFF ON OFF OFF ON OFF ON ON ON OFF OFF OFF -4Vdc
12 OFF OFF ON ON OFF ON OFF ON ON ON OFF OFF OFF -5Vdc

13 OFF ON OFF ON OFF ON OFF ON ON ON OFF OFF OFF -6Vdc

Figure 4 represents the schematic output voltage in one cycle

Fig 2.The general structure of the proposed MLI of fundamental voltage of the developed proposed inverter
C. Proposed 13-Level MLI Topology with the associated pulse pattern. As represent in Figure 4all
It has 13-switches and 6 equal DC sources. Here S13 is are turned on a reasonable switching frequency, which reduces
a bidirectional switch. It produces 13 levels of output with a switching losses
certain voltage combination.The proposed structure can 6Vdc
generate ±6Vdc, ±5Vdc, ±4Vdc, ±3Vdc, ±2Vdc, ±Vdc,and zero 5Vdc
voltage levels by applying an appropriate switching strategy. 4Vdc
The list of ON switches for producing the different voltage 3Vdc
2Vdc
levels is shown in Table 2. Further, the load current flow path
1Vdc
and equivalent circuit for different voltage levels and the
current path is shown in red line represent in Fig 5. -1Vdc
-2Vdc
-3Vdc
-4Vdc
-5Vdc
-6Vdc
S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

Fig 3.Proposed 13-Level MLI S11

S12

S13

Fig 4. Switching pattern of proposed converter in one cycle.

 3

D. Voltage stress across switches

S2 S2
V3
S3
V3
S3
The standing voltage across each and every switch, while
S1
V2
S9 S11 S1
V2
S9 S11
generating different output voltage level is represented in a bar
S4 S4

V1 V1
graph. This bar graph gives a clear idea about the switches
Load Load

V4
O

S13
X

R L
Y

V4
O
S13
X
R L
Y
which are not turned on while generating a particular output
S6 S12 S10
S6 S12 S10
voltage as well as the voltage across it at that point of time.
S5 V5 S5 V5

S7 S7
V6 V6
S8 S8
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13
(a) +Vdc (b) Vdc XVDC
20
S2
V3 V3
S2 18
S3 S3

V2 V2
16
S1 S1 S11
S9 S11 S9
S4
S4
14
V1 Load
V1 Load O X Y
O X Y S13 R L

V4
S13 R L
V4 12
S6 S12
S6 S12 S10 S5 V5
S10
10
S5 V5

S7
S7 V6 8
V6 S8
S8
6
(d) 2Vdc
(c) +2Vdc
4
S2
S2 2
V3 V3
S3 S3
0

6L
5L
3L
2L

4L
1L
-6L

-5L

-3L

-1L

0L
-4L

-2L
V2
V2 S1 S9 S11
S1 S9 S11 S4
S4

V1 Load
V1 Load O X Y
S13 R L

Fig 6.5 “Voltage-constraints-on-the-switches

O X Y
S13 R L V4
V4
S6 S12 S10
S6 S12 S5 V5
S5 V5
S10
Figure 6.5 presents the voltage constraints on the switches and
S7

V6
S7
V6
S8
circuit. Figure represents TSV for each levels (-6L,-5L,-
S8
(f) 3Vdc 4l,….0L,1L….5L,6L). [It-also-separates-the-voltage-standing-
(e) +3Vdc on-each-switch-for-levels-by-different-colors.]” It is observed
S2 S2
that the TSV of some group switches has the same value for
V3
S3
V3 S3
all levels. Figure 6.6 also depicts the voltage of switches on a
S1
V2
S9 S11 S1
V2

S4
S9 S11 circle graph, “in-which-switch-S1, S2, S3, S4, S5, S6, S7 and
S4

V1 Load
V1 Load
S8-have-low-voltage-standing-against” TSV for each level.
O X Y
O X Y
S13 S13 R L
R L
V4 V4
-6L
S6
S6 S12
S12 S10 6 xVDC
S5 V5
S10
S5 V5 6L -5L
5
S7
S7 V6
V6
S8 4
S8 5L -4L S1
(h) 4Vdc 3
(g) +4Vdc S2
2 S3
S2 S2
V3 4L S4
V3
S3 S3 -3L
S5
V2 V2
S1 S1
S4
S9 S11
S4
S9 S11
S6
V1 Load V1 Load S7
O X Y O X Y
S13 L

V4
S13 R L
V4
R
3L -2L S8

S6 S6 S12
S9
S12 S10 S10
S5 V5 S5 V5 S10

V6
S7
V6
S7
2L -1L S11
S8 S8
S12
(i) +5Vdc (j) 5Vdc 1L 0L S13
Fig 6.6 Voltage constraints on the switches
S2 S2
V3 V3
S3 S3

S1
V2

S4
S9 S11 S1
V2

S4
S9 S11
III. COMPARISON STUDY
V1
O X
Load
Y
V1
O

S13
X
Load
L
Y
The comparative study of the developed proposed structure to
S13 R L R

V4 V4
the currently published topologies is provided. Table 7.1
S5
S6
V5
S12 S10
S5
S6
V5
S12 S10
shows the different parameters of the suggested topologies and
V6
S7
V6
S7 the proposed topology for generating a 13-level output
S8 S8
voltage. Further, the entire expenses of all the topology is
(k) +6Vdc (l) 6Vdc compared based upon a cost function (CF).
𝑇𝑆𝑉
Fig 5 Current flow path and its equivalent circuit for different voltage levels of 𝐶𝐹 = (𝑁𝑆𝑊 + 𝑁𝐷𝑟 + 𝑁𝐷 + 𝑁𝐶 + 𝑁𝑃 + 𝛼 ( )) × 𝑁𝐷𝐶 (7.1)
𝑉 𝑜𝑚𝑎𝑥
proposed 13 level topology
 4

The proposed topology requires a lower number of switches, that the cost function provides more importance on the TSV of
drives, capacitor, and drivers for generating 13-level output the structure
voltage as compared to the MLI structure presented table. The From the below table, the developed proposed structure
proposed topology provides lower TSV as compared to the required a lower number of switches and drivers for
topology presented. The cost-function per number of levels generating 13-level output voltage as compared to the
(CF/NL) has been compared among all the topologies for a topologies presented in [15-18] and topology [13] has the
fair comparison study. For this study, the importance of TSV same number of drivers as compared with the proposed
for the comparison is 0.5, 1 and 1.5. When α=0.5, it indicates topology. This topology does not require any capacitor and
that the objective of the cost function is based on the reduction extra diode. Further, the developed structure provided lower
of the component count. Similarly, when α=1.5, it indicates TSV as compare with the topology presented except in [16
,21,22,23,27, and 28]. Further, the cost-function per output
TABLE III voltage-level (CF/NL) has been compared among all the
COMPARISON OF 13-LEVEL INVERTER STRUCTURE WITH THE RECENT
TOPOLOGIES topologies for a fair comparison study. For this study, the
importance of TSV in the cost function as compared to the
Topology Cost function (CF/NL) component count is represented by a factor indicated by α.
Presented NSW NDr ND NC NP NS TSV α = 0.5 α = 1 α = 1.5 The selected α value for the comparison is 0.5, 1 and 1.5.
[15] 16 16 18 9 7 2 35Vdc 5.30 5.52 5.75 When α=0.5, it indicates that the objective of the cost function
[16-a] 15 11 15 1 6 3 12Vdc 3.76 3.84 3.92
[16-b] 19 15 19 2 6 2 16Vdc 4.79 4.89 5 is based on the reduction of the component count. Similarly,
[17] 16 13 16 0 6 6 36Vdc 4.2 4.47 4.75 when α=1.5, it indicates that the cost function provides more
[18] 14 14 17 3 7 3 36Vdc 4.46 4.69 4.92 importance on the TSV of the structure. From Table 7.1, it can
[19] 14 12 14 0 4 6 38Vdc 3.62 3.87 4.11 be observed that for α=0.5, 1 and 1.5 the developed structure
[20] 16 16 16 0 3 6 42Vdc 4.19 4.46 4.73
[21] 14 11 14 2 7 2 32Vdc 3.89 4.10 4.30 provided lower CF/NL as compared to all the topologies
[22] 18 18 22 4 6 2 34Vdc 5.44 5.66 5.88 except [16a, 19, and 21]. From table 7.2 various plot have
[23] 15 15 18 3 7 3 30Vdc 4.65 4.84 5.03 been plotted for analysis the general proposed topology with
[24] 16 16 16 0 8 6 36Vdc 4.53 4.76 5 the existing new topology. These plots are figure 7.1 between
[25] 16 12 16 0 6 6 38Vdc 4.08 4.33 4.57
[26] 17 17 17 0 12 7 48Vdc 5.10 5.37 5.63 numbers of switches, diodes, drivers, TSV, cost function,
[27] 18 18 24 0 6 6 24Vdc 5.23 5.38 5.53 CF/NL as a function of voltage level.
[28] 14 14 14 0 7 6 24Vdc 3.99 4.32 4.64
PT 13 13 17 0 6 6 35Vdc 3.97 4.21 4.44

TABLE IV
COMPARISON OF SOME RECENT DEVELOPED MLI TOPOLOGIES AS A FUNCTION OF THE NUMBER OF LEVELS

Topology NSW NDr ND NC NP NS TSV

[15] 𝟕 𝟕 𝟖 𝟐 𝟐 𝟏 𝟏𝟕
[ (𝑵𝑳 − 𝟏)] + 𝟐 [ (𝑵𝑳 − 𝟏)] + 𝟐 [ (𝑵𝑳 − 𝟏)] + 𝟐 [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] + 𝟑 [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)]
𝟔 𝟔 𝟔 𝟔 𝟔 𝟔 𝟔

[16-a] 𝟏 𝟏 𝟏 1 𝟏 𝟏 𝟐(𝑵𝑳 − 𝟏) − 𝟖
𝟐 [( (𝑵𝑳 − 𝟏)) − 𝟏] + 𝟏𝟎 [( (𝑵𝑳 − 𝟏))] + 𝟖 𝟐 [( (𝑵𝑳 − 𝟏)) − 𝟏] + 𝟏𝟎 [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ ] + 𝟏𝟎
𝟒 𝟒 𝟒 𝟐 𝟒 (𝑵𝑳 − 𝟏)

[16-b] 𝟏 𝟏 𝟏 2 𝟏 𝟏 𝟐(𝑵𝑳 − 𝟏) − 𝟏𝟐
𝟐 [( (𝑵𝑳 − 𝟏)) − 𝟏] + 𝟏𝟔 [( (𝑵𝑳 − 𝟏))] + 𝟏𝟑 𝟐 [( (𝑵𝑳 − 𝟏)) − 𝟏] + 𝟏𝟔 [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ ] + 𝟏𝟔
𝟔 𝟔 𝟔 𝟐 𝟔 (𝑵𝑳 − 𝟏)

[17] 𝟏𝟏 𝟗 𝟏𝟏 0 𝟏 𝟏 𝟐𝟒
[ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)]
𝟖 𝟖 𝟖 𝟐 𝟐 𝟖

[18] 𝟕 𝟕 𝟏𝟕 𝟏 𝟕 𝟏 [𝟑(𝑵𝑳 − 𝟏)]

[ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵 − 𝟏)] [ (𝑵𝑳 − 𝟏)]
𝟔 𝟔 𝟏𝟐 𝑳 𝟒 𝟏𝟐 𝑳 𝟒

[19] (𝑵𝑳 + 𝟏) 𝟒 (𝑵𝑳 + 𝟏) 0 𝟏 𝟏 𝟐𝟎

[ (𝑵𝑳 − 𝟑)] + 𝟒 [ (𝑵𝑳 − 𝟑)] + 𝟐 [ (𝑵𝑳 − 𝟑)] + 𝟏 [ (𝑵𝑳 − 𝟑)] + 𝟒
𝟔 𝟔 𝟐 𝟔

[20] (𝑵𝑳 + 𝟑) (𝑵𝑳 + 𝟑) (𝑵𝑳 + 𝟑) 0 𝟏 𝟏 𝟐𝟎

[ (𝑵𝑳 − 𝟏)] + 𝟏 [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] + 𝟐
𝟔 𝟐 𝟔

[21] (𝑵𝑳 − 𝟏) (𝑵𝑳 − 𝟏) (𝑵𝑳 − 𝟏) (𝑵𝑳 − 𝟏) 𝟏 (𝑵𝑳 − 𝟏) (𝑵𝑳 − 𝟏)

𝟏𝟒 [ ] 𝟏𝟏 [ ] 𝟏𝟒 [ ] 𝟐[ ] [ (𝑵𝑳 − 𝟏)] 𝟐[ ] 𝟑𝟐 [ ]
𝟏𝟐 𝟏𝟐 𝟏𝟐 𝟏𝟐 𝟐 𝟏𝟐 𝟏𝟐

[22] 𝑵𝑳 − 𝟐 𝑵𝑳 − 𝟐 𝑵𝑳 − 𝟐 𝑵𝑳 − 𝟏 𝟏 𝑵𝑳 − 𝟐 𝑵𝑳 − 𝟐
𝟗[ + 𝟏] 𝟗[ + 𝟏] 𝟏𝟏 [ + 𝟏] 𝟐[ ] [ (𝑵𝑳 − 𝟏)] [ + 𝟏] 𝟏𝟕 [ + 𝟏]
𝟔 𝟔 𝟔 𝟔 𝟐 𝟔 𝟔

[23] 𝟏𝟎 𝟏𝟎 𝟏𝟐 𝟏 𝟓 𝟏 𝟐𝟎
[ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)] [ (𝑵𝑳 − 𝟏)]
𝟖 𝟖 𝟖 𝟒 𝟖 𝟒 𝟖

[24] (𝑵𝑳 − 𝟏) + 𝟒 (𝑵𝑳 − 𝟏) + 𝟒 (𝑵𝑳 − 𝟏) + 𝟒 0 𝟏 𝟏 [𝟑(𝑵𝑳 − 𝟏)]

[ (𝑵𝑳 − 𝟏)] + 𝟐 [ (𝑵𝑳 − 𝟏)]
𝟐 𝟐

[25] (𝑵𝑳 + 𝟑) 𝟏 (𝑵𝑳 + 𝟑) 0 𝟏 𝟏 [𝟒(𝑵𝒍 − 𝟏) +

𝟑
(𝑵𝒍 − 𝟏)𝟐 + 𝟏]
[( (𝑵𝑳 − 𝟏))] + 𝟔 [( (𝑵𝑳 − 𝟏))] + 𝟑 [ (𝑵𝑳 − 𝟏)] 𝟏𝟔
𝟐 𝟒 𝟐
𝟐

[26] 𝟓 𝟓 𝟓 0 𝟑 𝟏 𝟐𝟏
[ (𝑵𝑳 − 𝟏)] + 𝟔 [ (𝑵𝑳 − 𝟏)] + 𝟔 [ (𝑵𝑳 − 𝟏)] + 𝟔 [ (𝑵𝑳 − 𝟏)] + 𝟔 [ (𝑵𝑳 − 𝟏)] + 𝟏 [ (𝑵𝑳 − 𝟏)] + 𝟔
𝟔 𝟔 𝟔 𝟔 𝟐 𝟔
 5

A. Switching losses (PSW)

Switching losses of a power semiconductor switches occur

when the switch is in a transition state. In the transition state,
switches position changed from one state to another that is
from ON to OFF and from OFF to ON state. The
semiconductor switches waste some amount of power during
the switching turn-on and the turn-off as switching loss. This
switching loss is calculated for switch and diode is directly
proportional with the switching frequency (fs). The Turn-on
and turn-off energy loss (Eon, Eoff) can be represented as
(a) (b) follows:
𝑡 𝑡 𝑡 1
𝐸𝑖,𝑜𝑛 = ∫0 𝑜𝑛 𝑉𝑠𝑤,𝑖 (1 − ) 𝐼𝑖 ( ) 𝑑𝑡 = 𝑉 𝐼𝑡 (8.3)
𝑡 𝑡 𝑜𝑛 𝑜𝑛 6 𝑠𝑤,𝑖 𝑖 𝑜𝑛

𝑡 𝑡 𝑡 1
𝐸𝑖,𝑜𝑓𝑓 = ∫0 𝑜𝑓𝑓 𝑉𝑠𝑤,𝑖 (1 − ) 𝐼′𝑖 ( ) 𝑑𝑡 𝑉 𝐼 ′𝑡 (8.4)
𝑡 𝑜𝑓𝑓 𝑡𝑜𝑓𝑓 6 𝑠𝑤,𝑖 𝑖 𝑜𝑓𝑓

firstly calculate the number of ON transition (NON,i) and the

number of OFF transition (Noff,i) for per cycle. Then the
energy loss per cycle for the ith switches are given below

𝐸𝑖,𝑠𝑤 = (𝑁𝑜𝑛,𝑖 × 𝐸𝑖,𝑜𝑛 ) + (𝑁𝑜𝑓𝑓,𝑖 × 𝐸𝑖,𝑜𝑓𝑓 ) (8.5)

(c) (d) The switching power loss of the ith switch per cycle can be
expressed as
(𝑁𝑜𝑛,𝑖 ×𝐸𝑖,𝑜𝑛 )+(𝑁𝑜𝑓𝑓,𝑖 ×𝐸𝑖,𝑜𝑓𝑓 )
𝑃𝑖,𝑠𝑤 = (8.6)
𝑇

𝑁
𝑠𝑤𝑖𝑡𝑐ℎ 𝑠𝑤𝑖𝑡𝑐ℎ𝑁 (𝑁𝑜𝑛,𝑖 ×𝐸𝑖,𝑜𝑛 )+(𝑁𝑜𝑓𝑓,𝑖 ×𝐸𝑖,𝑜𝑓𝑓 )
𝑃𝑠𝑤 = ∑𝑖=1 𝑃𝑖,𝑠𝑤 = ∑𝑖=1 [ ] (8.7)
𝑇

B. Conduction losses (PCon)

(e) (f)
Fig 7.1 No of (a) switches, (b) diodes, (c) drivers, (d) TSV, (e) cost function,
(f) CF/NL as a function of voltage level
IV. CALCULATION OF LOSSES
The theoretical power losses and overall efficiency of the
proposed 13-level MLI structure based on (m=1) are
determined in this section. Mainly two types of losses are
associatewith this type of topology, which is switching losses
(PSW) and other is conduction losses (PCon). All calculations
are performed based on the fundamental switching-frequency
strategy. The total power-loss (PLoss) of the proposed MLI can
be represented by
𝑃𝐿𝑜𝑠𝑠 = 𝑃𝑆𝑊 + 𝑃𝐶𝑜𝑛
The overall efficiency of the inverter may be defined as
𝑃𝑜𝑢𝑡
𝜂=
𝑃𝑜𝑢𝑡+𝑃𝐿𝑜𝑠𝑠
function of the number of levels Use either SI (MKS) or CGS
as primary units. (SI units are strongly encouraged.)
Conduction losses are defined in ON – state of power
electronic devices. For this calculation, a typical power
transistor and diode are considered; then they will be
extending to an MLI. For calculating the conduction losses of
the developed 13-level MLI, the internal resistance of each
component, such as power semiconductor switches and diode,
should be taken into account.
(a) (b)
Fig 8.1 Equivalent circuits for evaluating conduction losses of the proposed
MLI when output voltage: (a) +Vo (b) +4Vo
(8.1)
Figure 8.1 (a) and (b) show the equivalent circuits of the
proposed topology when the output voltage level is +Vo and
(8.2) +4Vo. The equivalent circuits are clearly complementary to
others. Hence, the same amount of conduction losses will
occur in these voltage levels. As shown in Figure 8.1 (a) and
(b), the different Kirchhoff’s voltage law equations can be
expressed by

(4𝑟𝑜𝑛 + 2𝑟𝑑 + 𝑅𝐿 )𝐼+1 + 2𝑉𝐹 − 𝑉𝑑𝑐 = 0
(6𝑟𝑜𝑛 + 𝑅𝐿 )𝐼+4 − 4𝑉𝑑𝑐 = 0
The instantaneous conduction power loss during the first
positive voltage level can be expressed by (8.10).
𝑃+1 = (𝐼+1 )2 × (4𝑟𝑜𝑛 + 2𝑟𝑑 )
Similarly, the instantaneous conduction power loss during the
fourth positive voltage level can be depicted by (8.11).
𝑃+4 = (𝐼+4 )2 × 6𝑟𝑜𝑛
where I+1and I+4are the load current during the first and fourth
mode of operation respectively. The load current is
symmetrical in both half cycles; thus, the conduction power
loss remains the same during the first positive and negative
voltage levels.
The average conduction power loss during the first positive
and negative voltage levels can be expressed by (8.12).
2(𝑡2 −𝑡1 ) 4(𝑡2 −𝑡1 )
𝑃𝑎𝑣𝑔1 = (𝑃+1 + 𝑃−1 ) =
𝑇 𝑇
Similarly, the average conduction power losses for other
voltage level durations can be evaluated. Thus, the average
conduction losses over a cycle can be evaluated by (8.13).
𝑁
𝑠𝑤𝑖𝑡𝑐ℎ
𝑃𝑐𝑜𝑛 = ∑𝑗=1 𝑃𝑎𝑣𝑔,𝑗
From the above theoretical analysis for calculating the losses
of the power switch. The switching loss of the proposed 13
levels MLI is 23.231mW and the conduction loss is 14.24 W.
After the simulation, the output power came 426.3W. Hence
the overall efficiency of this topology is 97.35%.
Fig 8.2 Power losses of power electronics switching devices.
V. MODULATION STRATEGY
There are different methods of modulation techniques for the
multilevel inverter to generate the output voltage. These
modulation techniques can be divided in to two
categoriesbased on switching frequency: highfrequency
modulation (HFM) technique and low-frequency modulation
(LFM) technique.
A. Low-frequency modulation (LFM) technique
The proposed general structure for the 13-level inverter is
analyzed for LFM technique. The selected LFM technique is
6
known as Half-Height (H-H) fundamental switching
(8.8)
modulation technique. In the H-H modulation technique, a
(8.9) number of DC voltage levels are compared with the
modulating sinusoidal signal. For an N level inverter, the
transition point in different levels can be found out by (9.1).
1 2𝑖−1
𝑡𝑖 = sin−1 ( ) (9.1)
2𝜋𝑓 𝑁−1
(8.10)
Where ti= transition time for ith voltage level; f = fundamental
frequency.
For better understanding, the output voltage waveform for the
(8.11) 13-level inverter is shown in Figure 9.1 (a) for a positive half
cycle only. The modulating signal is sinusoidal and the
amplitude of the modulating signal is the same as the highest
output voltage level. When the modulating signal reaches half
of each voltage level, the transition of the voltage level occurs
in the output voltage waveform. As seen from Figure 9.1 (a),
when the modulating signal reaches to 1/12, the first transition
in output voltage level happens. Similarly, the other transitions
are at 3/12, 5/12, 7/12, 9/12 and 11/12 dc voltage levels.
Figure 9.1 (b) shows the sub-circuit for generating the
(𝑃+1 ) (8.12) transition points and corresponding logical signals. The
signals are (I0, I1, I2, I3, I4, I5, I6). The different switching
pulses for proposed 13-level inverter can be produced by the
logical OR operation on the signals (I0, I1, I2, I3, I4, I5, I6) as
presented in equation (9.2)-(9.14).
(8.13)
(a)
(b)
Fig 9.1 Figure present (a) output voltage waveform with modulating signal
and (b) sub-circuit for LFM
 7

S1 = I1 + I44 (9.2)
S2 = I6+I5+I4+I3+I66 (9.3)
S3 =I2+I1+I44+I55 (9.4)
S4 = I6+I5+I4+I3+I2+I55+I66 (9.5)
S5 = I4+I11 (9.6)
S6 =I6+I5+I22+I33+I44+I55+I66 (9.7)
S7 = I5+I4+I11+I22 (9.8)
S8 = I6+I33+I44+I55+I66 (9.9)
S9 = I0+I00+I44+I55+I66 (9.10)
S10 =I11+I22+I33+I44+I55+I66 (9.11)
S11 = I0+I00+I1+I2+I3+I4+I5+I6 (9.12)
S12 = I6+I5+I4 (9.13)
S13 = I3+I2+I1+I11+I22+I33 (9.14)

B. High-frequency modulation (HFM) technique

In this modulation technique, the high-frequency carrier
signals are compared with the modulating low-frequency
sinusoidal signal. For producing 13-level output voltage, the
number of the carrier signal is equal to 12. Figure 9.2 shows
the carrier and modulating signals in the positive and negative
output voltage cycle. The carrier signals in positive half-cycle
are C1, C2, C3, C4, C5, and C6. Figure 9.3 shows the sub-
circuits for producing the different switching pulses for this
modulation technique. In Figure 9.3(a), the modulating signal
mR is compared to the DC voltage levels 1/6, 2/6, 3/6, 4/6 and
5/6. The generated logical signals are W1, W2, W3, W4, W5, and
W6. These logical signals become the input signal in sub-
circuit 2. In sub-circuit 2 the modulating signal is compared to
the carrier signals and generating the logical signals are D1,
D1’, D2, D2’, D3, D3’, D4, D4’D5,D5’, D6 and D6’. Similarly, the
logical signals generated by the sub-circuit 2 in negative half-
cycle are D7, D7’, D8, D8’, D9, D9’, D10, D10’, D11,D11’, D12 and
D12’ The different switching gate pulses are created by the OR
logical operation on the output signals of the sub circuit 2 as
presented in (9.15)-(9.27).
Figure 9.2 Comparison of carrier signals with modulating signal
S1= D1+D2’+D10+D11’
S2= D3+D4’+D4+D5’+D5+D6’+D6+D12
S3= D1+D2’+D2+D3’+D10+D11’+D11+D12’
S4= D2+D3’+D3+D4’+D4+D5’+D5+D6’+D6+D11+D12’+D12
S5= D4+D5’+D8’+D7
S6= D5+D6’+D8+D9’+D9+D10’+D10+D11’+D11+D12’+D12
S7= D4+D5’+D5+D6’+D7+D8’+D8+D9’
S8 = D6+D9+D10’+D10+D11’+D11+D12’+D12
S9 = D10+D11’+D11+D12’+D12+D1’+D7’
S10 = D7+D8’+D8+D9’+D9+D10’+D10+D11’+D11+D12’+D12
S11 = D1+D2’+D2+D3’+D3+D4’+D4+D5’+D5+D6’+D6+D1’+D7’
S12 = D4+D5’+D5+D6’+D6
S13 = D1+D2’+D2+D3’+D3+D4’+D7+D8’+D8+D9’+D9+D10’
(a) (b)
Fig 9.3 Figure presents (a) sub-circuit 1, (b ) sub-circuit 2 of HFM
VI. SIMULATION RESULTS
A. Simulation results for basic structure of proposed topology
For 9Levels MLI, Low-frequency modulation scheme has
been implemented at unity modulation index. Simulation has
been performed for different loads as R, RL, L, and dynamic
load conditions. Considering the load as R-L (R= 80Ω and L=
50mH) load, R Load (R = 25Ω), L (L =150mH) and in
dynamic load (initial R =100Ω, final R=50Ω), It can be
observed that the output current is lagging the output voltage
under the L load condition. In dynamic load conditions load-
current and load-voltages of a sudden change in the loads. It is
seen that the load-current and load-voltages are stable after
rapid increment-decrement of the load. From Figure 10.1(e),
(9.15) the peak magnitude of the fundamental component of output
(9.16) voltage and THD of the output voltage are 121.2V and 8.42%
(9.17) respectively. Similarly, from Figure 10.1(f), the peak
(9.18) magnitude of the fundamental component of output current
(9.19)
and THD of output current is1.485A and 3.99% respectively.
(9.20)
(9.21) Figure 10.1(g) presents voltage stresses across the different
(9.22) switches of the proposed topology and it is clearly seen that
(9.23) voltage stress across switch S1,S5,andS6 have 30V, 60V, and
(9.24) 120V respectively, switches which form H-bridge having
(9.25) maximum voltage stresses.
(9.26)
(9.27)
 8

output current waveform under low frequency modulation technique (g) voltage
stress across the switch S1, S5 and S6 (h) current stress across the switch S2 and S5

B. Simulation results for basic structure of proposed topology

B.1. Simulation results for 13 Level proposed MLI
Considering the load as R-L(R=95Ω and L= 15.92mH)
loads, at unity modulation index and supply DC value is
50V

(a) (b)

(a)

(c) (b) (c)

(d) Fig 10.2 Figure presents (a) output voltage and current waveforms for R-L
load condition, (b) FFT analysis of output voltage waveform and (c) FFT
analysis of output current waveform under low-frequency modulation
technique.
The peak magnitude of the fundamental component of output
voltage and THD of the output voltage are 300.1V and 6.41%
respectively. Similarly, the peak magnitude of the fundamental
component of output current and THD of output current
is3.157A and 3.33% respectively. Further, the topology is
simulated for R (R=95Ω),L (L=318mH) and sudden load
change (R = 95Ω (initial), R = 47.5Ω (final), L = 15.92mH)
load conditions.

(e) (f)

(a)

(g) (h) (b) (c)

Fig 10.6 Figure presents (a) output voltage and current waveforms for R-L
load condition, (b) FFT analysis of output voltage waveform and (c) FFT
Fig 10.1 Figure presents output voltage and current waveforms for (a) R-L load analysis of output current waveform under high-frequency modulation
condition, (b) R load condition, (c) L load condition, (d) sudden load change technique.
condition (e) FFT analysis of output voltage waveform and (f) FFT analysis of
 9

300V
VL (t)
200V
IL (t) 5.277A
100V

Voltage (V)
0V

-100V -5.277A

-200V

-300V

0 0.01 0.02 0.03 0.04 0.05 0.06

(a)
Fig 10.7 Output voltage and current
waveforms of proposed 13-level
inverter under resistive (R) load
condition
Time (s)
(e) (f)
(b)
Fig 10.10 Voltage stress across different switches
Fig 10.8 Output voltage and current
waveforms of proposed 13-level
inverter under inductive load VII. HARDWARE REALIZATION OF PROPOSED BASIC
condition TOPOLOGY
The basic structure of the proposed topology has been
implemented through hardware and the results have been
obtained for various load conditions by varying the value of
voltage, resistance and inductance has been done. The
topology utilizes 4 DC sources and 7 gate driver circuits.The
block diagram explaining the procedure of the hardware
implementation is given in figure 11.1.

Fig 10.9 Output voltage & current waveforms of the proposed 13-level
inverter under sudden load change condition

B.2. Voltage stress across switches

It is clearly seen that voltage stress across switch S1,S2,S3 Figure 11.1.Block diagram for hardware implementation
have 50V while voltage across the switch S9,S11 having
300V respectively which is maximum voltage stress and
the voltage across the bidirectional switch S13 is 150V.

Figure 11.2 Complete hardware setup

A. Hardware implementation at each source is selected 30V

(a) (b)
Consider the different load conditions the output voltage and
current waveforms have been taken. ForR-L (R=80Ω and
L=50mH), R= 25Ω and L = 150mH for dynamic load
conditions initial (R = 100Ω and final R = 50Ω). Figure 11.4
(e) and (f) represents the voltage stresses across the switch S1,
S5, S6 and current stresses across the switch S2, S5
respectively. It is clearly observed from the result that the
switches which form H-bridge possess maximum stress
voltage
(c) (d)
 10

VIII. CONCLUSION
A basic structure as well as the generalised structure of the
novel proposed multilevel inverter has presented. The basic
structure can generate 9 levels of output in symmetrical
topology while in general structure if m =1 then it can
generate 13 levels of output with the reduced components.
Comparative studies indicate that the developed MLI structure
has the least device count. An analytical and simulation study
of the proposed topology has been carried out for both.
Hardware implementation of the basic structure was done. It
may be analysed to the simulation that the proposed topology
can effectively operate in various load condition such as R,
RL, L load and even in dynamic load change condition. The
proposed topology was compared with the recently developed
MLI topologies and it was clearly visible that the developed
structure requires lesser components for generating a
(a) (b) particular output-voltage level.

REFERENCES

[1] J. Rodriguez, J. S. Lai, and F. Z. Peng, “Mutilevel

inverters: A survey of topologies, controls, and
application,” IEEE Trans. Ind. Electron., vol.49, no. 4,
pp. 724–738, Aug. 2002.
[2] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro,
R.Portillo, and M. A. M. Prats, “The age of
multilevelconverters arrives,”IEEE Ind.Electron. Mag.,
Vol. 2, No.2, pp. 28–39, Jun. 2008.
[3] Rodriguez, J., Bernet, S., Steimer, P.K., et al.: ‘A
survey on neutral-point clamped inverters’, IEEE
Trans. Ind. Electron., 2010, 57, (8), pp. 2219–2230
[4] Hunag, J., Corzine, K.: ‘Extended operation of flying
capacitor multilevel inverters’, IEEE Trans. Power
(c) (d)
Electron., 2006, 21, (1), pp. 140–147.
[5] Babaei, E.: ‘A cascade multilevel converter topology
with reduced number of switches’, IEEE Trans. Power
Electron., 2008, 23, (6), pp. 2567–2664
[6] M. Trabelsi, and L. Ben-Brahim, “Development Of A
Grid Connected Photovoltaic Power Conditioning
System Based on Flying Capacitors Inverter”, 8th
International Multi-Conference on Systems, Signals &
Devices, pp. 1-6, May 2011
[7] J. Li, J. Liu, D. Boroyevich, P. Mattavelli, and Y. Xue,
“Comparative Analysis of Three-Level Diode Neural-
Point- Clamped and Active Neural-Point-Clamped
Zero-Current-Transition Inverters”, 8th International
Conference on Power Electronics, pp. 2290-2295, May
30-June 3, 2011
[8] M. T. Leon, and G. H. Thomas, “Novel multilevel
inverter carrier based PWM method” IEEE Transaction
(e) (f) On Industry Application Vol. 35, No. 5, pp. 1098-1107,
Sep. 1999
Figure 11.4 Figure presents output voltage and current waveforms for (a) R-L
load condition, (b) R load condition, (c) L load condition, (d) under dynamic [9] G. Grandi, C. Rossi, D. Ostojic, and D. Casadei, “A
load condition (e) voltage stress across the switches S1, S5, S6 (e) current new multilevel conversion structure for grid connected
stress across the switches S2, S5 PV application”, IEEE transaction on industrial
electronics, Vol. 56, No. 11, July 2009
[10] D. Zhong, O. Burak, M. T. Leon, and N. C. John, “DC–
 11

AC Cascaded H-Bridge Multilevel Boost Inverter with Inverter Topology With Switch Fault-Tolerance
No Inductors for Electric/Hybrid Electric Vehicle Capabilities” IEEE Transactions on industrial
Applications”, IEEE Trans. on Industry Applications, electronics, VOL. 64, NO. 3, March 2017
Vol. 45, No. 3, pp. 963-970, May/June 2009 [23] ElyasZamiri, NaserVosoughi, Seyed Hossein Hosseini
[11] Hossein NasiriAvanaki, Reza Barzegarkhoo, “A New Cascaded Switched-Capacitor Multilevel
ElyasZamiri, Yongheng Yang, FredeBlaabjerg Inverter Based on Improved Series–Parallel Conversion
“Reduced switch-count structure for symmetric With Less Number of Components” IEEE Transactions
multilevel inverters with a novel switched DC source On Industrial Electronics, VOL. 63, NO. 6, June 2016
sub module” IET Power Electron., 2019, Vol. 12 Iss. 2, [24] R. Reddy Karasani, Vijay B. Borghate,
pp. 311-321 PrafullachandraMeshram, “A Modified Switched-
[12] Natarajan Prabaharan, KaliannanPalanisamy “A Diode Topology for Cascaded Multilevel Inverters”
comprehensive review on reduced switch multilevel Journal of Power Electronics, Vol. 16, No. 5, pp. 1706-
inverter topologies, modulation techniques and 1715, 2016
applications” Renewable and Sustainable Energy [25] RasoulShalchiAlishah, Seyed Hossein Hosseini,
Reviews vol. 76, 2017, Elsevier EbrahimBabaei, Mehran Sabahi “A New General
[13] Krishna Kumar Gupta, AlekhRanjan, Multilevel Converter Topology Based on Cascaded
PallaveeBhatnagar “Multilevel inverter topologies with Connection of Submultilevel Units With Reduced
Reduced Switch count:A Review” IEEE transaction on Switching Components, DC Sources, and Blocked
power electronics 2016 Voltage by Switches” IEEE Transactions On Industrial
[14] RasoulShalchiAlishah, DaryooshNazarpour, Seyed Electronics, Vol. 63, No. 11, November 2016
Hossein Hosseini, “Reduction of power electronics [26] EbrahimBabaei, Sara Laali, and Zahra Bayat “A
elements in multilevel converters using a new cascaded Single-Phase Cascaded Multilevel Inverter Based on a
structure”IEEE transactions on industrial Electronics, New Basic Unit With Reduced Number of Power
Vol. 62, No. 1, January 2015 Switches” IEEE Transactions On Industrial
[15] Tapas Roy, Pradip Kumar Sadhu, AbhijitDasgupta Electronics, Vol. 62, No. 2, February 2015
“Cross-Switched Multilevel Inverter using Novel [27] AtaollahMokhberdoran and Ali Ajami “Symmetric and
Switched Capacitor Converters” IEEE transactions on Asymmetric Design and Implementation of New
industrial electronics (2019) Cascaded Multilevel Inverter Topology” IEEE
[16] Sze Sing Lee, Kyo-Beum Lee, Ibrahim Transactions On Power Electronics, Vol. 29, No. 12,
MohdAlsofyani, YeongsuBak “ Improved switched Dec2014
capacitor intergrated multilevel inverter with a DC [28] Mohammad FarhadiKangarlu, EbrahimBabaei “Cross-
source string” IEEE transactions on industrial switched multilevel inverter: an innovative Topology”
application (2019) The Institution of Engineering and Technology, Vol. 6,
[17] Saikat Kr. Maity, Tapas Roy “A Study of Symmetrical Iss. 4, pp. 642–651 2014
and various Asymmetrical DC Source Configurations
of a Novel Cascaded Multilevel Inverter Topology”
IEEE International Conference on Technologies for
Smart-City Energy Security and Power 2018
[18] SitakantDebata, Tapas Roy, AbhijitDasgupta, Pradip
Kumar Sadhu “A Novel Structure of Switched
Capacitor Multilevel Inverter with Reduced Device
Count” National Power Engineering Conference
(NPEC) 2018
[19] Sze Sing Lee, MichailSidorov, Chee Shen Lim, Nik
Rumzi Nik Idris, YehEnHeng “Hybrid Cascaded
Multilevel Inverter (HCMLI) With Improved
Symmetrical 4-Level Submodule” IEEE Transactions
On Power Electronics, VOL. 33, NO. 2, 2018
[20] Sze Sing Lee, MichailSidorov, Nik Rumzi Nik Idris,
YehEnHeng “A Symmetrical Cascaded Compact-
Module Multilevel Inverter (CCM-MLI) With
Pulsewidth Modulation” IEEE transactions on
industrial electronics, VOL. 65, NO. 6, June 2018
[21] E. Samadaei, M. Kaviani, K. Bertilsson “ A 13-levels
Module (K-Type) with two DC sources for Multilevel
Inverters” IEEE Transactions on Industrial Electronics
2018
[22] Shivam Prakash Gautam, Lalit Kumar, Shubhrata
Gupta, Nitesh Agrawal “A Single-Phase Five-Level