CMOS Combinational Circuits
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Pass Transistor Logic
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Boolean functions are implemented by Static CMOS
and Dynamic CMOS logic.
Inputs are applied to gate and outputs take at
drain and source of transistor.
Boolean function can be implemented by transistor
as a Switch, this is known as Pass Transistor logic.
Characteristics of an ideal switch
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Zero ON resistance
Vin = Vout
Infinite (very high) OFF resistance
Vout = 0V
Previous value retained in case of capacitive load
Relay is a ideal switch (Electromechanical Device)
In relay logic, presence of high voltage level is considered
to be ‘1’.
Absence of the HIGH voltage level is considered to be ‘0’.
Relay is slow in operation.
Pass Transistor logic is different from relay logic.
Vin Vout
Ideal Switch
Vin = Vout Vout = 0V
( when switch is ON ) ( when switch is OFF )
Vin = high Vin = not present
then, Vin = Vout then, Vout = 0V
Relay which is a electromechanical device can act as an
ideal switch
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NMOS Transistor as a Switch
Vdd Vdd
0V
0V Vdd Vdd – Vth
when Vgs = 0V, the transistor is OFF
when Vgs = Vdd, the transistor is ON
A low level signal can be passed without any degradation
A high level signal cannot be passed without any
degradation
If Vdd is applied to the input terminal, at the other end
we shall get (Vdd - Vt)
PMOS Transistor as a Switch
0V 0V
0V |Vtp| Vdd Vdd
when Vgs = Vdd, the transistor is OFF
when Vgs = 0V, the transistor is ON
A low level signal cannot be passed without any
degradation
A high level signal can be passed without any
degradation
Minimum voltage that it can pass is Vtp
Conduction of Logic Values
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Pass Transistor Logic Design Rules
One must not drive the gate of a pass transistor by
the output of another pass transistor
Vdd Vdd – Vt
Vdd
(5V) (3.5V)
Vdd – 2Vt
Vdd Vdd – Vth
Vdd (2V)
Vdd
Vdd=5V, Vtn=1V
Vdd - Vth = 4V
Vdd = 5V
Vdd = 5V 3V
Vdd 2V
It is essential to provide both Charging and Discharging
path to load Capacitance
a Vdd = f ?
f
Vdd b’ c
C L
By relay logic f = a + b’ c
a'
No path for discharging
0 a b c f
a
1 0 0 1
Vdd = f
Vdd 0 0 1 1
0 0 0 0
C L
0 1 0 0
b’ c
We have to provide the path for discharging the capacitor
Avoid simultaneous path to 0 and Vdd, path both from
low level as well as high level, this will lead to an
output which is undefined i.e. they will act as potential
divider as lead to output which is neither 0 or 1. So we
will get some undefined output.
0V
Pass
transistor
Network
Vdd C L
Control Logic
It happen due to mistake in Design. You have to avoide simultaneous path for 0 and
Vdd
Advantages and Disadvantages of PTL
Advantages of Pass Transistor Disadvantages of Pass Transistor
Logic Logic
Ratio less (You can realize Higher delay in long chain
circuit with minimum of pass transistors
dimension)
Multi-threshold Voltage
Lower area due to smaller drop (Vout = Vdd - Vth)
number of transistors
Lesser power dissipation: Complementary control
no static power and short- signals
circuit power dissipation Sneak Path
(No path from Vdd to
ground by design rule 3)
Transmission Gate
Vdd
To get best of both,
one PMOS and one
NMOS transistor can
0/Vdd 0/Vdd
be connected in
parallel with
complementary inputs
at their gates. This is 0
known as Transmission
Gate.
MOS transistors can be used as
switches with some limitations
Transmission gate provides near
optimal switch
In case of transmission gate, two
parallel transistors supply current
to the load Vin Vout
Realization of Boolean functions
using transmission gate require
large area
NMOS transistors are commonly
used to realize ‘Pass Transistor
Logic (PTL) circuits’
Transmission Gate
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VLSI Design 7 March 2023
2 to 1 Multiplexer
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VLSI Design 7 March 2023
Design XOR and XNOR gate using
Transmission Gate
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XOR Gate
XNOR Gate
Design Half adder using Transmission Gate
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Design Full adder using Transmission Gate
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